[deliverable/linux.git] / arch / arm64 / kernel / debug-monitors.c

/*
 * ARMv8 single-step debug support and mdscr context switching.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */

#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/hardirq.h>
#include <linux/init.h>
#include <linux/ptrace.h>
#include <linux/stat.h>
#include <linux/uaccess.h>

#include <asm/cpufeature.h>
#include <asm/cputype.h>
#include <asm/debug-monitors.h>
#include <asm/system_misc.h>

/* Determine debug architecture. */
u8 debug_monitors_arch(void)
{
	return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
						ID_AA64DFR0_DEBUGVER_SHIFT);
}

/*
 * MDSCR access routines.
 */
static void mdscr_write(u32 mdscr)
{
	unsigned long flags;
	local_dbg_save(flags);
	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
	local_dbg_restore(flags);
}

static u32 mdscr_read(void)
{
	u32 mdscr;
	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
	return mdscr;
}

/*
 * Allow root to disable self-hosted debug from userspace.
 * This is useful if you want to connect an external JTAG debugger.
 */
static bool debug_enabled = true;

static int create_debug_debugfs_entry(void)
{
	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
	return 0;
}
fs_initcall(create_debug_debugfs_entry);

static int __init early_debug_disable(char *buf)
{
	debug_enabled = false;
	return 0;
}

early_param("nodebugmon", early_debug_disable);

/*
 * Keep track of debug users on each core.
 * The ref counts are per-cpu so we use a local_t type.
 */
static DEFINE_PER_CPU(int, mde_ref_count);
static DEFINE_PER_CPU(int, kde_ref_count);

void enable_debug_monitors(enum dbg_active_el el)
{
	u32 mdscr, enable = 0;

	WARN_ON(preemptible());

	if (this_cpu_inc_return(mde_ref_count) == 1)
		enable = DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&
	    this_cpu_inc_return(kde_ref_count) == 1)
		enable |= DBG_MDSCR_KDE;

	if (enable && debug_enabled) {
		mdscr = mdscr_read();
		mdscr |= enable;
		mdscr_write(mdscr);
	}
}

void disable_debug_monitors(enum dbg_active_el el)
{
	u32 mdscr, disable = 0;

	WARN_ON(preemptible());

	if (this_cpu_dec_return(mde_ref_count) == 0)
		disable = ~DBG_MDSCR_MDE;

	if (el == DBG_ACTIVE_EL1 &&
	    this_cpu_dec_return(kde_ref_count) == 0)
		disable &= ~DBG_MDSCR_KDE;

	if (disable) {
		mdscr = mdscr_read();
		mdscr &= disable;
		mdscr_write(mdscr);
	}
}

/*
 * OS lock clearing.
 */
static void clear_os_lock(void *unused)
{
	asm volatile("msr oslar_el1, %0" : : "r" (0));
}

static int os_lock_notify(struct notifier_block *self,
				    unsigned long action, void *data)
{
	int cpu = (unsigned long)data;
	if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
		smp_call_function_single(cpu, clear_os_lock, NULL, 1);
	return NOTIFY_OK;
}

static struct notifier_block os_lock_nb = {
	.notifier_call = os_lock_notify,
};

static int debug_monitors_init(void)
{
	cpu_notifier_register_begin();

	/* Clear the OS lock. */
	on_each_cpu(clear_os_lock, NULL, 1);
	isb();
	local_dbg_enable();

	/* Register hotplug handler. */
	__register_cpu_notifier(&os_lock_nb);

	cpu_notifier_register_done();
	return 0;
}
postcore_initcall(debug_monitors_init);

/*
 * Single step API and exception handling.
 */
static void set_regs_spsr_ss(struct pt_regs *regs)
{
	unsigned long spsr;

	spsr = regs->pstate;
	spsr &= ~DBG_SPSR_SS;
	spsr |= DBG_SPSR_SS;
	regs->pstate = spsr;
}

static void clear_regs_spsr_ss(struct pt_regs *regs)
{
	unsigned long spsr;

	spsr = regs->pstate;
	spsr &= ~DBG_SPSR_SS;
	regs->pstate = spsr;
}

/* EL1 Single Step Handler hooks */
static LIST_HEAD(step_hook);
static DEFINE_RWLOCK(step_hook_lock);

void register_step_hook(struct step_hook *hook)
{
	write_lock(&step_hook_lock);
	list_add(&hook->node, &step_hook);
	write_unlock(&step_hook_lock);
}

void unregister_step_hook(struct step_hook *hook)
{
	write_lock(&step_hook_lock);
	list_del(&hook->node);
	write_unlock(&step_hook_lock);
}

/*
 * Call registered single step handlers
 * There is no Syndrome info to check for determining the handler.
 * So we call all the registered handlers, until the right handler is
 * found which returns zero.
 */
static int call_step_hook(struct pt_regs *regs, unsigned int esr)
{
	struct step_hook *hook;
	int retval = DBG_HOOK_ERROR;

	read_lock(&step_hook_lock);

	list_for_each_entry(hook, &step_hook, node)	{
		retval = hook->fn(regs, esr);
		if (retval == DBG_HOOK_HANDLED)
			break;
	}

	read_unlock(&step_hook_lock);

	return retval;
}

static void send_user_sigtrap(int si_code)
{
	struct pt_regs *regs = current_pt_regs();
	siginfo_t info = {
		.si_signo	= SIGTRAP,
		.si_errno	= 0,
		.si_code	= si_code,
		.si_addr	= (void __user *)instruction_pointer(regs),
	};

	if (WARN_ON(!user_mode(regs)))
		return;

	if (interrupts_enabled(regs))
		local_irq_enable();

	force_sig_info(SIGTRAP, &info, current);
}

static int single_step_handler(unsigned long addr, unsigned int esr,
			       struct pt_regs *regs)
{
	/*
	 * If we are stepping a pending breakpoint, call the hw_breakpoint
	 * handler first.
	 */
	if (!reinstall_suspended_bps(regs))
		return 0;

	if (user_mode(regs)) {
		send_user_sigtrap(TRAP_HWBKPT);

		/*
		 * ptrace will disable single step unless explicitly
		 * asked to re-enable it. For other clients, it makes
		 * sense to leave it enabled (i.e. rewind the controls
		 * to the active-not-pending state).
		 */
		user_rewind_single_step(current);
	} else {
		if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
			return 0;

		pr_warning("Unexpected kernel single-step exception at EL1\n");
		/*
		 * Re-enable stepping since we know that we will be
		 * returning to regs.
		 */
		set_regs_spsr_ss(regs);
	}

	return 0;
}

/*
 * Breakpoint handler is re-entrant as another breakpoint can
 * hit within breakpoint handler, especically in kprobes.
 * Use reader/writer locks instead of plain spinlock.
 */
static LIST_HEAD(break_hook);
static DEFINE_SPINLOCK(break_hook_lock);

void register_break_hook(struct break_hook *hook)
{
	spin_lock(&break_hook_lock);
	list_add_rcu(&hook->node, &break_hook);
	spin_unlock(&break_hook_lock);
}

void unregister_break_hook(struct break_hook *hook)
{
	spin_lock(&break_hook_lock);
	list_del_rcu(&hook->node);
	spin_unlock(&break_hook_lock);
	synchronize_rcu();
}

static int call_break_hook(struct pt_regs *regs, unsigned int esr)
{
	struct break_hook *hook;
	int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL;

	rcu_read_lock();
	list_for_each_entry_rcu(hook, &break_hook, node)
		if ((esr & hook->esr_mask) == hook->esr_val)
			fn = hook->fn;
	rcu_read_unlock();

	return fn ? fn(regs, esr) : DBG_HOOK_ERROR;
}

static int brk_handler(unsigned long addr, unsigned int esr,
		       struct pt_regs *regs)
{
	if (user_mode(regs)) {
		send_user_sigtrap(TRAP_BRKPT);
	} else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) {
		pr_warning("Unexpected kernel BRK exception at EL1\n");
		return -EFAULT;
	}

	return 0;
}

int aarch32_break_handler(struct pt_regs *regs)
{
	u32 arm_instr;
	u16 thumb_instr;
	bool bp = false;
	void __user *pc = (void __user *)instruction_pointer(regs);

	if (!compat_user_mode(regs))
		return -EFAULT;

	if (compat_thumb_mode(regs)) {
		/* get 16-bit Thumb instruction */
		get_user(thumb_instr, (u16 __user *)pc);
		thumb_instr = le16_to_cpu(thumb_instr);
		if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
			/* get second half of 32-bit Thumb-2 instruction */
			get_user(thumb_instr, (u16 __user *)(pc + 2));
			thumb_instr = le16_to_cpu(thumb_instr);
			bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
		} else {
			bp = thumb_instr == AARCH32_BREAK_THUMB;
		}
	} else {
		/* 32-bit ARM instruction */
		get_user(arm_instr, (u32 __user *)pc);
		arm_instr = le32_to_cpu(arm_instr);
		bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
	}

	if (!bp)
		return -EFAULT;

	send_user_sigtrap(TRAP_BRKPT);
	return 0;
}

static int __init debug_traps_init(void)
{
	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
			      TRAP_HWBKPT, "single-step handler");
	hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
			      TRAP_BRKPT, "ptrace BRK handler");
	return 0;
}
arch_initcall(debug_traps_init);

/* Re-enable single step for syscall restarting. */
void user_rewind_single_step(struct task_struct *task)
{
	/*
	 * If single step is active for this thread, then set SPSR.SS
	 * to 1 to avoid returning to the active-pending state.
	 */
	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
		set_regs_spsr_ss(task_pt_regs(task));
}

void user_fastforward_single_step(struct task_struct *task)
{
	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
		clear_regs_spsr_ss(task_pt_regs(task));
}

/* Kernel API */
void kernel_enable_single_step(struct pt_regs *regs)
{
	WARN_ON(!irqs_disabled());
	set_regs_spsr_ss(regs);
	mdscr_write(mdscr_read() | DBG_MDSCR_SS);
	enable_debug_monitors(DBG_ACTIVE_EL1);
}

void kernel_disable_single_step(void)
{
	WARN_ON(!irqs_disabled());
	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
	disable_debug_monitors(DBG_ACTIVE_EL1);
}

int kernel_active_single_step(void)
{
	WARN_ON(!irqs_disabled());
	return mdscr_read() & DBG_MDSCR_SS;
}

/* ptrace API */
void user_enable_single_step(struct task_struct *task)
{
	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	set_regs_spsr_ss(task_pt_regs(task));
}

void user_disable_single_step(struct task_struct *task)
{
	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
}
Commit	Line	Data
478fcb2c WD	1	/*
	2	* ARMv8 single-step debug support and mdscr context switching.
	3	*
	4	* Copyright (C) 2012 ARM Limited
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author: Will Deacon <will.deacon@arm.com>
	19	*/
	20
	21	#include <linux/cpu.h>
	22	#include <linux/debugfs.h>
	23	#include <linux/hardirq.h>
	24	#include <linux/init.h>
	25	#include <linux/ptrace.h>
	26	#include <linux/stat.h>
1442b6ed	27	#include <linux/uaccess.h>
478fcb2c	28
3085bb01	29	#include <asm/cpufeature.h>
478fcb2c	30	#include <asm/cputype.h>
3085bb01	31	#include <asm/debug-monitors.h>
478fcb2c WD	32	#include <asm/system_misc.h>
478fcb2c WD	33
478fcb2c WD	34	/* Determine debug architecture. */
	35	u8 debug_monitors_arch(void)
	36	{
3085bb01 SP	37	return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
3085bb01 SP	38	ID_AA64DFR0_DEBUGVER_SHIFT);
478fcb2c WD	39	}
	40
	41	/*
	42	* MDSCR access routines.
	43	*/
	44	static void mdscr_write(u32 mdscr)
	45	{
	46	unsigned long flags;
	47	local_dbg_save(flags);
	48	asm volatile("msr mdscr_el1, %0" :: "r" (mdscr));
	49	local_dbg_restore(flags);
	50	}
	51
	52	static u32 mdscr_read(void)
	53	{
	54	u32 mdscr;
	55	asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr));
	56	return mdscr;
	57	}
	58
	59	/*
	60	* Allow root to disable self-hosted debug from userspace.
	61	* This is useful if you want to connect an external JTAG debugger.
	62	*/
621a5f7a	63	static bool debug_enabled = true;
478fcb2c WD	64
	65	static int create_debug_debugfs_entry(void)
	66	{
	67	debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled);
	68	return 0;
	69	}
	70	fs_initcall(create_debug_debugfs_entry);
	71
	72	static int __init early_debug_disable(char *buf)
	73	{
621a5f7a	74	debug_enabled = false;
478fcb2c WD	75	return 0;
	76	}
	77
	78	early_param("nodebugmon", early_debug_disable);
	79
	80	/*
	81	* Keep track of debug users on each core.
	82	* The ref counts are per-cpu so we use a local_t type.
	83	*/
1436c1aa CL	84	static DEFINE_PER_CPU(int, mde_ref_count);
1436c1aa CL	85	static DEFINE_PER_CPU(int, kde_ref_count);
478fcb2c	86
6f883d10	87	void enable_debug_monitors(enum dbg_active_el el)
478fcb2c WD	88	{
	89	u32 mdscr, enable = 0;
	90
	91	WARN_ON(preemptible());
	92
1436c1aa	93	if (this_cpu_inc_return(mde_ref_count) == 1)
478fcb2c WD	94	enable = DBG_MDSCR_MDE;
	95
	96	if (el == DBG_ACTIVE_EL1 &&
1436c1aa	97	this_cpu_inc_return(kde_ref_count) == 1)
478fcb2c WD	98	enable \|= DBG_MDSCR_KDE;
	99
	100	if (enable && debug_enabled) {
	101	mdscr = mdscr_read();
	102	mdscr \|= enable;
	103	mdscr_write(mdscr);
	104	}
	105	}
	106
6f883d10	107	void disable_debug_monitors(enum dbg_active_el el)
478fcb2c WD	108	{
	109	u32 mdscr, disable = 0;
	110
	111	WARN_ON(preemptible());
	112
1436c1aa	113	if (this_cpu_dec_return(mde_ref_count) == 0)
478fcb2c WD	114	disable = ~DBG_MDSCR_MDE;
	115
	116	if (el == DBG_ACTIVE_EL1 &&
1436c1aa	117	this_cpu_dec_return(kde_ref_count) == 0)
478fcb2c WD	118	disable &= ~DBG_MDSCR_KDE;
	119
	120	if (disable) {
	121	mdscr = mdscr_read();
	122	mdscr &= disable;
	123	mdscr_write(mdscr);
	124	}
	125	}
	126
	127	/*
	128	* OS lock clearing.
	129	*/
	130	static void clear_os_lock(void *unused)
	131	{
478fcb2c	132	asm volatile("msr oslar_el1, %0" : : "r" (0));
478fcb2c WD	133	}
478fcb2c WD	134
b8c6453a	135	static int os_lock_notify(struct notifier_block *self,
478fcb2c WD	136	unsigned long action, void *data)
	137	{
	138	int cpu = (unsigned long)data;
e56d82a1	139	if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
478fcb2c WD	140	smp_call_function_single(cpu, clear_os_lock, NULL, 1);
	141	return NOTIFY_OK;
	142	}
	143
b8c6453a	144	static struct notifier_block os_lock_nb = {
478fcb2c WD	145	.notifier_call = os_lock_notify,
	146	};
	147
b8c6453a	148	static int debug_monitors_init(void)
478fcb2c	149	{
4b0b68af SB	150	cpu_notifier_register_begin();
4b0b68af SB	151
478fcb2c	152	/* Clear the OS lock. */
d8ed442a VK	153	on_each_cpu(clear_os_lock, NULL, 1);
	154	isb();
	155	local_dbg_enable();
478fcb2c WD	156
478fcb2c WD	157	/* Register hotplug handler. */
4b0b68af SB	158	__register_cpu_notifier(&os_lock_nb);
	159
	160	cpu_notifier_register_done();
478fcb2c WD	161	return 0;
	162	}
	163	postcore_initcall(debug_monitors_init);
	164
	165	/*
	166	* Single step API and exception handling.
	167	*/
	168	static void set_regs_spsr_ss(struct pt_regs *regs)
	169	{
	170	unsigned long spsr;
	171
	172	spsr = regs->pstate;
	173	spsr &= ~DBG_SPSR_SS;
	174	spsr \|= DBG_SPSR_SS;
	175	regs->pstate = spsr;
	176	}
	177
	178	static void clear_regs_spsr_ss(struct pt_regs *regs)
	179	{
	180	unsigned long spsr;
	181
	182	spsr = regs->pstate;
	183	spsr &= ~DBG_SPSR_SS;
	184	regs->pstate = spsr;
	185	}
	186
ee6214ce SP	187	/* EL1 Single Step Handler hooks */
ee6214ce SP	188	static LIST_HEAD(step_hook);
242c04bc	189	static DEFINE_RWLOCK(step_hook_lock);
ee6214ce SP	190
	191	void register_step_hook(struct step_hook *hook)
	192	{
	193	write_lock(&step_hook_lock);
	194	list_add(&hook->node, &step_hook);
	195	write_unlock(&step_hook_lock);
	196	}
	197
	198	void unregister_step_hook(struct step_hook *hook)
	199	{
	200	write_lock(&step_hook_lock);
	201	list_del(&hook->node);
	202	write_unlock(&step_hook_lock);
	203	}
	204
	205	/*
95485fdc	206	* Call registered single step handlers
ee6214ce SP	207	* There is no Syndrome info to check for determining the handler.
	208	* So we call all the registered handlers, until the right handler is
	209	* found which returns zero.
	210	*/
	211	static int call_step_hook(struct pt_regs *regs, unsigned int esr)
	212	{
	213	struct step_hook *hook;
	214	int retval = DBG_HOOK_ERROR;
	215
	216	read_lock(&step_hook_lock);
	217
	218	list_for_each_entry(hook, &step_hook, node) {
	219	retval = hook->fn(regs, esr);
	220	if (retval == DBG_HOOK_HANDLED)
	221	break;
	222	}
	223
	224	read_unlock(&step_hook_lock);
	225
	226	return retval;
	227	}
	228
e04a28d4 WD	229	static void send_user_sigtrap(int si_code)
	230	{
	231	struct pt_regs *regs = current_pt_regs();
	232	siginfo_t info = {
	233	.si_signo = SIGTRAP,
	234	.si_errno = 0,
	235	.si_code = si_code,
	236	.si_addr = (void __user *)instruction_pointer(regs),
	237	};
	238
	239	if (WARN_ON(!user_mode(regs)))
	240	return;
	241
	242	if (interrupts_enabled(regs))
	243	local_irq_enable();
	244
	245	force_sig_info(SIGTRAP, &info, current);
	246	}
	247
478fcb2c WD	248	static int single_step_handler(unsigned long addr, unsigned int esr,
	249	struct pt_regs *regs)
	250	{
478fcb2c WD	251	/*
	252	* If we are stepping a pending breakpoint, call the hw_breakpoint
	253	* handler first.
	254	*/
	255	if (!reinstall_suspended_bps(regs))
	256	return 0;
	257
	258	if (user_mode(regs)) {
e04a28d4	259	send_user_sigtrap(TRAP_HWBKPT);
478fcb2c WD	260
	261	/*
	262	* ptrace will disable single step unless explicitly
	263	* asked to re-enable it. For other clients, it makes
	264	* sense to leave it enabled (i.e. rewind the controls
	265	* to the active-not-pending state).
	266	*/
	267	user_rewind_single_step(current);
	268	} else {
ee6214ce SP	269	if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED)
	270	return 0;
	271
478fcb2c WD	272	pr_warning("Unexpected kernel single-step exception at EL1\n");
	273	/*
	274	* Re-enable stepping since we know that we will be
	275	* returning to regs.
	276	*/
	277	set_regs_spsr_ss(regs);
	278	}
	279
	280	return 0;
	281	}
	282
ee6214ce SP	283	/*
	284	* Breakpoint handler is re-entrant as another breakpoint can
	285	* hit within breakpoint handler, especically in kprobes.
	286	* Use reader/writer locks instead of plain spinlock.
	287	*/
	288	static LIST_HEAD(break_hook);
62c6c61a	289	static DEFINE_SPINLOCK(break_hook_lock);
ee6214ce SP	290
	291	void register_break_hook(struct break_hook *hook)
	292	{
62c6c61a YS	293	spin_lock(&break_hook_lock);
	294	list_add_rcu(&hook->node, &break_hook);
	295	spin_unlock(&break_hook_lock);
ee6214ce SP	296	}
	297
	298	void unregister_break_hook(struct break_hook *hook)
	299	{
62c6c61a YS	300	spin_lock(&break_hook_lock);
	301	list_del_rcu(&hook->node);
	302	spin_unlock(&break_hook_lock);
	303	synchronize_rcu();
ee6214ce SP	304	}
	305
	306	static int call_break_hook(struct pt_regs *regs, unsigned int esr)
	307	{
	308	struct break_hook *hook;
	309	int (fn)(struct pt_regs regs, unsigned int esr) = NULL;
	310
62c6c61a YS	311	rcu_read_lock();
62c6c61a YS	312	list_for_each_entry_rcu(hook, &break_hook, node)
ee6214ce SP	313	if ((esr & hook->esr_mask) == hook->esr_val)
ee6214ce SP	314	fn = hook->fn;
62c6c61a	315	rcu_read_unlock();
ee6214ce SP	316
	317	return fn ? fn(regs, esr) : DBG_HOOK_ERROR;
	318	}
	319
1442b6ed WD	320	static int brk_handler(unsigned long addr, unsigned int esr,
	321	struct pt_regs *regs)
	322	{
c878e0cf	323	if (user_mode(regs)) {
e04a28d4	324	send_user_sigtrap(TRAP_BRKPT);
c878e0cf WD	325	} else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) {
c878e0cf WD	326	pr_warning("Unexpected kernel BRK exception at EL1\n");
1442b6ed	327	return -EFAULT;
c878e0cf	328	}
1442b6ed	329
1442b6ed WD	330	return 0;
	331	}
	332
	333	int aarch32_break_handler(struct pt_regs *regs)
	334	{
2dacab73 ML	335	u32 arm_instr;
2dacab73 ML	336	u16 thumb_instr;
1442b6ed WD	337	bool bp = false;
	338	void __user pc = (void __user )instruction_pointer(regs);
	339
	340	if (!compat_user_mode(regs))
	341	return -EFAULT;
	342
	343	if (compat_thumb_mode(regs)) {
	344	/* get 16-bit Thumb instruction */
2dacab73 ML	345	get_user(thumb_instr, (u16 __user *)pc);
	346	thumb_instr = le16_to_cpu(thumb_instr);
	347	if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
1442b6ed	348	/* get second half of 32-bit Thumb-2 instruction */
2dacab73 ML	349	get_user(thumb_instr, (u16 __user *)(pc + 2));
	350	thumb_instr = le16_to_cpu(thumb_instr);
	351	bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
1442b6ed	352	} else {
2dacab73	353	bp = thumb_instr == AARCH32_BREAK_THUMB;
1442b6ed WD	354	}
	355	} else {
	356	/* 32-bit ARM instruction */
2dacab73 ML	357	get_user(arm_instr, (u32 __user *)pc);
	358	arm_instr = le32_to_cpu(arm_instr);
	359	bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
1442b6ed WD	360	}
	361
	362	if (!bp)
	363	return -EFAULT;
	364
e04a28d4	365	send_user_sigtrap(TRAP_BRKPT);
1442b6ed WD	366	return 0;
	367	}
	368
	369	static int __init debug_traps_init(void)
478fcb2c WD	370	{
	371	hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
	372	TRAP_HWBKPT, "single-step handler");
1442b6ed WD	373	hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
1442b6ed WD	374	TRAP_BRKPT, "ptrace BRK handler");
478fcb2c WD	375	return 0;
478fcb2c WD	376	}
1442b6ed	377	arch_initcall(debug_traps_init);
478fcb2c WD	378
	379	/* Re-enable single step for syscall restarting. */
	380	void user_rewind_single_step(struct task_struct *task)
	381	{
	382	/*
	383	* If single step is active for this thread, then set SPSR.SS
	384	* to 1 to avoid returning to the active-pending state.
	385	*/
	386	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
	387	set_regs_spsr_ss(task_pt_regs(task));
	388	}
	389
	390	void user_fastforward_single_step(struct task_struct *task)
	391	{
	392	if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP))
	393	clear_regs_spsr_ss(task_pt_regs(task));
	394	}
	395
	396	/* Kernel API */
	397	void kernel_enable_single_step(struct pt_regs *regs)
	398	{
	399	WARN_ON(!irqs_disabled());
	400	set_regs_spsr_ss(regs);
	401	mdscr_write(mdscr_read() \| DBG_MDSCR_SS);
	402	enable_debug_monitors(DBG_ACTIVE_EL1);
	403	}
	404
	405	void kernel_disable_single_step(void)
	406	{
	407	WARN_ON(!irqs_disabled());
	408	mdscr_write(mdscr_read() & ~DBG_MDSCR_SS);
	409	disable_debug_monitors(DBG_ACTIVE_EL1);
	410	}
	411
	412	int kernel_active_single_step(void)
	413	{
	414	WARN_ON(!irqs_disabled());
	415	return mdscr_read() & DBG_MDSCR_SS;
	416	}
	417
	418	/* ptrace API */
	419	void user_enable_single_step(struct task_struct *task)
	420	{
	421	set_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	422	set_regs_spsr_ss(task_pt_regs(task));
	423	}
	424
	425	void user_disable_single_step(struct task_struct *task)
	426	{
	427	clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP);
	428	}