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Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / arch / arm64 / kernel / perf_event.c
CommitLineData
03089688
WD		 1/*
2 * PMU support
3 *
4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
6 *
7 * This code is based heavily on the ARMv7 perf event code.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
03089688 21
03089688 22#include <asm/irq_regs.h>
b8cfadfc 23#include <asm/perf_event.h>
bf2d4782 24#include <asm/sysreg.h>
d98ecdac 25#include <asm/virt.h>
03089688 26
6475b2d8
MR		 27#include <linux/of.h>
28#include <linux/perf/arm_pmu.h>
29#include <linux/platform_device.h>
03089688
WD		 30
31/*
32 * ARMv8 PMUv3 Performance Events handling code.
33 * Common event types.
34 */
03089688 35
90381cba 36/* Required events. */
03598fdb
AK		 37#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
38#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
39#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
40#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
41#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
42#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
03089688 43
90381cba 44/* At least one of the following is required. */
03598fdb
AK		 45#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08
46#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B
03089688 47
90381cba 48/* Common architectural events. */
03598fdb
AK		 49#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06
50#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07
90381cba 51#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
03598fdb
AK		 52#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A
53#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B
54#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C
55#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D
56#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E
57#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F
58#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C
9e9caa6a
DR		 59#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
60#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
90381cba
DR		 61
62/* Common microarchitectural events. */
03598fdb
AK		 63#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01
64#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02
65#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05
90381cba 66#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
03598fdb
AK		 67#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14
68#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15
69#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16
70#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17
71#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18
90381cba 72#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
03598fdb 73#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A
90381cba 74#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
9e9caa6a
DR		 75#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
76#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
77#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
78#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
79#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
80#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
81#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
82#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
83#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
84#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
85#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
86#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
87#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
88#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
03598fdb 89#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E
9e9caa6a 90#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
03598fdb
AK		 91#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30
92
93/* ARMv8 recommended implementation defined event types */
94#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
95#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
96#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42
97#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43
0893f745
AK		 98#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44
99#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45
100#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46
101#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47
102#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48
103
03598fdb
AK		 104#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C
105#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D
106#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E
107#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F
0893f745
AK		 108#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50
109#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51
110#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52
111#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53
112
113#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56
114#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57
115#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58
116
117#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C
118#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D
119#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E
120#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F
121
122#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60
123#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61
124#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62
125#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63
126#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64
127#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65
128
129#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66
130#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67
131#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68
132#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69
133#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A
134
135#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C
136#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D
137#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E
138#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F
139#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70
140#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71
141#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72
142#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73
143#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74
144#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75
145#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76
146#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77
147#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78
148#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79
149#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A
150
151#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C
152#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D
153#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E
154
155#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81
156#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82
157#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83
158#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84
159
160#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86
161#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87
162#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88
163
164#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A
165#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B
166#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C
167#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D
168#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E
169#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F
170#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90
171#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91
172
173#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0
174#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1
175#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2
176#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3
177
178#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6
179#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7
180#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8
5f140cce 181
ac82d127 182/* ARMv8 Cortex-A53 specific event types. */
03598fdb 183#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
ac82d127 184
d0aa2bff 185/* ARMv8 Cavium ThunderX specific event types. */
03598fdb
AK		 186#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
187#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
188#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
189#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
190#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
62a4dda9 191
03089688
WD		 192/* PMUv3 HW events mapping. */
193static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
ae2fb7ec 194 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 195 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
196 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
197 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
198 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
199 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
03089688
WD		 200};
201
ac82d127
MR		 202/* ARM Cortex-A53 HW events mapping. */
203static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
204 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 205 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
206 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
207 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
208 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
209 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
210 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
ac82d127
MR		 211 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
212};
213
5d7ee877 214/* ARM Cortex-A57 and Cortex-A72 events mapping. */
62a4dda9
MR		 215static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
216 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 217 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
218 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
219 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
220 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
221 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 222 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
223};
224
d0aa2bff
JG		 225static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
226 PERF_MAP_ALL_UNSUPPORTED,
03598fdb
AK		 227 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
228 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
229 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
230 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
231 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
232 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
d0aa2bff
JG		 233 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
234 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
235};
236
201a72b2
AK		 237/* Broadcom Vulcan events mapping */
238static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
239 PERF_MAP_ALL_UNSUPPORTED,
240 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
241 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
242 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
243 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
244 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
245 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
246 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
247 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
248 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
249};
250
03089688
WD		 251static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
252 [PERF_COUNT_HW_CACHE_OP_MAX]
253 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
ae2fb7ec
MR		 254 PERF_CACHE_MAP_ALL_UNSUPPORTED,
255
03598fdb
AK		 256 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
257 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
258 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
259 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
ae2fb7ec 260
03598fdb
AK		 261 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
262 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
263 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
264 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
03089688
WD		 265};
266
ac82d127
MR		 267static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
268 [PERF_COUNT_HW_CACHE_OP_MAX]
269 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
270 PERF_CACHE_MAP_ALL_UNSUPPORTED,
271
03598fdb
AK		 272 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
273 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
274 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
275 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
276 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
ac82d127 277
03598fdb
AK		 278 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
279 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
ac82d127 280
03598fdb 281 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
ac82d127 282
03598fdb
AK		 283 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
284 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
285 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
286 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
ac82d127
MR		 287};
288
62a4dda9
MR		 289static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
290 [PERF_COUNT_HW_CACHE_OP_MAX]
291 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
292 PERF_CACHE_MAP_ALL_UNSUPPORTED,
293
03598fdb
AK		 294 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
295 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
296 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
297 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
62a4dda9 298
03598fdb
AK		 299 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
300 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
62a4dda9 301
03598fdb
AK		 302 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
303 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
62a4dda9 304
03598fdb 305 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
62a4dda9 306
03598fdb
AK		 307 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
308 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
309 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
310 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 311};
312
d0aa2bff
JG		 313static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
314 [PERF_COUNT_HW_CACHE_OP_MAX]
315 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
316 PERF_CACHE_MAP_ALL_UNSUPPORTED,
317
03598fdb
AK		 318 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
319 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
320 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
321 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
322 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
323 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
324
325 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
326 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
327 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
328 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
329
330 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
331 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
332 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
333 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
334
335 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
336
337 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
338 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
339 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
340 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
62a4dda9
MR		 341};
342
201a72b2
AK		 343static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
344 [PERF_COUNT_HW_CACHE_OP_MAX]
345 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
346 PERF_CACHE_MAP_ALL_UNSUPPORTED,
347
348 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
349 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
350 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
351 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
352
353 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
354 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
355
356 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
357 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
358
359 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
360 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
361 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
362 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
363
364 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
365 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
366 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
367 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
368
369 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
370 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
371};
4b1a9e69
AK		 372
373static ssize_t
374armv8pmu_events_sysfs_show(struct device *dev,
375 struct device_attribute *attr, char *page)
376{
377 struct perf_pmu_events_attr *pmu_attr;
378
379 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
380
381 return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
382}
383
9e9caa6a
DR		 384#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
385#define ARMV8_EVENT_ATTR(name, config) \
4b1a9e69
AK		 386 PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
387 config, armv8pmu_events_sysfs_show)
9e9caa6a 388
03598fdb
AK		 389ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
390ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
391ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
392ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
393ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
394ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
395ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
396ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
397ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
9e9caa6a 398ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
03598fdb
AK		 399ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
400ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
401ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
402ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
403ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
404ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
405ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
406ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
407ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
9e9caa6a 408ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
03598fdb
AK		 409ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
410ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
411ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
412ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
413ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
9e9caa6a 414ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
03598fdb
AK		 415ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
416ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
417ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
9e9caa6a 418ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
4ba2578f 419/* Don't expose the chain event in /sys, since it's useless in isolation */
9e9caa6a
DR		 420ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
421ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
422ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
423ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
424ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
425ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
426ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
427ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
428ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
429ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
430ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
431ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
432ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
433ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
434ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
03598fdb 435ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
9e9caa6a 436ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
03598fdb 437ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
9e9caa6a
DR		 438
439static struct attribute *armv8_pmuv3_event_attrs[] = {
440 &armv8_event_attr_sw_incr.attr.attr,
441 &armv8_event_attr_l1i_cache_refill.attr.attr,
442 &armv8_event_attr_l1i_tlb_refill.attr.attr,
443 &armv8_event_attr_l1d_cache_refill.attr.attr,
444 &armv8_event_attr_l1d_cache.attr.attr,
445 &armv8_event_attr_l1d_tlb_refill.attr.attr,
446 &armv8_event_attr_ld_retired.attr.attr,
447 &armv8_event_attr_st_retired.attr.attr,
448 &armv8_event_attr_inst_retired.attr.attr,
449 &armv8_event_attr_exc_taken.attr.attr,
450 &armv8_event_attr_exc_return.attr.attr,
451 &armv8_event_attr_cid_write_retired.attr.attr,
452 &armv8_event_attr_pc_write_retired.attr.attr,
453 &armv8_event_attr_br_immed_retired.attr.attr,
454 &armv8_event_attr_br_return_retired.attr.attr,
455 &armv8_event_attr_unaligned_ldst_retired.attr.attr,
456 &armv8_event_attr_br_mis_pred.attr.attr,
457 &armv8_event_attr_cpu_cycles.attr.attr,
458 &armv8_event_attr_br_pred.attr.attr,
459 &armv8_event_attr_mem_access.attr.attr,
460 &armv8_event_attr_l1i_cache.attr.attr,
461 &armv8_event_attr_l1d_cache_wb.attr.attr,
462 &armv8_event_attr_l2d_cache.attr.attr,
463 &armv8_event_attr_l2d_cache_refill.attr.attr,
464 &armv8_event_attr_l2d_cache_wb.attr.attr,
465 &armv8_event_attr_bus_access.attr.attr,
466 &armv8_event_attr_memory_error.attr.attr,
467 &armv8_event_attr_inst_spec.attr.attr,
468 &armv8_event_attr_ttbr_write_retired.attr.attr,
469 &armv8_event_attr_bus_cycles.attr.attr,
9e9caa6a
DR		 470 &armv8_event_attr_l1d_cache_allocate.attr.attr,
471 &armv8_event_attr_l2d_cache_allocate.attr.attr,
472 &armv8_event_attr_br_retired.attr.attr,
473 &armv8_event_attr_br_mis_pred_retired.attr.attr,
474 &armv8_event_attr_stall_frontend.attr.attr,
475 &armv8_event_attr_stall_backend.attr.attr,
476 &armv8_event_attr_l1d_tlb.attr.attr,
477 &armv8_event_attr_l1i_tlb.attr.attr,
478 &armv8_event_attr_l2i_cache.attr.attr,
479 &armv8_event_attr_l2i_cache_refill.attr.attr,
480 &armv8_event_attr_l3d_cache_allocate.attr.attr,
481 &armv8_event_attr_l3d_cache_refill.attr.attr,
482 &armv8_event_attr_l3d_cache.attr.attr,
483 &armv8_event_attr_l3d_cache_wb.attr.attr,
484 &armv8_event_attr_l2d_tlb_refill.attr.attr,
03598fdb 485 &armv8_event_attr_l2i_tlb_refill.attr.attr,
9e9caa6a 486 &armv8_event_attr_l2d_tlb.attr.attr,
03598fdb 487 &armv8_event_attr_l2i_tlb.attr.attr,
57d74123 488 NULL,
9e9caa6a
DR		 489};
490
4b1a9e69
AK		 491static umode_t
492armv8pmu_event_attr_is_visible(struct kobject *kobj,
493 struct attribute *attr, int unused)
494{
495 struct device *dev = kobj_to_dev(kobj);
496 struct pmu *pmu = dev_get_drvdata(dev);
497 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
498 struct perf_pmu_events_attr *pmu_attr;
499
500 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
501
502 if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
503 return attr->mode;
504
505 return 0;
506}
507
9e9caa6a
DR		 508static struct attribute_group armv8_pmuv3_events_attr_group = {
509 .name = "events",
510 .attrs = armv8_pmuv3_event_attrs,
4b1a9e69 511 .is_visible = armv8pmu_event_attr_is_visible,
9e9caa6a
DR		 512};
513
57d74123
WD		 514PMU_FORMAT_ATTR(event, "config:0-9");
515
516static struct attribute *armv8_pmuv3_format_attrs[] = {
517 &format_attr_event.attr,
518 NULL,
519};
520
521static struct attribute_group armv8_pmuv3_format_attr_group = {
522 .name = "format",
523 .attrs = armv8_pmuv3_format_attrs,
524};
525
03089688
WD		 526/*
527 * Perf Events' indices
528 */
529#define ARMV8_IDX_CYCLE_COUNTER 0
530#define ARMV8_IDX_COUNTER0 1
6475b2d8
MR		 531#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
532 (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
03089688 533
03089688
WD		 534/*
535 * ARMv8 low level PMU access
536 */
537
538/*
539 * Perf Event to low level counters mapping
540 */
541#define ARMV8_IDX_TO_COUNTER(x) \
b8cfadfc 542 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
03089688
WD		 543
544static inline u32 armv8pmu_pmcr_read(void)
545{
bf2d4782 546 return read_sysreg(pmcr_el0);
03089688
WD		 547}
548
549static inline void armv8pmu_pmcr_write(u32 val)
550{
b8cfadfc 551 val &= ARMV8_PMU_PMCR_MASK;
03089688 552 isb();
bf2d4782 553 write_sysreg(val, pmcr_el0);
03089688
WD		 554}
555
556static inline int armv8pmu_has_overflowed(u32 pmovsr)
557{
b8cfadfc 558 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
03089688
WD		 559}
560
6475b2d8 561static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
03089688 562{
6475b2d8
MR		 563 return idx >= ARMV8_IDX_CYCLE_COUNTER &&
564 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
03089688
WD		 565}
566
567static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
568{
6475b2d8 569 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
03089688
WD		 570}
571
572static inline int armv8pmu_select_counter(int idx)
573{
6475b2d8 574 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 575 write_sysreg(counter, pmselr_el0);
03089688
WD		 576 isb();
577
578 return idx;
579}
580
6475b2d8 581static inline u32 armv8pmu_read_counter(struct perf_event *event)
03089688 582{
6475b2d8
MR		 583 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
584 struct hw_perf_event *hwc = &event->hw;
585 int idx = hwc->idx;
03089688
WD		 586 u32 value = 0;
587
6475b2d8 588 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 589 pr_err("CPU%u reading wrong counter %d\n",
590 smp_processor_id(), idx);
591 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
bf2d4782 592 value = read_sysreg(pmccntr_el0);
03089688 593 else if (armv8pmu_select_counter(idx) == idx)
bf2d4782 594 value = read_sysreg(pmxevcntr_el0);
03089688
WD		 595
596 return value;
597}
598
6475b2d8 599static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
03089688 600{
6475b2d8
MR		 601 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
602 struct hw_perf_event *hwc = &event->hw;
603 int idx = hwc->idx;
604
605 if (!armv8pmu_counter_valid(cpu_pmu, idx))
03089688
WD		 606 pr_err("CPU%u writing wrong counter %d\n",
607 smp_processor_id(), idx);
7175f059
JG		 608 else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
609 /*
610 * Set the upper 32bits as this is a 64bit counter but we only
611 * count using the lower 32bits and we want an interrupt when
612 * it overflows.
613 */
614 u64 value64 = 0xffffffff00000000ULL | value;
615
bf2d4782 616 write_sysreg(value64, pmccntr_el0);
7175f059 617 } else if (armv8pmu_select_counter(idx) == idx)
bf2d4782 618 write_sysreg(value, pmxevcntr_el0);
03089688
WD		 619}
620
621static inline void armv8pmu_write_evtype(int idx, u32 val)
622{
623 if (armv8pmu_select_counter(idx) == idx) {
b8cfadfc 624 val &= ARMV8_PMU_EVTYPE_MASK;
bf2d4782 625 write_sysreg(val, pmxevtyper_el0);
03089688
WD		 626 }
627}
628
629static inline int armv8pmu_enable_counter(int idx)
630{
6475b2d8 631 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 632 write_sysreg(BIT(counter), pmcntenset_el0);
03089688
WD		 633 return idx;
634}
635
636static inline int armv8pmu_disable_counter(int idx)
637{
6475b2d8 638 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 639 write_sysreg(BIT(counter), pmcntenclr_el0);
03089688
WD		 640 return idx;
641}
642
643static inline int armv8pmu_enable_intens(int idx)
644{
6475b2d8 645 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 646 write_sysreg(BIT(counter), pmintenset_el1);
03089688
WD		 647 return idx;
648}
649
650static inline int armv8pmu_disable_intens(int idx)
651{
6475b2d8 652 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
bf2d4782 653 write_sysreg(BIT(counter), pmintenclr_el1);
03089688
WD		 654 isb();
655 /* Clear the overflow flag in case an interrupt is pending. */
bf2d4782 656 write_sysreg(BIT(counter), pmovsclr_el0);
03089688 657 isb();
6475b2d8 658
03089688
WD		 659 return idx;
660}
661
662static inline u32 armv8pmu_getreset_flags(void)
663{
664 u32 value;
665
666 /* Read */
bf2d4782 667 value = read_sysreg(pmovsclr_el0);
03089688
WD		 668
669 /* Write to clear flags */
b8cfadfc 670 value &= ARMV8_PMU_OVSR_MASK;
bf2d4782 671 write_sysreg(value, pmovsclr_el0);
03089688
WD		 672
673 return value;
674}
675
6475b2d8 676static void armv8pmu_enable_event(struct perf_event *event)
03089688
WD		 677{
678 unsigned long flags;
6475b2d8
MR		 679 struct hw_perf_event *hwc = &event->hw;
680 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
681 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
682 int idx = hwc->idx;
03089688
WD		 683
684 /*
685 * Enable counter and interrupt, and set the counter to count
686 * the event that we're interested in.
687 */
688 raw_spin_lock_irqsave(&events->pmu_lock, flags);
689
690 /*
691 * Disable counter
692 */
693 armv8pmu_disable_counter(idx);
694
695 /*
696 * Set event (if destined for PMNx counters).
697 */
698 armv8pmu_write_evtype(idx, hwc->config_base);
699
700 /*
701 * Enable interrupt for this counter
702 */
703 armv8pmu_enable_intens(idx);
704
705 /*
706 * Enable counter
707 */
708 armv8pmu_enable_counter(idx);
709
710 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
711}
712
6475b2d8 713static void armv8pmu_disable_event(struct perf_event *event)
03089688
WD		 714{
715 unsigned long flags;
6475b2d8
MR		 716 struct hw_perf_event *hwc = &event->hw;
717 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
718 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
719 int idx = hwc->idx;
03089688
WD		 720
721 /*
722 * Disable counter and interrupt
723 */
724 raw_spin_lock_irqsave(&events->pmu_lock, flags);
725
726 /*
727 * Disable counter
728 */
729 armv8pmu_disable_counter(idx);
730
731 /*
732 * Disable interrupt for this counter
733 */
734 armv8pmu_disable_intens(idx);
735
736 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
737}
738
739static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
740{
741 u32 pmovsr;
742 struct perf_sample_data data;
6475b2d8
MR		 743 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
744 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 745 struct pt_regs *regs;
746 int idx;
747
748 /*
749 * Get and reset the IRQ flags
750 */
751 pmovsr = armv8pmu_getreset_flags();
752
753 /*
754 * Did an overflow occur?
755 */
756 if (!armv8pmu_has_overflowed(pmovsr))
757 return IRQ_NONE;
758
759 /*
760 * Handle the counter(s) overflow(s)
761 */
762 regs = get_irq_regs();
763
03089688
WD		 764 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
765 struct perf_event *event = cpuc->events[idx];
766 struct hw_perf_event *hwc;
767
768 /* Ignore if we don't have an event. */
769 if (!event)
770 continue;
771
772 /*
773 * We have a single interrupt for all counters. Check that
774 * each counter has overflowed before we process it.
775 */
776 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
777 continue;
778
779 hwc = &event->hw;
6475b2d8 780 armpmu_event_update(event);
03089688 781 perf_sample_data_init(&data, 0, hwc->last_period);
6475b2d8 782 if (!armpmu_event_set_period(event))
03089688
WD		 783 continue;
784
785 if (perf_event_overflow(event, &data, regs))
6475b2d8 786 cpu_pmu->disable(event);
03089688
WD		 787 }
788
789 /*
790 * Handle the pending perf events.
791 *
792 * Note: this call *must* be run with interrupts disabled. For
793 * platforms that can have the PMU interrupts raised as an NMI, this
794 * will not work.
795 */
796 irq_work_run();
797
798 return IRQ_HANDLED;
799}
800
6475b2d8 801static void armv8pmu_start(struct arm_pmu *cpu_pmu)
03089688
WD		 802{
803 unsigned long flags;
6475b2d8 804 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 805
806 raw_spin_lock_irqsave(&events->pmu_lock, flags);
807 /* Enable all counters */
b8cfadfc 808 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
03089688
WD		 809 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
810}
811
6475b2d8 812static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
03089688
WD		 813{
814 unsigned long flags;
6475b2d8 815 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
03089688
WD		 816
817 raw_spin_lock_irqsave(&events->pmu_lock, flags);
818 /* Disable all counters */
b8cfadfc 819 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
03089688
WD		 820 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
821}
822
823static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
6475b2d8 824 struct perf_event *event)
03089688
WD		 825{
826 int idx;
6475b2d8
MR		 827 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
828 struct hw_perf_event *hwc = &event->hw;
b8cfadfc 829 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
03089688
WD		 830
831 /* Always place a cycle counter into the cycle counter. */
03598fdb 832 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
03089688
WD		 833 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
834 return -EAGAIN;
835
836 return ARMV8_IDX_CYCLE_COUNTER;
837 }
838
839 /*
840 * For anything other than a cycle counter, try and use
841 * the events counters
842 */
843 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
844 if (!test_and_set_bit(idx, cpuc->used_mask))
845 return idx;
846 }
847
848 /* The counters are all in use. */
849 return -EAGAIN;
850}
851
852/*
853 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
854 */
855static int armv8pmu_set_event_filter(struct hw_perf_event *event,
856 struct perf_event_attr *attr)
857{
858 unsigned long config_base = 0;
859
860 if (attr->exclude_idle)
861 return -EPERM;
d98ecdac
MZ		 862 if (is_kernel_in_hyp_mode() &&
863 attr->exclude_kernel != attr->exclude_hv)
864 return -EINVAL;
03089688 865 if (attr->exclude_user)
b8cfadfc 866 config_base |= ARMV8_PMU_EXCLUDE_EL0;
d98ecdac 867 if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
b8cfadfc 868 config_base |= ARMV8_PMU_EXCLUDE_EL1;
03089688 869 if (!attr->exclude_hv)
b8cfadfc 870 config_base |= ARMV8_PMU_INCLUDE_EL2;
03089688
WD		 871
872 /*
873 * Install the filter into config_base as this is used to
874 * construct the event type.
875 */
876 event->config_base = config_base;
877
878 return 0;
879}
880
881static void armv8pmu_reset(void *info)
882{
6475b2d8 883 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
03089688
WD		 884 u32 idx, nb_cnt = cpu_pmu->num_events;
885
886 /* The counter and interrupt enable registers are unknown at reset. */
6475b2d8
MR		 887 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
888 armv8pmu_disable_counter(idx);
889 armv8pmu_disable_intens(idx);
890 }
03089688 891
7175f059
JG		 892 /*
893 * Initialize & Reset PMNC. Request overflow interrupt for
894 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
895 */
b8cfadfc
SZ		 896 armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
897 ARMV8_PMU_PMCR_LC);
03089688
WD		 898}
899
900static int armv8_pmuv3_map_event(struct perf_event *event)
901{
6475b2d8 902 return armpmu_map_event(event, &armv8_pmuv3_perf_map,
c019de3d 903 &armv8_pmuv3_perf_cache_map,
b8cfadfc 904 ARMV8_PMU_EVTYPE_EVENT);
03089688
WD		 905}
906
ac82d127
MR		 907static int armv8_a53_map_event(struct perf_event *event)
908{
909 return armpmu_map_event(event, &armv8_a53_perf_map,
910 &armv8_a53_perf_cache_map,
b8cfadfc 911 ARMV8_PMU_EVTYPE_EVENT);
ac82d127
MR		 912}
913
62a4dda9
MR		 914static int armv8_a57_map_event(struct perf_event *event)
915{
916 return armpmu_map_event(event, &armv8_a57_perf_map,
917 &armv8_a57_perf_cache_map,
b8cfadfc 918 ARMV8_PMU_EVTYPE_EVENT);
62a4dda9
MR		 919}
920
d0aa2bff
JG		 921static int armv8_thunder_map_event(struct perf_event *event)
922{
923 return armpmu_map_event(event, &armv8_thunder_perf_map,
924 &armv8_thunder_perf_cache_map,
b8cfadfc 925 ARMV8_PMU_EVTYPE_EVENT);
d0aa2bff
JG		 926}
927
201a72b2
AK		 928static int armv8_vulcan_map_event(struct perf_event *event)
929{
930 return armpmu_map_event(event, &armv8_vulcan_perf_map,
931 &armv8_vulcan_perf_cache_map,
932 ARMV8_PMU_EVTYPE_EVENT);
933}
934
4b1a9e69 935static void __armv8pmu_probe_pmu(void *info)
03089688 936{
4b1a9e69
AK		 937 struct arm_pmu *cpu_pmu = info;
938 u32 pmceid[2];
03089688
WD		 939
940 /* Read the nb of CNTx counters supported from PMNC */
4b1a9e69
AK		 941 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
942 & ARMV8_PMU_PMCR_N_MASK;
03089688 943
6475b2d8 944 /* Add the CPU cycles counter */
4b1a9e69
AK		 945 cpu_pmu->num_events += 1;
946
947 pmceid[0] = read_sysreg(pmceid0_el0);
948 pmceid[1] = read_sysreg(pmceid1_el0);
949
950 bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
951 ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
952 ARRAY_SIZE(pmceid));
03089688
WD		 953}
954
4b1a9e69 955static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
03089688 956{
4b1a9e69
AK		 957 return smp_call_function_any(&cpu_pmu->supported_cpus,
958 __armv8pmu_probe_pmu,
959 cpu_pmu, 1);
03089688
WD		 960}
961
ac82d127 962static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
03089688 963{
6475b2d8
MR		 964 cpu_pmu->handle_irq = armv8pmu_handle_irq,
965 cpu_pmu->enable = armv8pmu_enable_event,
966 cpu_pmu->disable = armv8pmu_disable_event,
967 cpu_pmu->read_counter = armv8pmu_read_counter,
968 cpu_pmu->write_counter = armv8pmu_write_counter,
969 cpu_pmu->get_event_idx = armv8pmu_get_event_idx,
970 cpu_pmu->start = armv8pmu_start,
971 cpu_pmu->stop = armv8pmu_stop,
972 cpu_pmu->reset = armv8pmu_reset,
973 cpu_pmu->max_period = (1LLU << 32) - 1,
ac82d127
MR		 974 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
975}
976
977static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
978{
979 armv8_pmu_init(cpu_pmu);
6475b2d8
MR		 980 cpu_pmu->name = "armv8_pmuv3";
981 cpu_pmu->map_event = armv8_pmuv3_map_event;
569de902
MR		 982 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
983 &armv8_pmuv3_events_attr_group;
984 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
985 &armv8_pmuv3_format_attr_group;
4b1a9e69 986 return armv8pmu_probe_pmu(cpu_pmu);
ac82d127
MR		 987}
988
989static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
990{
991 armv8_pmu_init(cpu_pmu);
992 cpu_pmu->name = "armv8_cortex_a53";
993 cpu_pmu->map_event = armv8_a53_map_event;
569de902
MR		 994 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
995 &armv8_pmuv3_events_attr_group;
996 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
997 &armv8_pmuv3_format_attr_group;
4b1a9e69 998 return armv8pmu_probe_pmu(cpu_pmu);
03089688 999}
03089688 1000
62a4dda9
MR		 1001static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1002{
1003 armv8_pmu_init(cpu_pmu);
1004 cpu_pmu->name = "armv8_cortex_a57";
1005 cpu_pmu->map_event = armv8_a57_map_event;
569de902
MR		 1006 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1007 &armv8_pmuv3_events_attr_group;
1008 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1009 &armv8_pmuv3_format_attr_group;
4b1a9e69 1010 return armv8pmu_probe_pmu(cpu_pmu);
62a4dda9
MR		 1011}
1012
5d7ee877
WD		 1013static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1014{
1015 armv8_pmu_init(cpu_pmu);
1016 cpu_pmu->name = "armv8_cortex_a72";
1017 cpu_pmu->map_event = armv8_a57_map_event;
569de902
MR		 1018 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1019 &armv8_pmuv3_events_attr_group;
1020 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1021 &armv8_pmuv3_format_attr_group;
4b1a9e69 1022 return armv8pmu_probe_pmu(cpu_pmu);
5d7ee877
WD		 1023}
1024
d0aa2bff
JG		 1025static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1026{
1027 armv8_pmu_init(cpu_pmu);
1028 cpu_pmu->name = "armv8_cavium_thunder";
1029 cpu_pmu->map_event = armv8_thunder_map_event;
569de902
MR		 1030 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1031 &armv8_pmuv3_events_attr_group;
1032 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1033 &armv8_pmuv3_format_attr_group;
4b1a9e69 1034 return armv8pmu_probe_pmu(cpu_pmu);
d0aa2bff
JG		 1035}
1036
201a72b2
AK		 1037static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1038{
1039 armv8_pmu_init(cpu_pmu);
1040 cpu_pmu->name = "armv8_brcm_vulcan";
1041 cpu_pmu->map_event = armv8_vulcan_map_event;
569de902
MR		 1042 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1043 &armv8_pmuv3_events_attr_group;
1044 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1045 &armv8_pmuv3_format_attr_group;
201a72b2
AK		 1046 return armv8pmu_probe_pmu(cpu_pmu);
1047}
1048
6475b2d8
MR		 1049static const struct of_device_id armv8_pmu_of_device_ids[] = {
1050 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
ac82d127 1051 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
62a4dda9 1052 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
5d7ee877 1053 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
d0aa2bff 1054 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
201a72b2 1055 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
03089688
WD		 1056 {},
1057};
1058
6475b2d8 1059static int armv8_pmu_device_probe(struct platform_device *pdev)
03089688 1060{
6475b2d8 1061 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
03089688
WD		 1062}
1063
6475b2d8 1064static struct platform_driver armv8_pmu_driver = {
03089688 1065 .driver = {
6475b2d8
MR		 1066 .name = "armv8-pmu",
1067 .of_match_table = armv8_pmu_of_device_ids,
03089688 1068 },
6475b2d8 1069 .probe = armv8_pmu_device_probe,
03089688
WD		 1070};
1071
826d0562 1072builtin_platform_driver(armv8_pmu_driver);
Linux kernel - Deliverables
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