[deliverable/linux.git] / arch / arm64 / kernel / setup.c

/*
 * Based on arch/arm/kernel/setup.c
 *
 * Copyright (C) 1995-2001 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/acpi.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/utsname.h>
#include <linux/initrd.h>
#include <linux/console.h>
#include <linux/cache.h>
#include <linux/bootmem.h>
#include <linux/screen_info.h>
#include <linux/init.h>
#include <linux/kexec.h>
#include <linux/crash_dump.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/fs.h>
#include <linux/proc_fs.h>
#include <linux/memblock.h>
#include <linux/of_fdt.h>
#include <linux/efi.h>
#include <linux/psci.h>

#include <asm/acpi.h>
#include <asm/fixmap.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/elf.h>
#include <asm/cpufeature.h>
#include <asm/cpu_ops.h>
#include <asm/kasan.h>
#include <asm/numa.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/traps.h>
#include <asm/memblock.h>
#include <asm/efi.h>
#include <asm/xen/hypervisor.h>
#include <asm/mmu_context.h>

phys_addr_t __fdt_pointer __initdata;

/*
 * Standard memory resources
 */
static struct resource mem_res[] = {
	{
		.name = "Kernel code",
		.start = 0,
		.end = 0,
		.flags = IORESOURCE_SYSTEM_RAM
	},
	{
		.name = "Kernel data",
		.start = 0,
		.end = 0,
		.flags = IORESOURCE_SYSTEM_RAM
	}
};

#define kernel_code mem_res[0]
#define kernel_data mem_res[1]

/*
 * The recorded values of x0 .. x3 upon kernel entry.
 */
u64 __cacheline_aligned boot_args[4];

void __init smp_setup_processor_id(void)
{
	u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
	cpu_logical_map(0) = mpidr;

	/*
	 * clear __my_cpu_offset on boot CPU to avoid hang caused by
	 * using percpu variable early, for example, lockdep will
	 * access percpu variable inside lock_release
	 */
	set_my_cpu_offset(0);
	pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
}

bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
{
	return phys_id == cpu_logical_map(cpu);
}

struct mpidr_hash mpidr_hash;
/**
 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 *			  level in order to build a linear index from an
 *			  MPIDR value. Resulting algorithm is a collision
 *			  free hash carried out through shifting and ORing
 */
static void __init smp_build_mpidr_hash(void)
{
	u32 i, affinity, fs[4], bits[4], ls;
	u64 mask = 0;
	/*
	 * Pre-scan the list of MPIDRS and filter out bits that do
	 * not contribute to affinity levels, ie they never toggle.
	 */
	for_each_possible_cpu(i)
		mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
	pr_debug("mask of set bits %#llx\n", mask);
	/*
	 * Find and stash the last and first bit set at all affinity levels to
	 * check how many bits are required to represent them.
	 */
	for (i = 0; i < 4; i++) {
		affinity = MPIDR_AFFINITY_LEVEL(mask, i);
		/*
		 * Find the MSB bit and LSB bits position
		 * to determine how many bits are required
		 * to express the affinity level.
		 */
		ls = fls(affinity);
		fs[i] = affinity ? ffs(affinity) - 1 : 0;
		bits[i] = ls - fs[i];
	}
	/*
	 * An index can be created from the MPIDR_EL1 by isolating the
	 * significant bits at each affinity level and by shifting
	 * them in order to compress the 32 bits values space to a
	 * compressed set of values. This is equivalent to hashing
	 * the MPIDR_EL1 through shifting and ORing. It is a collision free
	 * hash though not minimal since some levels might contain a number
	 * of CPUs that is not an exact power of 2 and their bit
	 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
	 */
	mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
						(bits[1] + bits[0]);
	mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
				  fs[3] - (bits[2] + bits[1] + bits[0]);
	mpidr_hash.mask = mask;
	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
		mpidr_hash.shift_aff[0],
		mpidr_hash.shift_aff[1],
		mpidr_hash.shift_aff[2],
		mpidr_hash.shift_aff[3],
		mpidr_hash.mask,
		mpidr_hash.bits);
	/*
	 * 4x is an arbitrary value used to warn on a hash table much bigger
	 * than expected on most systems.
	 */
	if (mpidr_hash_size() > 4 * num_possible_cpus())
		pr_warn("Large number of MPIDR hash buckets detected\n");
}

static void __init setup_machine_fdt(phys_addr_t dt_phys)
{
	void *dt_virt = fixmap_remap_fdt(dt_phys);

	if (!dt_virt || !early_init_dt_scan(dt_virt)) {
		pr_crit("\n"
			"Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
			"The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
			"\nPlease check your bootloader.",
			&dt_phys, dt_virt);

		while (true)
			cpu_relax();
	}

	dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
}

static void __init request_standard_resources(void)
{
	struct memblock_region *region;
	struct resource *res;

	kernel_code.start   = virt_to_phys(_text);
	kernel_code.end     = virt_to_phys(__init_begin - 1);
	kernel_data.start   = virt_to_phys(_sdata);
	kernel_data.end     = virt_to_phys(_end - 1);

	for_each_memblock(memory, region) {
		res = alloc_bootmem_low(sizeof(*res));
		if (memblock_is_nomap(region)) {
			res->name  = "reserved";
			res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
		} else {
			res->name  = "System RAM";
			res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
		}
		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;

		request_resource(&iomem_resource, res);

		if (kernel_code.start >= res->start &&
		    kernel_code.end <= res->end)
			request_resource(res, &kernel_code);
		if (kernel_data.start >= res->start &&
		    kernel_data.end <= res->end)
			request_resource(res, &kernel_data);
	}
}

u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };

void __init setup_arch(char **cmdline_p)
{
	pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());

	sprintf(init_utsname()->machine, UTS_MACHINE);
	init_mm.start_code = (unsigned long) _text;
	init_mm.end_code   = (unsigned long) _etext;
	init_mm.end_data   = (unsigned long) _edata;
	init_mm.brk	   = (unsigned long) _end;

	*cmdline_p = boot_command_line;

	early_fixmap_init();
	early_ioremap_init();

	setup_machine_fdt(__fdt_pointer);

	parse_early_param();

	/*
	 *  Unmask asynchronous aborts after bringing up possible earlycon.
	 * (Report possible System Errors once we can report this occurred)
	 */
	local_async_enable();

	/*
	 * TTBR0 is only used for the identity mapping at this stage. Make it
	 * point to zero page to avoid speculatively fetching new entries.
	 */
	cpu_uninstall_idmap();

	xen_early_init();
	efi_init();
	arm64_memblock_init();

	paging_init();

	acpi_table_upgrade();

	/* Parse the ACPI tables for possible boot-time configuration */
	acpi_boot_table_init();

	if (acpi_disabled)
		unflatten_device_tree();

	bootmem_init();

	kasan_init();

	request_standard_resources();

	early_ioremap_reset();

	if (acpi_disabled)
		psci_dt_init();
	else
		psci_acpi_init();

	cpu_read_bootcpu_ops();
	smp_init_cpus();
	smp_build_mpidr_hash();

#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
	conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
#endif
#endif
	if (boot_args[1] || boot_args[2] || boot_args[3]) {
		pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
			"\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
			"This indicates a broken bootloader or old kernel\n",
			boot_args[1], boot_args[2], boot_args[3]);
	}
}

static int __init topology_init(void)
{
	int i;

	for_each_online_node(i)
		register_one_node(i);

	for_each_possible_cpu(i) {
		struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
		cpu->hotpluggable = 1;
		register_cpu(cpu, i);
	}

	return 0;
}
subsys_initcall(topology_init);

/*
 * Dump out kernel offset information on panic.
 */
static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
			      void *p)
{
	u64 const kaslr_offset = kimage_vaddr - KIMAGE_VADDR;

	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset > 0) {
		pr_emerg("Kernel Offset: 0x%llx from 0x%lx\n",
			 kaslr_offset, KIMAGE_VADDR);
	} else {
		pr_emerg("Kernel Offset: disabled\n");
	}
	return 0;
}

static struct notifier_block kernel_offset_notifier = {
	.notifier_call = dump_kernel_offset
};

static int __init register_kernel_offset_dumper(void)
{
	atomic_notifier_chain_register(&panic_notifier_list,
				       &kernel_offset_notifier);
	return 0;
}
__initcall(register_kernel_offset_dumper);
Commit	Line	Data
9703d9d7 CM	1	/*
	2	* Based on arch/arm/kernel/setup.c
	3	*
	4	* Copyright (C) 1995-2001 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
37655163	20	#include <linux/acpi.h>
9703d9d7 CM	21	#include <linux/export.h>
	22	#include <linux/kernel.h>
	23	#include <linux/stddef.h>
	24	#include <linux/ioport.h>
	25	#include <linux/delay.h>
	26	#include <linux/utsname.h>
	27	#include <linux/initrd.h>
	28	#include <linux/console.h>
a41dc0e8	29	#include <linux/cache.h>
9703d9d7	30	#include <linux/bootmem.h>
9703d9d7 CM	31	#include <linux/screen_info.h>
	32	#include <linux/init.h>
	33	#include <linux/kexec.h>
	34	#include <linux/crash_dump.h>
	35	#include <linux/root_dev.h>
	36	#include <linux/cpu.h>
	37	#include <linux/interrupt.h>
	38	#include <linux/smp.h>
	39	#include <linux/fs.h>
	40	#include <linux/proc_fs.h>
	41	#include <linux/memblock.h>
	42	#include <linux/of_fdt.h>
f84d0275	43	#include <linux/efi.h>
bff60792	44	#include <linux/psci.h>
9703d9d7	45
37655163	46	#include <asm/acpi.h>
bf4b558e	47	#include <asm/fixmap.h>
df857416	48	#include <asm/cpu.h>
9703d9d7 CM	49	#include <asm/cputype.h>
9703d9d7 CM	50	#include <asm/elf.h>
930da09f	51	#include <asm/cpufeature.h>
e8765b26	52	#include <asm/cpu_ops.h>
39d114dd	53	#include <asm/kasan.h>
1a2db300	54	#include <asm/numa.h>
9703d9d7 CM	55	#include <asm/sections.h>
9703d9d7 CM	56	#include <asm/setup.h>
4c7aa002	57	#include <asm/smp_plat.h>
9703d9d7 CM	58	#include <asm/cacheflush.h>
	59	#include <asm/tlbflush.h>
	60	#include <asm/traps.h>
	61	#include <asm/memblock.h>
f84d0275	62	#include <asm/efi.h>
5882bfef	63	#include <asm/xen/hypervisor.h>
9e8e865b	64	#include <asm/mmu_context.h>
9703d9d7	65
9703d9d7 CM	66	phys_addr_t __fdt_pointer __initdata;
	67
	68	/*
	69	* Standard memory resources
	70	*/
	71	static struct resource mem_res[] = {
	72	{
	73	.name = "Kernel code",
	74	.start = 0,
	75	.end = 0,
35d98e93	76	.flags = IORESOURCE_SYSTEM_RAM
9703d9d7 CM	77	},
	78	{
	79	.name = "Kernel data",
	80	.start = 0,
	81	.end = 0,
35d98e93	82	.flags = IORESOURCE_SYSTEM_RAM
9703d9d7 CM	83	}
	84	};
	85
	86	#define kernel_code mem_res[0]
	87	#define kernel_data mem_res[1]
	88
da9c177d AB	89	/*
	90	* The recorded values of x0 .. x3 upon kernel entry.
	91	*/
	92	u64 __cacheline_aligned boot_args[4];
	93
71586276 WD	94	void __init smp_setup_processor_id(void)
71586276 WD	95	{
80708677 MR	96	u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
	97	cpu_logical_map(0) = mpidr;
	98
71586276 WD	99	/*
	100	* clear __my_cpu_offset on boot CPU to avoid hang caused by
	101	* using percpu variable early, for example, lockdep will
	102	* access percpu variable inside lock_release
	103	*/
	104	set_my_cpu_offset(0);
80708677	105	pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
71586276 WD	106	}
71586276 WD	107
6e15d0e0 SK	108	bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
	109	{
	110	return phys_id == cpu_logical_map(cpu);
	111	}
	112
976d7d3f	113	struct mpidr_hash mpidr_hash;
976d7d3f LP	114	/**
	115	* smp_build_mpidr_hash - Pre-compute shifts required at each affinity
	116	* level in order to build a linear index from an
	117	* MPIDR value. Resulting algorithm is a collision
	118	* free hash carried out through shifting and ORing
	119	*/
	120	static void __init smp_build_mpidr_hash(void)
	121	{
	122	u32 i, affinity, fs[4], bits[4], ls;
	123	u64 mask = 0;
	124	/*
	125	* Pre-scan the list of MPIDRS and filter out bits that do
	126	* not contribute to affinity levels, ie they never toggle.
	127	*/
	128	for_each_possible_cpu(i)
	129	mask \|= (cpu_logical_map(i) ^ cpu_logical_map(0));
	130	pr_debug("mask of set bits %#llx\n", mask);
	131	/*
	132	* Find and stash the last and first bit set at all affinity levels to
	133	* check how many bits are required to represent them.
	134	*/
	135	for (i = 0; i < 4; i++) {
	136	affinity = MPIDR_AFFINITY_LEVEL(mask, i);
	137	/*
	138	* Find the MSB bit and LSB bits position
	139	* to determine how many bits are required
	140	* to express the affinity level.
	141	*/
	142	ls = fls(affinity);
	143	fs[i] = affinity ? ffs(affinity) - 1 : 0;
	144	bits[i] = ls - fs[i];
	145	}
	146	/*
	147	* An index can be created from the MPIDR_EL1 by isolating the
	148	* significant bits at each affinity level and by shifting
	149	* them in order to compress the 32 bits values space to a
	150	* compressed set of values. This is equivalent to hashing
	151	* the MPIDR_EL1 through shifting and ORing. It is a collision free
	152	* hash though not minimal since some levels might contain a number
	153	* of CPUs that is not an exact power of 2 and their bit
	154	* representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
	155	*/
	156	mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
	157	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
	158	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
	159	(bits[1] + bits[0]);
	160	mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
	161	fs[3] - (bits[2] + bits[1] + bits[0]);
	162	mpidr_hash.mask = mask;
	163	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
	164	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
	165	mpidr_hash.shift_aff[0],
	166	mpidr_hash.shift_aff[1],
	167	mpidr_hash.shift_aff[2],
	168	mpidr_hash.shift_aff[3],
	169	mpidr_hash.mask,
	170	mpidr_hash.bits);
	171	/*
	172	* 4x is an arbitrary value used to warn on a hash table much bigger
	173	* than expected on most systems.
	174	*/
	175	if (mpidr_hash_size() > 4 * num_possible_cpus())
	176	pr_warn("Large number of MPIDR hash buckets detected\n");
976d7d3f	177	}
137650aa	178
9703d9d7 CM	179	static void __init setup_machine_fdt(phys_addr_t dt_phys)
9703d9d7 CM	180	{
61bd93ce AB	181	void *dt_virt = fixmap_remap_fdt(dt_phys);
	182
	183	if (!dt_virt \|\| !early_init_dt_scan(dt_virt)) {
	184	pr_crit("\n"
	185	"Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
	186	"The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
	187	"\nPlease check your bootloader.",
	188	&dt_phys, dt_virt);
9703d9d7 CM	189
	190	while (true)
	191	cpu_relax();
	192	}
5e39977e	193
44b82b77	194	dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
9703d9d7 CM	195	}
9703d9d7 CM	196
9703d9d7 CM	197	static void __init request_standard_resources(void)
	198	{
	199	struct memblock_region *region;
	200	struct resource *res;
	201
	202	kernel_code.start = virt_to_phys(_text);
9fdc14c5	203	kernel_code.end = virt_to_phys(__init_begin - 1);
9703d9d7 CM	204	kernel_data.start = virt_to_phys(_sdata);
	205	kernel_data.end = virt_to_phys(_end - 1);
	206
	207	for_each_memblock(memory, region) {
	208	res = alloc_bootmem_low(sizeof(*res));
e7cd1903 AT	209	if (memblock_is_nomap(region)) {
	210	res->name = "reserved";
	211	res->flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	212	} else {
	213	res->name = "System RAM";
	214	res->flags = IORESOURCE_SYSTEM_RAM \| IORESOURCE_BUSY;
	215	}
9703d9d7 CM	216	res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
9703d9d7 CM	217	res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
9703d9d7 CM	218
	219	request_resource(&iomem_resource, res);
	220
	221	if (kernel_code.start >= res->start &&
	222	kernel_code.end <= res->end)
	223	request_resource(res, &kernel_code);
	224	if (kernel_data.start >= res->start &&
	225	kernel_data.end <= res->end)
	226	request_resource(res, &kernel_data);
	227	}
	228	}
	229
4c7aa002 JM	230	u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
4c7aa002 JM	231
9703d9d7 CM	232	void __init setup_arch(char **cmdline_p)
9703d9d7 CM	233	{
4b998ff1	234	pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
9703d9d7	235
cfa88c79	236	sprintf(init_utsname()->machine, UTS_MACHINE);
9703d9d7 CM	237	init_mm.start_code = (unsigned long) _text;
	238	init_mm.end_code = (unsigned long) _etext;
	239	init_mm.end_data = (unsigned long) _edata;
	240	init_mm.brk = (unsigned long) _end;
	241
	242	*cmdline_p = boot_command_line;
	243
af86e597	244	early_fixmap_init();
bf4b558e	245	early_ioremap_init();
0bf757c7	246
61bd93ce AB	247	setup_machine_fdt(__fdt_pointer);
61bd93ce AB	248
9703d9d7 CM	249	parse_early_param();
9703d9d7 CM	250
7a9c43be JM	251	/*
	252	* Unmask asynchronous aborts after bringing up possible earlycon.
	253	* (Report possible System Errors once we can report this occurred)
	254	*/
	255	local_async_enable();
	256
86ccce89 MR	257	/*
	258	* TTBR0 is only used for the identity mapping at this stage. Make it
	259	* point to zero page to avoid speculatively fetching new entries.
	260	*/
	261	cpu_uninstall_idmap();
	262
9b08aaa3	263	xen_early_init();
f84d0275	264	efi_init();
9703d9d7 CM	265	arm64_memblock_init();
9703d9d7 CM	266
38b04a74 JM	267	paging_init();
	268
	269	acpi_table_upgrade();
	270
37655163 AS	271	/* Parse the ACPI tables for possible boot-time configuration */
	272	acpi_boot_table_init();
	273
3194ac6e DD	274	if (acpi_disabled)
	275	unflatten_device_tree();
	276
	277	bootmem_init();
	278
39d114dd AR	279	kasan_init();
39d114dd AR	280
9703d9d7 CM	281	request_standard_resources();
9703d9d7 CM	282
0e63ea48	283	early_ioremap_reset();
f84d0275	284
3194ac6e	285	if (acpi_disabled)
7c59a3df	286	psci_dt_init();
3194ac6e	287	else
7c59a3df	288	psci_acpi_init();
3194ac6e	289
0f078336	290	cpu_read_bootcpu_ops();
0f078336	291	smp_init_cpus();
976d7d3f	292	smp_build_mpidr_hash();
9703d9d7 CM	293
	294	#ifdef CONFIG_VT
	295	#if defined(CONFIG_VGA_CONSOLE)
	296	conswitchp = &vga_con;
	297	#elif defined(CONFIG_DUMMY_CONSOLE)
	298	conswitchp = &dummy_con;
	299	#endif
	300	#endif
da9c177d AB	301	if (boot_args[1] \|\| boot_args[2] \|\| boot_args[3]) {
	302	pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
	303	"\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
	304	"This indicates a broken bootloader or old kernel\n",
	305	boot_args[1], boot_args[2], boot_args[3]);
	306	}
9703d9d7 CM	307	}
9703d9d7 CM	308
9703d9d7 CM	309	static int __init topology_init(void)
	310	{
	311	int i;
	312
1a2db300 GK	313	for_each_online_node(i)
	314	register_one_node(i);
	315
9703d9d7	316	for_each_possible_cpu(i) {
df857416	317	struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
9703d9d7 CM	318	cpu->hotpluggable = 1;
	319	register_cpu(cpu, i);
	320	}
	321
	322	return 0;
	323	}
	324	subsys_initcall(topology_init);
f80fb3a3 AB	325
	326	/*
	327	* Dump out kernel offset information on panic.
	328	*/
	329	static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
	330	void *p)
	331	{
	332	u64 const kaslr_offset = kimage_vaddr - KIMAGE_VADDR;
	333
	334	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset > 0) {
	335	pr_emerg("Kernel Offset: 0x%llx from 0x%lx\n",
	336	kaslr_offset, KIMAGE_VADDR);
	337	} else {
	338	pr_emerg("Kernel Offset: disabled\n");
	339	}
	340	return 0;
	341	}
	342
	343	static struct notifier_block kernel_offset_notifier = {
	344	.notifier_call = dump_kernel_offset
	345	};
	346
	347	static int __init register_kernel_offset_dumper(void)
	348	{
	349	atomic_notifier_chain_register(&panic_notifier_list,
	350	&kernel_offset_notifier);
	351	return 0;
	352	}
	353	__initcall(register_kernel_offset_dumper);