Commit | Line | Data |
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d329de3f MZ |
1 | /* |
2 | * Spin Table SMP initialisation | |
3 | * | |
4 | * Copyright (C) 2013 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
652af899 | 19 | #include <linux/delay.h> |
d329de3f MZ |
20 | #include <linux/init.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/smp.h> | |
113954c6 | 23 | #include <linux/types.h> |
d329de3f MZ |
24 | |
25 | #include <asm/cacheflush.h> | |
cd1aebf5 | 26 | #include <asm/cpu_ops.h> |
652af899 | 27 | #include <asm/cputype.h> |
59c68329 | 28 | #include <asm/io.h> |
652af899 MR |
29 | #include <asm/smp_plat.h> |
30 | ||
31 | extern void secondary_holding_pen(void); | |
b6113038 JM |
32 | volatile unsigned long __section(".mmuoff.data.read") |
33 | secondary_holding_pen_release = INVALID_HWID; | |
d329de3f MZ |
34 | |
35 | static phys_addr_t cpu_release_addr[NR_CPUS]; | |
652af899 MR |
36 | |
37 | /* | |
38 | * Write secondary_holding_pen_release in a way that is guaranteed to be | |
39 | * visible to all observers, irrespective of whether they're taking part | |
40 | * in coherency or not. This is necessary for the hotplug code to work | |
41 | * reliably. | |
42 | */ | |
43 | static void write_pen_release(u64 val) | |
44 | { | |
45 | void *start = (void *)&secondary_holding_pen_release; | |
46 | unsigned long size = sizeof(secondary_holding_pen_release); | |
47 | ||
48 | secondary_holding_pen_release = val; | |
49 | __flush_dcache_area(start, size); | |
50 | } | |
51 | ||
d329de3f | 52 | |
819a8826 | 53 | static int smp_spin_table_cpu_init(unsigned int cpu) |
d329de3f | 54 | { |
819a8826 | 55 | struct device_node *dn; |
2fee7d5b | 56 | int ret; |
819a8826 LP |
57 | |
58 | dn = of_get_cpu_node(cpu, NULL); | |
59 | if (!dn) | |
60 | return -ENODEV; | |
61 | ||
d329de3f MZ |
62 | /* |
63 | * Determine the address from which the CPU is polling. | |
64 | */ | |
2fee7d5b MY |
65 | ret = of_property_read_u64(dn, "cpu-release-addr", |
66 | &cpu_release_addr[cpu]); | |
67 | if (ret) | |
d329de3f MZ |
68 | pr_err("CPU %d: missing or invalid cpu-release-addr property\n", |
69 | cpu); | |
70 | ||
2fee7d5b | 71 | of_node_put(dn); |
d329de3f | 72 | |
2fee7d5b | 73 | return ret; |
d329de3f MZ |
74 | } |
75 | ||
cd1aebf5 | 76 | static int smp_spin_table_cpu_prepare(unsigned int cpu) |
d329de3f | 77 | { |
113954c6 | 78 | __le64 __iomem *release_addr; |
d329de3f MZ |
79 | |
80 | if (!cpu_release_addr[cpu]) | |
81 | return -ENODEV; | |
82 | ||
113954c6 MR |
83 | /* |
84 | * The cpu-release-addr may or may not be inside the linear mapping. | |
85 | * As ioremap_cache will either give us a new mapping or reuse the | |
86 | * existing linear mapping, we can use it to cover both cases. In | |
87 | * either case the memory will be MT_NORMAL. | |
88 | */ | |
89 | release_addr = ioremap_cache(cpu_release_addr[cpu], | |
90 | sizeof(*release_addr)); | |
91 | if (!release_addr) | |
92 | return -ENOMEM; | |
710be9ac ML |
93 | |
94 | /* | |
95 | * We write the release address as LE regardless of the native | |
96 | * endianess of the kernel. Therefore, any boot-loaders that | |
97 | * read this address need to convert this address to the | |
98 | * boot-loader's endianess before jumping. This is mandated by | |
99 | * the boot protocol. | |
100 | */ | |
113954c6 MR |
101 | writeq_relaxed(__pa(secondary_holding_pen), release_addr); |
102 | __flush_dcache_area((__force void *)release_addr, | |
103 | sizeof(*release_addr)); | |
d329de3f MZ |
104 | |
105 | /* | |
106 | * Send an event to wake up the secondary CPU. | |
107 | */ | |
108 | sev(); | |
109 | ||
113954c6 MR |
110 | iounmap(release_addr); |
111 | ||
d329de3f MZ |
112 | return 0; |
113 | } | |
114 | ||
652af899 MR |
115 | static int smp_spin_table_cpu_boot(unsigned int cpu) |
116 | { | |
652af899 MR |
117 | /* |
118 | * Update the pen release flag. | |
119 | */ | |
120 | write_pen_release(cpu_logical_map(cpu)); | |
121 | ||
122 | /* | |
123 | * Send an event, causing the secondaries to read pen_release. | |
124 | */ | |
125 | sev(); | |
126 | ||
64001113 | 127 | return 0; |
652af899 MR |
128 | } |
129 | ||
cd1aebf5 | 130 | const struct cpu_operations smp_spin_table_ops = { |
d329de3f | 131 | .name = "spin-table", |
cd1aebf5 MR |
132 | .cpu_init = smp_spin_table_cpu_init, |
133 | .cpu_prepare = smp_spin_table_cpu_prepare, | |
652af899 | 134 | .cpu_boot = smp_spin_table_cpu_boot, |
d329de3f | 135 | }; |