[deliverable/linux.git] / arch / mips / alchemy / common / clocks.c

/*
 * BRIEF MODULE DESCRIPTION
 *	Simple Au1xx0 clocks routines.
 *
 * Copyright 2001, 2008 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. <source@mvista.com>
 *
 *  This program is free software; you can redistribute	 it and/or modify it
 *  under  the terms of	 the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the	License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
 *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
 *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/spinlock.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>

/*
 * I haven't found anyone that doesn't use a 12 MHz source clock,
 * but just in case.....
 */
#define AU1000_SRC_CLK	12000000

static unsigned int au1x00_clock; /*  Hz */
static unsigned long uart_baud_base;

/*
 * Set the au1000_clock
 */
void set_au1x00_speed(unsigned int new_freq)
{
	au1x00_clock = new_freq;
}

unsigned int get_au1x00_speed(void)
{
	return au1x00_clock;
}
EXPORT_SYMBOL(get_au1x00_speed);

/*
 * The UART baud base is not known at compile time ... if
 * we want to be able to use the same code on different
 * speed CPUs.
 */
unsigned long get_au1x00_uart_baud_base(void)
{
	return uart_baud_base;
}

void set_au1x00_uart_baud_base(unsigned long new_baud_base)
{
	uart_baud_base = new_baud_base;
}

/*
 * We read the real processor speed from the PLL.  This is important
 * because it is more accurate than computing it from the 32 KHz
 * counter, if it exists.  If we don't have an accurate processor
 * speed, all of the peripherals that derive their clocks based on
 * this advertised speed will introduce error and sometimes not work
 * properly.  This function is further convoluted to still allow configurations
 * to do that in case they have really, really old silicon with a
 * write-only PLL register.			-- Dan
 */
unsigned long au1xxx_calc_clock(void)
{
	unsigned long cpu_speed;

	/*
	 * On early Au1000, sys_cpupll was write-only. Since these
	 * silicon versions of Au1000 are not sold by AMD, we don't bend
	 * over backwards trying to determine the frequency.
	 */
	if (au1xxx_cpu_has_pll_wo())
		cpu_speed = 396000000;
	else
		cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;

	/* On Alchemy CPU:counter ratio is 1:1 */
	mips_hpt_frequency = cpu_speed;
	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
							  & 0x03) + 2) * 16));

	set_au1x00_speed(cpu_speed);

	return cpu_speed;
}
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* BRIEF MODULE DESCRIPTION
c1dcb14e	3	* Simple Au1xx0 clocks routines.
1da177e4	4	*
c1dcb14e SS	5	* Copyright 2001, 2008 MontaVista Software Inc.
c1dcb14e SS	6	* Author: MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	14	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	15	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	16	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	17	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	18	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	19	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	20	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	21	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	22	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
	29	#include <linux/module.h>
2699cdfb ML	30	#include <linux/spinlock.h>
2699cdfb ML	31	#include <asm/time.h>
1da177e4 LT	32	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	33
2699cdfb ML	34	/*
	35	* I haven't found anyone that doesn't use a 12 MHz source clock,
	36	* but just in case.....
	37	*/
	38	#define AU1000_SRC_CLK 12000000
	39
c1dcb14e	40	static unsigned int au1x00_clock; /* Hz */
1da177e4 LT	41	static unsigned long uart_baud_base;
	42
	43	/*
	44	* Set the au1000_clock
	45	*/
	46	void set_au1x00_speed(unsigned int new_freq)
	47	{
	48	au1x00_clock = new_freq;
	49	}
	50
	51	unsigned int get_au1x00_speed(void)
	52	{
	53	return au1x00_clock;
	54	}
b1fb05cd	55	EXPORT_SYMBOL(get_au1x00_speed);
1da177e4	56
1da177e4 LT	57	/*
	58	* The UART baud base is not known at compile time ... if
	59	* we want to be able to use the same code on different
	60	* speed CPUs.
	61	*/
	62	unsigned long get_au1x00_uart_baud_base(void)
	63	{
	64	return uart_baud_base;
	65	}
	66
	67	void set_au1x00_uart_baud_base(unsigned long new_baud_base)
	68	{
	69	uart_baud_base = new_baud_base;
	70	}
2699cdfb ML	71
	72	/*
	73	* We read the real processor speed from the PLL. This is important
	74	* because it is more accurate than computing it from the 32 KHz
	75	* counter, if it exists. If we don't have an accurate processor
	76	* speed, all of the peripherals that derive their clocks based on
	77	* this advertised speed will introduce error and sometimes not work
25985edc	78	* properly. This function is further convoluted to still allow configurations
2699cdfb ML	79	* to do that in case they have really, really old silicon with a
	80	* write-only PLL register. -- Dan
	81	*/
	82	unsigned long au1xxx_calc_clock(void)
	83	{
	84	unsigned long cpu_speed;
2699cdfb ML	85
	86	/*
	87	* On early Au1000, sys_cpupll was write-only. Since these
	88	* silicon versions of Au1000 are not sold by AMD, we don't bend
	89	* over backwards trying to determine the frequency.
	90	*/
	91	if (au1xxx_cpu_has_pll_wo())
2699cdfb	92	cpu_speed = 396000000;
2699cdfb ML	93	else
	94	cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
	95
	96	/* On Alchemy CPU:counter ratio is 1:1 */
	97	mips_hpt_frequency = cpu_speed;
	98	/* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
	99	set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
	100	& 0x03) + 2) * 16));
	101
2699cdfb ML	102	set_au1x00_speed(cpu_speed);
	103
	104	return cpu_speed;
	105	}