MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)
[deliverable/linux.git] / arch / mips / include / asm / pgtable.h
CommitLineData
1da177e4
LT
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H
10
5bbea36a 11#include <linux/mm_types.h>
970d032f 12#include <linux/mmzone.h>
875d43e7 13#ifdef CONFIG_32BIT
1da177e4
LT
14#include <asm/pgtable-32.h>
15#endif
875d43e7 16#ifdef CONFIG_64BIT
1da177e4
LT
17#include <asm/pgtable-64.h>
18#endif
19
f10fae02 20#include <asm/io.h>
1da177e4
LT
21#include <asm/pgtable-bits.h>
22
8c65b4a6
TS
23struct mm_struct;
24struct vm_area_struct;
25
780602d7
PB
26#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \
27 _CACHE_CACHABLE_NONCOHERENT)
28#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
35133692 29 _page_cachable_default)
780602d7 30#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | \
be0c37c9 31 _page_cachable_default)
780602d7 32#define PAGE_READONLY __pgprot(_PAGE_PRESENT | \
35133692 33 _page_cachable_default)
1da177e4 34#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
35133692 35 _PAGE_GLOBAL | _page_cachable_default)
e2a9e5ad
PB
36#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
37 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
780602d7 38#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
35133692 39 _page_cachable_default)
1da177e4
LT
40#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
41 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
42
43/*
6dd9344c
DD
44 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
45 * execute, and consider it to be the same as read. Also, write
46 * permissions imply read permissions. This is the closest we can get
47 * by reasonable means..
1da177e4 48 */
1da177e4 49
35133692
CD
50/*
51 * Dummy values to fill the table in mmap.c
52 * The real values will be generated at runtime
53 */
54#define __P000 __pgprot(0)
55#define __P001 __pgprot(0)
56#define __P010 __pgprot(0)
57#define __P011 __pgprot(0)
58#define __P100 __pgprot(0)
59#define __P101 __pgprot(0)
60#define __P110 __pgprot(0)
61#define __P111 __pgprot(0)
62
63#define __S000 __pgprot(0)
64#define __S001 __pgprot(0)
65#define __S010 __pgprot(0)
66#define __S011 __pgprot(0)
67#define __S100 __pgprot(0)
68#define __S101 __pgprot(0)
69#define __S110 __pgprot(0)
70#define __S111 __pgprot(0)
71
72extern unsigned long _page_cachable_default;
1da177e4
LT
73
74/*
75 * ZERO_PAGE is a global shared page that is always zero; used
76 * for zero-mapped memory areas etc..
77 */
78
79extern unsigned long empty_zero_page;
80extern unsigned long zero_page_mask;
81
82#define ZERO_PAGE(vaddr) \
99e3b942 83 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
816422ad 84#define __HAVE_COLOR_ZERO_PAGE
62eede62 85
1da177e4
LT
86extern void paging_init(void);
87
88/*
89 * Conversion functions: convert a page and protection to a page entry,
90 * and a page entry and page directory to the page they refer to.
91 */
c9d06962 92#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
970d032f
RB
93
94#define __pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
95#ifndef CONFIG_TRANSPARENT_HUGEPAGE
96#define pmd_page(pmd) __pmd_page(pmd)
97#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
98
46a82b2d 99#define pmd_page_vaddr(pmd) pmd_val(pmd)
1da177e4 100
f1014d1b
MC
101#define htw_stop() \
102do { \
ed4cbc81
MC
103 unsigned long flags; \
104 \
461d1597 105 if (cpu_has_htw) { \
ed4cbc81
MC
106 local_irq_save(flags); \
107 if(!raw_current_cpu_data.htw_seq++) { \
108 write_c0_pwctl(read_c0_pwctl() & \
109 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
110 back_to_back_c0_hazard(); \
111 } \
112 local_irq_restore(flags); \
461d1597 113 } \
f1014d1b
MC
114} while(0)
115
116#define htw_start() \
117do { \
ed4cbc81
MC
118 unsigned long flags; \
119 \
f1014d1b 120 if (cpu_has_htw) { \
ed4cbc81
MC
121 local_irq_save(flags); \
122 if (!--raw_current_cpu_data.htw_seq) { \
123 write_c0_pwctl(read_c0_pwctl() | \
124 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
125 back_to_back_c0_hazard(); \
126 } \
127 local_irq_restore(flags); \
f1014d1b
MC
128 } \
129} while(0)
130
37d22a0d
PB
131static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
132 pte_t *ptep, pte_t pteval);
133
34adb28d 134#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
6e953891 135
7b2cb64f
PB
136#ifdef CONFIG_XPA
137# define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
138#else
139# define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
140#endif
141
6e953891 142#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
37d22a0d 143#define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC)
6e953891 144
1da177e4
LT
145static inline void set_pte(pte_t *ptep, pte_t pte)
146{
147 ptep->pte_high = pte.pte_high;
148 smp_wmb();
149 ptep->pte_low = pte.pte_low;
1da177e4 150
7b2cb64f 151#ifdef CONFIG_XPA
c5b36783 152 if (pte.pte_high & _PAGE_GLOBAL) {
7b2cb64f
PB
153#else
154 if (pte.pte_low & _PAGE_GLOBAL) {
155#endif
1da177e4
LT
156 pte_t *buddy = ptep_buddy(ptep);
157 /*
158 * Make sure the buddy is global too (if it's !none,
159 * it better already be global)
160 */
7b2cb64f
PB
161 if (pte_none(*buddy)) {
162 if (!config_enabled(CONFIG_XPA))
163 buddy->pte_low |= _PAGE_GLOBAL;
6e953891 164 buddy->pte_high |= _PAGE_GLOBAL;
7b2cb64f 165 }
1da177e4
LT
166 }
167}
1da177e4
LT
168
169static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
170{
6e953891
SS
171 pte_t null = __pte(0);
172
fde3538a 173 htw_stop();
1da177e4 174 /* Preserve global status for the pair */
7b2cb64f
PB
175 if (config_enabled(CONFIG_XPA)) {
176 if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
177 null.pte_high = _PAGE_GLOBAL;
178 } else {
179 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
180 null.pte_low = null.pte_high = _PAGE_GLOBAL;
181 }
6e953891
SS
182
183 set_pte_at(mm, addr, ptep, null);
fde3538a 184 htw_start();
1da177e4
LT
185}
186#else
6e953891
SS
187
188#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
189#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
37d22a0d 190#define pte_no_exec(pte) (pte_val(pte) & _PAGE_NO_EXEC)
6e953891 191
1da177e4
LT
192/*
193 * Certain architectures need to do special things when pte's
194 * within a page table are directly modified. Thus, the following
195 * hook is made available.
196 */
197static inline void set_pte(pte_t *ptep, pte_t pteval)
198{
199 *ptep = pteval;
200#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
201 if (pte_val(pteval) & _PAGE_GLOBAL) {
202 pte_t *buddy = ptep_buddy(ptep);
203 /*
204 * Make sure the buddy is global too (if it's !none,
205 * it better already be global)
206 */
46011e6e
DD
207#ifdef CONFIG_SMP
208 /*
209 * For SMP, multiple CPUs can race, so we need to do
210 * this atomically.
211 */
46011e6e
DD
212 unsigned long page_global = _PAGE_GLOBAL;
213 unsigned long tmp;
214
12863939
JK
215 if (kernel_uses_llsc && R10000_LLSC_WAR) {
216 __asm__ __volatile__ (
217 " .set arch=r4000 \n"
218 " .set push \n"
219 " .set noreorder \n"
220 "1:" __LL "%[tmp], %[buddy] \n"
221 " bnez %[tmp], 2f \n"
222 " or %[tmp], %[tmp], %[global] \n"
223 __SC "%[tmp], %[buddy] \n"
224 " beqzl %[tmp], 1b \n"
225 " nop \n"
226 "2: \n"
227 " .set pop \n"
228 " .set mips0 \n"
229 : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
46011e6e 230 : [global] "r" (page_global));
12863939
JK
231 } else if (kernel_uses_llsc) {
232 __asm__ __volatile__ (
233 " .set "MIPS_ISA_ARCH_LEVEL" \n"
234 " .set push \n"
235 " .set noreorder \n"
236 "1:" __LL "%[tmp], %[buddy] \n"
237 " bnez %[tmp], 2f \n"
238 " or %[tmp], %[tmp], %[global] \n"
239 __SC "%[tmp], %[buddy] \n"
240 " beqz %[tmp], 1b \n"
241 " nop \n"
242 "2: \n"
243 " .set pop \n"
244 " .set mips0 \n"
245 : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
246 : [global] "r" (page_global));
247 }
46011e6e 248#else /* !CONFIG_SMP */
1da177e4
LT
249 if (pte_none(*buddy))
250 pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
46011e6e 251#endif /* CONFIG_SMP */
1da177e4
LT
252 }
253#endif
254}
1da177e4
LT
255
256static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
257{
fde3538a 258 htw_stop();
1da177e4
LT
259#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
260 /* Preserve global status for the pair */
261 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
262 set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
263 else
264#endif
265 set_pte_at(mm, addr, ptep, __pte(0));
fde3538a 266 htw_start();
1da177e4
LT
267}
268#endif
269
37d22a0d
PB
270static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
271 pte_t *ptep, pte_t pteval)
272{
273 extern void __update_cache(unsigned long address, pte_t pte);
274
275 if (!pte_present(pteval))
276 goto cache_sync_done;
277
278 if (pte_present(*ptep) && (pte_pfn(*ptep) == pte_pfn(pteval)))
279 goto cache_sync_done;
280
281 __update_cache(addr, pteval);
282cache_sync_done:
283 set_pte(ptep, pteval);
284}
285
1da177e4 286/*
c6e8b587 287 * (pmds are folded into puds so this doesn't get actually called,
1da177e4
LT
288 * but the define is needed for a generic inline function.)
289 */
290#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
c6e8b587 291
325f8a0a 292#ifndef __PAGETABLE_PMD_FOLDED
c6e8b587
RB
293/*
294 * (puds are folded into pgds so this doesn't get actually called,
295 * but the define is needed for a generic inline function.)
296 */
297#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
298#endif
1da177e4 299
5ff97472
RB
300#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
301#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
302#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
1da177e4 303
9975e77d
RB
304/*
305 * We used to declare this array with size but gcc 3.3 and older are not able
306 * to find that this expression is a constant, so the size is dropped.
307 */
308extern pgd_t swapper_pg_dir[];
1da177e4
LT
309
310/*
311 * The following only work if pte_present() is true.
312 * Undefined behaviour if not..
313 */
34adb28d 314#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
6e953891
SS
315static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
316static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
317static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
6e953891 318
1da177e4
LT
319static inline pte_t pte_wrprotect(pte_t pte)
320{
c5b36783 321 pte.pte_low &= ~_PAGE_WRITE;
7b2cb64f
PB
322 if (!config_enabled(CONFIG_XPA))
323 pte.pte_low &= ~_PAGE_SILENT_WRITE;
6e953891 324 pte.pte_high &= ~_PAGE_SILENT_WRITE;
1da177e4
LT
325 return pte;
326}
327
1da177e4
LT
328static inline pte_t pte_mkclean(pte_t pte)
329{
c5b36783 330 pte.pte_low &= ~_PAGE_MODIFIED;
7b2cb64f
PB
331 if (!config_enabled(CONFIG_XPA))
332 pte.pte_low &= ~_PAGE_SILENT_WRITE;
6e953891 333 pte.pte_high &= ~_PAGE_SILENT_WRITE;
1da177e4
LT
334 return pte;
335}
336
337static inline pte_t pte_mkold(pte_t pte)
338{
c5b36783 339 pte.pte_low &= ~_PAGE_ACCESSED;
7b2cb64f
PB
340 if (!config_enabled(CONFIG_XPA))
341 pte.pte_low &= ~_PAGE_SILENT_READ;
6e953891 342 pte.pte_high &= ~_PAGE_SILENT_READ;
1da177e4
LT
343 return pte;
344}
345
346static inline pte_t pte_mkwrite(pte_t pte)
347{
6e953891 348 pte.pte_low |= _PAGE_WRITE;
7b2cb64f
PB
349 if (pte.pte_low & _PAGE_MODIFIED) {
350 if (!config_enabled(CONFIG_XPA))
351 pte.pte_low |= _PAGE_SILENT_WRITE;
6e953891 352 pte.pte_high |= _PAGE_SILENT_WRITE;
7b2cb64f 353 }
1da177e4
LT
354 return pte;
355}
356
1da177e4
LT
357static inline pte_t pte_mkdirty(pte_t pte)
358{
6e953891 359 pte.pte_low |= _PAGE_MODIFIED;
7b2cb64f
PB
360 if (pte.pte_low & _PAGE_WRITE) {
361 if (!config_enabled(CONFIG_XPA))
362 pte.pte_low |= _PAGE_SILENT_WRITE;
6e953891 363 pte.pte_high |= _PAGE_SILENT_WRITE;
7b2cb64f 364 }
1da177e4
LT
365 return pte;
366}
367
368static inline pte_t pte_mkyoung(pte_t pte)
369{
6e953891 370 pte.pte_low |= _PAGE_ACCESSED;
7b2cb64f
PB
371 if (!(pte.pte_low & _PAGE_NO_READ)) {
372 if (!config_enabled(CONFIG_XPA))
373 pte.pte_low |= _PAGE_SILENT_READ;
6e953891 374 pte.pte_high |= _PAGE_SILENT_READ;
7b2cb64f 375 }
1da177e4
LT
376 return pte;
377}
378#else
1da177e4
LT
379static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
380static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
381static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
1da177e4
LT
382
383static inline pte_t pte_wrprotect(pte_t pte)
384{
385 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
386 return pte;
387}
388
1da177e4
LT
389static inline pte_t pte_mkclean(pte_t pte)
390{
77a5c593 391 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
1da177e4
LT
392 return pte;
393}
394
395static inline pte_t pte_mkold(pte_t pte)
396{
77a5c593 397 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
1da177e4
LT
398 return pte;
399}
400
401static inline pte_t pte_mkwrite(pte_t pte)
402{
403 pte_val(pte) |= _PAGE_WRITE;
404 if (pte_val(pte) & _PAGE_MODIFIED)
405 pte_val(pte) |= _PAGE_SILENT_WRITE;
406 return pte;
407}
408
1da177e4
LT
409static inline pte_t pte_mkdirty(pte_t pte)
410{
411 pte_val(pte) |= _PAGE_MODIFIED;
412 if (pte_val(pte) & _PAGE_WRITE)
413 pte_val(pte) |= _PAGE_SILENT_WRITE;
414 return pte;
415}
416
417static inline pte_t pte_mkyoung(pte_t pte)
418{
419 pte_val(pte) |= _PAGE_ACCESSED;
be0c37c9
SH
420 if (!(pte_val(pte) & _PAGE_NO_READ))
421 pte_val(pte) |= _PAGE_SILENT_READ;
1da177e4
LT
422 return pte;
423}
dd794392 424
05f9883a 425#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
dd794392
DD
426static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
427
428static inline pte_t pte_mkhuge(pte_t pte)
429{
430 pte_val(pte) |= _PAGE_HUGE;
431 return pte;
432}
05f9883a 433#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1da177e4 434#endif
7e675137
NP
435static inline int pte_special(pte_t pte) { return 0; }
436static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
1da177e4
LT
437
438/*
70342287 439 * Macro to make mark a page protection value as "uncacheable". Note
1da177e4
LT
440 * that "protection" is really a misnomer here as the protection value
441 * contains the memory attribute bits, dirty bits, and various other
442 * bits as well.
443 */
444#define pgprot_noncached pgprot_noncached
445
446static inline pgprot_t pgprot_noncached(pgprot_t _prot)
447{
448 unsigned long prot = pgprot_val(_prot);
449
450 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
451
452 return __pgprot(prot);
453}
454
c4687b15
AS
455#define pgprot_writecombine pgprot_writecombine
456
4b050ba7
MC
457static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
458{
459 unsigned long prot = pgprot_val(_prot);
460
461 /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
462 prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
463
464 return __pgprot(prot);
465}
466
1da177e4
LT
467/*
468 * Conversion functions: convert a page and protection to a page entry,
469 * and a page entry and page directory to the page they refer to.
470 */
471#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
472
7b2cb64f 473#if defined(CONFIG_XPA)
1da177e4
LT
474static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
475{
c5b36783 476 pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
77a5c593 477 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
c5b36783
SH
478 pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
479 pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
1da177e4
LT
480 return pte;
481}
7b2cb64f
PB
482#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
483static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
484{
485 pte.pte_low &= _PAGE_CHG_MASK;
486 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
487 pte.pte_low |= pgprot_val(newprot);
488 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
489 return pte;
490}
1da177e4
LT
491#else
492static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
493{
494 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
495}
496#endif
497
498
499extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
500 pte_t pte);
1da177e4
LT
501
502static inline void update_mmu_cache(struct vm_area_struct *vma,
4b3073e1 503 unsigned long address, pte_t *ptep)
1da177e4 504{
4b3073e1 505 pte_t pte = *ptep;
1da177e4 506 __update_tlb(vma, address, pte);
1da177e4
LT
507}
508
970d032f
RB
509static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
510 unsigned long address, pmd_t *pmdp)
511{
512 pte_t pte = *(pte_t *)pmdp;
513
514 __update_tlb(vma, address, pte);
515}
516
1da177e4 517#define kern_addr_valid(addr) (1)
1da177e4 518
34adb28d 519#ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4
LT
520extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
521
1da177e4
LT
522static inline int io_remap_pfn_range(struct vm_area_struct *vma,
523 unsigned long vaddr,
524 unsigned long pfn,
525 unsigned long size,
526 pgprot_t prot)
527{
15d45cce 528 phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
ac5d8c02 529 return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
1da177e4 530}
40d158e6 531#define io_remap_pfn_range io_remap_pfn_range
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532#endif
533
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534#ifdef CONFIG_TRANSPARENT_HUGEPAGE
535
536extern int has_transparent_hugepage(void);
537
538static inline int pmd_trans_huge(pmd_t pmd)
539{
540 return !!(pmd_val(pmd) & _PAGE_HUGE);
541}
542
543static inline pmd_t pmd_mkhuge(pmd_t pmd)
544{
545 pmd_val(pmd) |= _PAGE_HUGE;
546
547 return pmd;
548}
549
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550extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
551 pmd_t *pmdp, pmd_t pmd);
552
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553#define __HAVE_ARCH_PMD_WRITE
554static inline int pmd_write(pmd_t pmd)
555{
556 return !!(pmd_val(pmd) & _PAGE_WRITE);
557}
558
559static inline pmd_t pmd_wrprotect(pmd_t pmd)
560{
561 pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
562 return pmd;
563}
564
565static inline pmd_t pmd_mkwrite(pmd_t pmd)
566{
567 pmd_val(pmd) |= _PAGE_WRITE;
568 if (pmd_val(pmd) & _PAGE_MODIFIED)
569 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
570
571 return pmd;
572}
573
574static inline int pmd_dirty(pmd_t pmd)
575{
576 return !!(pmd_val(pmd) & _PAGE_MODIFIED);
577}
578
579static inline pmd_t pmd_mkclean(pmd_t pmd)
580{
581 pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
582 return pmd;
583}
584
585static inline pmd_t pmd_mkdirty(pmd_t pmd)
586{
587 pmd_val(pmd) |= _PAGE_MODIFIED;
588 if (pmd_val(pmd) & _PAGE_WRITE)
589 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
590
591 return pmd;
592}
593
594static inline int pmd_young(pmd_t pmd)
595{
596 return !!(pmd_val(pmd) & _PAGE_ACCESSED);
597}
598
599static inline pmd_t pmd_mkold(pmd_t pmd)
600{
601 pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
602
603 return pmd;
604}
605
606static inline pmd_t pmd_mkyoung(pmd_t pmd)
607{
608 pmd_val(pmd) |= _PAGE_ACCESSED;
609
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610 if (!(pmd_val(pmd) & _PAGE_NO_READ))
611 pmd_val(pmd) |= _PAGE_SILENT_READ;
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612
613 return pmd;
614}
615
616/* Extern to avoid header file madness */
617extern pmd_t mk_pmd(struct page *page, pgprot_t prot);
618
619static inline unsigned long pmd_pfn(pmd_t pmd)
620{
621 return pmd_val(pmd) >> _PFN_SHIFT;
622}
623
624static inline struct page *pmd_page(pmd_t pmd)
625{
626 if (pmd_trans_huge(pmd))
627 return pfn_to_page(pmd_pfn(pmd));
628
629 return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
630}
631
632static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
633{
634 pmd_val(pmd) = (pmd_val(pmd) & _PAGE_CHG_MASK) | pgprot_val(newprot);
635 return pmd;
636}
637
638static inline pmd_t pmd_mknotpresent(pmd_t pmd)
639{
640 pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
641
642 return pmd;
643}
644
645/*
8809aa2d 646 * The generic version pmdp_huge_get_and_clear uses a version of pmd_clear() with a
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647 * different prototype.
648 */
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649#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
650static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
651 unsigned long address, pmd_t *pmdp)
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652{
653 pmd_t old = *pmdp;
654
655 pmd_clear(pmdp);
656
657 return old;
658}
659
660#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
661
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662#include <asm-generic/pgtable.h>
663
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664/*
665 * uncached accelerated TLB map for video memory access
666 */
667#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
668#define __HAVE_PHYS_MEM_ACCESS_PROT
669
670struct file;
671pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
672 unsigned long size, pgprot_t vma_prot);
673int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
674 unsigned long size, pgprot_t *vma_prot);
675#endif
676
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677/*
678 * We provide our own get_unmapped area to cope with the virtual aliasing
679 * constraints placed on us by the cache architecture.
680 */
681#define HAVE_ARCH_UNMAPPED_AREA
d0be89f6 682#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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683
684/*
685 * No page table caches to initialise
686 */
687#define pgtable_cache_init() do { } while (0)
688
689#endif /* _ASM_PGTABLE_H */
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