[deliverable/linux.git] / arch / mips / kernel / genex.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2001 MIPS Technologies, Inc.
 * Copyright (C) 2002 Maciej W. Rozycki
 */
#include <linux/init.h>

#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/irqflags.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/war.h>
#include <asm/page.h>

#define PANIC_PIC(msg)					\
		.set push;				\
		.set	reorder;			\
		PTR_LA	a0,8f;				\
		.set	noat;				\
		PTR_LA	AT, panic;			\
		jr	AT;				\
9:		b	9b;				\
		.set	pop;				\
		TEXT(msg)

	__INIT

NESTED(except_vec0_generic, 0, sp)
	PANIC_PIC("Exception vector 0 called")
	END(except_vec0_generic)

NESTED(except_vec1_generic, 0, sp)
	PANIC_PIC("Exception vector 1 called")
	END(except_vec1_generic)

/*
 * General exception vector for all other CPUs.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_generic, 0, sp)
	.set	push
	.set	noat
#if R5432_CP0_INTERRUPT_WAR
	mfc0	k0, CP0_INDEX
#endif
	mfc0	k1, CP0_CAUSE
	andi	k1, k1, 0x7c
#ifdef CONFIG_64BIT
	dsll	k1, k1, 1
#endif
	PTR_L	k0, exception_handlers(k1)
	jr	k0
	.set	pop
	END(except_vec3_generic)

/*
 * General exception handler for CPUs with virtual coherency exception.
 *
 * Be careful when changing this, it has to be at most 256 (as a special
 * exception) bytes to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_r4000, 0, sp)
	.set	push
	.set	mips3
	.set	noat
	mfc0	k1, CP0_CAUSE
	li	k0, 31<<2
	andi	k1, k1, 0x7c
	.set	push
	.set	noreorder
	.set	nomacro
	beq	k1, k0, handle_vced
	 li	k0, 14<<2
	beq	k1, k0, handle_vcei
#ifdef CONFIG_64BIT
	 dsll	k1, k1, 1
#endif
	.set	pop
	PTR_L	k0, exception_handlers(k1)
	jr	k0

	/*
	 * Big shit, we now may have two dirty primary cache lines for the same
	 * physical address.  We can safely invalidate the line pointed to by
	 * c0_badvaddr because after return from this exception handler the
	 * load / store will be re-executed.
	 */
handle_vced:
	MFC0	k0, CP0_BADVADDR
	li	k1, -4					# Is this ...
	and	k0, k1					# ... really needed?
	mtc0	zero, CP0_TAGLO
	cache	Index_Store_Tag_D, (k0)
	cache	Hit_Writeback_Inv_SD, (k0)
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vced_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret

handle_vcei:
	MFC0	k0, CP0_BADVADDR
	cache	Hit_Writeback_Inv_SD, (k0)		# also cleans pi
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vcei_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret
	.set	pop
	END(except_vec3_r4000)

	__FINIT

	.align  5
NESTED(handle_int, PT_SIZE, sp)
#ifdef CONFIG_TRACE_IRQFLAGS
	/*
	 * Check to see if the interrupted code has just disabled
	 * interrupts and ignore this interrupt for now if so.
	 *
	 * local_irq_disable() disables interrupts and then calls
	 * trace_hardirqs_off() to track the state. If an interrupt is taken
	 * after interrupts are disabled but before the state is updated
	 * it will appear to restore_all that it is incorrectly returning with
	 * interrupts disabled
	 */
	.set	push
	.set	noat
	mfc0	k0, CP0_STATUS
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
	and	k0, ST0_IEP
	bnez	k0, 1f

	mfc0	k0, CP0_EPC
	.set	noreorder
	j	k0
	rfe
#else
	and	k0, ST0_IE
	bnez	k0, 1f

	eret
#endif
1:
	.set pop
#endif
	SAVE_ALL
	CLI
	TRACE_IRQS_OFF

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)
	PTR_LA	ra, ret_from_irq
	j	plat_irq_dispatch
	END(handle_int)

	__INIT

/*
 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
 * This is a dedicated interrupt exception vector which reduces the
 * interrupt processing overhead.  The jump instruction will be replaced
 * at the initialization time.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec4, 0, sp)
1:	j	1b			/* Dummy, will be replaced */
	END(except_vec4)

/*
 * EJTAG debug exception handler.
 * The EJTAG debug exception entry point is 0xbfc00480, which
 * normally is in the boot PROM, so the boot PROM must do a
 * unconditional jump to this vector.
 */
NESTED(except_vec_ejtag_debug, 0, sp)
	j	ejtag_debug_handler
	END(except_vec_ejtag_debug)

	__FINIT

/*
 * Vectored interrupt handler.
 * This prototype is copied to ebase + n*IntCtl.VS and patched
 * to invoke the handler
 */
NESTED(except_vec_vi, 0, sp)
	SAVE_SOME
	SAVE_AT
	.set	push
	.set	noreorder
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * To keep from blindly blocking *all* interrupts
	 * during service by SMTC kernel, we also want to
	 * pass the IM value to be cleared.
	 */
FEXPORT(except_vec_vi_mori)
	ori	a0, $0, 0
#endif /* CONFIG_MIPS_MT_SMTC */
FEXPORT(except_vec_vi_lui)
	lui	v0, 0		/* Patched */
	j	except_vec_vi_handler
FEXPORT(except_vec_vi_ori)
	 ori	v0, 0		/* Patched */
	.set	pop
	END(except_vec_vi)
EXPORT(except_vec_vi_end)

/*
 * Common Vectored Interrupt code
 * Complete the register saves and invoke the handler which is passed in $v0
 */
NESTED(except_vec_vi_handler, 0, sp)
	SAVE_TEMP
	SAVE_STATIC
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * SMTC has an interesting problem that interrupts are level-triggered,
	 * and the CLI macro will clear EXL, potentially causing a duplicate
	 * interrupt service invocation. So we need to clear the associated
	 * IM bit of Status prior to doing CLI, and restore it after the
	 * service routine has been invoked - we must assume that the
	 * service routine will have cleared the state, and any active
	 * level represents a new or otherwised unserviced event...
	 */
	mfc0	t1, CP0_STATUS
	and	t0, a0, t1
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
	mfc0	t2, CP0_TCCONTEXT
	or	t0, t0, t2
	mtc0	t0, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
	xor	t1, t1, t0
	mtc0	t1, CP0_STATUS
	_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
	CLI
#ifdef CONFIG_TRACE_IRQFLAGS
	move	s0, v0
#ifdef CONFIG_MIPS_MT_SMTC
	move	s1, a0
#endif
	TRACE_IRQS_OFF
#ifdef CONFIG_MIPS_MT_SMTC
	move	a0, s1
#endif
	move	v0, s0
#endif

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)
	PTR_LA	ra, ret_from_irq
	jr	v0
	END(except_vec_vi_handler)

/*
 * EJTAG debug exception handler.
 */
NESTED(ejtag_debug_handler, PT_SIZE, sp)
	.set	push
	.set	noat
	MTC0	k0, CP0_DESAVE
	mfc0	k0, CP0_DEBUG

	sll	k0, k0, 30	# Check for SDBBP.
	bgez	k0, ejtag_return

	PTR_LA	k0, ejtag_debug_buffer
	LONG_S	k1, 0(k0)
	SAVE_ALL
	move	a0, sp
	jal	ejtag_exception_handler
	RESTORE_ALL
	PTR_LA	k0, ejtag_debug_buffer
	LONG_L	k1, 0(k0)

ejtag_return:
	MFC0	k0, CP0_DESAVE
	.set	mips32
	deret
	.set pop
	END(ejtag_debug_handler)

/*
 * This buffer is reserved for the use of the EJTAG debug
 * handler.
 */
	.data
EXPORT(ejtag_debug_buffer)
	.fill	LONGSIZE
	.previous

	__INIT

/*
 * NMI debug exception handler for MIPS reference boards.
 * The NMI debug exception entry point is 0xbfc00000, which
 * normally is in the boot PROM, so the boot PROM must do a
 * unconditional jump to this vector.
 */
NESTED(except_vec_nmi, 0, sp)
	j	nmi_handler
	END(except_vec_nmi)

	__FINIT

NESTED(nmi_handler, PT_SIZE, sp)
	.set	push
	.set	noat
	SAVE_ALL
 	move	a0, sp
	jal	nmi_exception_handler
	RESTORE_ALL
	.set	mips3
	eret
	.set	pop
	END(nmi_handler)

	.macro	__build_clear_none
	.endm

	.macro	__build_clear_sti
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__build_clear_cli
	CLI
	TRACE_IRQS_OFF
	.endm

	.macro	__build_clear_fpe
	cfc1	a1, fcr31
	li	a2, ~(0x3f << 12)
	and	a2, a1
	ctc1	a2, fcr31
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__build_clear_ade
	MFC0	t0, CP0_BADVADDR
	PTR_S	t0, PT_BVADDR(sp)
	KMODE
	.endm

	.macro	__BUILD_silent exception
	.endm

	/* Gas tries to parse the PRINT argument as a string containing
	   string escapes and emits bogus warnings if it believes to
	   recognize an unknown escape code.  So make the arguments
	   start with an n and gas will believe \n is ok ...  */
	.macro	__BUILD_verbose	nexception
	LONG_L	a1, PT_EPC(sp)
#ifdef CONFIG_32BIT
	PRINT("Got \nexception at %08lx\012")
#endif
#ifdef CONFIG_64BIT
	PRINT("Got \nexception at %016lx\012")
#endif
	.endm

	.macro	__BUILD_count exception
	LONG_L	t0,exception_count_\exception
	LONG_ADDIU t0, 1
	LONG_S	t0,exception_count_\exception
	.comm	exception_count\exception, 8, 8
	.endm

	.macro	__BUILD_HANDLER exception handler clear verbose ext
	.align	5
	NESTED(handle_\exception, PT_SIZE, sp)
	.set	noat
	SAVE_ALL
	FEXPORT(handle_\exception\ext)
	__BUILD_clear_\clear
	.set	at
	__BUILD_\verbose \exception
	move	a0, sp
	PTR_LA	ra, ret_from_exception
	j	do_\handler
	END(handle_\exception)
	.endm

	.macro	BUILD_HANDLER exception handler clear verbose
	__BUILD_HANDLER	\exception \handler \clear \verbose _int
	.endm

	BUILD_HANDLER adel ade ade silent		/* #4  */
	BUILD_HANDLER ades ade ade silent		/* #5  */
	BUILD_HANDLER ibe be cli silent			/* #6  */
	BUILD_HANDLER dbe be cli silent			/* #7  */
	BUILD_HANDLER bp bp sti silent			/* #9  */
	BUILD_HANDLER ri ri sti silent			/* #10 */
	BUILD_HANDLER cpu cpu sti silent		/* #11 */
	BUILD_HANDLER ov ov sti silent			/* #12 */
	BUILD_HANDLER tr tr sti silent			/* #13 */
	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */
	BUILD_HANDLER watch watch sti verbose		/* #23 */
	BUILD_HANDLER mcheck mcheck cli verbose		/* #24 */
	BUILD_HANDLER mt mt sti silent			/* #25 */
	BUILD_HANDLER dsp dsp sti silent		/* #26 */
	BUILD_HANDLER reserved reserved sti verbose	/* others */

	.align	5
	LEAF(handle_ri_rdhwr_vivt)
#ifdef CONFIG_MIPS_MT_SMTC
	PANIC_PIC("handle_ri_rdhwr_vivt called")
#else
	.set	push
	.set	noat
	.set	noreorder
	/* check if TLB contains a entry for EPC */
	MFC0	k1, CP0_ENTRYHI
	andi	k1, 0xff	/* ASID_MASK */
	MFC0	k0, CP0_EPC
	PTR_SRL	k0, PAGE_SHIFT + 1
	PTR_SLL	k0, PAGE_SHIFT + 1
	or	k1, k0
	MTC0	k1, CP0_ENTRYHI
	mtc0_tlbw_hazard
	tlbp
	tlb_probe_hazard
	mfc0	k1, CP0_INDEX
	.set	pop
	bltz	k1, handle_ri	/* slow path */
	/* fall thru */
#endif
	END(handle_ri_rdhwr_vivt)

	LEAF(handle_ri_rdhwr)
	.set	push
	.set	noat
	.set	noreorder
	/* 0x7c03e83b: rdhwr v1,$29 */
	MFC0	k1, CP0_EPC
	lui	k0, 0x7c03
	lw	k1, (k1)
	ori	k0, 0xe83b
	.set	reorder
	bne	k0, k1, handle_ri	/* if not ours */
	/* The insn is rdhwr.  No need to check CAUSE.BD here. */
	get_saved_sp	/* k1 := current_thread_info */
	.set	noreorder
	MFC0	k0, CP0_EPC
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	LONG_ADDIU	k0, 4
	jr	k0
	 rfe
#else
	LONG_ADDIU	k0, 4		/* stall on $k0 */
	MTC0	k0, CP0_EPC
	/* I hope three instructions between MTC0 and ERET are enough... */
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	.set	mips3
	eret
	.set	mips0
#endif
	.set	pop
	END(handle_ri_rdhwr)

#ifdef CONFIG_64BIT
/* A temporary overflow handler used by check_daddi(). */

	__INIT

	BUILD_HANDLER  daddi_ov daddi_ov none silent	/* #12 */
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	8	* Copyright (C) 2001 MIPS Technologies, Inc.
	9	* Copyright (C) 2002 Maciej W. Rozycki
	10	*/
1da177e4 LT	11	#include <linux/init.h>
	12
	13	#include <asm/asm.h>
41c594ab	14	#include <asm/asmmacro.h>
1da177e4	15	#include <asm/cacheops.h>
192ef366	16	#include <asm/irqflags.h>
1da177e4 LT	17	#include <asm/regdef.h>
	18	#include <asm/fpregdef.h>
	19	#include <asm/mipsregs.h>
	20	#include <asm/stackframe.h>
	21	#include <asm/war.h>
5b10496b	22	#include <asm/page.h>
1da177e4 LT	23
	24	#define PANIC_PIC(msg) \
	25	.set push; \
	26	.set reorder; \
	27	PTR_LA a0,8f; \
	28	.set noat; \
	29	PTR_LA AT, panic; \
	30	jr AT; \
	31	9: b 9b; \
	32	.set pop; \
	33	TEXT(msg)
	34
	35	__INIT
	36
	37	NESTED(except_vec0_generic, 0, sp)
	38	PANIC_PIC("Exception vector 0 called")
	39	END(except_vec0_generic)
	40
	41	NESTED(except_vec1_generic, 0, sp)
	42	PANIC_PIC("Exception vector 1 called")
	43	END(except_vec1_generic)
	44
	45	/*
	46	* General exception vector for all other CPUs.
	47	*
	48	* Be careful when changing this, it has to be at most 128 bytes
	49	* to fit into space reserved for the exception handler.
	50	*/
	51	NESTED(except_vec3_generic, 0, sp)
	52	.set push
	53	.set noat
	54	#if R5432_CP0_INTERRUPT_WAR
	55	mfc0 k0, CP0_INDEX
	56	#endif
	57	mfc0 k1, CP0_CAUSE
	58	andi k1, k1, 0x7c
875d43e7	59	#ifdef CONFIG_64BIT
1da177e4 LT	60	dsll k1, k1, 1
	61	#endif
	62	PTR_L k0, exception_handlers(k1)
	63	jr k0
	64	.set pop
	65	END(except_vec3_generic)
	66
	67	/*
	68	* General exception handler for CPUs with virtual coherency exception.
	69	*
	70	* Be careful when changing this, it has to be at most 256 (as a special
	71	* exception) bytes to fit into space reserved for the exception handler.
	72	*/
	73	NESTED(except_vec3_r4000, 0, sp)
	74	.set push
	75	.set mips3
	76	.set noat
	77	mfc0 k1, CP0_CAUSE
	78	li k0, 31<<2
	79	andi k1, k1, 0x7c
	80	.set push
	81	.set noreorder
	82	.set nomacro
	83	beq k1, k0, handle_vced
	84	li k0, 14<<2
	85	beq k1, k0, handle_vcei
875d43e7	86	#ifdef CONFIG_64BIT
69903d65	87	dsll k1, k1, 1
1da177e4 LT	88	#endif
	89	.set pop
	90	PTR_L k0, exception_handlers(k1)
	91	jr k0
	92
	93	/*
	94	* Big shit, we now may have two dirty primary cache lines for the same
69903d65	95	* physical address. We can safely invalidate the line pointed to by
1da177e4 LT	96	* c0_badvaddr because after return from this exception handler the
	97	* load / store will be re-executed.
	98	*/
	99	handle_vced:
69903d65	100	MFC0 k0, CP0_BADVADDR
1da177e4 LT	101	li k1, -4 # Is this ...
	102	and k0, k1 # ... really needed?
	103	mtc0 zero, CP0_TAGLO
69903d65 TS	104	cache Index_Store_Tag_D, (k0)
69903d65 TS	105	cache Hit_Writeback_Inv_SD, (k0)
1da177e4 LT	106	#ifdef CONFIG_PROC_FS
	107	PTR_LA k0, vced_count
	108	lw k1, (k0)
	109	addiu k1, 1
	110	sw k1, (k0)
	111	#endif
	112	eret
	113
	114	handle_vcei:
	115	MFC0 k0, CP0_BADVADDR
	116	cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
	117	#ifdef CONFIG_PROC_FS
	118	PTR_LA k0, vcei_count
	119	lw k1, (k0)
	120	addiu k1, 1
	121	sw k1, (k0)
	122	#endif
	123	eret
	124	.set pop
	125	END(except_vec3_r4000)
	126
e4ac58af RB	127	__FINIT
	128
	129	.align 5
	130	NESTED(handle_int, PT_SIZE, sp)
fe99f1b1 CD	131	#ifdef CONFIG_TRACE_IRQFLAGS
	132	/*
	133	* Check to see if the interrupted code has just disabled
	134	* interrupts and ignore this interrupt for now if so.
	135	*
	136	* local_irq_disable() disables interrupts and then calls
	137	* trace_hardirqs_off() to track the state. If an interrupt is taken
	138	* after interrupts are disabled but before the state is updated
	139	* it will appear to restore_all that it is incorrectly returning with
	140	* interrupts disabled
	141	*/
	142	.set push
	143	.set noat
	144	mfc0 k0, CP0_STATUS
	145	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	146	and k0, ST0_IEP
	147	bnez k0, 1f
	148
c6563e85	149	mfc0 k0, CP0_EPC
fe99f1b1 CD	150	.set noreorder
	151	j k0
	152	rfe
	153	#else
	154	and k0, ST0_IE
	155	bnez k0, 1f
	156
	157	eret
	158	#endif
	159	1:
	160	.set pop
	161	#endif
e4ac58af RB	162	SAVE_ALL
e4ac58af RB	163	CLI
192ef366	164	TRACE_IRQS_OFF
e4ac58af	165
937a8015 RB	166	LONG_L s0, TI_REGS($28)
937a8015 RB	167	LONG_S sp, TI_REGS($28)
f431baa5 AN	168	PTR_LA ra, ret_from_irq
f431baa5 AN	169	j plat_irq_dispatch
e4ac58af RB	170	END(handle_int)
	171
	172	__INIT
	173
1da177e4 LT	174	/*
	175	* Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
	176	* This is a dedicated interrupt exception vector which reduces the
	177	* interrupt processing overhead. The jump instruction will be replaced
	178	* at the initialization time.
	179	*
	180	* Be careful when changing this, it has to be at most 128 bytes
	181	* to fit into space reserved for the exception handler.
	182	*/
	183	NESTED(except_vec4, 0, sp)
	184	1: j 1b /* Dummy, will be replaced */
	185	END(except_vec4)
	186
	187	/*
	188	* EJTAG debug exception handler.
	189	* The EJTAG debug exception entry point is 0xbfc00480, which
	190	* normally is in the boot PROM, so the boot PROM must do a
	191	* unconditional jump to this vector.
	192	*/
	193	NESTED(except_vec_ejtag_debug, 0, sp)
	194	j ejtag_debug_handler
	195	END(except_vec_ejtag_debug)
	196
	197	__FINIT
	198
e01402b1 RB	199	/*
	200	* Vectored interrupt handler.
	201	* This prototype is copied to ebase + n*IntCtl.VS and patched
	202	* to invoke the handler
	203	*/
	204	NESTED(except_vec_vi, 0, sp)
	205	SAVE_SOME
	206	SAVE_AT
	207	.set push
	208	.set noreorder
41c594ab RB	209	#ifdef CONFIG_MIPS_MT_SMTC
	210	/*
	211	* To keep from blindly blocking all interrupts
	212	* during service by SMTC kernel, we also want to
	213	* pass the IM value to be cleared.
	214	*/
7df42461	215	FEXPORT(except_vec_vi_mori)
41c594ab RB	216	ori a0, $0, 0
41c594ab RB	217	#endif /* CONFIG_MIPS_MT_SMTC */
7df42461	218	FEXPORT(except_vec_vi_lui)
e01402b1 RB	219	lui v0, 0 /* Patched */
e01402b1 RB	220	j except_vec_vi_handler
7df42461	221	FEXPORT(except_vec_vi_ori)
e01402b1 RB	222	ori v0, 0 /* Patched */
	223	.set pop
	224	END(except_vec_vi)
	225	EXPORT(except_vec_vi_end)
	226
	227	/*
	228	* Common Vectored Interrupt code
	229	* Complete the register saves and invoke the handler which is passed in $v0
	230	*/
	231	NESTED(except_vec_vi_handler, 0, sp)
	232	SAVE_TEMP
	233	SAVE_STATIC
41c594ab RB	234	#ifdef CONFIG_MIPS_MT_SMTC
	235	/*
	236	* SMTC has an interesting problem that interrupts are level-triggered,
	237	* and the CLI macro will clear EXL, potentially causing a duplicate
	238	* interrupt service invocation. So we need to clear the associated
	239	* IM bit of Status prior to doing CLI, and restore it after the
	240	* service routine has been invoked - we must assume that the
	241	* service routine will have cleared the state, and any active
	242	* level represents a new or otherwised unserviced event...
	243	*/
	244	mfc0 t1, CP0_STATUS
	245	and t0, a0, t1
0db34215	246	#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
41c594ab RB	247	mfc0 t2, CP0_TCCONTEXT
	248	or t0, t0, t2
	249	mtc0 t0, CP0_TCCONTEXT
0db34215	250	#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
41c594ab RB	251	xor t1, t1, t0
41c594ab RB	252	mtc0 t1, CP0_STATUS
4277ff5e	253	_ehb
41c594ab	254	#endif /* CONFIG_MIPS_MT_SMTC */
e01402b1	255	CLI
8c364435 RB	256	#ifdef CONFIG_TRACE_IRQFLAGS
	257	move s0, v0
	258	#ifdef CONFIG_MIPS_MT_SMTC
	259	move s1, a0
	260	#endif
192ef366	261	TRACE_IRQS_OFF
8c364435 RB	262	#ifdef CONFIG_MIPS_MT_SMTC
	263	move a0, s1
	264	#endif
	265	move v0, s0
	266	#endif
937a8015 RB	267
	268	LONG_L s0, TI_REGS($28)
	269	LONG_S sp, TI_REGS($28)
23126692	270	PTR_LA ra, ret_from_irq
f431baa5	271	jr v0
e01402b1 RB	272	END(except_vec_vi_handler)
e01402b1 RB	273
1da177e4 LT	274	/*
	275	* EJTAG debug exception handler.
	276	*/
	277	NESTED(ejtag_debug_handler, PT_SIZE, sp)
	278	.set push
	279	.set noat
	280	MTC0 k0, CP0_DESAVE
	281	mfc0 k0, CP0_DEBUG
	282
	283	sll k0, k0, 30 # Check for SDBBP.
	284	bgez k0, ejtag_return
	285
	286	PTR_LA k0, ejtag_debug_buffer
	287	LONG_S k1, 0(k0)
	288	SAVE_ALL
	289	move a0, sp
	290	jal ejtag_exception_handler
	291	RESTORE_ALL
	292	PTR_LA k0, ejtag_debug_buffer
	293	LONG_L k1, 0(k0)
	294
	295	ejtag_return:
	296	MFC0 k0, CP0_DESAVE
	297	.set mips32
	298	deret
	299	.set pop
	300	END(ejtag_debug_handler)
	301
	302	/*
	303	* This buffer is reserved for the use of the EJTAG debug
	304	* handler.
	305	*/
	306	.data
	307	EXPORT(ejtag_debug_buffer)
	308	.fill LONGSIZE
	309	.previous
	310
	311	__INIT
	312
	313	/*
	314	* NMI debug exception handler for MIPS reference boards.
	315	* The NMI debug exception entry point is 0xbfc00000, which
	316	* normally is in the boot PROM, so the boot PROM must do a
	317	* unconditional jump to this vector.
	318	*/
	319	NESTED(except_vec_nmi, 0, sp)
	320	j nmi_handler
	321	END(except_vec_nmi)
	322
	323	__FINIT
	324
	325	NESTED(nmi_handler, PT_SIZE, sp)
	326	.set push
	327	.set noat
1da177e4 LT	328	SAVE_ALL
	329	move a0, sp
	330	jal nmi_exception_handler
	331	RESTORE_ALL
4f0638ba	332	.set mips3
1da177e4 LT	333	eret
	334	.set pop
	335	END(nmi_handler)
	336
	337	.macro __build_clear_none
	338	.endm
	339
	340	.macro __build_clear_sti
192ef366	341	TRACE_IRQS_ON
1da177e4 LT	342	STI
	343	.endm
	344
	345	.macro __build_clear_cli
	346	CLI
192ef366	347	TRACE_IRQS_OFF
1da177e4 LT	348	.endm
	349
	350	.macro __build_clear_fpe
	351	cfc1 a1, fcr31
	352	li a2, ~(0x3f << 12)
	353	and a2, a1
	354	ctc1 a2, fcr31
192ef366	355	TRACE_IRQS_ON
1da177e4 LT	356	STI
	357	.endm
	358
	359	.macro __build_clear_ade
	360	MFC0 t0, CP0_BADVADDR
	361	PTR_S t0, PT_BVADDR(sp)
	362	KMODE
	363	.endm
	364
	365	.macro __BUILD_silent exception
	366	.endm
	367
	368	/* Gas tries to parse the PRINT argument as a string containing
	369	string escapes and emits bogus warnings if it believes to
	370	recognize an unknown escape code. So make the arguments
	371	start with an n and gas will believe \n is ok ... */
	372	.macro __BUILD_verbose nexception
	373	LONG_L a1, PT_EPC(sp)
766160c2	374	#ifdef CONFIG_32BIT
1da177e4	375	PRINT("Got \nexception at %08lx\012")
42a3b4f2	376	#endif
766160c2	377	#ifdef CONFIG_64BIT
1da177e4	378	PRINT("Got \nexception at %016lx\012")
42a3b4f2	379	#endif
1da177e4 LT	380	.endm
	381
	382	.macro __BUILD_count exception
	383	LONG_L t0,exception_count_\exception
	384	LONG_ADDIU t0, 1
	385	LONG_S t0,exception_count_\exception
	386	.comm exception_count\exception, 8, 8
	387	.endm
	388
	389	.macro __BUILD_HANDLER exception handler clear verbose ext
	390	.align 5
	391	NESTED(handle_\exception, PT_SIZE, sp)
	392	.set noat
	393	SAVE_ALL
	394	FEXPORT(handle_\exception\ext)
	395	__BUILD_clear_\clear
	396	.set at
	397	__BUILD_\verbose \exception
	398	move a0, sp
23126692 AN	399	PTR_LA ra, ret_from_exception
23126692 AN	400	j do_\handler
1da177e4 LT	401	END(handle_\exception)
	402	.endm
	403
	404	.macro BUILD_HANDLER exception handler clear verbose
	405	__BUILD_HANDLER \exception \handler \clear \verbose _int
	406	.endm
	407
	408	BUILD_HANDLER adel ade ade silent /* #4 */
	409	BUILD_HANDLER ades ade ade silent /* #5 */
	410	BUILD_HANDLER ibe be cli silent /* #6 */
	411	BUILD_HANDLER dbe be cli silent /* #7 */
	412	BUILD_HANDLER bp bp sti silent /* #9 */
	413	BUILD_HANDLER ri ri sti silent /* #10 */
	414	BUILD_HANDLER cpu cpu sti silent /* #11 */
	415	BUILD_HANDLER ov ov sti silent /* #12 */
	416	BUILD_HANDLER tr tr sti silent /* #13 */
	417	BUILD_HANDLER fpe fpe fpe silent /* #15 */
	418	BUILD_HANDLER mdmx mdmx sti silent /* #22 */
	419	BUILD_HANDLER watch watch sti verbose /* #23 */
	420	BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
e35a5e35	421	BUILD_HANDLER mt mt sti silent /* #25 */
e50c0a8f	422	BUILD_HANDLER dsp dsp sti silent /* #26 */
1da177e4 LT	423	BUILD_HANDLER reserved reserved sti verbose /* others */
1da177e4 LT	424
5b10496b AN	425	.align 5
	426	LEAF(handle_ri_rdhwr_vivt)
	427	#ifdef CONFIG_MIPS_MT_SMTC
	428	PANIC_PIC("handle_ri_rdhwr_vivt called")
	429	#else
	430	.set push
	431	.set noat
	432	.set noreorder
	433	/* check if TLB contains a entry for EPC */
	434	MFC0 k1, CP0_ENTRYHI
	435	andi k1, 0xff /* ASID_MASK */
	436	MFC0 k0, CP0_EPC
	437	PTR_SRL k0, PAGE_SHIFT + 1
	438	PTR_SLL k0, PAGE_SHIFT + 1
	439	or k1, k0
	440	MTC0 k1, CP0_ENTRYHI
	441	mtc0_tlbw_hazard
	442	tlbp
	443	tlb_probe_hazard
	444	mfc0 k1, CP0_INDEX
	445	.set pop
	446	bltz k1, handle_ri /* slow path */
	447	/* fall thru */
	448	#endif
	449	END(handle_ri_rdhwr_vivt)
	450
	451	LEAF(handle_ri_rdhwr)
	452	.set push
	453	.set noat
	454	.set noreorder
	455	/* 0x7c03e83b: rdhwr v1,$29 */
	456	MFC0 k1, CP0_EPC
	457	lui k0, 0x7c03
	458	lw k1, (k1)
	459	ori k0, 0xe83b
	460	.set reorder
	461	bne k0, k1, handle_ri /* if not ours */
	462	/* The insn is rdhwr. No need to check CAUSE.BD here. */
	463	get_saved_sp /* k1 := current_thread_info */
	464	.set noreorder
	465	MFC0 k0, CP0_EPC
	466	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	467	ori k1, _THREAD_MASK
	468	xori k1, _THREAD_MASK
	469	LONG_L v1, TI_TP_VALUE(k1)
	470	LONG_ADDIU k0, 4
	471	jr k0
	472	rfe
	473	#else
	474	LONG_ADDIU k0, 4 /* stall on $k0 */
	475	MTC0 k0, CP0_EPC
	476	/* I hope three instructions between MTC0 and ERET are enough... */
	477	ori k1, _THREAD_MASK
	478	xori k1, _THREAD_MASK
	479	LONG_L v1, TI_TP_VALUE(k1)
	480	.set mips3
	481	eret
	482	.set mips0
	483	#endif
	484	.set pop
	485	END(handle_ri_rdhwr)
	486
875d43e7	487	#ifdef CONFIG_64BIT
1da177e4 LT	488	/* A temporary overflow handler used by check_daddi(). */
	489
	490	__INIT
	491
	492	BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
	493	#endif