[deliverable/linux.git] / arch / mips / kernel / smp-mt.c

/*
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
 *    Elizabeth Clarke (beth@mips.com)
 *    Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/compiler.h>
#include <linux/smp.h>

#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>

static void __init smvp_copy_vpe_config(void)
{
	write_vpe_c0_status(
		(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);

	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	write_vpe_c0_config( read_c0_config());

	/* make sure there are no software interrupts pending */
	write_vpe_c0_cause(0);

	/* Propagate Config7 */
	write_vpe_c0_config7(read_c0_config7());

	write_vpe_c0_count(read_c0_count());
}

static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
	unsigned int ncpu)
{
	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
		return ncpu;

	/* Deactivate all but VPE 0 */
	if (tc != 0) {
		unsigned long tmp = read_vpe_c0_vpeconf0();

		tmp &= ~VPECONF0_VPA;

		/* master VPE */
		tmp |= VPECONF0_MVP;
		write_vpe_c0_vpeconf0(tmp);

		/* Record this as available CPU */
		set_cpu_possible(tc, true);
		set_cpu_present(tc, true);
		__cpu_number_map[tc]	= ++ncpu;
		__cpu_logical_map[ncpu] = tc;
	}

	/* Disable multi-threading with TC's */
	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);

	if (tc != 0)
		smvp_copy_vpe_config();

	return ncpu;
}

static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
{
	unsigned long tmp;

	if (!tc)
		return;

	/* bind a TC to each VPE, May as well put all excess TC's
	   on the last VPE */
	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
		write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	else {
		write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);

		/* and set XTC */
		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
	}

	tmp = read_tc_c0_tcstatus();

	/* mark not allocated and not dynamically allocatable */
	tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
	tmp |= TCSTATUS_IXMT;		/* interrupt exempt */
	write_tc_c0_tcstatus(tmp);

	write_tc_c0_tchalt(TCHALT_H);
}

static void vsmp_send_ipi_single(int cpu, unsigned int action)
{
	int i;
	unsigned long flags;
	int vpflags;

#ifdef CONFIG_MIPS_GIC
	if (gic_present) {
		mips_smp_send_ipi_single(cpu, action);
		return;
	}
#endif
	local_irq_save(flags);

	vpflags = dvpe();	/* can't access the other CPU's registers whilst MVPE enabled */

	switch (action) {
	case SMP_CALL_FUNCTION:
		i = C_SW1;
		break;

	case SMP_RESCHEDULE_YOURSELF:
	default:
		i = C_SW0;
		break;
	}

	/* 1:1 mapping of vpe and tc... */
	settc(cpu);
	write_vpe_c0_cause(read_vpe_c0_cause() | i);
	evpe(vpflags);

	local_irq_restore(flags);
}

static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		vsmp_send_ipi_single(i, action);
}

static void vsmp_init_secondary(void)
{
#ifdef CONFIG_MIPS_GIC
	/* This is Malta specific: IPI,performance and timer interrupts */
	if (gic_present)
		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
					 STATUSF_IP4 | STATUSF_IP5 |
					 STATUSF_IP6 | STATUSF_IP7);
	else
#endif
		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
					 STATUSF_IP6 | STATUSF_IP7);
}

static void vsmp_smp_finish(void)
{
	/* CDFIXME: remove this? */
	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	local_irq_enable();
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it
 * running!
 * smp_bootstrap is the place to resume from
 * __KSTK_TOS(idle) is apparently the stack pointer
 * (unsigned long)idle->thread_info the gp
 * assumes a 1:1 mapping of TC => VPE
 */
static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
{
	struct thread_info *gp = task_thread_info(idle);
	dvpe();
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	settc(cpu);

	/* restart */
	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);

	/* enable the tc this vpe/cpu will be running */
	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);

	write_tc_c0_tchalt(0);

	/* enable the VPE */
	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);

	/* stack pointer */
	write_tc_gpr_sp( __KSTK_TOS(idle));

	/* global pointer */
	write_tc_gpr_gp((unsigned long)gp);

	flush_icache_range((unsigned long)gp,
			   (unsigned long)(gp + sizeof(struct thread_info)));

	/* finally out of configuration and into chaos */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	evpe(EVPE_ENABLE);
}

/*
 * Common setup before any secondaries are started
 * Make sure all CPU's are in a sensible state before we boot any of the
 * secondaries
 */
static void __init vsmp_smp_setup(void)
{
	unsigned int mvpconf0, ntc, tc, ncpu = 0;
	unsigned int nvpe;

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(0, &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
	if (!cpu_has_mipsmt)
		return;

	/* disable MT so we can configure */
	dvpe();
	dmt();

	/* Put MVPE's into 'configuration state' */
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	mvpconf0 = read_c0_mvpconf0();
	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;

	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	smp_num_siblings = nvpe;

	/* we'll always have more TC's than VPE's, so loop setting everything
	   to a sensible state */
	for (tc = 0; tc <= ntc; tc++) {
		settc(tc);

		smvp_tc_init(tc, mvpconf0);
		ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
	}

	/* Release config state */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	/* We'll wait until starting the secondaries before starting MVPE */

	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
}

static void __init vsmp_prepare_cpus(unsigned int max_cpus)
{
	mips_mt_set_cpuoptions();
}

struct plat_smp_ops vsmp_smp_ops = {
	.send_ipi_single	= vsmp_send_ipi_single,
	.send_ipi_mask		= vsmp_send_ipi_mask,
	.init_secondary		= vsmp_init_secondary,
	.smp_finish		= vsmp_smp_finish,
	.boot_secondary		= vsmp_boot_secondary,
	.smp_setup		= vsmp_smp_setup,
	.prepare_cpus		= vsmp_prepare_cpus,
};
Commit	Line	Data
340ee4b9	1	/*
340ee4b9 RB	2	* This program is free software; you can distribute it and/or modify it
	3	* under the terms of the GNU General Public License (Version 2) as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope it will be useful, but WITHOUT
	7	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	8	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	9	* for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License along
	12	* with this program; if not, write to the Free Software Foundation, Inc.,
	13	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	14	*
41c594ab RB	15	* Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
	16	* Elizabeth Clarke (beth@mips.com)
	17	* Ralf Baechle (ralf@linux-mips.org)
	18	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
340ee4b9 RB	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/cpumask.h>
	23	#include <linux/interrupt.h>
4060bbe9	24	#include <linux/irqchip/mips-gic.h>
340ee4b9	25	#include <linux/compiler.h>
0ab7aefc	26	#include <linux/smp.h>
340ee4b9	27
60063497	28	#include <linux/atomic.h>
41c594ab	29	#include <asm/cacheflush.h>
340ee4b9 RB	30	#include <asm/cpu.h>
340ee4b9 RB	31	#include <asm/processor.h>
340ee4b9 RB	32	#include <asm/hardirq.h>
340ee4b9 RB	33	#include <asm/mmu_context.h>
340ee4b9 RB	34	#include <asm/time.h>
	35	#include <asm/mipsregs.h>
	36	#include <asm/mipsmtregs.h>
41c594ab	37	#include <asm/mips_mt.h>
340ee4b9	38
39b8d525	39	static void __init smvp_copy_vpe_config(void)
781b0f8d RB	40	{
	41	write_vpe_c0_status(
	42	(read_c0_status() & ~(ST0_IM \| ST0_IE \| ST0_KSU)) \| ST0_CU0);
	43
	44	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	45	write_vpe_c0_config( read_c0_config());
	46
	47	/* make sure there are no software interrupts pending */
	48	write_vpe_c0_cause(0);
	49
	50	/* Propagate Config7 */
	51	write_vpe_c0_config7(read_c0_config7());
70e46f48 RB	52
70e46f48 RB	53	write_vpe_c0_count(read_c0_count());
781b0f8d RB	54	}
781b0f8d RB	55
39b8d525	56	static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
781b0f8d RB	57	unsigned int ncpu)
	58	{
	59	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
	60	return ncpu;
	61
	62	/* Deactivate all but VPE 0 */
	63	if (tc != 0) {
	64	unsigned long tmp = read_vpe_c0_vpeconf0();
	65
	66	tmp &= ~VPECONF0_VPA;
	67
	68	/* master VPE */
	69	tmp \|= VPECONF0_MVP;
	70	write_vpe_c0_vpeconf0(tmp);
	71
	72	/* Record this as available CPU */
4037ac6e	73	set_cpu_possible(tc, true);
c2c2a644	74	set_cpu_present(tc, true);
781b0f8d	75	__cpu_number_map[tc] = ++ncpu;
70342287	76	__cpu_logical_map[ncpu] = tc;
781b0f8d RB	77	}
	78
	79	/* Disable multi-threading with TC's */
	80	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
	81
	82	if (tc != 0)
39b8d525	83	smvp_copy_vpe_config();
781b0f8d RB	84
	85	return ncpu;
	86	}
	87
39b8d525	88	static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
781b0f8d RB	89	{
	90	unsigned long tmp;
	91
	92	if (!tc)
	93	return;
	94
	95	/* bind a TC to each VPE, May as well put all excess TC's
	96	on the last VPE */
	97	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
	98	write_tc_c0_tcbind(read_tc_c0_tcbind() \| ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	99	else {
	100	write_tc_c0_tcbind(read_tc_c0_tcbind() \| tc);
	101
	102	/* and set XTC */
	103	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| (tc << VPECONF0_XTC_SHIFT));
	104	}
	105
	106	tmp = read_tc_c0_tcstatus();
	107
	108	/* mark not allocated and not dynamically allocatable */
	109	tmp &= ~(TCSTATUS_A \| TCSTATUS_DA);
	110	tmp \|= TCSTATUS_IXMT; /* interrupt exempt */
	111	write_tc_c0_tcstatus(tmp);
	112
	113	write_tc_c0_tchalt(TCHALT_H);
	114	}
	115
87353d8a	116	static void vsmp_send_ipi_single(int cpu, unsigned int action)
340ee4b9	117	{
87353d8a RB	118	int i;
	119	unsigned long flags;
	120	int vpflags;
340ee4b9	121
8a19b8f1	122	#ifdef CONFIG_MIPS_GIC
5cf8b240	123	if (gic_present) {
bb11cff3	124	mips_smp_send_ipi_single(cpu, action);
5cf8b240 SH	125	return;
	126	}
	127	#endif
87353d8a	128	local_irq_save(flags);
340ee4b9	129
25985edc	130	vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
340ee4b9	131
87353d8a RB	132	switch (action) {
	133	case SMP_CALL_FUNCTION:
	134	i = C_SW1;
	135	break;
340ee4b9	136
87353d8a RB	137	case SMP_RESCHEDULE_YOURSELF:
	138	default:
	139	i = C_SW0;
	140	break;
	141	}
340ee4b9	142
87353d8a RB	143	/* 1:1 mapping of vpe and tc... */
	144	settc(cpu);
	145	write_vpe_c0_cause(read_vpe_c0_cause() \| i);
	146	evpe(vpflags);
0ab7aefc	147
87353d8a RB	148	local_irq_restore(flags);
87353d8a RB	149	}
340ee4b9	150
48a048fe	151	static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
87353d8a RB	152	{
87353d8a RB	153	unsigned int i;
340ee4b9	154
48a048fe	155	for_each_cpu(i, mask)
87353d8a RB	156	vsmp_send_ipi_single(i, action);
87353d8a RB	157	}
340ee4b9	158
078a55fc	159	static void vsmp_init_secondary(void)
87353d8a	160	{
8a19b8f1	161	#ifdef CONFIG_MIPS_GIC
d002aaad	162	/* This is Malta specific: IPI,performance and timer interrupts */
39b8d525	163	if (gic_present)
c3f134fb JH	164	change_c0_status(ST0_IM, STATUSF_IP2 \| STATUSF_IP3 \|
c3f134fb JH	165	STATUSF_IP4 \| STATUSF_IP5 \|
39b8d525 RB	166	STATUSF_IP6 \| STATUSF_IP7);
39b8d525 RB	167	else
1c599242	168	#endif
39b8d525 RB	169	change_c0_status(ST0_IM, STATUSF_IP0 \| STATUSF_IP1 \|
39b8d525 RB	170	STATUSF_IP6 \| STATUSF_IP7);
41c594ab	171	}
340ee4b9	172
078a55fc	173	static void vsmp_smp_finish(void)
41c594ab	174	{
39b8d525	175	/* CDFIXME: remove this? */
87353d8a	176	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
340ee4b9	177
87353d8a RB	178	#ifdef CONFIG_MIPS_MT_FPAFF
	179	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	180	if (cpu_has_fpu)
8dd92891	181	cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
87353d8a	182	#endif /* CONFIG_MIPS_MT_FPAFF */
340ee4b9	183
87353d8a RB	184	local_irq_enable();
87353d8a RB	185	}
340ee4b9	186
340ee4b9 RB	187	/*
	188	* Setup the PC, SP, and GP of a secondary processor and start it
	189	* running!
	190	* smp_bootstrap is the place to resume from
	191	* __KSTK_TOS(idle) is apparently the stack pointer
	192	* (unsigned long)idle->thread_info the gp
	193	* assumes a 1:1 mapping of TC => VPE
	194	*/
078a55fc	195	static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
340ee4b9	196	{
dc8f6029	197	struct thread_info *gp = task_thread_info(idle);
340ee4b9 RB	198	dvpe();
	199	set_c0_mvpcontrol(MVPCONTROL_VPC);
	200
	201	settc(cpu);
	202
	203	/* restart */
	204	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
	205
	206	/* enable the tc this vpe/cpu will be running */
	207	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) \| TCSTATUS_A);
	208
	209	write_tc_c0_tchalt(0);
	210
	211	/* enable the VPE */
	212	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| VPECONF0_VPA);
	213
	214	/* stack pointer */
	215	write_tc_gpr_sp( __KSTK_TOS(idle));
	216
	217	/* global pointer */
dc8f6029	218	write_tc_gpr_gp((unsigned long)gp);
340ee4b9	219
41c594ab	220	flush_icache_range((unsigned long)gp,
70342287	221	(unsigned long)(gp + sizeof(struct thread_info)));
340ee4b9 RB	222
	223	/* finally out of configuration and into chaos */
	224	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	225
	226	evpe(EVPE_ENABLE);
	227	}
	228
87353d8a RB	229	/*
	230	* Common setup before any secondaries are started
	231	* Make sure all CPU's are in a sensible state before we boot any of the
39b8d525	232	* secondaries
87353d8a RB	233	*/
87353d8a RB	234	static void __init vsmp_smp_setup(void)
340ee4b9	235	{
87353d8a RB	236	unsigned int mvpconf0, ntc, tc, ncpu = 0;
87353d8a RB	237	unsigned int nvpe;
340ee4b9	238
f088fc84 RB	239	#ifdef CONFIG_MIPS_MT_FPAFF
	240	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	241	if (cpu_has_fpu)
8dd92891	242	cpumask_set_cpu(0, &mt_fpu_cpumask);
f088fc84	243	#endif /* CONFIG_MIPS_MT_FPAFF */
87353d8a RB	244	if (!cpu_has_mipsmt)
87353d8a RB	245	return;
f088fc84	246
87353d8a RB	247	/* disable MT so we can configure */
	248	dvpe();
	249	dmt();
340ee4b9	250
87353d8a RB	251	/* Put MVPE's into 'configuration state' */
87353d8a RB	252	set_c0_mvpcontrol(MVPCONTROL_VPC);
340ee4b9	253
87353d8a RB	254	mvpconf0 = read_c0_mvpconf0();
87353d8a RB	255	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
340ee4b9	256
87353d8a RB	257	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
87353d8a RB	258	smp_num_siblings = nvpe;
340ee4b9	259
87353d8a RB	260	/* we'll always have more TC's than VPE's, so loop setting everything
	261	to a sensible state */
	262	for (tc = 0; tc <= ntc; tc++) {
	263	settc(tc);
340ee4b9	264
39b8d525 RB	265	smvp_tc_init(tc, mvpconf0);
39b8d525 RB	266	ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
87353d8a	267	}
340ee4b9	268
87353d8a RB	269	/* Release config state */
	270	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	271
	272	/* We'll wait until starting the secondaries before starting MVPE */
	273
	274	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
	275	}
	276
	277	static void __init vsmp_prepare_cpus(unsigned int max_cpus)
	278	{
	279	mips_mt_set_cpuoptions();
340ee4b9	280	}
87353d8a RB	281
	282	struct plat_smp_ops vsmp_smp_ops = {
	283	.send_ipi_single = vsmp_send_ipi_single,
	284	.send_ipi_mask = vsmp_send_ipi_mask,
	285	.init_secondary = vsmp_init_secondary,
	286	.smp_finish = vsmp_smp_finish,
87353d8a RB	287	.boot_secondary = vsmp_boot_secondary,
	288	.smp_setup = vsmp_smp_setup,
	289	.prepare_cpus = vsmp_prepare_cpus,
	290	};
d6d3c9af	291