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MIPS: Fix broken malta qemu
[deliverable/linux.git] / arch / mips / kernel / unaligned.c
CommitLineData
1da177e4
LT		 1/*
2 * Handle unaligned accesses by emulation.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
9d8e5736 10 * Copyright (C) 2014 Imagination Technologies Ltd.
1da177e4
LT		 11 *
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
16 *
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
22 *
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
70342287 25 * problems with user programs have been fixed. For programmers this is the
1da177e4
LT		 26 * right way to go.
27 *
28 * Fixing address errors is a per process option. The option is inherited
70342287 29 * across fork(2) and execve(2) calls. If you really want to use the
1da177e4
LT		 30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
32 *
33 * #include <sys/sysmips.h>
34 *
35 * ...
36 * sysmips(MIPS_FIXADE, x);
37 * ...
38 *
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
40 *
41 * Below a little program to play around with this feature.
42 *
43 * #include <stdio.h>
44 * #include <sys/sysmips.h>
45 *
46 * struct foo {
70342287 47 * unsigned char bar[8];
1da177e4
LT		 48 * };
49 *
50 * main(int argc, char *argv[])
51 * {
70342287
RB		 52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
54 * int i;
1da177e4 55 *
70342287
RB		 56 * if (argc > 1)
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
1da177e4 58 *
70342287 59 * printf("*p = %08lx\n", *p);
1da177e4 60 *
70342287 61 * *p = 0xdeadface;
1da177e4 62 *
70342287
RB		 63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
65 * printf("\n");
1da177e4
LT		 66 * }
67 *
68 * Coprocessor loads are not supported; I think this case is unimportant
69 * in the practice.
70 *
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
70342287
RB		 72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
1da177e4 75 */
c3fc5cd5 76#include <linux/context_tracking.h>
1da177e4 77#include <linux/mm.h>
1da177e4
LT		 78#include <linux/signal.h>
79#include <linux/smp.h>
e8edc6e0 80#include <linux/sched.h>
6312e0ee 81#include <linux/debugfs.h>
7f788d2d
DCZ		 82#include <linux/perf_event.h>
83
1da177e4
LT		 84#include <asm/asm.h>
85#include <asm/branch.h>
86#include <asm/byteorder.h>
69f3a7de 87#include <asm/cop2.h>
75dcfc1d 88#include <asm/debug.h>
102cedc3
LY		 89#include <asm/fpu.h>
90#include <asm/fpu_emulator.h>
1da177e4
LT		 91#include <asm/inst.h>
92#include <asm/uaccess.h>
1da177e4 93
70342287 94#define STR(x) __STR(x)
1da177e4
LT		 95#define __STR(x) #x
96
6312e0ee
AN		 97enum {
98 UNALIGNED_ACTION_QUIET,
99 UNALIGNED_ACTION_SIGNAL,
100 UNALIGNED_ACTION_SHOW,
101};
102#ifdef CONFIG_DEBUG_FS
103static u32 unaligned_instructions;
104static u32 unaligned_action;
105#else
106#define unaligned_action UNALIGNED_ACTION_QUIET
1da177e4 107#endif
6312e0ee 108extern void show_registers(struct pt_regs *regs);
1da177e4 109
34c2f668 110#ifdef __BIG_ENDIAN
eeb53895 111#define _LoadHW(addr, value, res, type) \
3563c32d 112do { \
34c2f668 113 __asm__ __volatile__ (".set\tnoat\n" \
eeb53895
MC		 114 "1:\t"type##_lb("%0", "0(%2)")"\n" \
115 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
34c2f668
LY		 116 "sll\t%0, 0x8\n\t" \
117 "or\t%0, $1\n\t" \
118 "li\t%1, 0\n" \
119 "3:\t.set\tat\n\t" \
120 ".insn\n\t" \
121 ".section\t.fixup,\"ax\"\n\t" \
122 "4:\tli\t%1, %3\n\t" \
123 "j\t3b\n\t" \
124 ".previous\n\t" \
125 ".section\t__ex_table,\"a\"\n\t" \
126 STR(PTR)"\t1b, 4b\n\t" \
127 STR(PTR)"\t2b, 4b\n\t" \
128 ".previous" \
129 : "=&r" (value), "=r" (res) \
3563c32d
MC		 130 : "r" (addr), "i" (-EFAULT)); \
131} while(0)
34c2f668 132
0593a44c 133#ifndef CONFIG_CPU_MIPSR6
eeb53895 134#define _LoadW(addr, value, res, type) \
3563c32d 135do { \
34c2f668 136 __asm__ __volatile__ ( \
eeb53895
MC		 137 "1:\t"type##_lwl("%0", "(%2)")"\n" \
138 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
34c2f668
LY		 139 "li\t%1, 0\n" \
140 "3:\n\t" \
141 ".insn\n\t" \
142 ".section\t.fixup,\"ax\"\n\t" \
143 "4:\tli\t%1, %3\n\t" \
144 "j\t3b\n\t" \
145 ".previous\n\t" \
146 ".section\t__ex_table,\"a\"\n\t" \
147 STR(PTR)"\t1b, 4b\n\t" \
148 STR(PTR)"\t2b, 4b\n\t" \
149 ".previous" \
150 : "=&r" (value), "=r" (res) \
3563c32d
MC		 151 : "r" (addr), "i" (-EFAULT)); \
152} while(0)
153
0593a44c
LY		 154#else
155/* MIPSR6 has no lwl instruction */
eeb53895 156#define _LoadW(addr, value, res, type) \
3563c32d 157do { \
0593a44c
LY		 158 __asm__ __volatile__ ( \
159 ".set\tpush\n" \
160 ".set\tnoat\n\t" \
eeb53895
MC		 161 "1:"type##_lb("%0", "0(%2)")"\n\t" \
162 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
0593a44c
LY		 163 "sll\t%0, 0x8\n\t" \
164 "or\t%0, $1\n\t" \
eeb53895 165 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
0593a44c
LY		 166 "sll\t%0, 0x8\n\t" \
167 "or\t%0, $1\n\t" \
eeb53895 168 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
0593a44c
LY		 169 "sll\t%0, 0x8\n\t" \
170 "or\t%0, $1\n\t" \
171 "li\t%1, 0\n" \
172 ".set\tpop\n" \
173 "10:\n\t" \
174 ".insn\n\t" \
175 ".section\t.fixup,\"ax\"\n\t" \
176 "11:\tli\t%1, %3\n\t" \
177 "j\t10b\n\t" \
178 ".previous\n\t" \
179 ".section\t__ex_table,\"a\"\n\t" \
180 STR(PTR)"\t1b, 11b\n\t" \
181 STR(PTR)"\t2b, 11b\n\t" \
182 STR(PTR)"\t3b, 11b\n\t" \
183 STR(PTR)"\t4b, 11b\n\t" \
184 ".previous" \
185 : "=&r" (value), "=r" (res) \
3563c32d
MC		 186 : "r" (addr), "i" (-EFAULT)); \
187} while(0)
188
0593a44c 189#endif /* CONFIG_CPU_MIPSR6 */
34c2f668 190
eeb53895 191#define _LoadHWU(addr, value, res, type) \
3563c32d 192do { \
34c2f668
LY		 193 __asm__ __volatile__ ( \
194 ".set\tnoat\n" \
eeb53895
MC		 195 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
196 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
34c2f668
LY		 197 "sll\t%0, 0x8\n\t" \
198 "or\t%0, $1\n\t" \
199 "li\t%1, 0\n" \
200 "3:\n\t" \
201 ".insn\n\t" \
202 ".set\tat\n\t" \
203 ".section\t.fixup,\"ax\"\n\t" \
204 "4:\tli\t%1, %3\n\t" \
205 "j\t3b\n\t" \
206 ".previous\n\t" \
207 ".section\t__ex_table,\"a\"\n\t" \
208 STR(PTR)"\t1b, 4b\n\t" \
209 STR(PTR)"\t2b, 4b\n\t" \
210 ".previous" \
211 : "=&r" (value), "=r" (res) \
3563c32d
MC		 212 : "r" (addr), "i" (-EFAULT)); \
213} while(0)
34c2f668 214
0593a44c 215#ifndef CONFIG_CPU_MIPSR6
eeb53895 216#define _LoadWU(addr, value, res, type) \
3563c32d 217do { \
34c2f668 218 __asm__ __volatile__ ( \
eeb53895
MC		 219 "1:\t"type##_lwl("%0", "(%2)")"\n" \
220 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
34c2f668
LY		 221 "dsll\t%0, %0, 32\n\t" \
222 "dsrl\t%0, %0, 32\n\t" \
223 "li\t%1, 0\n" \
224 "3:\n\t" \
225 ".insn\n\t" \
226 "\t.section\t.fixup,\"ax\"\n\t" \
227 "4:\tli\t%1, %3\n\t" \
228 "j\t3b\n\t" \
229 ".previous\n\t" \
230 ".section\t__ex_table,\"a\"\n\t" \
231 STR(PTR)"\t1b, 4b\n\t" \
232 STR(PTR)"\t2b, 4b\n\t" \
233 ".previous" \
234 : "=&r" (value), "=r" (res) \
3563c32d
MC		 235 : "r" (addr), "i" (-EFAULT)); \
236} while(0)
34c2f668 237
eeb53895 238#define _LoadDW(addr, value, res) \
3563c32d 239do { \
34c2f668
LY		 240 __asm__ __volatile__ ( \
241 "1:\tldl\t%0, (%2)\n" \
242 "2:\tldr\t%0, 7(%2)\n\t" \
243 "li\t%1, 0\n" \
244 "3:\n\t" \
245 ".insn\n\t" \
246 "\t.section\t.fixup,\"ax\"\n\t" \
247 "4:\tli\t%1, %3\n\t" \
248 "j\t3b\n\t" \
249 ".previous\n\t" \
250 ".section\t__ex_table,\"a\"\n\t" \
251 STR(PTR)"\t1b, 4b\n\t" \
252 STR(PTR)"\t2b, 4b\n\t" \
253 ".previous" \
254 : "=&r" (value), "=r" (res) \
3563c32d
MC		 255 : "r" (addr), "i" (-EFAULT)); \
256} while(0)
257
0593a44c
LY		 258#else
259/* MIPSR6 has not lwl and ldl instructions */
eeb53895 260#define _LoadWU(addr, value, res, type) \
3563c32d 261do { \
0593a44c
LY		 262 __asm__ __volatile__ ( \
263 ".set\tpush\n\t" \
264 ".set\tnoat\n\t" \
eeb53895
MC		 265 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
266 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
0593a44c
LY		 267 "sll\t%0, 0x8\n\t" \
268 "or\t%0, $1\n\t" \
eeb53895 269 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
0593a44c
LY		 270 "sll\t%0, 0x8\n\t" \
271 "or\t%0, $1\n\t" \
eeb53895 272 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
0593a44c
LY		 273 "sll\t%0, 0x8\n\t" \
274 "or\t%0, $1\n\t" \
275 "li\t%1, 0\n" \
276 ".set\tpop\n" \
277 "10:\n\t" \
278 ".insn\n\t" \
279 ".section\t.fixup,\"ax\"\n\t" \
280 "11:\tli\t%1, %3\n\t" \
281 "j\t10b\n\t" \
282 ".previous\n\t" \
283 ".section\t__ex_table,\"a\"\n\t" \
284 STR(PTR)"\t1b, 11b\n\t" \
285 STR(PTR)"\t2b, 11b\n\t" \
286 STR(PTR)"\t3b, 11b\n\t" \
287 STR(PTR)"\t4b, 11b\n\t" \
288 ".previous" \
289 : "=&r" (value), "=r" (res) \
3563c32d
MC		 290 : "r" (addr), "i" (-EFAULT)); \
291} while(0)
0593a44c 292
eeb53895 293#define _LoadDW(addr, value, res) \
3563c32d 294do { \
0593a44c
LY		 295 __asm__ __volatile__ ( \
296 ".set\tpush\n\t" \
297 ".set\tnoat\n\t" \
298 "1:lb\t%0, 0(%2)\n\t" \
299 "2:lbu\t $1, 1(%2)\n\t" \
300 "dsll\t%0, 0x8\n\t" \
301 "or\t%0, $1\n\t" \
302 "3:lbu\t$1, 2(%2)\n\t" \
303 "dsll\t%0, 0x8\n\t" \
304 "or\t%0, $1\n\t" \
305 "4:lbu\t$1, 3(%2)\n\t" \
306 "dsll\t%0, 0x8\n\t" \
307 "or\t%0, $1\n\t" \
308 "5:lbu\t$1, 4(%2)\n\t" \
309 "dsll\t%0, 0x8\n\t" \
310 "or\t%0, $1\n\t" \
311 "6:lbu\t$1, 5(%2)\n\t" \
312 "dsll\t%0, 0x8\n\t" \
313 "or\t%0, $1\n\t" \
314 "7:lbu\t$1, 6(%2)\n\t" \
315 "dsll\t%0, 0x8\n\t" \
316 "or\t%0, $1\n\t" \
317 "8:lbu\t$1, 7(%2)\n\t" \
318 "dsll\t%0, 0x8\n\t" \
319 "or\t%0, $1\n\t" \
320 "li\t%1, 0\n" \
321 ".set\tpop\n\t" \
322 "10:\n\t" \
323 ".insn\n\t" \
324 ".section\t.fixup,\"ax\"\n\t" \
325 "11:\tli\t%1, %3\n\t" \
326 "j\t10b\n\t" \
327 ".previous\n\t" \
328 ".section\t__ex_table,\"a\"\n\t" \
329 STR(PTR)"\t1b, 11b\n\t" \
330 STR(PTR)"\t2b, 11b\n\t" \
331 STR(PTR)"\t3b, 11b\n\t" \
332 STR(PTR)"\t4b, 11b\n\t" \
333 STR(PTR)"\t5b, 11b\n\t" \
334 STR(PTR)"\t6b, 11b\n\t" \
335 STR(PTR)"\t7b, 11b\n\t" \
336 STR(PTR)"\t8b, 11b\n\t" \
337 ".previous" \
338 : "=&r" (value), "=r" (res) \
3563c32d
MC		 339 : "r" (addr), "i" (-EFAULT)); \
340} while(0)
341
0593a44c
LY		 342#endif /* CONFIG_CPU_MIPSR6 */
343
34c2f668 344
eeb53895 345#define _StoreHW(addr, value, res, type) \
3563c32d 346do { \
34c2f668
LY		 347 __asm__ __volatile__ ( \
348 ".set\tnoat\n" \
eeb53895 349 "1:\t"type##_sb("%1", "1(%2)")"\n" \
34c2f668 350 "srl\t$1, %1, 0x8\n" \
eeb53895 351 "2:\t"type##_sb("$1", "0(%2)")"\n" \
34c2f668
LY		 352 ".set\tat\n\t" \
353 "li\t%0, 0\n" \
354 "3:\n\t" \
355 ".insn\n\t" \
356 ".section\t.fixup,\"ax\"\n\t" \
357 "4:\tli\t%0, %3\n\t" \
358 "j\t3b\n\t" \
359 ".previous\n\t" \
360 ".section\t__ex_table,\"a\"\n\t" \
361 STR(PTR)"\t1b, 4b\n\t" \
362 STR(PTR)"\t2b, 4b\n\t" \
363 ".previous" \
364 : "=r" (res) \
3563c32d
MC		 365 : "r" (value), "r" (addr), "i" (-EFAULT));\
366} while(0)
34c2f668 367
0593a44c 368#ifndef CONFIG_CPU_MIPSR6
eeb53895 369#define _StoreW(addr, value, res, type) \
3563c32d 370do { \
34c2f668 371 __asm__ __volatile__ ( \
eeb53895
MC		 372 "1:\t"type##_swl("%1", "(%2)")"\n" \
373 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
34c2f668
LY		 374 "li\t%0, 0\n" \
375 "3:\n\t" \
376 ".insn\n\t" \
377 ".section\t.fixup,\"ax\"\n\t" \
378 "4:\tli\t%0, %3\n\t" \
379 "j\t3b\n\t" \
380 ".previous\n\t" \
381 ".section\t__ex_table,\"a\"\n\t" \
382 STR(PTR)"\t1b, 4b\n\t" \
383 STR(PTR)"\t2b, 4b\n\t" \
384 ".previous" \
385 : "=r" (res) \
3563c32d
MC		 386 : "r" (value), "r" (addr), "i" (-EFAULT)); \
387} while(0)
34c2f668 388
eeb53895 389#define _StoreDW(addr, value, res) \
3563c32d 390do { \
34c2f668
LY		 391 __asm__ __volatile__ ( \
392 "1:\tsdl\t%1,(%2)\n" \
393 "2:\tsdr\t%1, 7(%2)\n\t" \
394 "li\t%0, 0\n" \
395 "3:\n\t" \
396 ".insn\n\t" \
397 ".section\t.fixup,\"ax\"\n\t" \
398 "4:\tli\t%0, %3\n\t" \
399 "j\t3b\n\t" \
400 ".previous\n\t" \
401 ".section\t__ex_table,\"a\"\n\t" \
402 STR(PTR)"\t1b, 4b\n\t" \
403 STR(PTR)"\t2b, 4b\n\t" \
404 ".previous" \
405 : "=r" (res) \
3563c32d
MC		 406 : "r" (value), "r" (addr), "i" (-EFAULT)); \
407} while(0)
408
0593a44c
LY		 409#else
410/* MIPSR6 has no swl and sdl instructions */
eeb53895 411#define _StoreW(addr, value, res, type) \
3563c32d 412do { \
0593a44c
LY		 413 __asm__ __volatile__ ( \
414 ".set\tpush\n\t" \
415 ".set\tnoat\n\t" \
eeb53895 416 "1:"type##_sb("%1", "3(%2)")"\n\t" \
0593a44c 417 "srl\t$1, %1, 0x8\n\t" \
eeb53895 418 "2:"type##_sb("$1", "2(%2)")"\n\t" \
0593a44c 419 "srl\t$1, $1, 0x8\n\t" \
eeb53895 420 "3:"type##_sb("$1", "1(%2)")"\n\t" \
0593a44c 421 "srl\t$1, $1, 0x8\n\t" \
eeb53895 422 "4:"type##_sb("$1", "0(%2)")"\n\t" \
0593a44c
LY		 423 ".set\tpop\n\t" \
424 "li\t%0, 0\n" \
425 "10:\n\t" \
426 ".insn\n\t" \
427 ".section\t.fixup,\"ax\"\n\t" \
428 "11:\tli\t%0, %3\n\t" \
429 "j\t10b\n\t" \
430 ".previous\n\t" \
431 ".section\t__ex_table,\"a\"\n\t" \
432 STR(PTR)"\t1b, 11b\n\t" \
433 STR(PTR)"\t2b, 11b\n\t" \
434 STR(PTR)"\t3b, 11b\n\t" \
435 STR(PTR)"\t4b, 11b\n\t" \
436 ".previous" \
437 : "=&r" (res) \
438 : "r" (value), "r" (addr), "i" (-EFAULT) \
3563c32d
MC		 439 : "memory"); \
440} while(0)
0593a44c 441
531a6d59 442#define _StoreDW(addr, value, res) \
3563c32d 443do { \
0593a44c
LY		 444 __asm__ __volatile__ ( \
445 ".set\tpush\n\t" \
446 ".set\tnoat\n\t" \
447 "1:sb\t%1, 7(%2)\n\t" \
448 "dsrl\t$1, %1, 0x8\n\t" \
449 "2:sb\t$1, 6(%2)\n\t" \
450 "dsrl\t$1, $1, 0x8\n\t" \
451 "3:sb\t$1, 5(%2)\n\t" \
452 "dsrl\t$1, $1, 0x8\n\t" \
453 "4:sb\t$1, 4(%2)\n\t" \
454 "dsrl\t$1, $1, 0x8\n\t" \
455 "5:sb\t$1, 3(%2)\n\t" \
456 "dsrl\t$1, $1, 0x8\n\t" \
457 "6:sb\t$1, 2(%2)\n\t" \
458 "dsrl\t$1, $1, 0x8\n\t" \
459 "7:sb\t$1, 1(%2)\n\t" \
460 "dsrl\t$1, $1, 0x8\n\t" \
461 "8:sb\t$1, 0(%2)\n\t" \
462 "dsrl\t$1, $1, 0x8\n\t" \
463 ".set\tpop\n\t" \
464 "li\t%0, 0\n" \
465 "10:\n\t" \
466 ".insn\n\t" \
467 ".section\t.fixup,\"ax\"\n\t" \
468 "11:\tli\t%0, %3\n\t" \
469 "j\t10b\n\t" \
470 ".previous\n\t" \
471 ".section\t__ex_table,\"a\"\n\t" \
472 STR(PTR)"\t1b, 11b\n\t" \
473 STR(PTR)"\t2b, 11b\n\t" \
474 STR(PTR)"\t3b, 11b\n\t" \
475 STR(PTR)"\t4b, 11b\n\t" \
476 STR(PTR)"\t5b, 11b\n\t" \
477 STR(PTR)"\t6b, 11b\n\t" \
478 STR(PTR)"\t7b, 11b\n\t" \
479 STR(PTR)"\t8b, 11b\n\t" \
480 ".previous" \
481 : "=&r" (res) \
482 : "r" (value), "r" (addr), "i" (-EFAULT) \
3563c32d
MC		 483 : "memory"); \
484} while(0)
485
0593a44c
LY		 486#endif /* CONFIG_CPU_MIPSR6 */
487
488#else /* __BIG_ENDIAN */
34c2f668 489
eeb53895 490#define _LoadHW(addr, value, res, type) \
3563c32d 491do { \
34c2f668 492 __asm__ __volatile__ (".set\tnoat\n" \
eeb53895
MC		 493 "1:\t"type##_lb("%0", "1(%2)")"\n" \
494 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
34c2f668
LY		 495 "sll\t%0, 0x8\n\t" \
496 "or\t%0, $1\n\t" \
497 "li\t%1, 0\n" \
498 "3:\t.set\tat\n\t" \
499 ".insn\n\t" \
500 ".section\t.fixup,\"ax\"\n\t" \
501 "4:\tli\t%1, %3\n\t" \
502 "j\t3b\n\t" \
503 ".previous\n\t" \
504 ".section\t__ex_table,\"a\"\n\t" \
505 STR(PTR)"\t1b, 4b\n\t" \
506 STR(PTR)"\t2b, 4b\n\t" \
507 ".previous" \
508 : "=&r" (value), "=r" (res) \
3563c32d
MC		 509 : "r" (addr), "i" (-EFAULT)); \
510} while(0)
34c2f668 511
0593a44c 512#ifndef CONFIG_CPU_MIPSR6
eeb53895 513#define _LoadW(addr, value, res, type) \
3563c32d 514do { \
34c2f668 515 __asm__ __volatile__ ( \
eeb53895
MC		 516 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
517 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
34c2f668
LY		 518 "li\t%1, 0\n" \
519 "3:\n\t" \
520 ".insn\n\t" \
521 ".section\t.fixup,\"ax\"\n\t" \
522 "4:\tli\t%1, %3\n\t" \
523 "j\t3b\n\t" \
524 ".previous\n\t" \
525 ".section\t__ex_table,\"a\"\n\t" \
526 STR(PTR)"\t1b, 4b\n\t" \
527 STR(PTR)"\t2b, 4b\n\t" \
528 ".previous" \
529 : "=&r" (value), "=r" (res) \
3563c32d
MC		 530 : "r" (addr), "i" (-EFAULT)); \
531} while(0)
532
0593a44c
LY		 533#else
534/* MIPSR6 has no lwl instruction */
eeb53895 535#define _LoadW(addr, value, res, type) \
3563c32d 536do { \
0593a44c
LY		 537 __asm__ __volatile__ ( \
538 ".set\tpush\n" \
539 ".set\tnoat\n\t" \
eeb53895
MC		 540 "1:"type##_lb("%0", "3(%2)")"\n\t" \
541 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
0593a44c
LY		 542 "sll\t%0, 0x8\n\t" \
543 "or\t%0, $1\n\t" \
eeb53895 544 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
0593a44c
LY		 545 "sll\t%0, 0x8\n\t" \
546 "or\t%0, $1\n\t" \
eeb53895 547 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
0593a44c
LY		 548 "sll\t%0, 0x8\n\t" \
549 "or\t%0, $1\n\t" \
550 "li\t%1, 0\n" \
551 ".set\tpop\n" \
552 "10:\n\t" \
553 ".insn\n\t" \
554 ".section\t.fixup,\"ax\"\n\t" \
555 "11:\tli\t%1, %3\n\t" \
556 "j\t10b\n\t" \
557 ".previous\n\t" \
558 ".section\t__ex_table,\"a\"\n\t" \
559 STR(PTR)"\t1b, 11b\n\t" \
560 STR(PTR)"\t2b, 11b\n\t" \
561 STR(PTR)"\t3b, 11b\n\t" \
562 STR(PTR)"\t4b, 11b\n\t" \
563 ".previous" \
564 : "=&r" (value), "=r" (res) \
3563c32d
MC		 565 : "r" (addr), "i" (-EFAULT)); \
566} while(0)
567
0593a44c
LY		 568#endif /* CONFIG_CPU_MIPSR6 */
569
34c2f668 570
eeb53895 571#define _LoadHWU(addr, value, res, type) \
3563c32d 572do { \
34c2f668
LY		 573 __asm__ __volatile__ ( \
574 ".set\tnoat\n" \
eeb53895
MC		 575 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
576 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
34c2f668
LY		 577 "sll\t%0, 0x8\n\t" \
578 "or\t%0, $1\n\t" \
579 "li\t%1, 0\n" \
580 "3:\n\t" \
581 ".insn\n\t" \
582 ".set\tat\n\t" \
583 ".section\t.fixup,\"ax\"\n\t" \
584 "4:\tli\t%1, %3\n\t" \
585 "j\t3b\n\t" \
586 ".previous\n\t" \
587 ".section\t__ex_table,\"a\"\n\t" \
588 STR(PTR)"\t1b, 4b\n\t" \
589 STR(PTR)"\t2b, 4b\n\t" \
590 ".previous" \
591 : "=&r" (value), "=r" (res) \
3563c32d
MC		 592 : "r" (addr), "i" (-EFAULT)); \
593} while(0)
34c2f668 594
0593a44c 595#ifndef CONFIG_CPU_MIPSR6
eeb53895 596#define _LoadWU(addr, value, res, type) \
3563c32d 597do { \
34c2f668 598 __asm__ __volatile__ ( \
eeb53895
MC		 599 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
600 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
34c2f668
LY		 601 "dsll\t%0, %0, 32\n\t" \
602 "dsrl\t%0, %0, 32\n\t" \
603 "li\t%1, 0\n" \
604 "3:\n\t" \
605 ".insn\n\t" \
606 "\t.section\t.fixup,\"ax\"\n\t" \
607 "4:\tli\t%1, %3\n\t" \
608 "j\t3b\n\t" \
609 ".previous\n\t" \
610 ".section\t__ex_table,\"a\"\n\t" \
611 STR(PTR)"\t1b, 4b\n\t" \
612 STR(PTR)"\t2b, 4b\n\t" \
613 ".previous" \
614 : "=&r" (value), "=r" (res) \
3563c32d
MC		 615 : "r" (addr), "i" (-EFAULT)); \
616} while(0)
34c2f668 617
eeb53895 618#define _LoadDW(addr, value, res) \
3563c32d 619do { \
34c2f668
LY		 620 __asm__ __volatile__ ( \
621 "1:\tldl\t%0, 7(%2)\n" \
622 "2:\tldr\t%0, (%2)\n\t" \
623 "li\t%1, 0\n" \
624 "3:\n\t" \
625 ".insn\n\t" \
626 "\t.section\t.fixup,\"ax\"\n\t" \
627 "4:\tli\t%1, %3\n\t" \
628 "j\t3b\n\t" \
629 ".previous\n\t" \
630 ".section\t__ex_table,\"a\"\n\t" \
631 STR(PTR)"\t1b, 4b\n\t" \
632 STR(PTR)"\t2b, 4b\n\t" \
633 ".previous" \
634 : "=&r" (value), "=r" (res) \
3563c32d
MC		 635 : "r" (addr), "i" (-EFAULT)); \
636} while(0)
637
0593a44c
LY		 638#else
639/* MIPSR6 has not lwl and ldl instructions */
eeb53895 640#define _LoadWU(addr, value, res, type) \
3563c32d 641do { \
0593a44c
LY		 642 __asm__ __volatile__ ( \
643 ".set\tpush\n\t" \
644 ".set\tnoat\n\t" \
eeb53895
MC		 645 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
646 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
0593a44c
LY		 647 "sll\t%0, 0x8\n\t" \
648 "or\t%0, $1\n\t" \
eeb53895 649 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
0593a44c
LY		 650 "sll\t%0, 0x8\n\t" \
651 "or\t%0, $1\n\t" \
eeb53895 652 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
0593a44c
LY		 653 "sll\t%0, 0x8\n\t" \
654 "or\t%0, $1\n\t" \
655 "li\t%1, 0\n" \
656 ".set\tpop\n" \
657 "10:\n\t" \
658 ".insn\n\t" \
659 ".section\t.fixup,\"ax\"\n\t" \
660 "11:\tli\t%1, %3\n\t" \
661 "j\t10b\n\t" \
662 ".previous\n\t" \
663 ".section\t__ex_table,\"a\"\n\t" \
664 STR(PTR)"\t1b, 11b\n\t" \
665 STR(PTR)"\t2b, 11b\n\t" \
666 STR(PTR)"\t3b, 11b\n\t" \
667 STR(PTR)"\t4b, 11b\n\t" \
668 ".previous" \
669 : "=&r" (value), "=r" (res) \
3563c32d
MC		 670 : "r" (addr), "i" (-EFAULT)); \
671} while(0)
0593a44c 672
eeb53895 673#define _LoadDW(addr, value, res) \
3563c32d 674do { \
0593a44c
LY		 675 __asm__ __volatile__ ( \
676 ".set\tpush\n\t" \
677 ".set\tnoat\n\t" \
678 "1:lb\t%0, 7(%2)\n\t" \
679 "2:lbu\t$1, 6(%2)\n\t" \
680 "dsll\t%0, 0x8\n\t" \
681 "or\t%0, $1\n\t" \
682 "3:lbu\t$1, 5(%2)\n\t" \
683 "dsll\t%0, 0x8\n\t" \
684 "or\t%0, $1\n\t" \
685 "4:lbu\t$1, 4(%2)\n\t" \
686 "dsll\t%0, 0x8\n\t" \
687 "or\t%0, $1\n\t" \
688 "5:lbu\t$1, 3(%2)\n\t" \
689 "dsll\t%0, 0x8\n\t" \
690 "or\t%0, $1\n\t" \
691 "6:lbu\t$1, 2(%2)\n\t" \
692 "dsll\t%0, 0x8\n\t" \
693 "or\t%0, $1\n\t" \
694 "7:lbu\t$1, 1(%2)\n\t" \
695 "dsll\t%0, 0x8\n\t" \
696 "or\t%0, $1\n\t" \
697 "8:lbu\t$1, 0(%2)\n\t" \
698 "dsll\t%0, 0x8\n\t" \
699 "or\t%0, $1\n\t" \
700 "li\t%1, 0\n" \
701 ".set\tpop\n\t" \
702 "10:\n\t" \
703 ".insn\n\t" \
704 ".section\t.fixup,\"ax\"\n\t" \
705 "11:\tli\t%1, %3\n\t" \
706 "j\t10b\n\t" \
707 ".previous\n\t" \
708 ".section\t__ex_table,\"a\"\n\t" \
709 STR(PTR)"\t1b, 11b\n\t" \
710 STR(PTR)"\t2b, 11b\n\t" \
711 STR(PTR)"\t3b, 11b\n\t" \
712 STR(PTR)"\t4b, 11b\n\t" \
713 STR(PTR)"\t5b, 11b\n\t" \
714 STR(PTR)"\t6b, 11b\n\t" \
715 STR(PTR)"\t7b, 11b\n\t" \
716 STR(PTR)"\t8b, 11b\n\t" \
717 ".previous" \
718 : "=&r" (value), "=r" (res) \
3563c32d
MC		 719 : "r" (addr), "i" (-EFAULT)); \
720} while(0)
0593a44c 721#endif /* CONFIG_CPU_MIPSR6 */
34c2f668 722
eeb53895 723#define _StoreHW(addr, value, res, type) \
3563c32d 724do { \
34c2f668
LY		 725 __asm__ __volatile__ ( \
726 ".set\tnoat\n" \
eeb53895 727 "1:\t"type##_sb("%1", "0(%2)")"\n" \
34c2f668 728 "srl\t$1,%1, 0x8\n" \
eeb53895 729 "2:\t"type##_sb("$1", "1(%2)")"\n" \
34c2f668
LY		 730 ".set\tat\n\t" \
731 "li\t%0, 0\n" \
732 "3:\n\t" \
733 ".insn\n\t" \
734 ".section\t.fixup,\"ax\"\n\t" \
735 "4:\tli\t%0, %3\n\t" \
736 "j\t3b\n\t" \
737 ".previous\n\t" \
738 ".section\t__ex_table,\"a\"\n\t" \
739 STR(PTR)"\t1b, 4b\n\t" \
740 STR(PTR)"\t2b, 4b\n\t" \
741 ".previous" \
742 : "=r" (res) \
3563c32d
MC		 743 : "r" (value), "r" (addr), "i" (-EFAULT));\
744} while(0)
745
0593a44c 746#ifndef CONFIG_CPU_MIPSR6
eeb53895 747#define _StoreW(addr, value, res, type) \
3563c32d 748do { \
34c2f668 749 __asm__ __volatile__ ( \
eeb53895
MC		 750 "1:\t"type##_swl("%1", "3(%2)")"\n" \
751 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
34c2f668
LY		 752 "li\t%0, 0\n" \
753 "3:\n\t" \
754 ".insn\n\t" \
755 ".section\t.fixup,\"ax\"\n\t" \
756 "4:\tli\t%0, %3\n\t" \
757 "j\t3b\n\t" \
758 ".previous\n\t" \
759 ".section\t__ex_table,\"a\"\n\t" \
760 STR(PTR)"\t1b, 4b\n\t" \
761 STR(PTR)"\t2b, 4b\n\t" \
762 ".previous" \
763 : "=r" (res) \
3563c32d
MC		 764 : "r" (value), "r" (addr), "i" (-EFAULT)); \
765} while(0)
34c2f668 766
eeb53895 767#define _StoreDW(addr, value, res) \
3563c32d 768do { \
34c2f668
LY		 769 __asm__ __volatile__ ( \
770 "1:\tsdl\t%1, 7(%2)\n" \
771 "2:\tsdr\t%1, (%2)\n\t" \
772 "li\t%0, 0\n" \
773 "3:\n\t" \
774 ".insn\n\t" \
775 ".section\t.fixup,\"ax\"\n\t" \
776 "4:\tli\t%0, %3\n\t" \
777 "j\t3b\n\t" \
778 ".previous\n\t" \
779 ".section\t__ex_table,\"a\"\n\t" \
780 STR(PTR)"\t1b, 4b\n\t" \
781 STR(PTR)"\t2b, 4b\n\t" \
782 ".previous" \
783 : "=r" (res) \
3563c32d
MC		 784 : "r" (value), "r" (addr), "i" (-EFAULT)); \
785} while(0)
786
0593a44c
LY		 787#else
788/* MIPSR6 has no swl and sdl instructions */
eeb53895 789#define _StoreW(addr, value, res, type) \
3563c32d 790do { \
0593a44c
LY		 791 __asm__ __volatile__ ( \
792 ".set\tpush\n\t" \
793 ".set\tnoat\n\t" \
eeb53895 794 "1:"type##_sb("%1", "0(%2)")"\n\t" \
0593a44c 795 "srl\t$1, %1, 0x8\n\t" \
eeb53895 796 "2:"type##_sb("$1", "1(%2)")"\n\t" \
0593a44c 797 "srl\t$1, $1, 0x8\n\t" \
eeb53895 798 "3:"type##_sb("$1", "2(%2)")"\n\t" \
0593a44c 799 "srl\t$1, $1, 0x8\n\t" \
eeb53895 800 "4:"type##_sb("$1", "3(%2)")"\n\t" \
0593a44c
LY		 801 ".set\tpop\n\t" \
802 "li\t%0, 0\n" \
803 "10:\n\t" \
804 ".insn\n\t" \
805 ".section\t.fixup,\"ax\"\n\t" \
806 "11:\tli\t%0, %3\n\t" \
807 "j\t10b\n\t" \
808 ".previous\n\t" \
809 ".section\t__ex_table,\"a\"\n\t" \
810 STR(PTR)"\t1b, 11b\n\t" \
811 STR(PTR)"\t2b, 11b\n\t" \
812 STR(PTR)"\t3b, 11b\n\t" \
813 STR(PTR)"\t4b, 11b\n\t" \
814 ".previous" \
815 : "=&r" (res) \
816 : "r" (value), "r" (addr), "i" (-EFAULT) \
3563c32d
MC		 817 : "memory"); \
818} while(0)
0593a44c 819
eeb53895 820#define _StoreDW(addr, value, res) \
3563c32d 821do { \
0593a44c
LY		 822 __asm__ __volatile__ ( \
823 ".set\tpush\n\t" \
824 ".set\tnoat\n\t" \
825 "1:sb\t%1, 0(%2)\n\t" \
826 "dsrl\t$1, %1, 0x8\n\t" \
827 "2:sb\t$1, 1(%2)\n\t" \
828 "dsrl\t$1, $1, 0x8\n\t" \
829 "3:sb\t$1, 2(%2)\n\t" \
830 "dsrl\t$1, $1, 0x8\n\t" \
831 "4:sb\t$1, 3(%2)\n\t" \
832 "dsrl\t$1, $1, 0x8\n\t" \
833 "5:sb\t$1, 4(%2)\n\t" \
834 "dsrl\t$1, $1, 0x8\n\t" \
835 "6:sb\t$1, 5(%2)\n\t" \
836 "dsrl\t$1, $1, 0x8\n\t" \
837 "7:sb\t$1, 6(%2)\n\t" \
838 "dsrl\t$1, $1, 0x8\n\t" \
839 "8:sb\t$1, 7(%2)\n\t" \
840 "dsrl\t$1, $1, 0x8\n\t" \
841 ".set\tpop\n\t" \
842 "li\t%0, 0\n" \
843 "10:\n\t" \
844 ".insn\n\t" \
845 ".section\t.fixup,\"ax\"\n\t" \
846 "11:\tli\t%0, %3\n\t" \
847 "j\t10b\n\t" \
848 ".previous\n\t" \
849 ".section\t__ex_table,\"a\"\n\t" \
850 STR(PTR)"\t1b, 11b\n\t" \
851 STR(PTR)"\t2b, 11b\n\t" \
852 STR(PTR)"\t3b, 11b\n\t" \
853 STR(PTR)"\t4b, 11b\n\t" \
854 STR(PTR)"\t5b, 11b\n\t" \
855 STR(PTR)"\t6b, 11b\n\t" \
856 STR(PTR)"\t7b, 11b\n\t" \
857 STR(PTR)"\t8b, 11b\n\t" \
858 ".previous" \
859 : "=&r" (res) \
860 : "r" (value), "r" (addr), "i" (-EFAULT) \
3563c32d
MC		 861 : "memory"); \
862} while(0)
863
0593a44c 864#endif /* CONFIG_CPU_MIPSR6 */
34c2f668
LY		 865#endif
866
eeb53895
MC		 867#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
868#define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
869#define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
870#define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
871#define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
872#define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
873#define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
874#define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
875#define LoadDW(addr, value, res) _LoadDW(addr, value, res)
876
877#define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
878#define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
879#define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
880#define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
881#define StoreDW(addr, value, res) _StoreDW(addr, value, res)
882
7f18f151
RB		 883static void emulate_load_store_insn(struct pt_regs *regs,
884 void __user *addr, unsigned int __user *pc)
1da177e4
LT		 885{
886 union mips_instruction insn;
887 unsigned long value;
888 unsigned int res;
34c2f668
LY		 889 unsigned long origpc;
890 unsigned long orig31;
102cedc3 891 void __user *fault_addr = NULL;
c1771216
LY		 892#ifdef CONFIG_EVA
893 mm_segment_t seg;
894#endif
e4aa1f15
LY		 895 union fpureg *fpr;
896 enum msa_2b_fmt df;
897 unsigned int wd;
34c2f668
LY		 898 origpc = (unsigned long)pc;
899 orig31 = regs->regs[31];
900
a8b0ca17 901 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
7f788d2d 902
1da177e4
LT		 903 /*
904 * This load never faults.
905 */
fe00f943 906 __get_user(insn.word, pc);
1da177e4
LT		 907
908 switch (insn.i_format.opcode) {
34c2f668
LY		 909 /*
910 * These are instructions that a compiler doesn't generate. We
911 * can assume therefore that the code is MIPS-aware and
912 * really buggy. Emulating these instructions would break the
913 * semantics anyway.
914 */
1da177e4
LT		 915 case ll_op:
916 case lld_op:
917 case sc_op:
918 case scd_op:
919
34c2f668
LY		 920 /*
921 * For these instructions the only way to create an address
922 * error is an attempted access to kernel/supervisor address
923 * space.
924 */
1da177e4
LT		 925 case ldl_op:
926 case ldr_op:
927 case lwl_op:
928 case lwr_op:
929 case sdl_op:
930 case sdr_op:
931 case swl_op:
932 case swr_op:
933 case lb_op:
934 case lbu_op:
935 case sb_op:
936 goto sigbus;
937
34c2f668
LY		 938 /*
939 * The remaining opcodes are the ones that are really of
940 * interest.
941 */
c1771216
LY		 942#ifdef CONFIG_EVA
943 case spec3_op:
944 /*
945 * we can land here only from kernel accessing user memory,
946 * so we need to "switch" the address limit to user space, so
947 * address check can work properly.
948 */
949 seg = get_fs();
950 set_fs(USER_DS);
951 switch (insn.spec3_format.func) {
952 case lhe_op:
953 if (!access_ok(VERIFY_READ, addr, 2)) {
954 set_fs(seg);
955 goto sigbus;
956 }
eeb53895 957 LoadHWE(addr, value, res);
c1771216
LY		 958 if (res) {
959 set_fs(seg);
960 goto fault;
961 }
962 compute_return_epc(regs);
963 regs->regs[insn.spec3_format.rt] = value;
964 break;
965 case lwe_op:
966 if (!access_ok(VERIFY_READ, addr, 4)) {
967 set_fs(seg);
968 goto sigbus;
969 }
eeb53895 970 LoadWE(addr, value, res);
c1771216
LY		 971 if (res) {
972 set_fs(seg);
973 goto fault;
974 }
975 compute_return_epc(regs);
976 regs->regs[insn.spec3_format.rt] = value;
977 break;
978 case lhue_op:
979 if (!access_ok(VERIFY_READ, addr, 2)) {
980 set_fs(seg);
981 goto sigbus;
982 }
eeb53895 983 LoadHWUE(addr, value, res);
c1771216
LY		 984 if (res) {
985 set_fs(seg);
986 goto fault;
987 }
988 compute_return_epc(regs);
989 regs->regs[insn.spec3_format.rt] = value;
990 break;
991 case she_op:
992 if (!access_ok(VERIFY_WRITE, addr, 2)) {
993 set_fs(seg);
994 goto sigbus;
995 }
996 compute_return_epc(regs);
997 value = regs->regs[insn.spec3_format.rt];
eeb53895 998 StoreHWE(addr, value, res);
c1771216
LY		 999 if (res) {
1000 set_fs(seg);
1001 goto fault;
1002 }
1003 break;
1004 case swe_op:
1005 if (!access_ok(VERIFY_WRITE, addr, 4)) {
1006 set_fs(seg);
1007 goto sigbus;
1008 }
1009 compute_return_epc(regs);
1010 value = regs->regs[insn.spec3_format.rt];
eeb53895 1011 StoreWE(addr, value, res);
c1771216
LY		 1012 if (res) {
1013 set_fs(seg);
1014 goto fault;
1015 }
1016 break;
1017 default:
1018 set_fs(seg);
1019 goto sigill;
1020 }
1021 set_fs(seg);
1022 break;
1023#endif
1da177e4
LT		 1024 case lh_op:
1025 if (!access_ok(VERIFY_READ, addr, 2))
1026 goto sigbus;
1027
6eae3548
MC		 1028 if (config_enabled(CONFIG_EVA)) {
1029 if (segment_eq(get_fs(), get_ds()))
1030 LoadHW(addr, value, res);
1031 else
1032 LoadHWE(addr, value, res);
1033 } else {
1034 LoadHW(addr, value, res);
1035 }
1036
1da177e4
LT		 1037 if (res)
1038 goto fault;
7f18f151
RB		 1039 compute_return_epc(regs);
1040 regs->regs[insn.i_format.rt] = value;
1da177e4
LT		 1041 break;
1042
1043 case lw_op:
1044 if (!access_ok(VERIFY_READ, addr, 4))
1045 goto sigbus;
1046
6eae3548
MC		 1047 if (config_enabled(CONFIG_EVA)) {
1048 if (segment_eq(get_fs(), get_ds()))
1049 LoadW(addr, value, res);
1050 else
1051 LoadWE(addr, value, res);
1052 } else {
1053 LoadW(addr, value, res);
1054 }
1055
1da177e4
LT		 1056 if (res)
1057 goto fault;
7f18f151
RB		 1058 compute_return_epc(regs);
1059 regs->regs[insn.i_format.rt] = value;
1da177e4
LT		 1060 break;
1061
1062 case lhu_op:
1063 if (!access_ok(VERIFY_READ, addr, 2))
1064 goto sigbus;
1065
6eae3548
MC		 1066 if (config_enabled(CONFIG_EVA)) {
1067 if (segment_eq(get_fs(), get_ds()))
1068 LoadHWU(addr, value, res);
1069 else
1070 LoadHWUE(addr, value, res);
1071 } else {
1072 LoadHWU(addr, value, res);
1073 }
1074
1da177e4
LT		 1075 if (res)
1076 goto fault;
7f18f151
RB		 1077 compute_return_epc(regs);
1078 regs->regs[insn.i_format.rt] = value;
1da177e4
LT		 1079 break;
1080
1081 case lwu_op:
875d43e7 1082#ifdef CONFIG_64BIT
1da177e4
LT		 1083 /*
1084 * A 32-bit kernel might be running on a 64-bit processor. But
1085 * if we're on a 32-bit processor and an i-cache incoherency
1086 * or race makes us see a 64-bit instruction here the sdl/sdr
1087 * would blow up, so for now we don't handle unaligned 64-bit
1088 * instructions on 32-bit kernels.
1089 */
1090 if (!access_ok(VERIFY_READ, addr, 4))
1091 goto sigbus;
1092
34c2f668 1093 LoadWU(addr, value, res);
1da177e4
LT		 1094 if (res)
1095 goto fault;
7f18f151
RB		 1096 compute_return_epc(regs);
1097 regs->regs[insn.i_format.rt] = value;
1da177e4 1098 break;
875d43e7 1099#endif /* CONFIG_64BIT */
1da177e4
LT		 1100
1101 /* Cannot handle 64-bit instructions in 32-bit kernel */
1102 goto sigill;
1103
1104 case ld_op:
875d43e7 1105#ifdef CONFIG_64BIT
1da177e4
LT		 1106 /*
1107 * A 32-bit kernel might be running on a 64-bit processor. But
1108 * if we're on a 32-bit processor and an i-cache incoherency
1109 * or race makes us see a 64-bit instruction here the sdl/sdr
1110 * would blow up, so for now we don't handle unaligned 64-bit
1111 * instructions on 32-bit kernels.
1112 */
1113 if (!access_ok(VERIFY_READ, addr, 8))
1114 goto sigbus;
1115
34c2f668 1116 LoadDW(addr, value, res);
1da177e4
LT		 1117 if (res)
1118 goto fault;
7f18f151
RB		 1119 compute_return_epc(regs);
1120 regs->regs[insn.i_format.rt] = value;
1da177e4 1121 break;
875d43e7 1122#endif /* CONFIG_64BIT */
1da177e4
LT		 1123
1124 /* Cannot handle 64-bit instructions in 32-bit kernel */
1125 goto sigill;
1126
1127 case sh_op:
1128 if (!access_ok(VERIFY_WRITE, addr, 2))
1129 goto sigbus;
1130
34c2f668 1131 compute_return_epc(regs);
1da177e4 1132 value = regs->regs[insn.i_format.rt];
6eae3548
MC		 1133
1134 if (config_enabled(CONFIG_EVA)) {
1135 if (segment_eq(get_fs(), get_ds()))
1136 StoreHW(addr, value, res);
1137 else
1138 StoreHWE(addr, value, res);
1139 } else {
1140 StoreHW(addr, value, res);
1141 }
1142
1da177e4
LT		 1143 if (res)
1144 goto fault;
1145 break;
1146
1147 case sw_op:
1148 if (!access_ok(VERIFY_WRITE, addr, 4))
1149 goto sigbus;
1150
34c2f668 1151 compute_return_epc(regs);
1da177e4 1152 value = regs->regs[insn.i_format.rt];
6eae3548
MC		 1153
1154 if (config_enabled(CONFIG_EVA)) {
1155 if (segment_eq(get_fs(), get_ds()))
1156 StoreW(addr, value, res);
1157 else
1158 StoreWE(addr, value, res);
1159 } else {
1160 StoreW(addr, value, res);
1161 }
1162
1da177e4
LT		 1163 if (res)
1164 goto fault;
1165 break;
1166
1167 case sd_op:
875d43e7 1168#ifdef CONFIG_64BIT
1da177e4
LT		 1169 /*
1170 * A 32-bit kernel might be running on a 64-bit processor. But
1171 * if we're on a 32-bit processor and an i-cache incoherency
1172 * or race makes us see a 64-bit instruction here the sdl/sdr
1173 * would blow up, so for now we don't handle unaligned 64-bit
1174 * instructions on 32-bit kernels.
1175 */
1176 if (!access_ok(VERIFY_WRITE, addr, 8))
1177 goto sigbus;
1178
34c2f668 1179 compute_return_epc(regs);
1da177e4 1180 value = regs->regs[insn.i_format.rt];
34c2f668 1181 StoreDW(addr, value, res);
1da177e4
LT		 1182 if (res)
1183 goto fault;
1184 break;
875d43e7 1185#endif /* CONFIG_64BIT */
1da177e4
LT		 1186
1187 /* Cannot handle 64-bit instructions in 32-bit kernel */
1188 goto sigill;
1189
1190 case lwc1_op:
1191 case ldc1_op:
1192 case swc1_op:
1193 case sdc1_op:
102cedc3
LY		 1194 die_if_kernel("Unaligned FP access in kernel code", regs);
1195 BUG_ON(!used_math());
102cedc3
LY		 1196
1197 lose_fpu(1); /* Save FPU state for the emulator. */
1198 res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1199 &fault_addr);
1200 own_fpu(1); /* Restore FPU state. */
1201
1202 /* Signal if something went wrong. */
304acb71 1203 process_fpemu_return(res, fault_addr, 0);
102cedc3
LY		 1204
1205 if (res == 0)
1206 break;
1207 return;
1da177e4 1208
e4aa1f15
LY		 1209 case msa_op:
1210 if (!cpu_has_msa)
1211 goto sigill;
1212
1213 /*
1214 * If we've reached this point then userland should have taken
1215 * the MSA disabled exception & initialised vector context at
1216 * some point in the past.
1217 */
1218 BUG_ON(!thread_msa_context_live());
1219
1220 df = insn.msa_mi10_format.df;
1221 wd = insn.msa_mi10_format.wd;
1222 fpr = &current->thread.fpu.fpr[wd];
1223
1224 switch (insn.msa_mi10_format.func) {
1225 case msa_ld_op:
1226 if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
1227 goto sigbus;
1228
1229 /*
1230 * Disable preemption to avoid a race between copying
1231 * state from userland, migrating to another CPU and
1232 * updating the hardware vector register below.
1233 */
1234 preempt_disable();
1235
1236 res = __copy_from_user_inatomic(fpr, addr,
1237 sizeof(*fpr));
1238 if (res)
1239 goto fault;
1240
1241 /*
1242 * Update the hardware register if it is in use by the
1243 * task in this quantum, in order to avoid having to
1244 * save & restore the whole vector context.
1245 */
1246 if (test_thread_flag(TIF_USEDMSA))
1247 write_msa_wr(wd, fpr, df);
1248
1249 preempt_enable();
1250 break;
1251
1252 case msa_st_op:
1253 if (!access_ok(VERIFY_WRITE, addr, sizeof(*fpr)))
1254 goto sigbus;
1255
1256 /*
1257 * Update from the hardware register if it is in use by
1258 * the task in this quantum, in order to avoid having to
1259 * save & restore the whole vector context.
1260 */
1261 preempt_disable();
1262 if (test_thread_flag(TIF_USEDMSA))
1263 read_msa_wr(wd, fpr, df);
1264 preempt_enable();
1265
1266 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
1267 if (res)
1268 goto fault;
1269 break;
1270
1271 default:
1272 goto sigbus;
1273 }
1274
1275 compute_return_epc(regs);
1276 break;
1277
0593a44c 1278#ifndef CONFIG_CPU_MIPSR6
69f3a7de
RB		 1279 /*
1280 * COP2 is available to implementor for application specific use.
1281 * It's up to applications to register a notifier chain and do
1282 * whatever they have to do, including possible sending of signals.
0593a44c
LY		 1283 *
1284 * This instruction has been reallocated in Release 6
69f3a7de 1285 */
1da177e4 1286 case lwc2_op:
69f3a7de
RB		 1287 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1288 break;
1289
1da177e4 1290 case ldc2_op:
69f3a7de
RB		 1291 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1292 break;
1293
1da177e4 1294 case swc2_op:
69f3a7de
RB		 1295 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1296 break;
1297
1da177e4 1298 case sdc2_op:
69f3a7de
RB		 1299 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1300 break;
0593a44c 1301#endif
1da177e4
LT		 1302 default:
1303 /*
1304 * Pheeee... We encountered an yet unknown instruction or
1305 * cache coherence problem. Die sucker, die ...
1306 */
1307 goto sigill;
1308 }
1309
6312e0ee 1310#ifdef CONFIG_DEBUG_FS
1da177e4
LT		 1311 unaligned_instructions++;
1312#endif
1313
7f18f151 1314 return;
1da177e4
LT		 1315
1316fault:
34c2f668
LY		 1317 /* roll back jump/branch */
1318 regs->cp0_epc = origpc;
1319 regs->regs[31] = orig31;
1320 /* Did we have an exception handler installed? */
1321 if (fixup_exception(regs))
1322 return;
1323
1324 die_if_kernel("Unhandled kernel unaligned access", regs);
1325 force_sig(SIGSEGV, current);
1326
1327 return;
1328
1329sigbus:
1330 die_if_kernel("Unhandled kernel unaligned access", regs);
1331 force_sig(SIGBUS, current);
1332
1333 return;
1334
1335sigill:
1336 die_if_kernel
1337 ("Unhandled kernel unaligned access or invalid instruction", regs);
1338 force_sig(SIGILL, current);
1339}
1340
1341/* Recode table from 16-bit register notation to 32-bit GPR. */
1342const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1343
1344/* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1345const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1346
74338805
DD		 1347static void emulate_load_store_microMIPS(struct pt_regs *regs,
1348 void __user *addr)
34c2f668
LY		 1349{
1350 unsigned long value;
1351 unsigned int res;
1352 int i;
1353 unsigned int reg = 0, rvar;
1354 unsigned long orig31;
1355 u16 __user *pc16;
1356 u16 halfword;
1357 unsigned int word;
1358 unsigned long origpc, contpc;
1359 union mips_instruction insn;
1360 struct mm_decoded_insn mminsn;
1361 void __user *fault_addr = NULL;
1362
1363 origpc = regs->cp0_epc;
1364 orig31 = regs->regs[31];
1365
1366 mminsn.micro_mips_mode = 1;
1367
1368 /*
1369 * This load never faults.
1370 */
1371 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1372 __get_user(halfword, pc16);
1373 pc16++;
1374 contpc = regs->cp0_epc + 2;
1375 word = ((unsigned int)halfword << 16);
1376 mminsn.pc_inc = 2;
1377
1378 if (!mm_insn_16bit(halfword)) {
1379 __get_user(halfword, pc16);
1380 pc16++;
1381 contpc = regs->cp0_epc + 4;
1382 mminsn.pc_inc = 4;
1383 word |= halfword;
1384 }
1385 mminsn.insn = word;
1386
1387 if (get_user(halfword, pc16))
1388 goto fault;
1389 mminsn.next_pc_inc = 2;
1390 word = ((unsigned int)halfword << 16);
1391
1392 if (!mm_insn_16bit(halfword)) {
1393 pc16++;
1394 if (get_user(halfword, pc16))
1395 goto fault;
1396 mminsn.next_pc_inc = 4;
1397 word |= halfword;
1398 }
1399 mminsn.next_insn = word;
1400
1401 insn = (union mips_instruction)(mminsn.insn);
1402 if (mm_isBranchInstr(regs, mminsn, &contpc))
1403 insn = (union mips_instruction)(mminsn.next_insn);
1404
1405 /* Parse instruction to find what to do */
1406
1407 switch (insn.mm_i_format.opcode) {
1408
1409 case mm_pool32a_op:
1410 switch (insn.mm_x_format.func) {
1411 case mm_lwxs_op:
1412 reg = insn.mm_x_format.rd;
1413 goto loadW;
1414 }
1415
1416 goto sigbus;
1417
1418 case mm_pool32b_op:
1419 switch (insn.mm_m_format.func) {
1420 case mm_lwp_func:
1421 reg = insn.mm_m_format.rd;
1422 if (reg == 31)
1423 goto sigbus;
1424
1425 if (!access_ok(VERIFY_READ, addr, 8))
1426 goto sigbus;
1427
1428 LoadW(addr, value, res);
1429 if (res)
1430 goto fault;
1431 regs->regs[reg] = value;
1432 addr += 4;
1433 LoadW(addr, value, res);
1434 if (res)
1435 goto fault;
1436 regs->regs[reg + 1] = value;
1437 goto success;
1438
1439 case mm_swp_func:
1440 reg = insn.mm_m_format.rd;
1441 if (reg == 31)
1442 goto sigbus;
1443
1444 if (!access_ok(VERIFY_WRITE, addr, 8))
1445 goto sigbus;
1446
1447 value = regs->regs[reg];
1448 StoreW(addr, value, res);
1449 if (res)
1450 goto fault;
1451 addr += 4;
1452 value = regs->regs[reg + 1];
1453 StoreW(addr, value, res);
1454 if (res)
1455 goto fault;
1456 goto success;
1457
1458 case mm_ldp_func:
1459#ifdef CONFIG_64BIT
1460 reg = insn.mm_m_format.rd;
1461 if (reg == 31)
1462 goto sigbus;
1463
1464 if (!access_ok(VERIFY_READ, addr, 16))
1465 goto sigbus;
1466
1467 LoadDW(addr, value, res);
1468 if (res)
1469 goto fault;
1470 regs->regs[reg] = value;
1471 addr += 8;
1472 LoadDW(addr, value, res);
1473 if (res)
1474 goto fault;
1475 regs->regs[reg + 1] = value;
1476 goto success;
1477#endif /* CONFIG_64BIT */
1478
1479 goto sigill;
1480
1481 case mm_sdp_func:
1482#ifdef CONFIG_64BIT
1483 reg = insn.mm_m_format.rd;
1484 if (reg == 31)
1485 goto sigbus;
1486
1487 if (!access_ok(VERIFY_WRITE, addr, 16))
1488 goto sigbus;
1489
1490 value = regs->regs[reg];
1491 StoreDW(addr, value, res);
1492 if (res)
1493 goto fault;
1494 addr += 8;
1495 value = regs->regs[reg + 1];
1496 StoreDW(addr, value, res);
1497 if (res)
1498 goto fault;
1499 goto success;
1500#endif /* CONFIG_64BIT */
1501
1502 goto sigill;
1503
1504 case mm_lwm32_func:
1505 reg = insn.mm_m_format.rd;
1506 rvar = reg & 0xf;
1507 if ((rvar > 9) || !reg)
1508 goto sigill;
1509 if (reg & 0x10) {
1510 if (!access_ok
1511 (VERIFY_READ, addr, 4 * (rvar + 1)))
1512 goto sigbus;
1513 } else {
1514 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1515 goto sigbus;
1516 }
1517 if (rvar == 9)
1518 rvar = 8;
1519 for (i = 16; rvar; rvar--, i++) {
1520 LoadW(addr, value, res);
1521 if (res)
1522 goto fault;
1523 addr += 4;
1524 regs->regs[i] = value;
1525 }
1526 if ((reg & 0xf) == 9) {
1527 LoadW(addr, value, res);
1528 if (res)
1529 goto fault;
1530 addr += 4;
1531 regs->regs[30] = value;
1532 }
1533 if (reg & 0x10) {
1534 LoadW(addr, value, res);
1535 if (res)
1536 goto fault;
1537 regs->regs[31] = value;
1538 }
1539 goto success;
1540
1541 case mm_swm32_func:
1542 reg = insn.mm_m_format.rd;
1543 rvar = reg & 0xf;
1544 if ((rvar > 9) || !reg)
1545 goto sigill;
1546 if (reg & 0x10) {
1547 if (!access_ok
1548 (VERIFY_WRITE, addr, 4 * (rvar + 1)))
1549 goto sigbus;
1550 } else {
1551 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1552 goto sigbus;
1553 }
1554 if (rvar == 9)
1555 rvar = 8;
1556 for (i = 16; rvar; rvar--, i++) {
1557 value = regs->regs[i];
1558 StoreW(addr, value, res);
1559 if (res)
1560 goto fault;
1561 addr += 4;
1562 }
1563 if ((reg & 0xf) == 9) {
1564 value = regs->regs[30];
1565 StoreW(addr, value, res);
1566 if (res)
1567 goto fault;
1568 addr += 4;
1569 }
1570 if (reg & 0x10) {
1571 value = regs->regs[31];
1572 StoreW(addr, value, res);
1573 if (res)
1574 goto fault;
1575 }
1576 goto success;
1577
1578 case mm_ldm_func:
1579#ifdef CONFIG_64BIT
1580 reg = insn.mm_m_format.rd;
1581 rvar = reg & 0xf;
1582 if ((rvar > 9) || !reg)
1583 goto sigill;
1584 if (reg & 0x10) {
1585 if (!access_ok
1586 (VERIFY_READ, addr, 8 * (rvar + 1)))
1587 goto sigbus;
1588 } else {
1589 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1590 goto sigbus;
1591 }
1592 if (rvar == 9)
1593 rvar = 8;
1594
1595 for (i = 16; rvar; rvar--, i++) {
1596 LoadDW(addr, value, res);
1597 if (res)
1598 goto fault;
1599 addr += 4;
1600 regs->regs[i] = value;
1601 }
1602 if ((reg & 0xf) == 9) {
1603 LoadDW(addr, value, res);
1604 if (res)
1605 goto fault;
1606 addr += 8;
1607 regs->regs[30] = value;
1608 }
1609 if (reg & 0x10) {
1610 LoadDW(addr, value, res);
1611 if (res)
1612 goto fault;
1613 regs->regs[31] = value;
1614 }
1615 goto success;
1616#endif /* CONFIG_64BIT */
1617
1618 goto sigill;
1619
1620 case mm_sdm_func:
1621#ifdef CONFIG_64BIT
1622 reg = insn.mm_m_format.rd;
1623 rvar = reg & 0xf;
1624 if ((rvar > 9) || !reg)
1625 goto sigill;
1626 if (reg & 0x10) {
1627 if (!access_ok
1628 (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1629 goto sigbus;
1630 } else {
1631 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1632 goto sigbus;
1633 }
1634 if (rvar == 9)
1635 rvar = 8;
1636
1637 for (i = 16; rvar; rvar--, i++) {
1638 value = regs->regs[i];
1639 StoreDW(addr, value, res);
1640 if (res)
1641 goto fault;
1642 addr += 8;
1643 }
1644 if ((reg & 0xf) == 9) {
1645 value = regs->regs[30];
1646 StoreDW(addr, value, res);
1647 if (res)
1648 goto fault;
1649 addr += 8;
1650 }
1651 if (reg & 0x10) {
1652 value = regs->regs[31];
1653 StoreDW(addr, value, res);
1654 if (res)
1655 goto fault;
1656 }
1657 goto success;
1658#endif /* CONFIG_64BIT */
1659
1660 goto sigill;
1661
1662 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1663 }
1664
1665 goto sigbus;
1666
1667 case mm_pool32c_op:
1668 switch (insn.mm_m_format.func) {
1669 case mm_lwu_func:
1670 reg = insn.mm_m_format.rd;
1671 goto loadWU;
1672 }
1673
1674 /* LL,SC,LLD,SCD are not serviced */
1675 goto sigbus;
1676
1677 case mm_pool32f_op:
1678 switch (insn.mm_x_format.func) {
1679 case mm_lwxc1_func:
1680 case mm_swxc1_func:
1681 case mm_ldxc1_func:
1682 case mm_sdxc1_func:
1683 goto fpu_emul;
1684 }
1685
1686 goto sigbus;
1687
1688 case mm_ldc132_op:
1689 case mm_sdc132_op:
1690 case mm_lwc132_op:
1691 case mm_swc132_op:
1692fpu_emul:
1693 /* roll back jump/branch */
1694 regs->cp0_epc = origpc;
1695 regs->regs[31] = orig31;
1696
1697 die_if_kernel("Unaligned FP access in kernel code", regs);
1698 BUG_ON(!used_math());
1699 BUG_ON(!is_fpu_owner());
1700
1701 lose_fpu(1); /* save the FPU state for the emulator */
1702 res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
1703 &fault_addr);
1704 own_fpu(1); /* restore FPU state */
1705
1706 /* If something went wrong, signal */
304acb71 1707 process_fpemu_return(res, fault_addr, 0);
34c2f668
LY		 1708
1709 if (res == 0)
1710 goto success;
1711 return;
1712
1713 case mm_lh32_op:
1714 reg = insn.mm_i_format.rt;
1715 goto loadHW;
1716
1717 case mm_lhu32_op:
1718 reg = insn.mm_i_format.rt;
1719 goto loadHWU;
1720
1721 case mm_lw32_op:
1722 reg = insn.mm_i_format.rt;
1723 goto loadW;
1724
1725 case mm_sh32_op:
1726 reg = insn.mm_i_format.rt;
1727 goto storeHW;
1728
1729 case mm_sw32_op:
1730 reg = insn.mm_i_format.rt;
1731 goto storeW;
1732
1733 case mm_ld32_op:
1734 reg = insn.mm_i_format.rt;
1735 goto loadDW;
1736
1737 case mm_sd32_op:
1738 reg = insn.mm_i_format.rt;
1739 goto storeDW;
1740
1741 case mm_pool16c_op:
1742 switch (insn.mm16_m_format.func) {
1743 case mm_lwm16_op:
1744 reg = insn.mm16_m_format.rlist;
1745 rvar = reg + 1;
1746 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1747 goto sigbus;
1748
1749 for (i = 16; rvar; rvar--, i++) {
1750 LoadW(addr, value, res);
1751 if (res)
1752 goto fault;
1753 addr += 4;
1754 regs->regs[i] = value;
1755 }
1756 LoadW(addr, value, res);
1757 if (res)
1758 goto fault;
1759 regs->regs[31] = value;
1760
1761 goto success;
1762
1763 case mm_swm16_op:
1764 reg = insn.mm16_m_format.rlist;
1765 rvar = reg + 1;
1766 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1767 goto sigbus;
1768
1769 for (i = 16; rvar; rvar--, i++) {
1770 value = regs->regs[i];
1771 StoreW(addr, value, res);
1772 if (res)
1773 goto fault;
1774 addr += 4;
1775 }
1776 value = regs->regs[31];
1777 StoreW(addr, value, res);
1778 if (res)
1779 goto fault;
1780
1781 goto success;
1782
1783 }
1784
1785 goto sigbus;
1786
1787 case mm_lhu16_op:
1788 reg = reg16to32[insn.mm16_rb_format.rt];
1789 goto loadHWU;
1790
1791 case mm_lw16_op:
1792 reg = reg16to32[insn.mm16_rb_format.rt];
1793 goto loadW;
1794
1795 case mm_sh16_op:
1796 reg = reg16to32st[insn.mm16_rb_format.rt];
1797 goto storeHW;
1798
1799 case mm_sw16_op:
1800 reg = reg16to32st[insn.mm16_rb_format.rt];
1801 goto storeW;
1802
1803 case mm_lwsp16_op:
1804 reg = insn.mm16_r5_format.rt;
1805 goto loadW;
1806
1807 case mm_swsp16_op:
1808 reg = insn.mm16_r5_format.rt;
1809 goto storeW;
1810
1811 case mm_lwgp16_op:
1812 reg = reg16to32[insn.mm16_r3_format.rt];
1813 goto loadW;
1814
1815 default:
1816 goto sigill;
1817 }
1818
1819loadHW:
1820 if (!access_ok(VERIFY_READ, addr, 2))
1821 goto sigbus;
1822
1823 LoadHW(addr, value, res);
1824 if (res)
1825 goto fault;
1826 regs->regs[reg] = value;
1827 goto success;
1828
1829loadHWU:
1830 if (!access_ok(VERIFY_READ, addr, 2))
1831 goto sigbus;
1832
1833 LoadHWU(addr, value, res);
1834 if (res)
1835 goto fault;
1836 regs->regs[reg] = value;
1837 goto success;
1838
1839loadW:
1840 if (!access_ok(VERIFY_READ, addr, 4))
1841 goto sigbus;
1842
1843 LoadW(addr, value, res);
1844 if (res)
1845 goto fault;
1846 regs->regs[reg] = value;
1847 goto success;
1848
1849loadWU:
1850#ifdef CONFIG_64BIT
1851 /*
1852 * A 32-bit kernel might be running on a 64-bit processor. But
1853 * if we're on a 32-bit processor and an i-cache incoherency
1854 * or race makes us see a 64-bit instruction here the sdl/sdr
1855 * would blow up, so for now we don't handle unaligned 64-bit
1856 * instructions on 32-bit kernels.
1857 */
1858 if (!access_ok(VERIFY_READ, addr, 4))
1859 goto sigbus;
1860
1861 LoadWU(addr, value, res);
1862 if (res)
1863 goto fault;
1864 regs->regs[reg] = value;
1865 goto success;
1866#endif /* CONFIG_64BIT */
1867
1868 /* Cannot handle 64-bit instructions in 32-bit kernel */
1869 goto sigill;
1870
1871loadDW:
1872#ifdef CONFIG_64BIT
1873 /*
1874 * A 32-bit kernel might be running on a 64-bit processor. But
1875 * if we're on a 32-bit processor and an i-cache incoherency
1876 * or race makes us see a 64-bit instruction here the sdl/sdr
1877 * would blow up, so for now we don't handle unaligned 64-bit
1878 * instructions on 32-bit kernels.
1879 */
1880 if (!access_ok(VERIFY_READ, addr, 8))
1881 goto sigbus;
1882
1883 LoadDW(addr, value, res);
1884 if (res)
1885 goto fault;
1886 regs->regs[reg] = value;
1887 goto success;
1888#endif /* CONFIG_64BIT */
1889
1890 /* Cannot handle 64-bit instructions in 32-bit kernel */
1891 goto sigill;
1892
1893storeHW:
1894 if (!access_ok(VERIFY_WRITE, addr, 2))
1895 goto sigbus;
1896
1897 value = regs->regs[reg];
1898 StoreHW(addr, value, res);
1899 if (res)
1900 goto fault;
1901 goto success;
1902
1903storeW:
1904 if (!access_ok(VERIFY_WRITE, addr, 4))
1905 goto sigbus;
1906
1907 value = regs->regs[reg];
1908 StoreW(addr, value, res);
1909 if (res)
1910 goto fault;
1911 goto success;
1912
1913storeDW:
1914#ifdef CONFIG_64BIT
1915 /*
1916 * A 32-bit kernel might be running on a 64-bit processor. But
1917 * if we're on a 32-bit processor and an i-cache incoherency
1918 * or race makes us see a 64-bit instruction here the sdl/sdr
1919 * would blow up, so for now we don't handle unaligned 64-bit
1920 * instructions on 32-bit kernels.
1921 */
1922 if (!access_ok(VERIFY_WRITE, addr, 8))
1923 goto sigbus;
1924
1925 value = regs->regs[reg];
1926 StoreDW(addr, value, res);
1927 if (res)
1928 goto fault;
1929 goto success;
1930#endif /* CONFIG_64BIT */
1931
1932 /* Cannot handle 64-bit instructions in 32-bit kernel */
1933 goto sigill;
1934
1935success:
1936 regs->cp0_epc = contpc; /* advance or branch */
1937
1938#ifdef CONFIG_DEBUG_FS
1939 unaligned_instructions++;
1940#endif
1941 return;
1942
1943fault:
1944 /* roll back jump/branch */
1945 regs->cp0_epc = origpc;
1946 regs->regs[31] = orig31;
1da177e4
LT		 1947 /* Did we have an exception handler installed? */
1948 if (fixup_exception(regs))
7f18f151 1949 return;
1da177e4 1950
49a89efb 1951 die_if_kernel("Unhandled kernel unaligned access", regs);
a6d5ff04 1952 force_sig(SIGSEGV, current);
1da177e4 1953
7f18f151 1954 return;
1da177e4
LT		 1955
1956sigbus:
1957 die_if_kernel("Unhandled kernel unaligned access", regs);
a6d5ff04 1958 force_sig(SIGBUS, current);
1da177e4 1959
7f18f151 1960 return;
1da177e4
LT		 1961
1962sigill:
34c2f668
LY		 1963 die_if_kernel
1964 ("Unhandled kernel unaligned access or invalid instruction", regs);
a6d5ff04 1965 force_sig(SIGILL, current);
1da177e4
LT		 1966}
1967
451b001b
SH		 1968static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1969{
1970 unsigned long value;
1971 unsigned int res;
1972 int reg;
1973 unsigned long orig31;
1974 u16 __user *pc16;
1975 unsigned long origpc;
1976 union mips16e_instruction mips16inst, oldinst;
1977
1978 origpc = regs->cp0_epc;
1979 orig31 = regs->regs[31];
1980 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1981 /*
1982 * This load never faults.
1983 */
1984 __get_user(mips16inst.full, pc16);
1985 oldinst = mips16inst;
1986
1987 /* skip EXTEND instruction */
1988 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1989 pc16++;
1990 __get_user(mips16inst.full, pc16);
1991 } else if (delay_slot(regs)) {
1992 /* skip jump instructions */
1993 /* JAL/JALX are 32 bits but have OPCODE in first short int */
1994 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1995 pc16++;
1996 pc16++;
1997 if (get_user(mips16inst.full, pc16))
1998 goto sigbus;
1999 }
2000
2001 switch (mips16inst.ri.opcode) {
2002 case MIPS16e_i64_op: /* I64 or RI64 instruction */
2003 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
2004 case MIPS16e_ldpc_func:
2005 case MIPS16e_ldsp_func:
2006 reg = reg16to32[mips16inst.ri64.ry];
2007 goto loadDW;
2008
2009 case MIPS16e_sdsp_func:
2010 reg = reg16to32[mips16inst.ri64.ry];
2011 goto writeDW;
2012
2013 case MIPS16e_sdrasp_func:
2014 reg = 29; /* GPRSP */
2015 goto writeDW;
2016 }
2017
2018 goto sigbus;
2019
2020 case MIPS16e_swsp_op:
2021 case MIPS16e_lwpc_op:
2022 case MIPS16e_lwsp_op:
2023 reg = reg16to32[mips16inst.ri.rx];
2024 break;
2025
2026 case MIPS16e_i8_op:
2027 if (mips16inst.i8.func != MIPS16e_swrasp_func)
2028 goto sigbus;
2029 reg = 29; /* GPRSP */
2030 break;
2031
2032 default:
2033 reg = reg16to32[mips16inst.rri.ry];
2034 break;
2035 }
2036
2037 switch (mips16inst.ri.opcode) {
2038
2039 case MIPS16e_lb_op:
2040 case MIPS16e_lbu_op:
2041 case MIPS16e_sb_op:
2042 goto sigbus;
2043
2044 case MIPS16e_lh_op:
2045 if (!access_ok(VERIFY_READ, addr, 2))
2046 goto sigbus;
2047
2048 LoadHW(addr, value, res);
2049 if (res)
2050 goto fault;
2051 MIPS16e_compute_return_epc(regs, &oldinst);
2052 regs->regs[reg] = value;
2053 break;
2054
2055 case MIPS16e_lhu_op:
2056 if (!access_ok(VERIFY_READ, addr, 2))
2057 goto sigbus;
2058
2059 LoadHWU(addr, value, res);
2060 if (res)
2061 goto fault;
2062 MIPS16e_compute_return_epc(regs, &oldinst);
2063 regs->regs[reg] = value;
2064 break;
2065
2066 case MIPS16e_lw_op:
2067 case MIPS16e_lwpc_op:
2068 case MIPS16e_lwsp_op:
2069 if (!access_ok(VERIFY_READ, addr, 4))
2070 goto sigbus;
2071
2072 LoadW(addr, value, res);
2073 if (res)
2074 goto fault;
2075 MIPS16e_compute_return_epc(regs, &oldinst);
2076 regs->regs[reg] = value;
2077 break;
2078
2079 case MIPS16e_lwu_op:
2080#ifdef CONFIG_64BIT
2081 /*
2082 * A 32-bit kernel might be running on a 64-bit processor. But
2083 * if we're on a 32-bit processor and an i-cache incoherency
2084 * or race makes us see a 64-bit instruction here the sdl/sdr
2085 * would blow up, so for now we don't handle unaligned 64-bit
2086 * instructions on 32-bit kernels.
2087 */
2088 if (!access_ok(VERIFY_READ, addr, 4))
2089 goto sigbus;
2090
2091 LoadWU(addr, value, res);
2092 if (res)
2093 goto fault;
2094 MIPS16e_compute_return_epc(regs, &oldinst);
2095 regs->regs[reg] = value;
2096 break;
2097#endif /* CONFIG_64BIT */
2098
2099 /* Cannot handle 64-bit instructions in 32-bit kernel */
2100 goto sigill;
2101
2102 case MIPS16e_ld_op:
2103loadDW:
2104#ifdef CONFIG_64BIT
2105 /*
2106 * A 32-bit kernel might be running on a 64-bit processor. But
2107 * if we're on a 32-bit processor and an i-cache incoherency
2108 * or race makes us see a 64-bit instruction here the sdl/sdr
2109 * would blow up, so for now we don't handle unaligned 64-bit
2110 * instructions on 32-bit kernels.
2111 */
2112 if (!access_ok(VERIFY_READ, addr, 8))
2113 goto sigbus;
2114
2115 LoadDW(addr, value, res);
2116 if (res)
2117 goto fault;
2118 MIPS16e_compute_return_epc(regs, &oldinst);
2119 regs->regs[reg] = value;
2120 break;
2121#endif /* CONFIG_64BIT */
2122
2123 /* Cannot handle 64-bit instructions in 32-bit kernel */
2124 goto sigill;
2125
2126 case MIPS16e_sh_op:
2127 if (!access_ok(VERIFY_WRITE, addr, 2))
2128 goto sigbus;
2129
2130 MIPS16e_compute_return_epc(regs, &oldinst);
2131 value = regs->regs[reg];
2132 StoreHW(addr, value, res);
2133 if (res)
2134 goto fault;
2135 break;
2136
2137 case MIPS16e_sw_op:
2138 case MIPS16e_swsp_op:
2139 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
2140 if (!access_ok(VERIFY_WRITE, addr, 4))
2141 goto sigbus;
2142
2143 MIPS16e_compute_return_epc(regs, &oldinst);
2144 value = regs->regs[reg];
2145 StoreW(addr, value, res);
2146 if (res)
2147 goto fault;
2148 break;
2149
2150 case MIPS16e_sd_op:
2151writeDW:
2152#ifdef CONFIG_64BIT
2153 /*
2154 * A 32-bit kernel might be running on a 64-bit processor. But
2155 * if we're on a 32-bit processor and an i-cache incoherency
2156 * or race makes us see a 64-bit instruction here the sdl/sdr
2157 * would blow up, so for now we don't handle unaligned 64-bit
2158 * instructions on 32-bit kernels.
2159 */
2160 if (!access_ok(VERIFY_WRITE, addr, 8))
2161 goto sigbus;
2162
2163 MIPS16e_compute_return_epc(regs, &oldinst);
2164 value = regs->regs[reg];
2165 StoreDW(addr, value, res);
2166 if (res)
2167 goto fault;
2168 break;
2169#endif /* CONFIG_64BIT */
2170
2171 /* Cannot handle 64-bit instructions in 32-bit kernel */
2172 goto sigill;
2173
2174 default:
2175 /*
2176 * Pheeee... We encountered an yet unknown instruction or
2177 * cache coherence problem. Die sucker, die ...
2178 */
2179 goto sigill;
2180 }
2181
2182#ifdef CONFIG_DEBUG_FS
2183 unaligned_instructions++;
2184#endif
2185
2186 return;
2187
2188fault:
2189 /* roll back jump/branch */
2190 regs->cp0_epc = origpc;
2191 regs->regs[31] = orig31;
2192 /* Did we have an exception handler installed? */
2193 if (fixup_exception(regs))
2194 return;
2195
2196 die_if_kernel("Unhandled kernel unaligned access", regs);
2197 force_sig(SIGSEGV, current);
2198
2199 return;
2200
2201sigbus:
2202 die_if_kernel("Unhandled kernel unaligned access", regs);
2203 force_sig(SIGBUS, current);
2204
2205 return;
2206
2207sigill:
2208 die_if_kernel
2209 ("Unhandled kernel unaligned access or invalid instruction", regs);
2210 force_sig(SIGILL, current);
2211}
fc192e50 2212
1da177e4
LT		 2213asmlinkage void do_ade(struct pt_regs *regs)
2214{
c3fc5cd5 2215 enum ctx_state prev_state;
fe00f943 2216 unsigned int __user *pc;
1da177e4 2217 mm_segment_t seg;
1da177e4 2218
c3fc5cd5 2219 prev_state = exception_enter();
7f788d2d 2220 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
a8b0ca17 2221 1, regs, regs->cp0_badvaddr);
1da177e4
LT		 2222 /*
2223 * Did we catch a fault trying to load an instruction?
1da177e4 2224 */
34c2f668 2225 if (regs->cp0_badvaddr == regs->cp0_epc)
1da177e4
LT		 2226 goto sigbus;
2227
293c5bd1 2228 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
1da177e4 2229 goto sigbus;
6312e0ee
AN		 2230 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2231 goto sigbus;
1da177e4
LT		 2232
2233 /*
2234 * Do branch emulation only if we didn't forward the exception.
2235 * This is all so but ugly ...
2236 */
34c2f668
LY		 2237
2238 /*
2239 * Are we running in microMIPS mode?
2240 */
2241 if (get_isa16_mode(regs->cp0_epc)) {
2242 /*
2243 * Did we catch a fault trying to load an instruction in
2244 * 16-bit mode?
2245 */
2246 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2247 goto sigbus;
2248 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2249 show_registers(regs);
2250
2251 if (cpu_has_mmips) {
2252 seg = get_fs();
2253 if (!user_mode(regs))
2254 set_fs(KERNEL_DS);
2255 emulate_load_store_microMIPS(regs,
2256 (void __user *)regs->cp0_badvaddr);
2257 set_fs(seg);
2258
2259 return;
2260 }
2261
451b001b
SH		 2262 if (cpu_has_mips16) {
2263 seg = get_fs();
2264 if (!user_mode(regs))
2265 set_fs(KERNEL_DS);
2266 emulate_load_store_MIPS16e(regs,
2267 (void __user *)regs->cp0_badvaddr);
2268 set_fs(seg);
2269
2270 return;
2271 }
2272
34c2f668
LY		 2273 goto sigbus;
2274 }
2275
2276 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2277 show_registers(regs);
2278 pc = (unsigned int __user *)exception_epc(regs);
2279
1da177e4
LT		 2280 seg = get_fs();
2281 if (!user_mode(regs))
2282 set_fs(KERNEL_DS);
7f18f151 2283 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
1da177e4
LT		 2284 set_fs(seg);
2285
2286 return;
2287
2288sigbus:
2289 die_if_kernel("Kernel unaligned instruction access", regs);
2290 force_sig(SIGBUS, current);
2291
2292 /*
2293 * XXX On return from the signal handler we should advance the epc
2294 */
c3fc5cd5 2295 exception_exit(prev_state);
1da177e4 2296}
6312e0ee
AN		 2297
2298#ifdef CONFIG_DEBUG_FS
6312e0ee
AN		 2299static int __init debugfs_unaligned(void)
2300{
2301 struct dentry *d;
2302
2303 if (!mips_debugfs_dir)
2304 return -ENODEV;
2305 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
2306 mips_debugfs_dir, &unaligned_instructions);
b517531c
Z		 2307 if (!d)
2308 return -ENOMEM;
6312e0ee
AN		 2309 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2310 mips_debugfs_dir, &unaligned_action);
b517531c
Z		 2311 if (!d)
2312 return -ENOMEM;
6312e0ee
AN		 2313 return 0;
2314}
8d6b591c 2315arch_initcall(debugfs_unaligned);
6312e0ee 2316#endif
Linux kernel - Deliverables
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