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KVM: Use simple waitqueue for vcpu->wq
[deliverable/linux.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e
SL		 11
12#include <linux/errno.h>
13#include <linux/err.h>
98e91b84 14#include <linux/kdebug.h>
669e846e
SL		 15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
f798217d 19#include <asm/fpu.h>
669e846e
SL		 20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
c4c6f2ca 23#include <asm/pgtable.h>
669e846e
SL		 24
25#include <linux/kvm_host.h>
26
d7d5b05f
DCZ		 27#include "interrupt.h"
28#include "commpage.h"
669e846e
SL		 29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
d116e812 37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 38struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
c2537ed9 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
1c0cd66a 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
c2537ed9 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
d116e812 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
62bea5bf 58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
d116e812 59 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 60 {NULL}
61};
62
63static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
64{
65 int i;
d116e812 66
669e846e
SL		 67 for_each_possible_cpu(i) {
68 vcpu->arch.guest_kernel_asid[i] = 0;
69 vcpu->arch.guest_user_asid[i] = 0;
70 }
d116e812 71
669e846e
SL		 72 return 0;
73}
74
d116e812
DCZ		 75/*
76 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
77 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 78 */
79int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
80{
81 return !!(vcpu->arch.pending_exceptions);
82}
83
84int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
85{
86 return 1;
87}
88
13a34e06 89int kvm_arch_hardware_enable(void)
669e846e
SL		 90{
91 return 0;
92}
93
669e846e
SL		 94int kvm_arch_hardware_setup(void)
95{
96 return 0;
97}
98
669e846e
SL		 99void kvm_arch_check_processor_compat(void *rtn)
100{
d98403a5 101 *(int *)rtn = 0;
669e846e
SL		 102}
103
104static void kvm_mips_init_tlbs(struct kvm *kvm)
105{
106 unsigned long wired;
107
d116e812
DCZ		 108 /*
109 * Add a wired entry to the TLB, it is used to map the commpage to
110 * the Guest kernel
111 */
669e846e
SL		 112 wired = read_c0_wired();
113 write_c0_wired(wired + 1);
114 mtc0_tlbw_hazard();
115 kvm->arch.commpage_tlb = wired;
116
117 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
118 kvm->arch.commpage_tlb);
119}
120
121static void kvm_mips_init_vm_percpu(void *arg)
122{
123 struct kvm *kvm = (struct kvm *)arg;
124
125 kvm_mips_init_tlbs(kvm);
126 kvm_mips_callbacks->vm_init(kvm);
127
128}
129
130int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
131{
132 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 133 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
134 __func__);
669e846e
SL		 135 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
136 }
137
669e846e
SL		 138 return 0;
139}
140
141void kvm_mips_free_vcpus(struct kvm *kvm)
142{
143 unsigned int i;
144 struct kvm_vcpu *vcpu;
145
146 /* Put the pages we reserved for the guest pmap */
147 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
148 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
149 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
150 }
c6c0a663 151 kfree(kvm->arch.guest_pmap);
669e846e
SL		 152
153 kvm_for_each_vcpu(i, vcpu, kvm) {
154 kvm_arch_vcpu_free(vcpu);
155 }
156
157 mutex_lock(&kvm->lock);
158
159 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
160 kvm->vcpus[i] = NULL;
161
162 atomic_set(&kvm->online_vcpus, 0);
163
164 mutex_unlock(&kvm->lock);
165}
166
669e846e
SL		 167static void kvm_mips_uninit_tlbs(void *arg)
168{
169 /* Restore wired count */
170 write_c0_wired(0);
171 mtc0_tlbw_hazard();
172 /* Clear out all the TLBs */
173 kvm_local_flush_tlb_all();
174}
175
176void kvm_arch_destroy_vm(struct kvm *kvm)
177{
178 kvm_mips_free_vcpus(kvm);
179
180 /* If this is the last instance, restore wired count */
181 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 182 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
183 __func__);
669e846e
SL		 184 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
185 }
186}
187
d116e812
DCZ		 188long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
189 unsigned long arg)
669e846e 190{
ed829857 191 return -ENOIOCTLCMD;
669e846e
SL		 192}
193
5587027c
AK		 194int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
195 unsigned long npages)
669e846e
SL		 196{
197 return 0;
198}
199
200int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812 201 struct kvm_memory_slot *memslot,
09170a49 202 const struct kvm_userspace_memory_region *mem,
d116e812 203 enum kvm_mr_change change)
669e846e
SL		 204{
205 return 0;
206}
207
208void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 209 const struct kvm_userspace_memory_region *mem,
d116e812 210 const struct kvm_memory_slot *old,
f36f3f28 211 const struct kvm_memory_slot *new,
d116e812 212 enum kvm_mr_change change)
669e846e
SL		 213{
214 unsigned long npages = 0;
d98403a5 215 int i;
669e846e
SL		 216
217 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
218 __func__, kvm, mem->slot, mem->guest_phys_addr,
219 mem->memory_size, mem->userspace_addr);
220
221 /* Setup Guest PMAP table */
222 if (!kvm->arch.guest_pmap) {
223 if (mem->slot == 0)
224 npages = mem->memory_size >> PAGE_SHIFT;
225
226 if (npages) {
227 kvm->arch.guest_pmap_npages = npages;
228 kvm->arch.guest_pmap =
229 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
230
231 if (!kvm->arch.guest_pmap) {
f7fdcb60 232 kvm_err("Failed to allocate guest PMAP\n");
d98403a5 233 return;
669e846e
SL		 234 }
235
6e95bfd2
JH		 236 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
237 npages, kvm->arch.guest_pmap);
669e846e
SL		 238
239 /* Now setup the page table */
d116e812 240 for (i = 0; i < npages; i++)
669e846e 241 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 242 }
243 }
669e846e
SL		 244}
245
669e846e
SL		 246struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
247{
669e846e
SL		 248 int err, size, offset;
249 void *gebase;
250 int i;
251
252 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
253
254 if (!vcpu) {
255 err = -ENOMEM;
256 goto out;
257 }
258
259 err = kvm_vcpu_init(vcpu, kvm, id);
260
261 if (err)
262 goto out_free_cpu;
263
6e95bfd2 264 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 265
d116e812
DCZ		 266 /*
267 * Allocate space for host mode exception handlers that handle
669e846e
SL		 268 * guest mode exits
269 */
d116e812 270 if (cpu_has_veic || cpu_has_vint)
669e846e 271 size = 0x200 + VECTORSPACING * 64;
d116e812 272 else
7006e2df 273 size = 0x4000;
669e846e
SL		 274
275 /* Save Linux EBASE */
276 vcpu->arch.host_ebase = (void *)read_c0_ebase();
277
278 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
279
280 if (!gebase) {
281 err = -ENOMEM;
585bb8f9 282 goto out_uninit_cpu;
669e846e 283 }
6e95bfd2
JH		 284 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
285 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 286
287 /* Save new ebase */
288 vcpu->arch.guest_ebase = gebase;
289
290 /* Copy L1 Guest Exception handler to correct offset */
291
292 /* TLB Refill, EXL = 0 */
293 memcpy(gebase, mips32_exception,
294 mips32_exceptionEnd - mips32_exception);
295
296 /* General Exception Entry point */
297 memcpy(gebase + 0x180, mips32_exception,
298 mips32_exceptionEnd - mips32_exception);
299
300 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
301 for (i = 0; i < 8; i++) {
302 kvm_debug("L1 Vectored handler @ %p\n",
303 gebase + 0x200 + (i * VECTORSPACING));
304 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
305 mips32_exceptionEnd - mips32_exception);
306 }
307
308 /* General handler, relocate to unmapped space for sanity's sake */
309 offset = 0x2000;
6e95bfd2
JH		 310 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
311 gebase + offset,
312 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 313
314 memcpy(gebase + offset, mips32_GuestException,
315 mips32_GuestExceptionEnd - mips32_GuestException);
316
317 /* Invalidate the icache for these ranges */
facaaec1
JH		 318 local_flush_icache_range((unsigned long)gebase,
319 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 320
d116e812
DCZ		 321 /*
322 * Allocate comm page for guest kernel, a TLB will be reserved for
323 * mapping GVA @ 0xFFFF8000 to this page
324 */
669e846e
SL		 325 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
326
327 if (!vcpu->arch.kseg0_commpage) {
328 err = -ENOMEM;
329 goto out_free_gebase;
330 }
331
6e95bfd2 332 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 333 kvm_mips_commpage_init(vcpu);
334
335 /* Init */
336 vcpu->arch.last_sched_cpu = -1;
337
338 /* Start off the timer */
e30492bb 339 kvm_mips_init_count(vcpu);
669e846e
SL		 340
341 return vcpu;
342
343out_free_gebase:
344 kfree(gebase);
345
585bb8f9
JH		 346out_uninit_cpu:
347 kvm_vcpu_uninit(vcpu);
348
669e846e
SL		 349out_free_cpu:
350 kfree(vcpu);
351
352out:
353 return ERR_PTR(err);
354}
355
356void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
357{
358 hrtimer_cancel(&vcpu->arch.comparecount_timer);
359
360 kvm_vcpu_uninit(vcpu);
361
362 kvm_mips_dump_stats(vcpu);
363
c6c0a663
JH		 364 kfree(vcpu->arch.guest_ebase);
365 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 366 kfree(vcpu);
669e846e
SL		 367}
368
369void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
370{
371 kvm_arch_vcpu_free(vcpu);
372}
373
d116e812
DCZ		 374int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
375 struct kvm_guest_debug *dbg)
669e846e 376{
ed829857 377 return -ENOIOCTLCMD;
669e846e
SL		 378}
379
380int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
381{
382 int r = 0;
383 sigset_t sigsaved;
384
385 if (vcpu->sigset_active)
386 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
387
388 if (vcpu->mmio_needed) {
389 if (!vcpu->mmio_is_write)
390 kvm_mips_complete_mmio_load(vcpu, run);
391 vcpu->mmio_needed = 0;
392 }
393
f798217d
JH		 394 lose_fpu(1);
395
044f0f03 396 local_irq_disable();
669e846e
SL		 397 /* Check if we have any exceptions/interrupts pending */
398 kvm_mips_deliver_interrupts(vcpu,
399 kvm_read_c0_guest_cause(vcpu->arch.cop0));
400
ccf73aaf 401 __kvm_guest_enter();
669e846e 402
c4c6f2ca
JH		 403 /* Disable hardware page table walking while in guest */
404 htw_stop();
405
669e846e
SL		 406 r = __kvm_mips_vcpu_run(run, vcpu);
407
c4c6f2ca
JH		 408 /* Re-enable HTW before enabling interrupts */
409 htw_start();
410
ccf73aaf 411 __kvm_guest_exit();
669e846e
SL		 412 local_irq_enable();
413
414 if (vcpu->sigset_active)
415 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
416
417 return r;
418}
419
d116e812
DCZ		 420int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
421 struct kvm_mips_interrupt *irq)
669e846e
SL		 422{
423 int intr = (int)irq->irq;
424 struct kvm_vcpu *dvcpu = NULL;
425
426 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
427 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
428 (int)intr);
429
430 if (irq->cpu == -1)
431 dvcpu = vcpu;
432 else
433 dvcpu = vcpu->kvm->vcpus[irq->cpu];
434
435 if (intr == 2 || intr == 3 || intr == 4) {
436 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
437
438 } else if (intr == -2 || intr == -3 || intr == -4) {
439 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
440 } else {
441 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
442 irq->cpu, irq->irq);
443 return -EINVAL;
444 }
445
446 dvcpu->arch.wait = 0;
447
8577370f
MT		 448 if (swait_active(&dvcpu->wq))
449 swake_up(&dvcpu->wq);
669e846e
SL		 450
451 return 0;
452}
453
d116e812
DCZ		 454int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
455 struct kvm_mp_state *mp_state)
669e846e 456{
ed829857 457 return -ENOIOCTLCMD;
669e846e
SL		 458}
459
d116e812
DCZ		 460int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
461 struct kvm_mp_state *mp_state)
669e846e 462{
ed829857 463 return -ENOIOCTLCMD;
669e846e
SL		 464}
465
4c73fb2b
DD		 466static u64 kvm_mips_get_one_regs[] = {
467 KVM_REG_MIPS_R0,
468 KVM_REG_MIPS_R1,
469 KVM_REG_MIPS_R2,
470 KVM_REG_MIPS_R3,
471 KVM_REG_MIPS_R4,
472 KVM_REG_MIPS_R5,
473 KVM_REG_MIPS_R6,
474 KVM_REG_MIPS_R7,
475 KVM_REG_MIPS_R8,
476 KVM_REG_MIPS_R9,
477 KVM_REG_MIPS_R10,
478 KVM_REG_MIPS_R11,
479 KVM_REG_MIPS_R12,
480 KVM_REG_MIPS_R13,
481 KVM_REG_MIPS_R14,
482 KVM_REG_MIPS_R15,
483 KVM_REG_MIPS_R16,
484 KVM_REG_MIPS_R17,
485 KVM_REG_MIPS_R18,
486 KVM_REG_MIPS_R19,
487 KVM_REG_MIPS_R20,
488 KVM_REG_MIPS_R21,
489 KVM_REG_MIPS_R22,
490 KVM_REG_MIPS_R23,
491 KVM_REG_MIPS_R24,
492 KVM_REG_MIPS_R25,
493 KVM_REG_MIPS_R26,
494 KVM_REG_MIPS_R27,
495 KVM_REG_MIPS_R28,
496 KVM_REG_MIPS_R29,
497 KVM_REG_MIPS_R30,
498 KVM_REG_MIPS_R31,
499
500 KVM_REG_MIPS_HI,
501 KVM_REG_MIPS_LO,
502 KVM_REG_MIPS_PC,
503
504 KVM_REG_MIPS_CP0_INDEX,
505 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 506 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 507 KVM_REG_MIPS_CP0_PAGEMASK,
508 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 509 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 510 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 511 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 512 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 513 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 514 KVM_REG_MIPS_CP0_STATUS,
515 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 516 KVM_REG_MIPS_CP0_EPC,
1068eaaf 517 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 518 KVM_REG_MIPS_CP0_CONFIG,
519 KVM_REG_MIPS_CP0_CONFIG1,
520 KVM_REG_MIPS_CP0_CONFIG2,
521 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 522 KVM_REG_MIPS_CP0_CONFIG4,
523 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 524 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 525 KVM_REG_MIPS_CP0_ERROREPC,
526
527 KVM_REG_MIPS_COUNT_CTL,
528 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 529 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 530};
531
532static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
533 const struct kvm_one_reg *reg)
534{
4c73fb2b 535 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd 536 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
f8be02da 537 int ret;
4c73fb2b 538 s64 v;
ab86bd60 539 s64 vs[2];
379245cd 540 unsigned int idx;
4c73fb2b
DD		 541
542 switch (reg->id) {
379245cd 543 /* General purpose registers */
4c73fb2b
DD		 544 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
545 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
546 break;
547 case KVM_REG_MIPS_HI:
548 v = (long)vcpu->arch.hi;
549 break;
550 case KVM_REG_MIPS_LO:
551 v = (long)vcpu->arch.lo;
552 break;
553 case KVM_REG_MIPS_PC:
554 v = (long)vcpu->arch.pc;
555 break;
556
379245cd
JH		 557 /* Floating point registers */
558 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
559 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
560 return -EINVAL;
561 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
562 /* Odd singles in top of even double when FR=0 */
563 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
564 v = get_fpr32(&fpu->fpr[idx], 0);
565 else
566 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
567 break;
568 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
569 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
570 return -EINVAL;
571 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
572 /* Can't access odd doubles in FR=0 mode */
573 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
574 return -EINVAL;
575 v = get_fpr64(&fpu->fpr[idx], 0);
576 break;
577 case KVM_REG_MIPS_FCR_IR:
578 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
579 return -EINVAL;
580 v = boot_cpu_data.fpu_id;
581 break;
582 case KVM_REG_MIPS_FCR_CSR:
583 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
584 return -EINVAL;
585 v = fpu->fcr31;
586 break;
587
ab86bd60
JH		 588 /* MIPS SIMD Architecture (MSA) registers */
589 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
590 if (!kvm_mips_guest_has_msa(&vcpu->arch))
591 return -EINVAL;
592 /* Can't access MSA registers in FR=0 mode */
593 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
594 return -EINVAL;
595 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
596#ifdef CONFIG_CPU_LITTLE_ENDIAN
597 /* least significant byte first */
598 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
599 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
600#else
601 /* most significant byte first */
602 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
603 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
604#endif
605 break;
606 case KVM_REG_MIPS_MSA_IR:
607 if (!kvm_mips_guest_has_msa(&vcpu->arch))
608 return -EINVAL;
609 v = boot_cpu_data.msa_id;
610 break;
611 case KVM_REG_MIPS_MSA_CSR:
612 if (!kvm_mips_guest_has_msa(&vcpu->arch))
613 return -EINVAL;
614 v = fpu->msacsr;
615 break;
616
379245cd 617 /* Co-processor 0 registers */
4c73fb2b
DD		 618 case KVM_REG_MIPS_CP0_INDEX:
619 v = (long)kvm_read_c0_guest_index(cop0);
620 break;
621 case KVM_REG_MIPS_CP0_CONTEXT:
622 v = (long)kvm_read_c0_guest_context(cop0);
623 break;
7767b7d2
JH		 624 case KVM_REG_MIPS_CP0_USERLOCAL:
625 v = (long)kvm_read_c0_guest_userlocal(cop0);
626 break;
4c73fb2b
DD		 627 case KVM_REG_MIPS_CP0_PAGEMASK:
628 v = (long)kvm_read_c0_guest_pagemask(cop0);
629 break;
630 case KVM_REG_MIPS_CP0_WIRED:
631 v = (long)kvm_read_c0_guest_wired(cop0);
632 break;
16fd5c1d
JH		 633 case KVM_REG_MIPS_CP0_HWRENA:
634 v = (long)kvm_read_c0_guest_hwrena(cop0);
635 break;
4c73fb2b
DD		 636 case KVM_REG_MIPS_CP0_BADVADDR:
637 v = (long)kvm_read_c0_guest_badvaddr(cop0);
638 break;
639 case KVM_REG_MIPS_CP0_ENTRYHI:
640 v = (long)kvm_read_c0_guest_entryhi(cop0);
641 break;
f8be02da
JH		 642 case KVM_REG_MIPS_CP0_COMPARE:
643 v = (long)kvm_read_c0_guest_compare(cop0);
644 break;
4c73fb2b
DD		 645 case KVM_REG_MIPS_CP0_STATUS:
646 v = (long)kvm_read_c0_guest_status(cop0);
647 break;
648 case KVM_REG_MIPS_CP0_CAUSE:
649 v = (long)kvm_read_c0_guest_cause(cop0);
650 break;
fb6df0cd
JH		 651 case KVM_REG_MIPS_CP0_EPC:
652 v = (long)kvm_read_c0_guest_epc(cop0);
653 break;
1068eaaf
JH		 654 case KVM_REG_MIPS_CP0_PRID:
655 v = (long)kvm_read_c0_guest_prid(cop0);
656 break;
4c73fb2b
DD		 657 case KVM_REG_MIPS_CP0_CONFIG:
658 v = (long)kvm_read_c0_guest_config(cop0);
659 break;
660 case KVM_REG_MIPS_CP0_CONFIG1:
661 v = (long)kvm_read_c0_guest_config1(cop0);
662 break;
663 case KVM_REG_MIPS_CP0_CONFIG2:
664 v = (long)kvm_read_c0_guest_config2(cop0);
665 break;
666 case KVM_REG_MIPS_CP0_CONFIG3:
667 v = (long)kvm_read_c0_guest_config3(cop0);
668 break;
c771607a
JH		 669 case KVM_REG_MIPS_CP0_CONFIG4:
670 v = (long)kvm_read_c0_guest_config4(cop0);
671 break;
672 case KVM_REG_MIPS_CP0_CONFIG5:
673 v = (long)kvm_read_c0_guest_config5(cop0);
674 break;
4c73fb2b
DD		 675 case KVM_REG_MIPS_CP0_CONFIG7:
676 v = (long)kvm_read_c0_guest_config7(cop0);
677 break;
e93d4c15
JH		 678 case KVM_REG_MIPS_CP0_ERROREPC:
679 v = (long)kvm_read_c0_guest_errorepc(cop0);
680 break;
f8be02da
JH		 681 /* registers to be handled specially */
682 case KVM_REG_MIPS_CP0_COUNT:
f8239342
JH		 683 case KVM_REG_MIPS_COUNT_CTL:
684 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 685 case KVM_REG_MIPS_COUNT_HZ:
f8be02da
JH		 686 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
687 if (ret)
688 return ret;
689 break;
4c73fb2b
DD		 690 default:
691 return -EINVAL;
692 }
681865d4
DD		 693 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
694 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 695
681865d4
DD		 696 return put_user(v, uaddr64);
697 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
698 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
699 u32 v32 = (u32)v;
d116e812 700
681865d4 701 return put_user(v32, uaddr32);
ab86bd60
JH		 702 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
703 void __user *uaddr = (void __user *)(long)reg->addr;
704
705 return copy_to_user(uaddr, vs, 16);
681865d4
DD		 706 } else {
707 return -EINVAL;
708 }
4c73fb2b
DD		 709}
710
711static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
712 const struct kvm_one_reg *reg)
713{
4c73fb2b 714 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd
JH		 715 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
716 s64 v;
ab86bd60 717 s64 vs[2];
379245cd 718 unsigned int idx;
4c73fb2b 719
681865d4
DD		 720 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
721 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
722
723 if (get_user(v, uaddr64) != 0)
724 return -EFAULT;
725 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
726 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
727 s32 v32;
728
729 if (get_user(v32, uaddr32) != 0)
730 return -EFAULT;
731 v = (s64)v32;
ab86bd60
JH		 732 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
733 void __user *uaddr = (void __user *)(long)reg->addr;
734
735 return copy_from_user(vs, uaddr, 16);
681865d4
DD		 736 } else {
737 return -EINVAL;
738 }
4c73fb2b
DD		 739
740 switch (reg->id) {
379245cd 741 /* General purpose registers */
4c73fb2b
DD		 742 case KVM_REG_MIPS_R0:
743 /* Silently ignore requests to set $0 */
744 break;
745 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
746 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
747 break;
748 case KVM_REG_MIPS_HI:
749 vcpu->arch.hi = v;
750 break;
751 case KVM_REG_MIPS_LO:
752 vcpu->arch.lo = v;
753 break;
754 case KVM_REG_MIPS_PC:
755 vcpu->arch.pc = v;
756 break;
757
379245cd
JH		 758 /* Floating point registers */
759 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
760 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
761 return -EINVAL;
762 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
763 /* Odd singles in top of even double when FR=0 */
764 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
765 set_fpr32(&fpu->fpr[idx], 0, v);
766 else
767 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
768 break;
769 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
770 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
771 return -EINVAL;
772 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
773 /* Can't access odd doubles in FR=0 mode */
774 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
775 return -EINVAL;
776 set_fpr64(&fpu->fpr[idx], 0, v);
777 break;
778 case KVM_REG_MIPS_FCR_IR:
779 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
780 return -EINVAL;
781 /* Read-only */
782 break;
783 case KVM_REG_MIPS_FCR_CSR:
784 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
785 return -EINVAL;
786 fpu->fcr31 = v;
787 break;
788
ab86bd60
JH		 789 /* MIPS SIMD Architecture (MSA) registers */
790 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
791 if (!kvm_mips_guest_has_msa(&vcpu->arch))
792 return -EINVAL;
793 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
794#ifdef CONFIG_CPU_LITTLE_ENDIAN
795 /* least significant byte first */
796 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
797 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
798#else
799 /* most significant byte first */
800 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
801 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
802#endif
803 break;
804 case KVM_REG_MIPS_MSA_IR:
805 if (!kvm_mips_guest_has_msa(&vcpu->arch))
806 return -EINVAL;
807 /* Read-only */
808 break;
809 case KVM_REG_MIPS_MSA_CSR:
810 if (!kvm_mips_guest_has_msa(&vcpu->arch))
811 return -EINVAL;
812 fpu->msacsr = v;
813 break;
814
379245cd 815 /* Co-processor 0 registers */
4c73fb2b
DD		 816 case KVM_REG_MIPS_CP0_INDEX:
817 kvm_write_c0_guest_index(cop0, v);
818 break;
819 case KVM_REG_MIPS_CP0_CONTEXT:
820 kvm_write_c0_guest_context(cop0, v);
821 break;
7767b7d2
JH		 822 case KVM_REG_MIPS_CP0_USERLOCAL:
823 kvm_write_c0_guest_userlocal(cop0, v);
824 break;
4c73fb2b
DD		 825 case KVM_REG_MIPS_CP0_PAGEMASK:
826 kvm_write_c0_guest_pagemask(cop0, v);
827 break;
828 case KVM_REG_MIPS_CP0_WIRED:
829 kvm_write_c0_guest_wired(cop0, v);
830 break;
16fd5c1d
JH		 831 case KVM_REG_MIPS_CP0_HWRENA:
832 kvm_write_c0_guest_hwrena(cop0, v);
833 break;
4c73fb2b
DD		 834 case KVM_REG_MIPS_CP0_BADVADDR:
835 kvm_write_c0_guest_badvaddr(cop0, v);
836 break;
837 case KVM_REG_MIPS_CP0_ENTRYHI:
838 kvm_write_c0_guest_entryhi(cop0, v);
839 break;
840 case KVM_REG_MIPS_CP0_STATUS:
841 kvm_write_c0_guest_status(cop0, v);
842 break;
fb6df0cd
JH		 843 case KVM_REG_MIPS_CP0_EPC:
844 kvm_write_c0_guest_epc(cop0, v);
845 break;
1068eaaf
JH		 846 case KVM_REG_MIPS_CP0_PRID:
847 kvm_write_c0_guest_prid(cop0, v);
848 break;
4c73fb2b
DD		 849 case KVM_REG_MIPS_CP0_ERROREPC:
850 kvm_write_c0_guest_errorepc(cop0, v);
851 break;
f8be02da
JH		 852 /* registers to be handled specially */
853 case KVM_REG_MIPS_CP0_COUNT:
854 case KVM_REG_MIPS_CP0_COMPARE:
e30492bb 855 case KVM_REG_MIPS_CP0_CAUSE:
c771607a
JH		 856 case KVM_REG_MIPS_CP0_CONFIG:
857 case KVM_REG_MIPS_CP0_CONFIG1:
858 case KVM_REG_MIPS_CP0_CONFIG2:
859 case KVM_REG_MIPS_CP0_CONFIG3:
860 case KVM_REG_MIPS_CP0_CONFIG4:
861 case KVM_REG_MIPS_CP0_CONFIG5:
f8239342
JH		 862 case KVM_REG_MIPS_COUNT_CTL:
863 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 864 case KVM_REG_MIPS_COUNT_HZ:
f8be02da 865 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 866 default:
867 return -EINVAL;
868 }
869 return 0;
870}
871
5fafd874
JH		 872static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
873 struct kvm_enable_cap *cap)
874{
875 int r = 0;
876
877 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
878 return -EINVAL;
879 if (cap->flags)
880 return -EINVAL;
881 if (cap->args[0])
882 return -EINVAL;
883
884 switch (cap->cap) {
885 case KVM_CAP_MIPS_FPU:
886 vcpu->arch.fpu_enabled = true;
887 break;
d952bd07
JH		 888 case KVM_CAP_MIPS_MSA:
889 vcpu->arch.msa_enabled = true;
890 break;
5fafd874
JH		 891 default:
892 r = -EINVAL;
893 break;
894 }
895
896 return r;
897}
898
d116e812
DCZ		 899long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
900 unsigned long arg)
669e846e
SL		 901{
902 struct kvm_vcpu *vcpu = filp->private_data;
903 void __user *argp = (void __user *)arg;
904 long r;
669e846e
SL		 905
906 switch (ioctl) {
4c73fb2b
DD		 907 case KVM_SET_ONE_REG:
908 case KVM_GET_ONE_REG: {
909 struct kvm_one_reg reg;
d116e812 910
4c73fb2b
DD		 911 if (copy_from_user(&reg, argp, sizeof(reg)))
912 return -EFAULT;
913 if (ioctl == KVM_SET_ONE_REG)
914 return kvm_mips_set_reg(vcpu, &reg);
915 else
916 return kvm_mips_get_reg(vcpu, &reg);
917 }
918 case KVM_GET_REG_LIST: {
919 struct kvm_reg_list __user *user_list = argp;
920 u64 __user *reg_dest;
921 struct kvm_reg_list reg_list;
922 unsigned n;
923
924 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
925 return -EFAULT;
926 n = reg_list.n;
927 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
928 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
929 return -EFAULT;
930 if (n < reg_list.n)
931 return -E2BIG;
932 reg_dest = user_list->reg;
933 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
934 sizeof(kvm_mips_get_one_regs)))
935 return -EFAULT;
936 return 0;
937 }
669e846e
SL		 938 case KVM_NMI:
939 /* Treat the NMI as a CPU reset */
940 r = kvm_mips_reset_vcpu(vcpu);
941 break;
942 case KVM_INTERRUPT:
943 {
944 struct kvm_mips_interrupt irq;
d116e812 945
669e846e
SL		 946 r = -EFAULT;
947 if (copy_from_user(&irq, argp, sizeof(irq)))
948 goto out;
949
669e846e
SL		 950 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
951 irq.irq);
952
953 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
954 break;
955 }
5fafd874
JH		 956 case KVM_ENABLE_CAP: {
957 struct kvm_enable_cap cap;
958
959 r = -EFAULT;
960 if (copy_from_user(&cap, argp, sizeof(cap)))
961 goto out;
962 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
963 break;
964 }
669e846e 965 default:
4c73fb2b 966 r = -ENOIOCTLCMD;
669e846e
SL		 967 }
968
969out:
970 return r;
971}
972
d116e812 973/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 974int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
975{
9f6b8029 976 struct kvm_memslots *slots;
669e846e
SL		 977 struct kvm_memory_slot *memslot;
978 unsigned long ga, ga_end;
979 int is_dirty = 0;
980 int r;
981 unsigned long n;
982
983 mutex_lock(&kvm->slots_lock);
984
985 r = kvm_get_dirty_log(kvm, log, &is_dirty);
986 if (r)
987 goto out;
988
989 /* If nothing is dirty, don't bother messing with page tables. */
990 if (is_dirty) {
9f6b8029
PB		 991 slots = kvm_memslots(kvm);
992 memslot = id_to_memslot(slots, log->slot);
669e846e
SL		 993
994 ga = memslot->base_gfn << PAGE_SHIFT;
995 ga_end = ga + (memslot->npages << PAGE_SHIFT);
996
6ad78a5c
DCZ		 997 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
998 ga_end);
669e846e
SL		 999
1000 n = kvm_dirty_bitmap_bytes(memslot);
1001 memset(memslot->dirty_bitmap, 0, n);
1002 }
1003
1004 r = 0;
1005out:
1006 mutex_unlock(&kvm->slots_lock);
1007 return r;
1008
1009}
1010
1011long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1012{
1013 long r;
1014
1015 switch (ioctl) {
1016 default:
ed829857 1017 r = -ENOIOCTLCMD;
669e846e
SL		 1018 }
1019
1020 return r;
1021}
1022
1023int kvm_arch_init(void *opaque)
1024{
669e846e
SL		 1025 if (kvm_mips_callbacks) {
1026 kvm_err("kvm: module already exists\n");
1027 return -EEXIST;
1028 }
1029
d98403a5 1030 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 1031}
1032
1033void kvm_arch_exit(void)
1034{
1035 kvm_mips_callbacks = NULL;
1036}
1037
d116e812
DCZ		 1038int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1039 struct kvm_sregs *sregs)
669e846e 1040{
ed829857 1041 return -ENOIOCTLCMD;
669e846e
SL		 1042}
1043
d116e812
DCZ		 1044int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1045 struct kvm_sregs *sregs)
669e846e 1046{
ed829857 1047 return -ENOIOCTLCMD;
669e846e
SL		 1048}
1049
31928aa5 1050void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 1051{
669e846e
SL		 1052}
1053
1054int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055{
ed829857 1056 return -ENOIOCTLCMD;
669e846e
SL		 1057}
1058
1059int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1060{
ed829857 1061 return -ENOIOCTLCMD;
669e846e
SL		 1062}
1063
1064int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1065{
1066 return VM_FAULT_SIGBUS;
1067}
1068
784aa3d7 1069int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 1070{
1071 int r;
1072
1073 switch (ext) {
4c73fb2b 1074 case KVM_CAP_ONE_REG:
5fafd874 1075 case KVM_CAP_ENABLE_CAP:
4c73fb2b
DD		 1076 r = 1;
1077 break;
669e846e
SL		 1078 case KVM_CAP_COALESCED_MMIO:
1079 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1080 break;
5fafd874
JH		 1081 case KVM_CAP_MIPS_FPU:
1082 r = !!cpu_has_fpu;
1083 break;
d952bd07
JH		 1084 case KVM_CAP_MIPS_MSA:
1085 /*
1086 * We don't support MSA vector partitioning yet:
1087 * 1) It would require explicit support which can't be tested
1088 * yet due to lack of support in current hardware.
1089 * 2) It extends the state that would need to be saved/restored
1090 * by e.g. QEMU for migration.
1091 *
1092 * When vector partitioning hardware becomes available, support
1093 * could be added by requiring a flag when enabling
1094 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1095 * to save/restore the appropriate extra state.
1096 */
1097 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1098 break;
669e846e
SL		 1099 default:
1100 r = 0;
1101 break;
1102 }
1103 return r;
669e846e
SL		 1104}
1105
1106int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1107{
1108 return kvm_mips_pending_timer(vcpu);
1109}
1110
1111int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1112{
1113 int i;
1114 struct mips_coproc *cop0;
1115
1116 if (!vcpu)
1117 return -1;
1118
6ad78a5c
DCZ		 1119 kvm_debug("VCPU Register Dump:\n");
1120 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1121 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 1122
1123 for (i = 0; i < 32; i += 4) {
6ad78a5c 1124 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 1125 vcpu->arch.gprs[i],
1126 vcpu->arch.gprs[i + 1],
1127 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1128 }
6ad78a5c
DCZ		 1129 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1130 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 1131
1132 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 1133 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1134 kvm_read_c0_guest_status(cop0),
1135 kvm_read_c0_guest_cause(cop0));
669e846e 1136
6ad78a5c 1137 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 1138
1139 return 0;
1140}
1141
1142int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1143{
1144 int i;
1145
8d17dd04 1146 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1147 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 1148 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 1149 vcpu->arch.hi = regs->hi;
1150 vcpu->arch.lo = regs->lo;
1151 vcpu->arch.pc = regs->pc;
1152
4c73fb2b 1153 return 0;
669e846e
SL		 1154}
1155
1156int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1157{
1158 int i;
1159
8d17dd04 1160 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1161 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 1162
1163 regs->hi = vcpu->arch.hi;
1164 regs->lo = vcpu->arch.lo;
1165 regs->pc = vcpu->arch.pc;
1166
4c73fb2b 1167 return 0;
669e846e
SL		 1168}
1169
0fae34f4 1170static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 1171{
1172 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1173
1174 kvm_mips_callbacks->queue_timer_int(vcpu);
1175
1176 vcpu->arch.wait = 0;
8577370f
MT		 1177 if (swait_active(&vcpu->wq))
1178 swake_up(&vcpu->wq);
669e846e
SL		 1179}
1180
d116e812 1181/* low level hrtimer wake routine */
0fae34f4 1182static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 1183{
1184 struct kvm_vcpu *vcpu;
1185
1186 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1187 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 1188 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 1189}
1190
1191int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1192{
1193 kvm_mips_callbacks->vcpu_init(vcpu);
1194 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1195 HRTIMER_MODE_REL);
1196 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 1197 return 0;
1198}
1199
d116e812
DCZ		 1200int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1201 struct kvm_translation *tr)
669e846e
SL		 1202{
1203 return 0;
1204}
1205
1206/* Initial guest state */
1207int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1208{
1209 return kvm_mips_callbacks->vcpu_setup(vcpu);
1210}
1211
d116e812 1212static void kvm_mips_set_c0_status(void)
669e846e
SL		 1213{
1214 uint32_t status = read_c0_status();
1215
669e846e
SL		 1216 if (cpu_has_dsp)
1217 status |= (ST0_MX);
1218
1219 write_c0_status(status);
1220 ehb();
1221}
1222
1223/*
1224 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1225 */
1226int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1227{
1228 uint32_t cause = vcpu->arch.host_cp0_cause;
1229 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1230 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1231 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1232 enum emulation_result er = EMULATE_DONE;
1233 int ret = RESUME_GUEST;
1234
c4c6f2ca
JH		 1235 /* re-enable HTW before enabling interrupts */
1236 htw_start();
1237
669e846e
SL		 1238 /* Set a default exit reason */
1239 run->exit_reason = KVM_EXIT_UNKNOWN;
1240 run->ready_for_interrupt_injection = 1;
1241
d116e812
DCZ		 1242 /*
1243 * Set the appropriate status bits based on host CPU features,
1244 * before we hit the scheduler
1245 */
669e846e
SL		 1246 kvm_mips_set_c0_status();
1247
1248 local_irq_enable();
1249
1250 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1251 cause, opc, run, vcpu);
1252
d116e812
DCZ		 1253 /*
1254 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1255 * causing an exception to be delivered to the Guest Kernel
1256 */
1257 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1258 if (er == EMULATE_PRIV_FAIL) {
1259 goto skip_emul;
1260 } else if (er == EMULATE_FAIL) {
1261 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1262 ret = RESUME_HOST;
1263 goto skip_emul;
1264 }
1265
1266 switch (exccode) {
16d100db
JH		 1267 case EXCCODE_INT:
1268 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
669e846e
SL		 1269
1270 ++vcpu->stat.int_exits;
1271 trace_kvm_exit(vcpu, INT_EXITS);
1272
d116e812 1273 if (need_resched())
669e846e 1274 cond_resched();
669e846e
SL		 1275
1276 ret = RESUME_GUEST;
1277 break;
1278
16d100db
JH		 1279 case EXCCODE_CPU:
1280 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
669e846e
SL		 1281
1282 ++vcpu->stat.cop_unusable_exits;
1283 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1284 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1285 /* XXXKYMA: Might need to return to user space */
d116e812 1286 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1287 ret = RESUME_HOST;
669e846e
SL		 1288 break;
1289
16d100db 1290 case EXCCODE_MOD:
669e846e
SL		 1291 ++vcpu->stat.tlbmod_exits;
1292 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1293 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1294 break;
1295
16d100db 1296 case EXCCODE_TLBS:
d116e812
DCZ		 1297 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1298 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1299 badvaddr);
669e846e
SL		 1300
1301 ++vcpu->stat.tlbmiss_st_exits;
1302 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1303 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1304 break;
1305
16d100db 1306 case EXCCODE_TLBL:
669e846e
SL		 1307 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1308 cause, opc, badvaddr);
1309
1310 ++vcpu->stat.tlbmiss_ld_exits;
1311 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1312 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1313 break;
1314
16d100db 1315 case EXCCODE_ADES:
669e846e
SL		 1316 ++vcpu->stat.addrerr_st_exits;
1317 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1318 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1319 break;
1320
16d100db 1321 case EXCCODE_ADEL:
669e846e
SL		 1322 ++vcpu->stat.addrerr_ld_exits;
1323 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1324 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1325 break;
1326
16d100db 1327 case EXCCODE_SYS:
669e846e
SL		 1328 ++vcpu->stat.syscall_exits;
1329 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1330 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1331 break;
1332
16d100db 1333 case EXCCODE_RI:
669e846e
SL		 1334 ++vcpu->stat.resvd_inst_exits;
1335 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1336 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1337 break;
1338
16d100db 1339 case EXCCODE_BP:
669e846e
SL		 1340 ++vcpu->stat.break_inst_exits;
1341 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1342 ret = kvm_mips_callbacks->handle_break(vcpu);
1343 break;
1344
16d100db 1345 case EXCCODE_TR:
0a560427
JH		 1346 ++vcpu->stat.trap_inst_exits;
1347 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1348 ret = kvm_mips_callbacks->handle_trap(vcpu);
1349 break;
1350
16d100db 1351 case EXCCODE_MSAFPE:
c2537ed9
JH		 1352 ++vcpu->stat.msa_fpe_exits;
1353 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1354 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1355 break;
1356
16d100db 1357 case EXCCODE_FPE:
1c0cd66a
JH		 1358 ++vcpu->stat.fpe_exits;
1359 trace_kvm_exit(vcpu, FPE_EXITS);
1360 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1361 break;
1362
16d100db 1363 case EXCCODE_MSADIS:
c2537ed9
JH		 1364 ++vcpu->stat.msa_disabled_exits;
1365 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
98119ad5
JH		 1366 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1367 break;
1368
669e846e 1369 default:
d116e812
DCZ		 1370 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1371 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1372 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1373 kvm_arch_vcpu_dump_regs(vcpu);
1374 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1375 ret = RESUME_HOST;
1376 break;
1377
1378 }
1379
1380skip_emul:
1381 local_irq_disable();
1382
1383 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1384 kvm_mips_deliver_interrupts(vcpu, cause);
1385
1386 if (!(ret & RESUME_HOST)) {
d116e812 1387 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1388 if (signal_pending(current)) {
1389 run->exit_reason = KVM_EXIT_INTR;
1390 ret = (-EINTR << 2) | RESUME_HOST;
1391 ++vcpu->stat.signal_exits;
1392 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1393 }
1394 }
1395
98e91b84
JH		 1396 if (ret == RESUME_GUEST) {
1397 /*
539cb89f
JH		 1398 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1399 * is live), restore FCR31 / MSACSR.
98e91b84
JH		 1400 *
1401 * This should be before returning to the guest exception
539cb89f
JH		 1402 * vector, as it may well cause an [MSA] FP exception if there
1403 * are pending exception bits unmasked. (see
98e91b84
JH		 1404 * kvm_mips_csr_die_notifier() for how that is handled).
1405 */
1406 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1407 read_c0_status() & ST0_CU1)
1408 __kvm_restore_fcsr(&vcpu->arch);
539cb89f
JH		 1409
1410 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1411 read_c0_config5() & MIPS_CONF5_MSAEN)
1412 __kvm_restore_msacsr(&vcpu->arch);
98e91b84
JH		 1413 }
1414
c4c6f2ca
JH		 1415 /* Disable HTW before returning to guest or host */
1416 htw_stop();
1417
669e846e
SL		 1418 return ret;
1419}
1420
98e91b84
JH		 1421/* Enable FPU for guest and restore context */
1422void kvm_own_fpu(struct kvm_vcpu *vcpu)
1423{
1424 struct mips_coproc *cop0 = vcpu->arch.cop0;
1425 unsigned int sr, cfg5;
1426
1427 preempt_disable();
1428
539cb89f
JH		 1429 sr = kvm_read_c0_guest_status(cop0);
1430
1431 /*
1432 * If MSA state is already live, it is undefined how it interacts with
1433 * FR=0 FPU state, and we don't want to hit reserved instruction
1434 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1435 * play it safe and save it first.
1436 *
1437 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1438 * get called when guest CU1 is set, however we can't trust the guest
1439 * not to clobber the status register directly via the commpage.
1440 */
1441 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1442 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1443 kvm_lose_fpu(vcpu);
1444
98e91b84
JH		 1445 /*
1446 * Enable FPU for guest
1447 * We set FR and FRE according to guest context
1448 */
98e91b84
JH		 1449 change_c0_status(ST0_CU1 | ST0_FR, sr);
1450 if (cpu_has_fre) {
1451 cfg5 = kvm_read_c0_guest_config5(cop0);
1452 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1453 }
1454 enable_fpu_hazard();
1455
1456 /* If guest FPU state not active, restore it now */
1457 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1458 __kvm_restore_fpu(&vcpu->arch);
1459 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1460 }
1461
1462 preempt_enable();
1463}
1464
539cb89f
JH		 1465#ifdef CONFIG_CPU_HAS_MSA
1466/* Enable MSA for guest and restore context */
1467void kvm_own_msa(struct kvm_vcpu *vcpu)
1468{
1469 struct mips_coproc *cop0 = vcpu->arch.cop0;
1470 unsigned int sr, cfg5;
1471
1472 preempt_disable();
1473
1474 /*
1475 * Enable FPU if enabled in guest, since we're restoring FPU context
1476 * anyway. We set FR and FRE according to guest context.
1477 */
1478 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1479 sr = kvm_read_c0_guest_status(cop0);
1480
1481 /*
1482 * If FR=0 FPU state is already live, it is undefined how it
1483 * interacts with MSA state, so play it safe and save it first.
1484 */
1485 if (!(sr & ST0_FR) &&
1486 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1487 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1488 kvm_lose_fpu(vcpu);
1489
1490 change_c0_status(ST0_CU1 | ST0_FR, sr);
1491 if (sr & ST0_CU1 && cpu_has_fre) {
1492 cfg5 = kvm_read_c0_guest_config5(cop0);
1493 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1494 }
1495 }
1496
1497 /* Enable MSA for guest */
1498 set_c0_config5(MIPS_CONF5_MSAEN);
1499 enable_fpu_hazard();
1500
1501 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1502 case KVM_MIPS_FPU_FPU:
1503 /*
1504 * Guest FPU state already loaded, only restore upper MSA state
1505 */
1506 __kvm_restore_msa_upper(&vcpu->arch);
1507 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1508 break;
1509 case 0:
1510 /* Neither FPU or MSA already active, restore full MSA state */
1511 __kvm_restore_msa(&vcpu->arch);
1512 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1513 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1514 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1515 break;
1516 default:
1517 break;
1518 }
1519
1520 preempt_enable();
1521}
1522#endif
1523
1524/* Drop FPU & MSA without saving it */
98e91b84
JH		 1525void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1526{
1527 preempt_disable();
539cb89f
JH		 1528 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1529 disable_msa();
1530 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1531 }
98e91b84
JH		 1532 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1533 clear_c0_status(ST0_CU1 | ST0_FR);
1534 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1535 }
1536 preempt_enable();
1537}
1538
539cb89f 1539/* Save and disable FPU & MSA */
98e91b84
JH		 1540void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1541{
1542 /*
539cb89f
JH		 1543 * FPU & MSA get disabled in root context (hardware) when it is disabled
1544 * in guest context (software), but the register state in the hardware
1545 * may still be in use. This is why we explicitly re-enable the hardware
98e91b84
JH		 1546 * before saving.
1547 */
1548
1549 preempt_disable();
539cb89f
JH		 1550 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1551 set_c0_config5(MIPS_CONF5_MSAEN);
1552 enable_fpu_hazard();
1553
1554 __kvm_save_msa(&vcpu->arch);
1555
1556 /* Disable MSA & FPU */
1557 disable_msa();
1558 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1559 clear_c0_status(ST0_CU1 | ST0_FR);
1560 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1561 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
98e91b84
JH		 1562 set_c0_status(ST0_CU1);
1563 enable_fpu_hazard();
1564
1565 __kvm_save_fpu(&vcpu->arch);
1566 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1567
1568 /* Disable FPU */
1569 clear_c0_status(ST0_CU1 | ST0_FR);
1570 }
1571 preempt_enable();
1572}
1573
1574/*
539cb89f
JH		 1575 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1576 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1577 * exception if cause bits are set in the value being written.
98e91b84
JH		 1578 */
1579static int kvm_mips_csr_die_notify(struct notifier_block *self,
1580 unsigned long cmd, void *ptr)
1581{
1582 struct die_args *args = (struct die_args *)ptr;
1583 struct pt_regs *regs = args->regs;
1584 unsigned long pc;
1585
539cb89f
JH		 1586 /* Only interested in FPE and MSAFPE */
1587 if (cmd != DIE_FP && cmd != DIE_MSAFP)
98e91b84
JH		 1588 return NOTIFY_DONE;
1589
1590 /* Return immediately if guest context isn't active */
1591 if (!(current->flags & PF_VCPU))
1592 return NOTIFY_DONE;
1593
1594 /* Should never get here from user mode */
1595 BUG_ON(user_mode(regs));
1596
1597 pc = instruction_pointer(regs);
1598 switch (cmd) {
1599 case DIE_FP:
1600 /* match 2nd instruction in __kvm_restore_fcsr */
1601 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1602 return NOTIFY_DONE;
1603 break;
539cb89f
JH		 1604 case DIE_MSAFP:
1605 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1606 if (!cpu_has_msa ||
1607 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1608 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1609 return NOTIFY_DONE;
1610 break;
98e91b84
JH		 1611 }
1612
1613 /* Move PC forward a little and continue executing */
1614 instruction_pointer(regs) += 4;
1615
1616 return NOTIFY_STOP;
1617}
1618
1619static struct notifier_block kvm_mips_csr_die_notifier = {
1620 .notifier_call = kvm_mips_csr_die_notify,
1621};
1622
2db9d233 1623static int __init kvm_mips_init(void)
669e846e
SL		 1624{
1625 int ret;
1626
1627 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1628
1629 if (ret)
1630 return ret;
1631
98e91b84
JH		 1632 register_die_notifier(&kvm_mips_csr_die_notifier);
1633
d116e812
DCZ		 1634 /*
1635 * On MIPS, kernel modules are executed from "mapped space", which
1636 * requires TLBs. The TLB handling code is statically linked with
d7d5b05f 1637 * the rest of the kernel (tlb.c) to avoid the possibility of
d116e812
DCZ		 1638 * double faulting. The issue is that the TLB code references
1639 * routines that are part of the the KVM module, which are only
1640 * available once the module is loaded.
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SL		 1641 */
1642 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1643 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1644 kvm_mips_is_error_pfn = is_error_pfn;
1645
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SL		 1646 return 0;
1647}
1648
2db9d233 1649static void __exit kvm_mips_exit(void)
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SL		 1650{
1651 kvm_exit();
1652
1653 kvm_mips_gfn_to_pfn = NULL;
1654 kvm_mips_release_pfn_clean = NULL;
1655 kvm_mips_is_error_pfn = NULL;
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JH		 1656
1657 unregister_die_notifier(&kvm_mips_csr_die_notifier);
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SL		 1658}
1659
1660module_init(kvm_mips_init);
1661module_exit(kvm_mips_exit);
1662
1663EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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