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MIPS: KVM: Add guest mode switch trace events
[deliverable/linux.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e
SL		 11
12#include <linux/errno.h>
13#include <linux/err.h>
98e91b84 14#include <linux/kdebug.h>
669e846e
SL		 15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
f798217d 19#include <asm/fpu.h>
669e846e
SL		 20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
c4c6f2ca 23#include <asm/pgtable.h>
669e846e
SL		 24
25#include <linux/kvm_host.h>
26
d7d5b05f
DCZ		 27#include "interrupt.h"
28#include "commpage.h"
669e846e
SL		 29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
d116e812 37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 38struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
c2537ed9 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
1c0cd66a 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
c2537ed9 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
d116e812 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
62bea5bf 58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
3491caf2 59 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
d116e812 60 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 61 {NULL}
62};
63
64static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
65{
66 int i;
d116e812 67
669e846e
SL		 68 for_each_possible_cpu(i) {
69 vcpu->arch.guest_kernel_asid[i] = 0;
70 vcpu->arch.guest_user_asid[i] = 0;
71 }
d116e812 72
669e846e
SL		 73 return 0;
74}
75
d116e812
DCZ		 76/*
77 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
78 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 79 */
80int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
81{
82 return !!(vcpu->arch.pending_exceptions);
83}
84
85int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
86{
87 return 1;
88}
89
13a34e06 90int kvm_arch_hardware_enable(void)
669e846e
SL		 91{
92 return 0;
93}
94
669e846e
SL		 95int kvm_arch_hardware_setup(void)
96{
97 return 0;
98}
99
669e846e
SL		 100void kvm_arch_check_processor_compat(void *rtn)
101{
d98403a5 102 *(int *)rtn = 0;
669e846e
SL		 103}
104
105static void kvm_mips_init_tlbs(struct kvm *kvm)
106{
107 unsigned long wired;
108
d116e812
DCZ		 109 /*
110 * Add a wired entry to the TLB, it is used to map the commpage to
111 * the Guest kernel
112 */
669e846e
SL		 113 wired = read_c0_wired();
114 write_c0_wired(wired + 1);
115 mtc0_tlbw_hazard();
116 kvm->arch.commpage_tlb = wired;
117
118 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
119 kvm->arch.commpage_tlb);
120}
121
122static void kvm_mips_init_vm_percpu(void *arg)
123{
124 struct kvm *kvm = (struct kvm *)arg;
125
126 kvm_mips_init_tlbs(kvm);
127 kvm_mips_callbacks->vm_init(kvm);
128
129}
130
131int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
132{
133 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 134 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
135 __func__);
669e846e
SL		 136 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
137 }
138
669e846e
SL		 139 return 0;
140}
141
142void kvm_mips_free_vcpus(struct kvm *kvm)
143{
144 unsigned int i;
145 struct kvm_vcpu *vcpu;
146
147 /* Put the pages we reserved for the guest pmap */
148 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
149 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
9befad23 150 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
669e846e 151 }
c6c0a663 152 kfree(kvm->arch.guest_pmap);
669e846e
SL		 153
154 kvm_for_each_vcpu(i, vcpu, kvm) {
155 kvm_arch_vcpu_free(vcpu);
156 }
157
158 mutex_lock(&kvm->lock);
159
160 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
161 kvm->vcpus[i] = NULL;
162
163 atomic_set(&kvm->online_vcpus, 0);
164
165 mutex_unlock(&kvm->lock);
166}
167
669e846e
SL		 168static void kvm_mips_uninit_tlbs(void *arg)
169{
170 /* Restore wired count */
171 write_c0_wired(0);
172 mtc0_tlbw_hazard();
173 /* Clear out all the TLBs */
174 kvm_local_flush_tlb_all();
175}
176
177void kvm_arch_destroy_vm(struct kvm *kvm)
178{
179 kvm_mips_free_vcpus(kvm);
180
181 /* If this is the last instance, restore wired count */
182 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 183 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
184 __func__);
669e846e
SL		 185 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
186 }
187}
188
d116e812
DCZ		 189long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
190 unsigned long arg)
669e846e 191{
ed829857 192 return -ENOIOCTLCMD;
669e846e
SL		 193}
194
5587027c
AK		 195int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
196 unsigned long npages)
669e846e
SL		 197{
198 return 0;
199}
200
201int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812 202 struct kvm_memory_slot *memslot,
09170a49 203 const struct kvm_userspace_memory_region *mem,
d116e812 204 enum kvm_mr_change change)
669e846e
SL		 205{
206 return 0;
207}
208
209void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 210 const struct kvm_userspace_memory_region *mem,
d116e812 211 const struct kvm_memory_slot *old,
f36f3f28 212 const struct kvm_memory_slot *new,
d116e812 213 enum kvm_mr_change change)
669e846e
SL		 214{
215 unsigned long npages = 0;
d98403a5 216 int i;
669e846e
SL		 217
218 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
219 __func__, kvm, mem->slot, mem->guest_phys_addr,
220 mem->memory_size, mem->userspace_addr);
221
222 /* Setup Guest PMAP table */
223 if (!kvm->arch.guest_pmap) {
224 if (mem->slot == 0)
225 npages = mem->memory_size >> PAGE_SHIFT;
226
227 if (npages) {
228 kvm->arch.guest_pmap_npages = npages;
229 kvm->arch.guest_pmap =
230 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
231
232 if (!kvm->arch.guest_pmap) {
f7fdcb60 233 kvm_err("Failed to allocate guest PMAP\n");
d98403a5 234 return;
669e846e
SL		 235 }
236
6e95bfd2
JH		 237 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
238 npages, kvm->arch.guest_pmap);
669e846e
SL		 239
240 /* Now setup the page table */
d116e812 241 for (i = 0; i < npages; i++)
669e846e 242 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 243 }
244 }
669e846e
SL		 245}
246
669e846e
SL		 247struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
248{
669e846e
SL		 249 int err, size, offset;
250 void *gebase;
251 int i;
252
253 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
254
255 if (!vcpu) {
256 err = -ENOMEM;
257 goto out;
258 }
259
260 err = kvm_vcpu_init(vcpu, kvm, id);
261
262 if (err)
263 goto out_free_cpu;
264
6e95bfd2 265 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 266
d116e812
DCZ		 267 /*
268 * Allocate space for host mode exception handlers that handle
669e846e
SL		 269 * guest mode exits
270 */
d116e812 271 if (cpu_has_veic || cpu_has_vint)
669e846e 272 size = 0x200 + VECTORSPACING * 64;
d116e812 273 else
7006e2df 274 size = 0x4000;
669e846e 275
669e846e
SL		 276 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
277
278 if (!gebase) {
279 err = -ENOMEM;
585bb8f9 280 goto out_uninit_cpu;
669e846e 281 }
6e95bfd2
JH		 282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 284
285 /* Save new ebase */
286 vcpu->arch.guest_ebase = gebase;
287
288 /* Copy L1 Guest Exception handler to correct offset */
289
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase, mips32_exception,
292 mips32_exceptionEnd - mips32_exception);
293
294 /* General Exception Entry point */
295 memcpy(gebase + 0x180, mips32_exception,
296 mips32_exceptionEnd - mips32_exception);
297
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i = 0; i < 8; i++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase + 0x200 + (i * VECTORSPACING));
302 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
303 mips32_exceptionEnd - mips32_exception);
304 }
305
306 /* General handler, relocate to unmapped space for sanity's sake */
307 offset = 0x2000;
6e95bfd2
JH		 308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
309 gebase + offset,
310 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 311
312 memcpy(gebase + offset, mips32_GuestException,
313 mips32_GuestExceptionEnd - mips32_GuestException);
314
797179bc
JH		 315#ifdef MODULE
316 offset += mips32_GuestExceptionEnd - mips32_GuestException;
317 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
318 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
319 vcpu->arch.vcpu_run = gebase + offset;
320#else
321 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
322#endif
323
669e846e 324 /* Invalidate the icache for these ranges */
facaaec1
JH		 325 local_flush_icache_range((unsigned long)gebase,
326 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 327
d116e812
DCZ		 328 /*
329 * Allocate comm page for guest kernel, a TLB will be reserved for
330 * mapping GVA @ 0xFFFF8000 to this page
331 */
669e846e
SL		 332 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
333
334 if (!vcpu->arch.kseg0_commpage) {
335 err = -ENOMEM;
336 goto out_free_gebase;
337 }
338
6e95bfd2 339 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 340 kvm_mips_commpage_init(vcpu);
341
342 /* Init */
343 vcpu->arch.last_sched_cpu = -1;
344
345 /* Start off the timer */
e30492bb 346 kvm_mips_init_count(vcpu);
669e846e
SL		 347
348 return vcpu;
349
350out_free_gebase:
351 kfree(gebase);
352
585bb8f9
JH		 353out_uninit_cpu:
354 kvm_vcpu_uninit(vcpu);
355
669e846e
SL		 356out_free_cpu:
357 kfree(vcpu);
358
359out:
360 return ERR_PTR(err);
361}
362
363void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
364{
365 hrtimer_cancel(&vcpu->arch.comparecount_timer);
366
367 kvm_vcpu_uninit(vcpu);
368
369 kvm_mips_dump_stats(vcpu);
370
c6c0a663
JH		 371 kfree(vcpu->arch.guest_ebase);
372 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 373 kfree(vcpu);
669e846e
SL		 374}
375
376void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
377{
378 kvm_arch_vcpu_free(vcpu);
379}
380
d116e812
DCZ		 381int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
382 struct kvm_guest_debug *dbg)
669e846e 383{
ed829857 384 return -ENOIOCTLCMD;
669e846e
SL		 385}
386
387int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
388{
389 int r = 0;
390 sigset_t sigsaved;
391
392 if (vcpu->sigset_active)
393 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
394
395 if (vcpu->mmio_needed) {
396 if (!vcpu->mmio_is_write)
397 kvm_mips_complete_mmio_load(vcpu, run);
398 vcpu->mmio_needed = 0;
399 }
400
f798217d
JH		 401 lose_fpu(1);
402
044f0f03 403 local_irq_disable();
669e846e
SL		 404 /* Check if we have any exceptions/interrupts pending */
405 kvm_mips_deliver_interrupts(vcpu,
406 kvm_read_c0_guest_cause(vcpu->arch.cop0));
407
ccf73aaf 408 __kvm_guest_enter();
669e846e 409
c4c6f2ca
JH		 410 /* Disable hardware page table walking while in guest */
411 htw_stop();
412
93258604 413 trace_kvm_enter(vcpu);
797179bc 414 r = vcpu->arch.vcpu_run(run, vcpu);
93258604 415 trace_kvm_out(vcpu);
669e846e 416
c4c6f2ca
JH		 417 /* Re-enable HTW before enabling interrupts */
418 htw_start();
419
ccf73aaf 420 __kvm_guest_exit();
669e846e
SL		 421 local_irq_enable();
422
423 if (vcpu->sigset_active)
424 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
425
426 return r;
427}
428
d116e812
DCZ		 429int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
430 struct kvm_mips_interrupt *irq)
669e846e
SL		 431{
432 int intr = (int)irq->irq;
433 struct kvm_vcpu *dvcpu = NULL;
434
435 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
436 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
437 (int)intr);
438
439 if (irq->cpu == -1)
440 dvcpu = vcpu;
441 else
442 dvcpu = vcpu->kvm->vcpus[irq->cpu];
443
444 if (intr == 2 || intr == 3 || intr == 4) {
445 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
446
447 } else if (intr == -2 || intr == -3 || intr == -4) {
448 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
449 } else {
450 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
451 irq->cpu, irq->irq);
452 return -EINVAL;
453 }
454
455 dvcpu->arch.wait = 0;
456
8577370f
MT		 457 if (swait_active(&dvcpu->wq))
458 swake_up(&dvcpu->wq);
669e846e
SL		 459
460 return 0;
461}
462
d116e812
DCZ		 463int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
464 struct kvm_mp_state *mp_state)
669e846e 465{
ed829857 466 return -ENOIOCTLCMD;
669e846e
SL		 467}
468
d116e812
DCZ		 469int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
470 struct kvm_mp_state *mp_state)
669e846e 471{
ed829857 472 return -ENOIOCTLCMD;
669e846e
SL		 473}
474
4c73fb2b
DD		 475static u64 kvm_mips_get_one_regs[] = {
476 KVM_REG_MIPS_R0,
477 KVM_REG_MIPS_R1,
478 KVM_REG_MIPS_R2,
479 KVM_REG_MIPS_R3,
480 KVM_REG_MIPS_R4,
481 KVM_REG_MIPS_R5,
482 KVM_REG_MIPS_R6,
483 KVM_REG_MIPS_R7,
484 KVM_REG_MIPS_R8,
485 KVM_REG_MIPS_R9,
486 KVM_REG_MIPS_R10,
487 KVM_REG_MIPS_R11,
488 KVM_REG_MIPS_R12,
489 KVM_REG_MIPS_R13,
490 KVM_REG_MIPS_R14,
491 KVM_REG_MIPS_R15,
492 KVM_REG_MIPS_R16,
493 KVM_REG_MIPS_R17,
494 KVM_REG_MIPS_R18,
495 KVM_REG_MIPS_R19,
496 KVM_REG_MIPS_R20,
497 KVM_REG_MIPS_R21,
498 KVM_REG_MIPS_R22,
499 KVM_REG_MIPS_R23,
500 KVM_REG_MIPS_R24,
501 KVM_REG_MIPS_R25,
502 KVM_REG_MIPS_R26,
503 KVM_REG_MIPS_R27,
504 KVM_REG_MIPS_R28,
505 KVM_REG_MIPS_R29,
506 KVM_REG_MIPS_R30,
507 KVM_REG_MIPS_R31,
508
509 KVM_REG_MIPS_HI,
510 KVM_REG_MIPS_LO,
511 KVM_REG_MIPS_PC,
512
513 KVM_REG_MIPS_CP0_INDEX,
514 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 515 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 516 KVM_REG_MIPS_CP0_PAGEMASK,
517 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 518 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 519 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 520 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 521 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 522 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 523 KVM_REG_MIPS_CP0_STATUS,
524 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 525 KVM_REG_MIPS_CP0_EPC,
1068eaaf 526 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 527 KVM_REG_MIPS_CP0_CONFIG,
528 KVM_REG_MIPS_CP0_CONFIG1,
529 KVM_REG_MIPS_CP0_CONFIG2,
530 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 531 KVM_REG_MIPS_CP0_CONFIG4,
532 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 533 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 534 KVM_REG_MIPS_CP0_ERROREPC,
535
536 KVM_REG_MIPS_COUNT_CTL,
537 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 538 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 539};
540
541static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
542 const struct kvm_one_reg *reg)
543{
4c73fb2b 544 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd 545 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
f8be02da 546 int ret;
4c73fb2b 547 s64 v;
ab86bd60 548 s64 vs[2];
379245cd 549 unsigned int idx;
4c73fb2b
DD		 550
551 switch (reg->id) {
379245cd 552 /* General purpose registers */
4c73fb2b
DD		 553 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
554 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
555 break;
556 case KVM_REG_MIPS_HI:
557 v = (long)vcpu->arch.hi;
558 break;
559 case KVM_REG_MIPS_LO:
560 v = (long)vcpu->arch.lo;
561 break;
562 case KVM_REG_MIPS_PC:
563 v = (long)vcpu->arch.pc;
564 break;
565
379245cd
JH		 566 /* Floating point registers */
567 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
568 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
569 return -EINVAL;
570 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
571 /* Odd singles in top of even double when FR=0 */
572 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
573 v = get_fpr32(&fpu->fpr[idx], 0);
574 else
575 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
576 break;
577 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
578 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
579 return -EINVAL;
580 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
581 /* Can't access odd doubles in FR=0 mode */
582 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
583 return -EINVAL;
584 v = get_fpr64(&fpu->fpr[idx], 0);
585 break;
586 case KVM_REG_MIPS_FCR_IR:
587 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
588 return -EINVAL;
589 v = boot_cpu_data.fpu_id;
590 break;
591 case KVM_REG_MIPS_FCR_CSR:
592 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
593 return -EINVAL;
594 v = fpu->fcr31;
595 break;
596
ab86bd60
JH		 597 /* MIPS SIMD Architecture (MSA) registers */
598 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
599 if (!kvm_mips_guest_has_msa(&vcpu->arch))
600 return -EINVAL;
601 /* Can't access MSA registers in FR=0 mode */
602 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
603 return -EINVAL;
604 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
605#ifdef CONFIG_CPU_LITTLE_ENDIAN
606 /* least significant byte first */
607 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
608 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
609#else
610 /* most significant byte first */
611 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
612 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
613#endif
614 break;
615 case KVM_REG_MIPS_MSA_IR:
616 if (!kvm_mips_guest_has_msa(&vcpu->arch))
617 return -EINVAL;
618 v = boot_cpu_data.msa_id;
619 break;
620 case KVM_REG_MIPS_MSA_CSR:
621 if (!kvm_mips_guest_has_msa(&vcpu->arch))
622 return -EINVAL;
623 v = fpu->msacsr;
624 break;
625
379245cd 626 /* Co-processor 0 registers */
4c73fb2b
DD		 627 case KVM_REG_MIPS_CP0_INDEX:
628 v = (long)kvm_read_c0_guest_index(cop0);
629 break;
630 case KVM_REG_MIPS_CP0_CONTEXT:
631 v = (long)kvm_read_c0_guest_context(cop0);
632 break;
7767b7d2
JH		 633 case KVM_REG_MIPS_CP0_USERLOCAL:
634 v = (long)kvm_read_c0_guest_userlocal(cop0);
635 break;
4c73fb2b
DD		 636 case KVM_REG_MIPS_CP0_PAGEMASK:
637 v = (long)kvm_read_c0_guest_pagemask(cop0);
638 break;
639 case KVM_REG_MIPS_CP0_WIRED:
640 v = (long)kvm_read_c0_guest_wired(cop0);
641 break;
16fd5c1d
JH		 642 case KVM_REG_MIPS_CP0_HWRENA:
643 v = (long)kvm_read_c0_guest_hwrena(cop0);
644 break;
4c73fb2b
DD		 645 case KVM_REG_MIPS_CP0_BADVADDR:
646 v = (long)kvm_read_c0_guest_badvaddr(cop0);
647 break;
648 case KVM_REG_MIPS_CP0_ENTRYHI:
649 v = (long)kvm_read_c0_guest_entryhi(cop0);
650 break;
f8be02da
JH		 651 case KVM_REG_MIPS_CP0_COMPARE:
652 v = (long)kvm_read_c0_guest_compare(cop0);
653 break;
4c73fb2b
DD		 654 case KVM_REG_MIPS_CP0_STATUS:
655 v = (long)kvm_read_c0_guest_status(cop0);
656 break;
657 case KVM_REG_MIPS_CP0_CAUSE:
658 v = (long)kvm_read_c0_guest_cause(cop0);
659 break;
fb6df0cd
JH		 660 case KVM_REG_MIPS_CP0_EPC:
661 v = (long)kvm_read_c0_guest_epc(cop0);
662 break;
1068eaaf
JH		 663 case KVM_REG_MIPS_CP0_PRID:
664 v = (long)kvm_read_c0_guest_prid(cop0);
665 break;
4c73fb2b
DD		 666 case KVM_REG_MIPS_CP0_CONFIG:
667 v = (long)kvm_read_c0_guest_config(cop0);
668 break;
669 case KVM_REG_MIPS_CP0_CONFIG1:
670 v = (long)kvm_read_c0_guest_config1(cop0);
671 break;
672 case KVM_REG_MIPS_CP0_CONFIG2:
673 v = (long)kvm_read_c0_guest_config2(cop0);
674 break;
675 case KVM_REG_MIPS_CP0_CONFIG3:
676 v = (long)kvm_read_c0_guest_config3(cop0);
677 break;
c771607a
JH		 678 case KVM_REG_MIPS_CP0_CONFIG4:
679 v = (long)kvm_read_c0_guest_config4(cop0);
680 break;
681 case KVM_REG_MIPS_CP0_CONFIG5:
682 v = (long)kvm_read_c0_guest_config5(cop0);
683 break;
4c73fb2b
DD		 684 case KVM_REG_MIPS_CP0_CONFIG7:
685 v = (long)kvm_read_c0_guest_config7(cop0);
686 break;
e93d4c15
JH		 687 case KVM_REG_MIPS_CP0_ERROREPC:
688 v = (long)kvm_read_c0_guest_errorepc(cop0);
689 break;
f8be02da
JH		 690 /* registers to be handled specially */
691 case KVM_REG_MIPS_CP0_COUNT:
f8239342
JH		 692 case KVM_REG_MIPS_COUNT_CTL:
693 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 694 case KVM_REG_MIPS_COUNT_HZ:
f8be02da
JH		 695 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
696 if (ret)
697 return ret;
698 break;
4c73fb2b
DD		 699 default:
700 return -EINVAL;
701 }
681865d4
DD		 702 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
703 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 704
681865d4
DD		 705 return put_user(v, uaddr64);
706 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
707 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
708 u32 v32 = (u32)v;
d116e812 709
681865d4 710 return put_user(v32, uaddr32);
ab86bd60
JH		 711 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
712 void __user *uaddr = (void __user *)(long)reg->addr;
713
0178fd7d 714 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
681865d4
DD		 715 } else {
716 return -EINVAL;
717 }
4c73fb2b
DD		 718}
719
720static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
721 const struct kvm_one_reg *reg)
722{
4c73fb2b 723 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd
JH		 724 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
725 s64 v;
ab86bd60 726 s64 vs[2];
379245cd 727 unsigned int idx;
4c73fb2b 728
681865d4
DD		 729 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
730 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
731
732 if (get_user(v, uaddr64) != 0)
733 return -EFAULT;
734 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
735 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
736 s32 v32;
737
738 if (get_user(v32, uaddr32) != 0)
739 return -EFAULT;
740 v = (s64)v32;
ab86bd60
JH		 741 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
742 void __user *uaddr = (void __user *)(long)reg->addr;
743
0178fd7d 744 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
681865d4
DD		 745 } else {
746 return -EINVAL;
747 }
4c73fb2b
DD		 748
749 switch (reg->id) {
379245cd 750 /* General purpose registers */
4c73fb2b
DD		 751 case KVM_REG_MIPS_R0:
752 /* Silently ignore requests to set $0 */
753 break;
754 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
755 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
756 break;
757 case KVM_REG_MIPS_HI:
758 vcpu->arch.hi = v;
759 break;
760 case KVM_REG_MIPS_LO:
761 vcpu->arch.lo = v;
762 break;
763 case KVM_REG_MIPS_PC:
764 vcpu->arch.pc = v;
765 break;
766
379245cd
JH		 767 /* Floating point registers */
768 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
769 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
770 return -EINVAL;
771 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
772 /* Odd singles in top of even double when FR=0 */
773 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
774 set_fpr32(&fpu->fpr[idx], 0, v);
775 else
776 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
777 break;
778 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
779 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
780 return -EINVAL;
781 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
782 /* Can't access odd doubles in FR=0 mode */
783 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
784 return -EINVAL;
785 set_fpr64(&fpu->fpr[idx], 0, v);
786 break;
787 case KVM_REG_MIPS_FCR_IR:
788 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
789 return -EINVAL;
790 /* Read-only */
791 break;
792 case KVM_REG_MIPS_FCR_CSR:
793 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
794 return -EINVAL;
795 fpu->fcr31 = v;
796 break;
797
ab86bd60
JH		 798 /* MIPS SIMD Architecture (MSA) registers */
799 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
800 if (!kvm_mips_guest_has_msa(&vcpu->arch))
801 return -EINVAL;
802 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
803#ifdef CONFIG_CPU_LITTLE_ENDIAN
804 /* least significant byte first */
805 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
806 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
807#else
808 /* most significant byte first */
809 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
810 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
811#endif
812 break;
813 case KVM_REG_MIPS_MSA_IR:
814 if (!kvm_mips_guest_has_msa(&vcpu->arch))
815 return -EINVAL;
816 /* Read-only */
817 break;
818 case KVM_REG_MIPS_MSA_CSR:
819 if (!kvm_mips_guest_has_msa(&vcpu->arch))
820 return -EINVAL;
821 fpu->msacsr = v;
822 break;
823
379245cd 824 /* Co-processor 0 registers */
4c73fb2b
DD		 825 case KVM_REG_MIPS_CP0_INDEX:
826 kvm_write_c0_guest_index(cop0, v);
827 break;
828 case KVM_REG_MIPS_CP0_CONTEXT:
829 kvm_write_c0_guest_context(cop0, v);
830 break;
7767b7d2
JH		 831 case KVM_REG_MIPS_CP0_USERLOCAL:
832 kvm_write_c0_guest_userlocal(cop0, v);
833 break;
4c73fb2b
DD		 834 case KVM_REG_MIPS_CP0_PAGEMASK:
835 kvm_write_c0_guest_pagemask(cop0, v);
836 break;
837 case KVM_REG_MIPS_CP0_WIRED:
838 kvm_write_c0_guest_wired(cop0, v);
839 break;
16fd5c1d
JH		 840 case KVM_REG_MIPS_CP0_HWRENA:
841 kvm_write_c0_guest_hwrena(cop0, v);
842 break;
4c73fb2b
DD		 843 case KVM_REG_MIPS_CP0_BADVADDR:
844 kvm_write_c0_guest_badvaddr(cop0, v);
845 break;
846 case KVM_REG_MIPS_CP0_ENTRYHI:
847 kvm_write_c0_guest_entryhi(cop0, v);
848 break;
849 case KVM_REG_MIPS_CP0_STATUS:
850 kvm_write_c0_guest_status(cop0, v);
851 break;
fb6df0cd
JH		 852 case KVM_REG_MIPS_CP0_EPC:
853 kvm_write_c0_guest_epc(cop0, v);
854 break;
1068eaaf
JH		 855 case KVM_REG_MIPS_CP0_PRID:
856 kvm_write_c0_guest_prid(cop0, v);
857 break;
4c73fb2b
DD		 858 case KVM_REG_MIPS_CP0_ERROREPC:
859 kvm_write_c0_guest_errorepc(cop0, v);
860 break;
f8be02da
JH		 861 /* registers to be handled specially */
862 case KVM_REG_MIPS_CP0_COUNT:
863 case KVM_REG_MIPS_CP0_COMPARE:
e30492bb 864 case KVM_REG_MIPS_CP0_CAUSE:
c771607a
JH		 865 case KVM_REG_MIPS_CP0_CONFIG:
866 case KVM_REG_MIPS_CP0_CONFIG1:
867 case KVM_REG_MIPS_CP0_CONFIG2:
868 case KVM_REG_MIPS_CP0_CONFIG3:
869 case KVM_REG_MIPS_CP0_CONFIG4:
870 case KVM_REG_MIPS_CP0_CONFIG5:
f8239342
JH		 871 case KVM_REG_MIPS_COUNT_CTL:
872 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 873 case KVM_REG_MIPS_COUNT_HZ:
f8be02da 874 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 875 default:
876 return -EINVAL;
877 }
878 return 0;
879}
880
5fafd874
JH		 881static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
882 struct kvm_enable_cap *cap)
883{
884 int r = 0;
885
886 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
887 return -EINVAL;
888 if (cap->flags)
889 return -EINVAL;
890 if (cap->args[0])
891 return -EINVAL;
892
893 switch (cap->cap) {
894 case KVM_CAP_MIPS_FPU:
895 vcpu->arch.fpu_enabled = true;
896 break;
d952bd07
JH		 897 case KVM_CAP_MIPS_MSA:
898 vcpu->arch.msa_enabled = true;
899 break;
5fafd874
JH		 900 default:
901 r = -EINVAL;
902 break;
903 }
904
905 return r;
906}
907
d116e812
DCZ		 908long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
909 unsigned long arg)
669e846e
SL		 910{
911 struct kvm_vcpu *vcpu = filp->private_data;
912 void __user *argp = (void __user *)arg;
913 long r;
669e846e
SL		 914
915 switch (ioctl) {
4c73fb2b
DD		 916 case KVM_SET_ONE_REG:
917 case KVM_GET_ONE_REG: {
918 struct kvm_one_reg reg;
d116e812 919
4c73fb2b
DD		 920 if (copy_from_user(&reg, argp, sizeof(reg)))
921 return -EFAULT;
922 if (ioctl == KVM_SET_ONE_REG)
923 return kvm_mips_set_reg(vcpu, &reg);
924 else
925 return kvm_mips_get_reg(vcpu, &reg);
926 }
927 case KVM_GET_REG_LIST: {
928 struct kvm_reg_list __user *user_list = argp;
929 u64 __user *reg_dest;
930 struct kvm_reg_list reg_list;
931 unsigned n;
932
933 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
934 return -EFAULT;
935 n = reg_list.n;
936 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
937 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
938 return -EFAULT;
939 if (n < reg_list.n)
940 return -E2BIG;
941 reg_dest = user_list->reg;
942 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
943 sizeof(kvm_mips_get_one_regs)))
944 return -EFAULT;
945 return 0;
946 }
669e846e
SL		 947 case KVM_NMI:
948 /* Treat the NMI as a CPU reset */
949 r = kvm_mips_reset_vcpu(vcpu);
950 break;
951 case KVM_INTERRUPT:
952 {
953 struct kvm_mips_interrupt irq;
d116e812 954
669e846e
SL		 955 r = -EFAULT;
956 if (copy_from_user(&irq, argp, sizeof(irq)))
957 goto out;
958
669e846e
SL		 959 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
960 irq.irq);
961
962 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
963 break;
964 }
5fafd874
JH		 965 case KVM_ENABLE_CAP: {
966 struct kvm_enable_cap cap;
967
968 r = -EFAULT;
969 if (copy_from_user(&cap, argp, sizeof(cap)))
970 goto out;
971 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
972 break;
973 }
669e846e 974 default:
4c73fb2b 975 r = -ENOIOCTLCMD;
669e846e
SL		 976 }
977
978out:
979 return r;
980}
981
d116e812 982/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 983int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
984{
9f6b8029 985 struct kvm_memslots *slots;
669e846e
SL		 986 struct kvm_memory_slot *memslot;
987 unsigned long ga, ga_end;
988 int is_dirty = 0;
989 int r;
990 unsigned long n;
991
992 mutex_lock(&kvm->slots_lock);
993
994 r = kvm_get_dirty_log(kvm, log, &is_dirty);
995 if (r)
996 goto out;
997
998 /* If nothing is dirty, don't bother messing with page tables. */
999 if (is_dirty) {
9f6b8029
PB		 1000 slots = kvm_memslots(kvm);
1001 memslot = id_to_memslot(slots, log->slot);
669e846e
SL		 1002
1003 ga = memslot->base_gfn << PAGE_SHIFT;
1004 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1005
6ad78a5c
DCZ		 1006 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1007 ga_end);
669e846e
SL		 1008
1009 n = kvm_dirty_bitmap_bytes(memslot);
1010 memset(memslot->dirty_bitmap, 0, n);
1011 }
1012
1013 r = 0;
1014out:
1015 mutex_unlock(&kvm->slots_lock);
1016 return r;
1017
1018}
1019
1020long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1021{
1022 long r;
1023
1024 switch (ioctl) {
1025 default:
ed829857 1026 r = -ENOIOCTLCMD;
669e846e
SL		 1027 }
1028
1029 return r;
1030}
1031
1032int kvm_arch_init(void *opaque)
1033{
669e846e
SL		 1034 if (kvm_mips_callbacks) {
1035 kvm_err("kvm: module already exists\n");
1036 return -EEXIST;
1037 }
1038
d98403a5 1039 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 1040}
1041
1042void kvm_arch_exit(void)
1043{
1044 kvm_mips_callbacks = NULL;
1045}
1046
d116e812
DCZ		 1047int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1048 struct kvm_sregs *sregs)
669e846e 1049{
ed829857 1050 return -ENOIOCTLCMD;
669e846e
SL		 1051}
1052
d116e812
DCZ		 1053int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1054 struct kvm_sregs *sregs)
669e846e 1055{
ed829857 1056 return -ENOIOCTLCMD;
669e846e
SL		 1057}
1058
31928aa5 1059void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 1060{
669e846e
SL		 1061}
1062
1063int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1064{
ed829857 1065 return -ENOIOCTLCMD;
669e846e
SL		 1066}
1067
1068int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1069{
ed829857 1070 return -ENOIOCTLCMD;
669e846e
SL		 1071}
1072
1073int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1074{
1075 return VM_FAULT_SIGBUS;
1076}
1077
784aa3d7 1078int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 1079{
1080 int r;
1081
1082 switch (ext) {
4c73fb2b 1083 case KVM_CAP_ONE_REG:
5fafd874 1084 case KVM_CAP_ENABLE_CAP:
4c73fb2b
DD		 1085 r = 1;
1086 break;
669e846e
SL		 1087 case KVM_CAP_COALESCED_MMIO:
1088 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1089 break;
5fafd874 1090 case KVM_CAP_MIPS_FPU:
556f2a52
JH		 1091 /* We don't handle systems with inconsistent cpu_has_fpu */
1092 r = !!raw_cpu_has_fpu;
5fafd874 1093 break;
d952bd07
JH		 1094 case KVM_CAP_MIPS_MSA:
1095 /*
1096 * We don't support MSA vector partitioning yet:
1097 * 1) It would require explicit support which can't be tested
1098 * yet due to lack of support in current hardware.
1099 * 2) It extends the state that would need to be saved/restored
1100 * by e.g. QEMU for migration.
1101 *
1102 * When vector partitioning hardware becomes available, support
1103 * could be added by requiring a flag when enabling
1104 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1105 * to save/restore the appropriate extra state.
1106 */
1107 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1108 break;
669e846e
SL		 1109 default:
1110 r = 0;
1111 break;
1112 }
1113 return r;
669e846e
SL		 1114}
1115
1116int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1117{
1118 return kvm_mips_pending_timer(vcpu);
1119}
1120
1121int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1122{
1123 int i;
1124 struct mips_coproc *cop0;
1125
1126 if (!vcpu)
1127 return -1;
1128
6ad78a5c
DCZ		 1129 kvm_debug("VCPU Register Dump:\n");
1130 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1131 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 1132
1133 for (i = 0; i < 32; i += 4) {
6ad78a5c 1134 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 1135 vcpu->arch.gprs[i],
1136 vcpu->arch.gprs[i + 1],
1137 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1138 }
6ad78a5c
DCZ		 1139 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1140 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 1141
1142 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 1143 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1144 kvm_read_c0_guest_status(cop0),
1145 kvm_read_c0_guest_cause(cop0));
669e846e 1146
6ad78a5c 1147 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 1148
1149 return 0;
1150}
1151
1152int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1153{
1154 int i;
1155
8d17dd04 1156 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1157 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 1158 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 1159 vcpu->arch.hi = regs->hi;
1160 vcpu->arch.lo = regs->lo;
1161 vcpu->arch.pc = regs->pc;
1162
4c73fb2b 1163 return 0;
669e846e
SL		 1164}
1165
1166int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1167{
1168 int i;
1169
8d17dd04 1170 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1171 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 1172
1173 regs->hi = vcpu->arch.hi;
1174 regs->lo = vcpu->arch.lo;
1175 regs->pc = vcpu->arch.pc;
1176
4c73fb2b 1177 return 0;
669e846e
SL		 1178}
1179
0fae34f4 1180static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 1181{
1182 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1183
1184 kvm_mips_callbacks->queue_timer_int(vcpu);
1185
1186 vcpu->arch.wait = 0;
8577370f
MT		 1187 if (swait_active(&vcpu->wq))
1188 swake_up(&vcpu->wq);
669e846e
SL		 1189}
1190
d116e812 1191/* low level hrtimer wake routine */
0fae34f4 1192static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 1193{
1194 struct kvm_vcpu *vcpu;
1195
1196 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1197 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 1198 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 1199}
1200
1201int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1202{
1203 kvm_mips_callbacks->vcpu_init(vcpu);
1204 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1205 HRTIMER_MODE_REL);
1206 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 1207 return 0;
1208}
1209
d116e812
DCZ		 1210int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1211 struct kvm_translation *tr)
669e846e
SL		 1212{
1213 return 0;
1214}
1215
1216/* Initial guest state */
1217int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1218{
1219 return kvm_mips_callbacks->vcpu_setup(vcpu);
1220}
1221
d116e812 1222static void kvm_mips_set_c0_status(void)
669e846e 1223{
8cffd197 1224 u32 status = read_c0_status();
669e846e 1225
669e846e
SL		 1226 if (cpu_has_dsp)
1227 status |= (ST0_MX);
1228
1229 write_c0_status(status);
1230 ehb();
1231}
1232
1233/*
1234 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1235 */
1236int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1237{
8cffd197
JH		 1238 u32 cause = vcpu->arch.host_cp0_cause;
1239 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1240 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
669e846e
SL		 1241 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1242 enum emulation_result er = EMULATE_DONE;
1243 int ret = RESUME_GUEST;
1244
c4c6f2ca
JH		 1245 /* re-enable HTW before enabling interrupts */
1246 htw_start();
1247
669e846e
SL		 1248 /* Set a default exit reason */
1249 run->exit_reason = KVM_EXIT_UNKNOWN;
1250 run->ready_for_interrupt_injection = 1;
1251
d116e812
DCZ		 1252 /*
1253 * Set the appropriate status bits based on host CPU features,
1254 * before we hit the scheduler
1255 */
669e846e
SL		 1256 kvm_mips_set_c0_status();
1257
1258 local_irq_enable();
1259
1260 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1261 cause, opc, run, vcpu);
1e09e86a 1262 trace_kvm_exit(vcpu, exccode);
669e846e 1263
d116e812
DCZ		 1264 /*
1265 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1266 * causing an exception to be delivered to the Guest Kernel
1267 */
1268 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1269 if (er == EMULATE_PRIV_FAIL) {
1270 goto skip_emul;
1271 } else if (er == EMULATE_FAIL) {
1272 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1273 ret = RESUME_HOST;
1274 goto skip_emul;
1275 }
1276
1277 switch (exccode) {
16d100db
JH		 1278 case EXCCODE_INT:
1279 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
669e846e
SL		 1280
1281 ++vcpu->stat.int_exits;
669e846e 1282
d116e812 1283 if (need_resched())
669e846e 1284 cond_resched();
669e846e
SL		 1285
1286 ret = RESUME_GUEST;
1287 break;
1288
16d100db
JH		 1289 case EXCCODE_CPU:
1290 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
669e846e
SL		 1291
1292 ++vcpu->stat.cop_unusable_exits;
669e846e
SL		 1293 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1294 /* XXXKYMA: Might need to return to user space */
d116e812 1295 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1296 ret = RESUME_HOST;
669e846e
SL		 1297 break;
1298
16d100db 1299 case EXCCODE_MOD:
669e846e 1300 ++vcpu->stat.tlbmod_exits;
669e846e
SL		 1301 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1302 break;
1303
16d100db 1304 case EXCCODE_TLBS:
d116e812
DCZ		 1305 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1306 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1307 badvaddr);
669e846e
SL		 1308
1309 ++vcpu->stat.tlbmiss_st_exits;
669e846e
SL		 1310 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1311 break;
1312
16d100db 1313 case EXCCODE_TLBL:
669e846e
SL		 1314 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1315 cause, opc, badvaddr);
1316
1317 ++vcpu->stat.tlbmiss_ld_exits;
669e846e
SL		 1318 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1319 break;
1320
16d100db 1321 case EXCCODE_ADES:
669e846e 1322 ++vcpu->stat.addrerr_st_exits;
669e846e
SL		 1323 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1324 break;
1325
16d100db 1326 case EXCCODE_ADEL:
669e846e 1327 ++vcpu->stat.addrerr_ld_exits;
669e846e
SL		 1328 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1329 break;
1330
16d100db 1331 case EXCCODE_SYS:
669e846e 1332 ++vcpu->stat.syscall_exits;
669e846e
SL		 1333 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1334 break;
1335
16d100db 1336 case EXCCODE_RI:
669e846e 1337 ++vcpu->stat.resvd_inst_exits;
669e846e
SL		 1338 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1339 break;
1340
16d100db 1341 case EXCCODE_BP:
669e846e 1342 ++vcpu->stat.break_inst_exits;
669e846e
SL		 1343 ret = kvm_mips_callbacks->handle_break(vcpu);
1344 break;
1345
16d100db 1346 case EXCCODE_TR:
0a560427 1347 ++vcpu->stat.trap_inst_exits;
0a560427
JH		 1348 ret = kvm_mips_callbacks->handle_trap(vcpu);
1349 break;
1350
16d100db 1351 case EXCCODE_MSAFPE:
c2537ed9 1352 ++vcpu->stat.msa_fpe_exits;
c2537ed9
JH		 1353 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1354 break;
1355
16d100db 1356 case EXCCODE_FPE:
1c0cd66a 1357 ++vcpu->stat.fpe_exits;
1c0cd66a
JH		 1358 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1359 break;
1360
16d100db 1361 case EXCCODE_MSADIS:
c2537ed9 1362 ++vcpu->stat.msa_disabled_exits;
98119ad5
JH		 1363 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1364 break;
1365
669e846e 1366 default:
d116e812
DCZ		 1367 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1368 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1369 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1370 kvm_arch_vcpu_dump_regs(vcpu);
1371 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1372 ret = RESUME_HOST;
1373 break;
1374
1375 }
1376
1377skip_emul:
1378 local_irq_disable();
1379
1380 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1381 kvm_mips_deliver_interrupts(vcpu, cause);
1382
1383 if (!(ret & RESUME_HOST)) {
d116e812 1384 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1385 if (signal_pending(current)) {
1386 run->exit_reason = KVM_EXIT_INTR;
1387 ret = (-EINTR << 2) | RESUME_HOST;
1388 ++vcpu->stat.signal_exits;
1e09e86a 1389 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
669e846e
SL		 1390 }
1391 }
1392
98e91b84 1393 if (ret == RESUME_GUEST) {
93258604
JH		 1394 trace_kvm_reenter(vcpu);
1395
98e91b84 1396 /*
539cb89f
JH		 1397 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1398 * is live), restore FCR31 / MSACSR.
98e91b84
JH		 1399 *
1400 * This should be before returning to the guest exception
539cb89f
JH		 1401 * vector, as it may well cause an [MSA] FP exception if there
1402 * are pending exception bits unmasked. (see
98e91b84
JH		 1403 * kvm_mips_csr_die_notifier() for how that is handled).
1404 */
1405 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1406 read_c0_status() & ST0_CU1)
1407 __kvm_restore_fcsr(&vcpu->arch);
539cb89f
JH		 1408
1409 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1410 read_c0_config5() & MIPS_CONF5_MSAEN)
1411 __kvm_restore_msacsr(&vcpu->arch);
98e91b84
JH		 1412 }
1413
c4c6f2ca
JH		 1414 /* Disable HTW before returning to guest or host */
1415 htw_stop();
1416
669e846e
SL		 1417 return ret;
1418}
1419
98e91b84
JH		 1420/* Enable FPU for guest and restore context */
1421void kvm_own_fpu(struct kvm_vcpu *vcpu)
1422{
1423 struct mips_coproc *cop0 = vcpu->arch.cop0;
1424 unsigned int sr, cfg5;
1425
1426 preempt_disable();
1427
539cb89f
JH		 1428 sr = kvm_read_c0_guest_status(cop0);
1429
1430 /*
1431 * If MSA state is already live, it is undefined how it interacts with
1432 * FR=0 FPU state, and we don't want to hit reserved instruction
1433 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1434 * play it safe and save it first.
1435 *
1436 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1437 * get called when guest CU1 is set, however we can't trust the guest
1438 * not to clobber the status register directly via the commpage.
1439 */
1440 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
f943176a 1441 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
539cb89f
JH		 1442 kvm_lose_fpu(vcpu);
1443
98e91b84
JH		 1444 /*
1445 * Enable FPU for guest
1446 * We set FR and FRE according to guest context
1447 */
98e91b84
JH		 1448 change_c0_status(ST0_CU1 | ST0_FR, sr);
1449 if (cpu_has_fre) {
1450 cfg5 = kvm_read_c0_guest_config5(cop0);
1451 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1452 }
1453 enable_fpu_hazard();
1454
1455 /* If guest FPU state not active, restore it now */
f943176a 1456 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
98e91b84 1457 __kvm_restore_fpu(&vcpu->arch);
f943176a 1458 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1459 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1460 } else {
1461 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1462 }
1463
1464 preempt_enable();
1465}
1466
539cb89f
JH		 1467#ifdef CONFIG_CPU_HAS_MSA
1468/* Enable MSA for guest and restore context */
1469void kvm_own_msa(struct kvm_vcpu *vcpu)
1470{
1471 struct mips_coproc *cop0 = vcpu->arch.cop0;
1472 unsigned int sr, cfg5;
1473
1474 preempt_disable();
1475
1476 /*
1477 * Enable FPU if enabled in guest, since we're restoring FPU context
1478 * anyway. We set FR and FRE according to guest context.
1479 */
1480 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1481 sr = kvm_read_c0_guest_status(cop0);
1482
1483 /*
1484 * If FR=0 FPU state is already live, it is undefined how it
1485 * interacts with MSA state, so play it safe and save it first.
1486 */
1487 if (!(sr & ST0_FR) &&
f943176a
JH		 1488 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1489 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
539cb89f
JH		 1490 kvm_lose_fpu(vcpu);
1491
1492 change_c0_status(ST0_CU1 | ST0_FR, sr);
1493 if (sr & ST0_CU1 && cpu_has_fre) {
1494 cfg5 = kvm_read_c0_guest_config5(cop0);
1495 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1496 }
1497 }
1498
1499 /* Enable MSA for guest */
1500 set_c0_config5(MIPS_CONF5_MSAEN);
1501 enable_fpu_hazard();
1502
f943176a
JH		 1503 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1504 case KVM_MIPS_AUX_FPU:
539cb89f
JH		 1505 /*
1506 * Guest FPU state already loaded, only restore upper MSA state
1507 */
1508 __kvm_restore_msa_upper(&vcpu->arch);
f943176a 1509 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
04ebebf4 1510 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1511 break;
1512 case 0:
1513 /* Neither FPU or MSA already active, restore full MSA state */
1514 __kvm_restore_msa(&vcpu->arch);
f943176a 1515 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
539cb89f 1516 if (kvm_mips_guest_has_fpu(&vcpu->arch))
f943176a 1517 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1519 KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1520 break;
1521 default:
04ebebf4 1522 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1523 break;
1524 }
1525
1526 preempt_enable();
1527}
1528#endif
1529
1530/* Drop FPU & MSA without saving it */
98e91b84
JH		 1531void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1532{
1533 preempt_disable();
f943176a 1534 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f 1535 disable_msa();
04ebebf4 1536 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
f943176a 1537 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
539cb89f 1538 }
f943176a 1539 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84 1540 clear_c0_status(ST0_CU1 | ST0_FR);
04ebebf4 1541 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
f943176a 1542 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
98e91b84
JH		 1543 }
1544 preempt_enable();
1545}
1546
539cb89f 1547/* Save and disable FPU & MSA */
98e91b84
JH		 1548void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1549{
1550 /*
539cb89f
JH		 1551 * FPU & MSA get disabled in root context (hardware) when it is disabled
1552 * in guest context (software), but the register state in the hardware
1553 * may still be in use. This is why we explicitly re-enable the hardware
98e91b84
JH		 1554 * before saving.
1555 */
1556
1557 preempt_disable();
f943176a 1558 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f
JH		 1559 set_c0_config5(MIPS_CONF5_MSAEN);
1560 enable_fpu_hazard();
1561
1562 __kvm_save_msa(&vcpu->arch);
04ebebf4 1563 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1564
1565 /* Disable MSA & FPU */
1566 disable_msa();
f943176a 1567 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
539cb89f 1568 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429
JH		 1569 disable_fpu_hazard();
1570 }
f943176a
JH		 1571 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1572 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84
JH		 1573 set_c0_status(ST0_CU1);
1574 enable_fpu_hazard();
1575
1576 __kvm_save_fpu(&vcpu->arch);
f943176a 1577 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
04ebebf4 1578 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1579
1580 /* Disable FPU */
1581 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429 1582 disable_fpu_hazard();
98e91b84
JH		 1583 }
1584 preempt_enable();
1585}
1586
1587/*
539cb89f
JH		 1588 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1589 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1590 * exception if cause bits are set in the value being written.
98e91b84
JH		 1591 */
1592static int kvm_mips_csr_die_notify(struct notifier_block *self,
1593 unsigned long cmd, void *ptr)
1594{
1595 struct die_args *args = (struct die_args *)ptr;
1596 struct pt_regs *regs = args->regs;
1597 unsigned long pc;
1598
539cb89f
JH		 1599 /* Only interested in FPE and MSAFPE */
1600 if (cmd != DIE_FP && cmd != DIE_MSAFP)
98e91b84
JH		 1601 return NOTIFY_DONE;
1602
1603 /* Return immediately if guest context isn't active */
1604 if (!(current->flags & PF_VCPU))
1605 return NOTIFY_DONE;
1606
1607 /* Should never get here from user mode */
1608 BUG_ON(user_mode(regs));
1609
1610 pc = instruction_pointer(regs);
1611 switch (cmd) {
1612 case DIE_FP:
1613 /* match 2nd instruction in __kvm_restore_fcsr */
1614 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1615 return NOTIFY_DONE;
1616 break;
539cb89f
JH		 1617 case DIE_MSAFP:
1618 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1619 if (!cpu_has_msa ||
1620 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1621 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1622 return NOTIFY_DONE;
1623 break;
98e91b84
JH		 1624 }
1625
1626 /* Move PC forward a little and continue executing */
1627 instruction_pointer(regs) += 4;
1628
1629 return NOTIFY_STOP;
1630}
1631
1632static struct notifier_block kvm_mips_csr_die_notifier = {
1633 .notifier_call = kvm_mips_csr_die_notify,
1634};
1635
2db9d233 1636static int __init kvm_mips_init(void)
669e846e
SL		 1637{
1638 int ret;
1639
1640 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1641
1642 if (ret)
1643 return ret;
1644
98e91b84
JH		 1645 register_die_notifier(&kvm_mips_csr_die_notifier);
1646
669e846e
SL		 1647 return 0;
1648}
1649
2db9d233 1650static void __exit kvm_mips_exit(void)
669e846e
SL		 1651{
1652 kvm_exit();
1653
98e91b84 1654 unregister_die_notifier(&kvm_mips_csr_die_notifier);
669e846e
SL		 1655}
1656
1657module_init(kvm_mips_init);
1658module_exit(kvm_mips_exit);
1659
1660EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux kernel - Deliverables
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