[deliverable/linux.git] / arch / mips / math-emu / sp_sub.c

/* IEEE754 floating point arithmetic
 * single precision
 */
/*
 * MIPS floating point support
 * Copyright (C) 1994-2000 Algorithmics Ltd.
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
 */

#include "ieee754sp.h"

union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
{
	int s;

	COMPXSP;
	COMPYSP;

	EXPLODEXSP;
	EXPLODEYSP;

	ieee754_clearcx();

	FLUSHXSP;
	FLUSHYSP;

	switch (CLPAIR(xc, yc)) {
	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
		return ieee754sp_nanxcpt(y);

	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
		return ieee754sp_nanxcpt(x);

	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
		return y;

	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
		return x;


	/*
	 * Infinity handling
	 */
	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
		if (xs != ys)
			return x;
		ieee754_setcx(IEEE754_INVALID_OPERATION);
		return ieee754sp_indef();

	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
		return ieee754sp_inf(ys ^ 1);

	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
		return x;

	/*
	 * Zero handling
	 */
	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
		if (xs != ys)
			return x;
		else
			return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);

	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
		return x;

	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
		/* quick fix up */
		SPSIGN(y) ^= 1;
		return y;

	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
		SPDNORMX;

	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
		SPDNORMY;
		break;

	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
		SPDNORMX;
		break;

	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
		break;
	}
	/* flip sign of y and handle as add */
	ys ^= 1;

	assert(xm & SP_HIDDEN_BIT);
	assert(ym & SP_HIDDEN_BIT);


	/* provide guard,round and stick bit space */
	xm <<= 3;
	ym <<= 3;

	if (xe > ye) {
		/*
		 * have to shift y fraction right to align
		 */
		s = xe - ye;
		ym = XSPSRS(ym, s);
		ye += s;
	} else if (ye > xe) {
		/*
		 * have to shift x fraction right to align
		 */
		s = ye - xe;
		xm = XSPSRS(xm, s);
		xe += s;
	}
	assert(xe == ye);
	assert(xe <= SP_EMAX);

	if (xs == ys) {
		/* generate 28 bit result of adding two 27 bit numbers
		 */
		xm = xm + ym;

		if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
			SPXSRSX1();	/* shift preserving sticky */
		}
	} else {
		if (xm >= ym) {
			xm = xm - ym;
		} else {
			xm = ym - xm;
			xs = ys;
		}
		if (xm == 0) {
			if (ieee754_csr.rm == FPU_CSR_RD)
				return ieee754sp_zero(1);	/* round negative inf. => sign = -1 */
			else
				return ieee754sp_zero(0);	/* other round modes   => sign = 1 */
		}
		/* normalize to rounding precision
		 */
		while ((xm >> (SP_FBITS + 3)) == 0) {
			xm <<= 1;
			xe--;
		}
	}

	return ieee754sp_format(xs, xe, xm);
}
Commit	Line	Data
1da177e4 LT	1	/* IEEE754 floating point arithmetic
	2	* single precision
	3	*/
	4	/*
	5	* MIPS floating point support
	6	* Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4	7	*
1da177e4 LT	8	* This program is free software; you can distribute it and/or modify it
	9	* under the terms of the GNU General Public License (Version 2) as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, write to the Free Software Foundation, Inc.,
3f7cac41	19	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1da177e4 LT	20	*/
1da177e4 LT	21
1da177e4 LT	22	#include "ieee754sp.h"
1da177e4 LT	23
2209bcb1	24	union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
1da177e4	25	{
3f7cac41 RB	26	int s;
3f7cac41 RB	27
1da177e4 LT	28	COMPXSP;
	29	COMPYSP;
	30
	31	EXPLODEXSP;
	32	EXPLODEYSP;
	33
9e8bad1f	34	ieee754_clearcx();
1da177e4 LT	35
	36	FLUSHXSP;
	37	FLUSHYSP;
	38
	39	switch (CLPAIR(xc, yc)) {
1da177e4	40	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
1da177e4 LT	41	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
	42	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
	43	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
	44	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
d5afa7e9 MR	45	return ieee754sp_nanxcpt(y);
	46
	47	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
	48	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
1da177e4 LT	49	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
	50	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
	51	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
	52	case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
d5afa7e9	53	return ieee754sp_nanxcpt(x);
1da177e4 LT	54
	55	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
	56	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
	57	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
	58	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
	59	return y;
	60
	61	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
	62	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
	63	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
	64	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
	65	case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
	66	return x;
	67
	68
3f7cac41 RB	69	/*
	70	* Infinity handling
	71	*/
1da177e4 LT	72	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
	73	if (xs != ys)
	74	return x;
9e8bad1f	75	ieee754_setcx(IEEE754_INVALID_OPERATION);
90efba36	76	return ieee754sp_indef();
1da177e4 LT	77
	78	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
	79	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
	80	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
	81	return ieee754sp_inf(ys ^ 1);
	82
	83	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
	84	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
	85	case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
	86	return x;
	87
3f7cac41 RB	88	/*
	89	* Zero handling
	90	*/
1da177e4 LT	91	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
	92	if (xs != ys)
	93	return x;
	94	else
56a64733	95	return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
1da177e4 LT	96
	97	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
	98	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
	99	return x;
	100
	101	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
	102	case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
	103	/* quick fix up */
3e160aad	104	SPSIGN(y) ^= 1;
1da177e4 LT	105	return y;
	106
	107	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
	108	SPDNORMX;
	109
	110	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
	111	SPDNORMY;
	112	break;
	113
	114	case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
	115	SPDNORMX;
	116	break;
	117
	118	case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
	119	break;
	120	}
	121	/* flip sign of y and handle as add */
	122	ys ^= 1;
	123
	124	assert(xm & SP_HIDDEN_BIT);
	125	assert(ym & SP_HIDDEN_BIT);
	126
	127
	128	/* provide guard,round and stick bit space */
	129	xm <<= 3;
	130	ym <<= 3;
	131
	132	if (xe > ye) {
3f7cac41 RB	133	/*
3f7cac41 RB	134	* have to shift y fraction right to align
1da177e4	135	*/
3f7cac41	136	s = xe - ye;
db57f29d PB	137	ym = XSPSRS(ym, s);
db57f29d PB	138	ye += s;
1da177e4	139	} else if (ye > xe) {
3f7cac41 RB	140	/*
3f7cac41 RB	141	* have to shift x fraction right to align
1da177e4	142	*/
3f7cac41	143	s = ye - xe;
db57f29d PB	144	xm = XSPSRS(xm, s);
db57f29d PB	145	xe += s;
1da177e4 LT	146	}
	147	assert(xe == ye);
	148	assert(xe <= SP_EMAX);
	149
	150	if (xs == ys) {
	151	/* generate 28 bit result of adding two 27 bit numbers
	152	*/
	153	xm = xm + ym;
1da177e4	154
ad8fb553	155	if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
1da177e4 LT	156	SPXSRSX1(); /* shift preserving sticky */
	157	}
	158	} else {
	159	if (xm >= ym) {
	160	xm = xm - ym;
1da177e4 LT	161	} else {
1da177e4 LT	162	xm = ym - xm;
1da177e4 LT	163	xs = ys;
	164	}
	165	if (xm == 0) {
56a64733	166	if (ieee754_csr.rm == FPU_CSR_RD)
1da177e4 LT	167	return ieee754sp_zero(1); /* round negative inf. => sign = -1 */
	168	else
	169	return ieee754sp_zero(0); /* other round modes => sign = 1 */
	170	}
	171	/* normalize to rounding precision
	172	*/
ad8fb553	173	while ((xm >> (SP_FBITS + 3)) == 0) {
1da177e4 LT	174	xm <<= 1;
	175	xe--;
	176	}
	177	}
90efba36 RB	178
90efba36 RB	179	return ieee754sp_format(xs, xe, xm);
1da177e4	180	}