Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
95affdda | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
41c594ab RB |
12 | * |
13 | * ... and the days got worse and worse and now you see | |
14 | * I've gone completly out of my mind. | |
15 | * | |
16 | * They're coming to take me a away haha | |
17 | * they're coming to take me a away hoho hihi haha | |
18 | * to the funny farm where code is beautiful all the time ... | |
19 | * | |
20 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
21 | */ |
22 | ||
95affdda | 23 | #include <linux/bug.h> |
1da177e4 LT |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
631330f5 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/string.h> |
28 | #include <linux/init.h> | |
29 | ||
1da177e4 | 30 | #include <asm/mmu_context.h> |
1da177e4 LT |
31 | #include <asm/war.h> |
32 | ||
e30ec452 TS |
33 | #include "uasm.h" |
34 | ||
aeffdbba | 35 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
36 | { |
37 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
38 | return 0; | |
39 | } | |
40 | ||
aeffdbba | 41 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
42 | { |
43 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
44 | return 0; | |
45 | } | |
46 | ||
aeffdbba | 47 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
48 | { |
49 | return BCM1250_M3_WAR; | |
50 | } | |
51 | ||
aeffdbba | 52 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
53 | { |
54 | return R10000_LLSC_WAR; | |
55 | } | |
56 | ||
8df5beac MR |
57 | /* |
58 | * Found by experiment: At least some revisions of the 4kc throw under | |
59 | * some circumstances a machine check exception, triggered by invalid | |
60 | * values in the index register. Delaying the tlbp instruction until | |
61 | * after the next branch, plus adding an additional nop in front of | |
62 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
63 | * why; it's not an issue caused by the core RTL. | |
64 | * | |
65 | */ | |
234fcd14 | 66 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
67 | { |
68 | return (current_cpu_data.processor_id & 0xffff00) == | |
69 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
70 | } | |
71 | ||
e30ec452 | 72 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 73 | enum label_id { |
e30ec452 | 74 | label_second_part = 1, |
1da177e4 | 75 | label_leave, |
656be92f AN |
76 | #ifdef MODULE_START |
77 | label_module_alloc, | |
78 | #endif | |
1da177e4 LT |
79 | label_vmalloc, |
80 | label_vmalloc_done, | |
81 | label_tlbw_hazard, | |
82 | label_split, | |
83 | label_nopage_tlbl, | |
84 | label_nopage_tlbs, | |
85 | label_nopage_tlbm, | |
86 | label_smp_pgtable_change, | |
87 | label_r3000_write_probe_fail, | |
fd062c84 DD |
88 | #ifdef CONFIG_HUGETLB_PAGE |
89 | label_tlb_huge_update, | |
90 | #endif | |
1da177e4 LT |
91 | }; |
92 | ||
e30ec452 TS |
93 | UASM_L_LA(_second_part) |
94 | UASM_L_LA(_leave) | |
656be92f | 95 | #ifdef MODULE_START |
e30ec452 | 96 | UASM_L_LA(_module_alloc) |
619b6e18 | 97 | #endif |
e30ec452 TS |
98 | UASM_L_LA(_vmalloc) |
99 | UASM_L_LA(_vmalloc_done) | |
100 | UASM_L_LA(_tlbw_hazard) | |
101 | UASM_L_LA(_split) | |
102 | UASM_L_LA(_nopage_tlbl) | |
103 | UASM_L_LA(_nopage_tlbs) | |
104 | UASM_L_LA(_nopage_tlbm) | |
105 | UASM_L_LA(_smp_pgtable_change) | |
106 | UASM_L_LA(_r3000_write_probe_fail) | |
fd062c84 DD |
107 | #ifdef CONFIG_HUGETLB_PAGE |
108 | UASM_L_LA(_tlb_huge_update) | |
109 | #endif | |
656be92f | 110 | |
92b1e6a6 FBH |
111 | /* |
112 | * For debug purposes. | |
113 | */ | |
114 | static inline void dump_handler(const u32 *handler, int count) | |
115 | { | |
116 | int i; | |
117 | ||
118 | pr_debug("\t.set push\n"); | |
119 | pr_debug("\t.set noreorder\n"); | |
120 | ||
121 | for (i = 0; i < count; i++) | |
122 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
123 | ||
124 | pr_debug("\t.set pop\n"); | |
125 | } | |
126 | ||
1da177e4 LT |
127 | /* The only general purpose registers allowed in TLB handlers. */ |
128 | #define K0 26 | |
129 | #define K1 27 | |
130 | ||
131 | /* Some CP0 registers */ | |
41c594ab RB |
132 | #define C0_INDEX 0, 0 |
133 | #define C0_ENTRYLO0 2, 0 | |
134 | #define C0_TCBIND 2, 2 | |
135 | #define C0_ENTRYLO1 3, 0 | |
136 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 137 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
138 | #define C0_BADVADDR 8, 0 |
139 | #define C0_ENTRYHI 10, 0 | |
140 | #define C0_EPC 14, 0 | |
141 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 142 | |
875d43e7 | 143 | #ifdef CONFIG_64BIT |
e30ec452 | 144 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 145 | #else |
e30ec452 | 146 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
147 | #endif |
148 | ||
149 | /* The worst case length of the handler is around 18 instructions for | |
150 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
151 | * Maximum space available is 32 instructions for R3000 and 64 | |
152 | * instructions for R4000. | |
153 | * | |
154 | * We deliberately chose a buffer size of 128, so we won't scribble | |
155 | * over anything important on overflow before we panic. | |
156 | */ | |
234fcd14 | 157 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
158 | |
159 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
160 | static struct uasm_label labels[128] __cpuinitdata; |
161 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 LT |
162 | |
163 | /* | |
164 | * The R3000 TLB handler is simple. | |
165 | */ | |
234fcd14 | 166 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
167 | { |
168 | long pgdc = (long)pgd_current; | |
169 | u32 *p; | |
170 | ||
171 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
172 | p = tlb_handler; | |
173 | ||
e30ec452 TS |
174 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
175 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
176 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
177 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
178 | uasm_i_sll(&p, K0, K0, 2); | |
179 | uasm_i_addu(&p, K1, K1, K0); | |
180 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
181 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
182 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
183 | uasm_i_addu(&p, K1, K1, K0); | |
184 | uasm_i_lw(&p, K0, 0, K1); | |
185 | uasm_i_nop(&p); /* load delay */ | |
186 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
187 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
188 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
189 | uasm_i_jr(&p, K1); | |
190 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
191 | |
192 | if (p > tlb_handler + 32) | |
193 | panic("TLB refill handler space exceeded"); | |
194 | ||
e30ec452 TS |
195 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
196 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 197 | |
91b05e67 | 198 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
199 | |
200 | dump_handler((u32 *)ebase, 32); | |
1da177e4 LT |
201 | } |
202 | ||
203 | /* | |
204 | * The R4000 TLB handler is much more complicated. We have two | |
205 | * consecutive handler areas with 32 instructions space each. | |
206 | * Since they aren't used at the same time, we can overflow in the | |
207 | * other one.To keep things simple, we first assume linear space, | |
208 | * then we relocate it to the final handler layout as needed. | |
209 | */ | |
234fcd14 | 210 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
211 | |
212 | /* | |
213 | * Hazards | |
214 | * | |
215 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
216 | * 2. A timing hazard exists for the TLBP instruction. | |
217 | * | |
218 | * stalling_instruction | |
219 | * TLBP | |
220 | * | |
221 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
222 | * previous instruction. This is not really correct as the stalling instruction | |
223 | * can modify the address used to access the JTLB. The failure symptom is that | |
224 | * the TLBP instruction will use an address created for the stalling instruction | |
225 | * and not the address held in C0_ENHI and thus report the wrong results. | |
226 | * | |
227 | * The software work-around is to not allow the instruction preceding the TLBP | |
228 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
229 | * | |
230 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
231 | * | |
232 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
233 | */ | |
234fcd14 | 234 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 235 | { |
10cc3529 | 236 | switch (current_cpu_type()) { |
326e2e1a | 237 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 238 | case CPU_R4600: |
326e2e1a | 239 | case CPU_R4700: |
1da177e4 LT |
240 | case CPU_R5000: |
241 | case CPU_R5000A: | |
242 | case CPU_NEVADA: | |
e30ec452 TS |
243 | uasm_i_nop(p); |
244 | uasm_i_tlbp(p); | |
1da177e4 LT |
245 | break; |
246 | ||
247 | default: | |
e30ec452 | 248 | uasm_i_tlbp(p); |
1da177e4 LT |
249 | break; |
250 | } | |
251 | } | |
252 | ||
253 | /* | |
254 | * Write random or indexed TLB entry, and care about the hazards from | |
255 | * the preceeding mtc0 and for the following eret. | |
256 | */ | |
257 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
258 | ||
234fcd14 | 259 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 260 | struct uasm_reloc **r, |
1da177e4 LT |
261 | enum tlb_write_entry wmode) |
262 | { | |
263 | void(*tlbw)(u32 **) = NULL; | |
264 | ||
265 | switch (wmode) { | |
e30ec452 TS |
266 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
267 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
268 | } |
269 | ||
161548bf | 270 | if (cpu_has_mips_r2) { |
41f0e4d0 DD |
271 | if (cpu_has_mips_r2_exec_hazard) |
272 | uasm_i_ehb(p); | |
161548bf RB |
273 | tlbw(p); |
274 | return; | |
275 | } | |
276 | ||
10cc3529 | 277 | switch (current_cpu_type()) { |
1da177e4 LT |
278 | case CPU_R4000PC: |
279 | case CPU_R4000SC: | |
280 | case CPU_R4000MC: | |
281 | case CPU_R4400PC: | |
282 | case CPU_R4400SC: | |
283 | case CPU_R4400MC: | |
284 | /* | |
285 | * This branch uses up a mtc0 hazard nop slot and saves | |
286 | * two nops after the tlbw instruction. | |
287 | */ | |
e30ec452 | 288 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 289 | tlbw(p); |
e30ec452 TS |
290 | uasm_l_tlbw_hazard(l, *p); |
291 | uasm_i_nop(p); | |
1da177e4 LT |
292 | break; |
293 | ||
294 | case CPU_R4600: | |
295 | case CPU_R4700: | |
296 | case CPU_R5000: | |
297 | case CPU_R5000A: | |
e30ec452 | 298 | uasm_i_nop(p); |
2c93e12c | 299 | tlbw(p); |
e30ec452 | 300 | uasm_i_nop(p); |
2c93e12c MR |
301 | break; |
302 | ||
303 | case CPU_R4300: | |
1da177e4 LT |
304 | case CPU_5KC: |
305 | case CPU_TX49XX: | |
bdf21b18 | 306 | case CPU_PR4450: |
e30ec452 | 307 | uasm_i_nop(p); |
1da177e4 LT |
308 | tlbw(p); |
309 | break; | |
310 | ||
311 | case CPU_R10000: | |
312 | case CPU_R12000: | |
44d921b2 | 313 | case CPU_R14000: |
1da177e4 | 314 | case CPU_4KC: |
b1ec4c8e | 315 | case CPU_4KEC: |
1da177e4 | 316 | case CPU_SB1: |
93ce2f52 | 317 | case CPU_SB1A: |
1da177e4 LT |
318 | case CPU_4KSC: |
319 | case CPU_20KC: | |
320 | case CPU_25KF: | |
1c0c13eb AJ |
321 | case CPU_BCM3302: |
322 | case CPU_BCM4710: | |
2a21c730 | 323 | case CPU_LOONGSON2: |
0de663ef MB |
324 | case CPU_BCM6338: |
325 | case CPU_BCM6345: | |
326 | case CPU_BCM6348: | |
327 | case CPU_BCM6358: | |
a644b277 | 328 | case CPU_R5500: |
8df5beac | 329 | if (m4kc_tlbp_war()) |
e30ec452 | 330 | uasm_i_nop(p); |
2f794d09 | 331 | case CPU_ALCHEMY: |
1da177e4 LT |
332 | tlbw(p); |
333 | break; | |
334 | ||
335 | case CPU_NEVADA: | |
e30ec452 | 336 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
337 | /* |
338 | * This branch uses up a mtc0 hazard nop slot and saves | |
339 | * a nop after the tlbw instruction. | |
340 | */ | |
e30ec452 | 341 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 342 | tlbw(p); |
e30ec452 | 343 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
344 | break; |
345 | ||
346 | case CPU_RM7000: | |
e30ec452 TS |
347 | uasm_i_nop(p); |
348 | uasm_i_nop(p); | |
349 | uasm_i_nop(p); | |
350 | uasm_i_nop(p); | |
1da177e4 LT |
351 | tlbw(p); |
352 | break; | |
353 | ||
1da177e4 LT |
354 | case CPU_RM9000: |
355 | /* | |
356 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
357 | * use of the JTLB for instructions should not occur for 4 | |
358 | * cpu cycles and use for data translations should not occur | |
359 | * for 3 cpu cycles. | |
360 | */ | |
e30ec452 TS |
361 | uasm_i_ssnop(p); |
362 | uasm_i_ssnop(p); | |
363 | uasm_i_ssnop(p); | |
364 | uasm_i_ssnop(p); | |
1da177e4 | 365 | tlbw(p); |
e30ec452 TS |
366 | uasm_i_ssnop(p); |
367 | uasm_i_ssnop(p); | |
368 | uasm_i_ssnop(p); | |
369 | uasm_i_ssnop(p); | |
1da177e4 LT |
370 | break; |
371 | ||
372 | case CPU_VR4111: | |
373 | case CPU_VR4121: | |
374 | case CPU_VR4122: | |
375 | case CPU_VR4181: | |
376 | case CPU_VR4181A: | |
e30ec452 TS |
377 | uasm_i_nop(p); |
378 | uasm_i_nop(p); | |
1da177e4 | 379 | tlbw(p); |
e30ec452 TS |
380 | uasm_i_nop(p); |
381 | uasm_i_nop(p); | |
1da177e4 LT |
382 | break; |
383 | ||
384 | case CPU_VR4131: | |
385 | case CPU_VR4133: | |
7623debf | 386 | case CPU_R5432: |
e30ec452 TS |
387 | uasm_i_nop(p); |
388 | uasm_i_nop(p); | |
1da177e4 LT |
389 | tlbw(p); |
390 | break; | |
391 | ||
392 | default: | |
393 | panic("No TLB refill handler yet (CPU type: %d)", | |
394 | current_cpu_data.cputype); | |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
fd062c84 DD |
399 | #ifdef CONFIG_HUGETLB_PAGE |
400 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, | |
401 | struct uasm_label **l, | |
402 | struct uasm_reloc **r, | |
403 | unsigned int tmp, | |
404 | enum tlb_write_entry wmode) | |
405 | { | |
406 | /* Set huge page tlb entry size */ | |
407 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
408 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
409 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
410 | ||
411 | build_tlb_write_entry(p, l, r, wmode); | |
412 | ||
413 | /* Reset default page size */ | |
414 | if (PM_DEFAULT_MASK >> 16) { | |
415 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
416 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
417 | uasm_il_b(p, r, label_leave); | |
418 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
419 | } else if (PM_DEFAULT_MASK) { | |
420 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
421 | uasm_il_b(p, r, label_leave); | |
422 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
423 | } else { | |
424 | uasm_il_b(p, r, label_leave); | |
425 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
426 | } | |
427 | } | |
428 | ||
429 | /* | |
430 | * Check if Huge PTE is present, if so then jump to LABEL. | |
431 | */ | |
432 | static void __cpuinit | |
433 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
434 | unsigned int pmd, int lid) | |
435 | { | |
436 | UASM_i_LW(p, tmp, 0, pmd); | |
437 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
438 | uasm_il_bnez(p, r, tmp, lid); | |
439 | } | |
440 | ||
441 | static __cpuinit void build_huge_update_entries(u32 **p, | |
442 | unsigned int pte, | |
443 | unsigned int tmp) | |
444 | { | |
445 | int small_sequence; | |
446 | ||
447 | /* | |
448 | * A huge PTE describes an area the size of the | |
449 | * configured huge page size. This is twice the | |
450 | * of the large TLB entry size we intend to use. | |
451 | * A TLB entry half the size of the configured | |
452 | * huge page size is configured into entrylo0 | |
453 | * and entrylo1 to cover the contiguous huge PTE | |
454 | * address space. | |
455 | */ | |
456 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
457 | ||
458 | /* We can clobber tmp. It isn't used after this.*/ | |
459 | if (!small_sequence) | |
460 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
461 | ||
462 | UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ | |
463 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */ | |
464 | /* convert to entrylo1 */ | |
465 | if (small_sequence) | |
466 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
467 | else | |
468 | UASM_i_ADDU(p, pte, pte, tmp); | |
469 | ||
470 | uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */ | |
471 | } | |
472 | ||
473 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
474 | struct uasm_reloc **r, | |
475 | struct uasm_label **l, | |
476 | unsigned int pte, | |
477 | unsigned int ptr) | |
478 | { | |
479 | #ifdef CONFIG_SMP | |
480 | UASM_i_SC(p, pte, 0, ptr); | |
481 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
482 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
483 | #else | |
484 | UASM_i_SW(p, pte, 0, ptr); | |
485 | #endif | |
486 | build_huge_update_entries(p, pte, ptr); | |
487 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); | |
488 | } | |
489 | #endif /* CONFIG_HUGETLB_PAGE */ | |
490 | ||
875d43e7 | 491 | #ifdef CONFIG_64BIT |
1da177e4 LT |
492 | /* |
493 | * TMP and PTR are scratch. | |
494 | * TMP will be clobbered, PTR will hold the pmd entry. | |
495 | */ | |
234fcd14 | 496 | static void __cpuinit |
e30ec452 | 497 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
498 | unsigned int tmp, unsigned int ptr) |
499 | { | |
500 | long pgdc = (long)pgd_current; | |
501 | ||
502 | /* | |
503 | * The vmalloc handling is not in the hotpath. | |
504 | */ | |
e30ec452 | 505 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
e30ec452 | 506 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
e30ec452 | 507 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 LT |
508 | |
509 | #ifdef CONFIG_SMP | |
41c594ab RB |
510 | # ifdef CONFIG_MIPS_MT_SMTC |
511 | /* | |
512 | * SMTC uses TCBind value as "CPU" index | |
513 | */ | |
e30ec452 TS |
514 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
515 | uasm_i_dsrl(p, ptr, ptr, 19); | |
41c594ab | 516 | # else |
1da177e4 | 517 | /* |
1b3a6e97 | 518 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
519 | * stored in CONTEXT. |
520 | */ | |
e30ec452 TS |
521 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
522 | uasm_i_dsrl(p, ptr, ptr, 23); | |
41c594ab | 523 | #endif |
e30ec452 TS |
524 | UASM_i_LA_mostly(p, tmp, pgdc); |
525 | uasm_i_daddu(p, ptr, ptr, tmp); | |
526 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
527 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 528 | #else |
e30ec452 TS |
529 | UASM_i_LA_mostly(p, ptr, pgdc); |
530 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
531 | #endif |
532 | ||
e30ec452 | 533 | uasm_l_vmalloc_done(l, *p); |
242954b5 RB |
534 | |
535 | if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ | |
e30ec452 | 536 | uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); |
242954b5 | 537 | else |
e30ec452 TS |
538 | uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); |
539 | ||
540 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
541 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
542 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
543 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
544 | uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
545 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
546 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
1da177e4 LT |
547 | } |
548 | ||
549 | /* | |
550 | * BVADDR is the faulting address, PTR is scratch. | |
551 | * PTR will hold the pgd for vmalloc. | |
552 | */ | |
234fcd14 | 553 | static void __cpuinit |
e30ec452 | 554 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
555 | unsigned int bvaddr, unsigned int ptr) |
556 | { | |
557 | long swpd = (long)swapper_pg_dir; | |
558 | ||
e30ec452 | 559 | uasm_l_vmalloc(l, *p); |
1da177e4 | 560 | |
e30ec452 TS |
561 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { |
562 | uasm_il_b(p, r, label_vmalloc_done); | |
563 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
1da177e4 | 564 | } else { |
e30ec452 TS |
565 | UASM_i_LA_mostly(p, ptr, swpd); |
566 | uasm_il_b(p, r, label_vmalloc_done); | |
567 | if (uasm_in_compat_space_p(swpd)) | |
568 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
619b6e18 | 569 | else |
e30ec452 | 570 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
1da177e4 LT |
571 | } |
572 | } | |
573 | ||
875d43e7 | 574 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
575 | |
576 | /* | |
577 | * TMP and PTR are scratch. | |
578 | * TMP will be clobbered, PTR will hold the pgd entry. | |
579 | */ | |
234fcd14 | 580 | static void __cpuinit __maybe_unused |
1da177e4 LT |
581 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
582 | { | |
583 | long pgdc = (long)pgd_current; | |
584 | ||
585 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
586 | #ifdef CONFIG_SMP | |
41c594ab RB |
587 | #ifdef CONFIG_MIPS_MT_SMTC |
588 | /* | |
589 | * SMTC uses TCBind value as "CPU" index | |
590 | */ | |
e30ec452 TS |
591 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
592 | UASM_i_LA_mostly(p, tmp, pgdc); | |
593 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
594 | #else |
595 | /* | |
596 | * smp_processor_id() << 3 is stored in CONTEXT. | |
597 | */ | |
e30ec452 TS |
598 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
599 | UASM_i_LA_mostly(p, tmp, pgdc); | |
600 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 601 | #endif |
e30ec452 | 602 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 603 | #else |
e30ec452 | 604 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 605 | #endif |
e30ec452 TS |
606 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
607 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
608 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
609 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
610 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
611 | } |
612 | ||
875d43e7 | 613 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 614 | |
234fcd14 | 615 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 616 | { |
242954b5 | 617 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
618 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
619 | ||
10cc3529 | 620 | switch (current_cpu_type()) { |
1da177e4 LT |
621 | case CPU_VR41XX: |
622 | case CPU_VR4111: | |
623 | case CPU_VR4121: | |
624 | case CPU_VR4122: | |
625 | case CPU_VR4131: | |
626 | case CPU_VR4181: | |
627 | case CPU_VR4181A: | |
628 | case CPU_VR4133: | |
629 | shift += 2; | |
630 | break; | |
631 | ||
632 | default: | |
633 | break; | |
634 | } | |
635 | ||
636 | if (shift) | |
e30ec452 TS |
637 | UASM_i_SRL(p, ctx, ctx, shift); |
638 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
639 | } |
640 | ||
234fcd14 | 641 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
642 | { |
643 | /* | |
644 | * Bug workaround for the Nevada. It seems as if under certain | |
645 | * circumstances the move from cp0_context might produce a | |
646 | * bogus result when the mfc0 instruction and its consumer are | |
647 | * in a different cacheline or a load instruction, probably any | |
648 | * memory reference, is between them. | |
649 | */ | |
10cc3529 | 650 | switch (current_cpu_type()) { |
1da177e4 | 651 | case CPU_NEVADA: |
e30ec452 | 652 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
653 | GET_CONTEXT(p, tmp); /* get context reg */ |
654 | break; | |
655 | ||
656 | default: | |
657 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 658 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
659 | break; |
660 | } | |
661 | ||
662 | build_adjust_context(p, tmp); | |
e30ec452 | 663 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
664 | } |
665 | ||
234fcd14 | 666 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
667 | unsigned int ptep) |
668 | { | |
669 | /* | |
670 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
671 | * Kernel is a special case. Only a few CPUs use it. | |
672 | */ | |
673 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
674 | if (cpu_has_64bits) { | |
e30ec452 TS |
675 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
676 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
677 | uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
678 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
679 | uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
680 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
681 | } else { |
682 | int pte_off_even = sizeof(pte_t) / 2; | |
683 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
684 | ||
685 | /* The pte entries are pre-shifted */ | |
e30ec452 TS |
686 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
687 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
688 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
689 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
690 | } |
691 | #else | |
e30ec452 TS |
692 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
693 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
694 | if (r45k_bvahwbug()) |
695 | build_tlb_probe_entry(p); | |
e30ec452 | 696 | UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ |
1da177e4 | 697 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
698 | uasm_i_mtc0(p, 0, C0_ENTRYLO0); |
699 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
700 | UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1da177e4 | 701 | if (r45k_bvahwbug()) |
e30ec452 | 702 | uasm_i_mfc0(p, tmp, C0_INDEX); |
1da177e4 | 703 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
704 | uasm_i_mtc0(p, 0, C0_ENTRYLO1); |
705 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
706 | #endif |
707 | } | |
708 | ||
e6f72d3a DD |
709 | /* |
710 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
711 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
712 | * slots before the XTLB refill exception handler which belong to the | |
713 | * unused TLB refill exception. | |
714 | */ | |
715 | #define MIPS64_REFILL_INSNS 32 | |
716 | ||
234fcd14 | 717 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
718 | { |
719 | u32 *p = tlb_handler; | |
e30ec452 TS |
720 | struct uasm_label *l = labels; |
721 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
722 | u32 *f; |
723 | unsigned int final_len; | |
724 | ||
725 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
726 | memset(labels, 0, sizeof(labels)); | |
727 | memset(relocs, 0, sizeof(relocs)); | |
728 | memset(final_handler, 0, sizeof(final_handler)); | |
729 | ||
730 | /* | |
731 | * create the plain linear handler | |
732 | */ | |
733 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
734 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
735 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
736 | uasm_i_xor(&p, K0, K0, K1); | |
737 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
738 | uasm_il_bnez(&p, &r, K0, label_leave); | |
739 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
740 | } |
741 | ||
875d43e7 | 742 | #ifdef CONFIG_64BIT |
1da177e4 LT |
743 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
744 | #else | |
745 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
746 | #endif | |
747 | ||
fd062c84 DD |
748 | #ifdef CONFIG_HUGETLB_PAGE |
749 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); | |
750 | #endif | |
751 | ||
1da177e4 LT |
752 | build_get_ptep(&p, K0, K1); |
753 | build_update_entries(&p, K0, K1); | |
754 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
755 | uasm_l_leave(&l, p); |
756 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 757 | |
fd062c84 DD |
758 | #ifdef CONFIG_HUGETLB_PAGE |
759 | uasm_l_tlb_huge_update(&l, p); | |
760 | UASM_i_LW(&p, K0, 0, K1); | |
761 | build_huge_update_entries(&p, K0, K1); | |
762 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); | |
763 | #endif | |
764 | ||
875d43e7 | 765 | #ifdef CONFIG_64BIT |
1da177e4 LT |
766 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
767 | #endif | |
768 | ||
769 | /* | |
770 | * Overflow check: For the 64bit handler, we need at least one | |
771 | * free instruction slot for the wrap-around branch. In worst | |
772 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 773 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
774 | * unused. |
775 | */ | |
2a21c730 FZ |
776 | /* Loongson2 ebase is different than r4k, we have more space */ |
777 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
778 | if ((p - tlb_handler) > 64) |
779 | panic("TLB refill handler space exceeded"); | |
780 | #else | |
e6f72d3a DD |
781 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
782 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
783 | && uasm_insn_has_bdelay(relocs, | |
784 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
785 | panic("TLB refill handler space exceeded"); |
786 | #endif | |
787 | ||
788 | /* | |
789 | * Now fold the handler in the TLB refill handler space. | |
790 | */ | |
2a21c730 | 791 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
792 | f = final_handler; |
793 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 794 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 795 | final_len = p - tlb_handler; |
875d43e7 | 796 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
797 | f = final_handler + MIPS64_REFILL_INSNS; |
798 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 799 | /* Just copy the handler. */ |
e30ec452 | 800 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
801 | final_len = p - tlb_handler; |
802 | } else { | |
fd062c84 DD |
803 | #if defined(CONFIG_HUGETLB_PAGE) |
804 | const enum label_id ls = label_tlb_huge_update; | |
805 | #elif defined(MODULE_START) | |
95affdda DD |
806 | const enum label_id ls = label_module_alloc; |
807 | #else | |
808 | const enum label_id ls = label_vmalloc; | |
809 | #endif | |
810 | u32 *split; | |
811 | int ov = 0; | |
812 | int i; | |
813 | ||
814 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
815 | ; | |
816 | BUG_ON(i == ARRAY_SIZE(labels)); | |
817 | split = labels[i].addr; | |
1da177e4 LT |
818 | |
819 | /* | |
95affdda | 820 | * See if we have overflown one way or the other. |
1da177e4 | 821 | */ |
95affdda DD |
822 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
823 | split < p - MIPS64_REFILL_INSNS) | |
824 | ov = 1; | |
825 | ||
826 | if (ov) { | |
827 | /* | |
828 | * Split two instructions before the end. One | |
829 | * for the branch and one for the instruction | |
830 | * in the delay slot. | |
831 | */ | |
832 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
833 | ||
834 | /* | |
835 | * If the branch would fall in a delay slot, | |
836 | * we must back up an additional instruction | |
837 | * so that it is no longer in a delay slot. | |
838 | */ | |
839 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
840 | split--; | |
841 | } | |
1da177e4 | 842 | /* Copy first part of the handler. */ |
e30ec452 | 843 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
844 | f += split - tlb_handler; |
845 | ||
95affdda DD |
846 | if (ov) { |
847 | /* Insert branch. */ | |
848 | uasm_l_split(&l, final_handler); | |
849 | uasm_il_b(&f, &r, label_split); | |
850 | if (uasm_insn_has_bdelay(relocs, split)) | |
851 | uasm_i_nop(&f); | |
852 | else { | |
853 | uasm_copy_handler(relocs, labels, | |
854 | split, split + 1, f); | |
855 | uasm_move_labels(labels, f, f + 1, -1); | |
856 | f++; | |
857 | split++; | |
858 | } | |
1da177e4 LT |
859 | } |
860 | ||
861 | /* Copy the rest of the handler. */ | |
e30ec452 | 862 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
863 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
864 | (p - split); | |
1da177e4 | 865 | } |
875d43e7 | 866 | #endif /* CONFIG_64BIT */ |
1da177e4 | 867 | |
e30ec452 TS |
868 | uasm_resolve_relocs(relocs, labels); |
869 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
870 | final_len); | |
1da177e4 | 871 | |
91b05e67 | 872 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
873 | |
874 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
875 | } |
876 | ||
877 | /* | |
878 | * TLB load/store/modify handlers. | |
879 | * | |
880 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
881 | * do_page_fault remains normal asm. | |
882 | */ | |
883 | extern void tlb_do_page_fault_0(void); | |
884 | extern void tlb_do_page_fault_1(void); | |
885 | ||
1da177e4 LT |
886 | /* |
887 | * 128 instructions for the fastpath handler is generous and should | |
888 | * never be exceeded. | |
889 | */ | |
890 | #define FASTPATH_SIZE 128 | |
891 | ||
cbdbe07f FBH |
892 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
893 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
894 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
1da177e4 | 895 | |
234fcd14 | 896 | static void __cpuinit |
bd1437e4 | 897 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
898 | { |
899 | #ifdef CONFIG_SMP | |
900 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
901 | if (cpu_has_64bits) | |
e30ec452 | 902 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
903 | else |
904 | # endif | |
e30ec452 | 905 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
906 | #else |
907 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
908 | if (cpu_has_64bits) | |
e30ec452 | 909 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
910 | else |
911 | # endif | |
e30ec452 | 912 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
913 | #endif |
914 | } | |
915 | ||
234fcd14 | 916 | static void __cpuinit |
e30ec452 | 917 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 918 | unsigned int mode) |
1da177e4 | 919 | { |
63b2d2f4 TS |
920 | #ifdef CONFIG_64BIT_PHYS_ADDR |
921 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
922 | #endif | |
923 | ||
e30ec452 | 924 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
925 | #ifdef CONFIG_SMP |
926 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
927 | if (cpu_has_64bits) | |
e30ec452 | 928 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
929 | else |
930 | # endif | |
e30ec452 | 931 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
932 | |
933 | if (r10000_llsc_war()) | |
e30ec452 | 934 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 935 | else |
e30ec452 | 936 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
937 | |
938 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
939 | if (!cpu_has_64bits) { | |
e30ec452 TS |
940 | /* no uasm_i_nop needed */ |
941 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
942 | uasm_i_ori(p, pte, pte, hwmode); | |
943 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
944 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
945 | /* no uasm_i_nop needed */ | |
946 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 947 | } else |
e30ec452 | 948 | uasm_i_nop(p); |
1da177e4 | 949 | # else |
e30ec452 | 950 | uasm_i_nop(p); |
1da177e4 LT |
951 | # endif |
952 | #else | |
953 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
954 | if (cpu_has_64bits) | |
e30ec452 | 955 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
956 | else |
957 | # endif | |
e30ec452 | 958 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
959 | |
960 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
961 | if (!cpu_has_64bits) { | |
e30ec452 TS |
962 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
963 | uasm_i_ori(p, pte, pte, hwmode); | |
964 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
965 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
966 | } |
967 | # endif | |
968 | #endif | |
969 | } | |
970 | ||
971 | /* | |
972 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
973 | * the page table where this PTE is located, PTE will be re-loaded | |
974 | * with it's original value. | |
975 | */ | |
234fcd14 | 976 | static void __cpuinit |
bd1437e4 | 977 | build_pte_present(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
978 | unsigned int pte, unsigned int ptr, enum label_id lid) |
979 | { | |
e30ec452 TS |
980 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); |
981 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
982 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 983 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
984 | } |
985 | ||
986 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 987 | static void __cpuinit |
e30ec452 | 988 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
989 | unsigned int ptr) |
990 | { | |
63b2d2f4 TS |
991 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
992 | ||
993 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
994 | } |
995 | ||
996 | /* | |
997 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
998 | * restore PTE with value from PTR when done. | |
999 | */ | |
234fcd14 | 1000 | static void __cpuinit |
bd1437e4 | 1001 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1002 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1003 | { | |
e30ec452 TS |
1004 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); |
1005 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1006 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 1007 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1008 | } |
1009 | ||
1010 | /* Make PTE writable, update software status bits as well, then store | |
1011 | * at PTR. | |
1012 | */ | |
234fcd14 | 1013 | static void __cpuinit |
e30ec452 | 1014 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1015 | unsigned int ptr) |
1016 | { | |
63b2d2f4 TS |
1017 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1018 | | _PAGE_DIRTY); | |
1019 | ||
1020 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1021 | } |
1022 | ||
1023 | /* | |
1024 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1025 | * restore PTE with value from PTR when done. | |
1026 | */ | |
234fcd14 | 1027 | static void __cpuinit |
bd1437e4 | 1028 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1029 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1030 | { | |
e30ec452 TS |
1031 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); |
1032 | uasm_il_beqz(p, r, pte, lid); | |
bd1437e4 | 1033 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1034 | } |
1035 | ||
1036 | /* | |
1037 | * R3000 style TLB load/store/modify handlers. | |
1038 | */ | |
1039 | ||
fded2e50 MR |
1040 | /* |
1041 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1042 | * Then it returns. | |
1043 | */ | |
234fcd14 | 1044 | static void __cpuinit |
fded2e50 | 1045 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1046 | { |
e30ec452 TS |
1047 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1048 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1049 | uasm_i_tlbwi(p); | |
1050 | uasm_i_jr(p, tmp); | |
1051 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1052 | } |
1053 | ||
1054 | /* | |
fded2e50 MR |
1055 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1056 | * or tlbwr as appropriate. This is because the index register | |
1057 | * may have the probe fail bit set as a result of a trap on a | |
1058 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1059 | */ |
234fcd14 | 1060 | static void __cpuinit |
e30ec452 TS |
1061 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1062 | struct uasm_reloc **r, unsigned int pte, | |
1063 | unsigned int tmp) | |
1064 | { | |
1065 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1066 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1067 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1068 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1069 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1070 | uasm_i_jr(p, tmp); | |
1071 | uasm_i_rfe(p); /* branch delay */ | |
1072 | uasm_l_r3000_write_probe_fail(l, *p); | |
1073 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1074 | uasm_i_jr(p, tmp); | |
1075 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1076 | } |
1077 | ||
234fcd14 | 1078 | static void __cpuinit |
1da177e4 LT |
1079 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1080 | unsigned int ptr) | |
1081 | { | |
1082 | long pgdc = (long)pgd_current; | |
1083 | ||
e30ec452 TS |
1084 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1085 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1086 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1087 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1088 | uasm_i_sll(p, pte, pte, 2); | |
1089 | uasm_i_addu(p, ptr, ptr, pte); | |
1090 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1091 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1092 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1093 | uasm_i_addu(p, ptr, ptr, pte); | |
1094 | uasm_i_lw(p, pte, 0, ptr); | |
1095 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1096 | } |
1097 | ||
234fcd14 | 1098 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1099 | { |
1100 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1101 | struct uasm_label *l = labels; |
1102 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1103 | |
1104 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1105 | memset(labels, 0, sizeof(labels)); | |
1106 | memset(relocs, 0, sizeof(relocs)); | |
1107 | ||
1108 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1109 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
e30ec452 | 1110 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1111 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1112 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1113 | |
e30ec452 TS |
1114 | uasm_l_nopage_tlbl(&l, p); |
1115 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1116 | uasm_i_nop(&p); | |
1da177e4 LT |
1117 | |
1118 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1119 | panic("TLB load handler fastpath space exceeded"); | |
1120 | ||
e30ec452 TS |
1121 | uasm_resolve_relocs(relocs, labels); |
1122 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1123 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1124 | |
92b1e6a6 | 1125 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1126 | } |
1127 | ||
234fcd14 | 1128 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1129 | { |
1130 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1131 | struct uasm_label *l = labels; |
1132 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1133 | |
1134 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1135 | memset(labels, 0, sizeof(labels)); | |
1136 | memset(relocs, 0, sizeof(relocs)); | |
1137 | ||
1138 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1139 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
e30ec452 | 1140 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1141 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1142 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1143 | |
e30ec452 TS |
1144 | uasm_l_nopage_tlbs(&l, p); |
1145 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1146 | uasm_i_nop(&p); | |
1da177e4 LT |
1147 | |
1148 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1149 | panic("TLB store handler fastpath space exceeded"); | |
1150 | ||
e30ec452 TS |
1151 | uasm_resolve_relocs(relocs, labels); |
1152 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1153 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1154 | |
92b1e6a6 | 1155 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1156 | } |
1157 | ||
234fcd14 | 1158 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1159 | { |
1160 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1161 | struct uasm_label *l = labels; |
1162 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1163 | |
1164 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1165 | memset(labels, 0, sizeof(labels)); | |
1166 | memset(relocs, 0, sizeof(relocs)); | |
1167 | ||
1168 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1169 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
e30ec452 | 1170 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1171 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1172 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1173 | |
e30ec452 TS |
1174 | uasm_l_nopage_tlbm(&l, p); |
1175 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1176 | uasm_i_nop(&p); | |
1da177e4 LT |
1177 | |
1178 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1179 | panic("TLB modify handler fastpath space exceeded"); | |
1180 | ||
e30ec452 TS |
1181 | uasm_resolve_relocs(relocs, labels); |
1182 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1183 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1184 | |
92b1e6a6 | 1185 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1186 | } |
1187 | ||
1188 | /* | |
1189 | * R4000 style TLB load/store/modify handlers. | |
1190 | */ | |
234fcd14 | 1191 | static void __cpuinit |
e30ec452 TS |
1192 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1193 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1194 | unsigned int ptr) |
1195 | { | |
875d43e7 | 1196 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1197 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1198 | #else | |
1199 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1200 | #endif | |
1201 | ||
fd062c84 DD |
1202 | #ifdef CONFIG_HUGETLB_PAGE |
1203 | /* | |
1204 | * For huge tlb entries, pmd doesn't contain an address but | |
1205 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1206 | * see if we need to jump to huge tlb processing. | |
1207 | */ | |
1208 | build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update); | |
1209 | #endif | |
1210 | ||
e30ec452 TS |
1211 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1212 | UASM_i_LW(p, ptr, 0, ptr); | |
1213 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1214 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1215 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1216 | |
1217 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1218 | uasm_l_smp_pgtable_change(l, *p); |
1219 | #endif | |
bd1437e4 | 1220 | iPTE_LW(p, pte, ptr); /* get even pte */ |
8df5beac MR |
1221 | if (!m4kc_tlbp_war()) |
1222 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1223 | } |
1224 | ||
234fcd14 | 1225 | static void __cpuinit |
e30ec452 TS |
1226 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1227 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1228 | unsigned int ptr) |
1229 | { | |
e30ec452 TS |
1230 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1231 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1232 | build_update_entries(p, tmp, ptr); |
1233 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1234 | uasm_l_leave(l, *p); |
1235 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1236 | |
875d43e7 | 1237 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1238 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1239 | #endif | |
1240 | } | |
1241 | ||
234fcd14 | 1242 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1243 | { |
1244 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1245 | struct uasm_label *l = labels; |
1246 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1247 | |
1248 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1249 | memset(labels, 0, sizeof(labels)); | |
1250 | memset(relocs, 0, sizeof(relocs)); | |
1251 | ||
1252 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
1253 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
1254 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
1255 | uasm_i_xor(&p, K0, K0, K1); | |
1256 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1257 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1258 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1262 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
8df5beac MR |
1263 | if (m4kc_tlbp_war()) |
1264 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1265 | build_make_valid(&p, &r, K0, K1); |
1266 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1267 | ||
fd062c84 DD |
1268 | #ifdef CONFIG_HUGETLB_PAGE |
1269 | /* | |
1270 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1271 | * spots a huge page. | |
1272 | */ | |
1273 | uasm_l_tlb_huge_update(&l, p); | |
1274 | iPTE_LW(&p, K0, K1); | |
1275 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); | |
1276 | build_tlb_probe_entry(&p); | |
1277 | uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); | |
1278 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1279 | #endif | |
1280 | ||
e30ec452 TS |
1281 | uasm_l_nopage_tlbl(&l, p); |
1282 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1283 | uasm_i_nop(&p); | |
1da177e4 LT |
1284 | |
1285 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1286 | panic("TLB load handler fastpath space exceeded"); | |
1287 | ||
e30ec452 TS |
1288 | uasm_resolve_relocs(relocs, labels); |
1289 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1290 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1291 | |
92b1e6a6 | 1292 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1293 | } |
1294 | ||
234fcd14 | 1295 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1296 | { |
1297 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1298 | struct uasm_label *l = labels; |
1299 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1300 | |
1301 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1302 | memset(labels, 0, sizeof(labels)); | |
1303 | memset(relocs, 0, sizeof(relocs)); | |
1304 | ||
1305 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1306 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
8df5beac MR |
1307 | if (m4kc_tlbp_war()) |
1308 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1309 | build_make_write(&p, &r, K0, K1); |
1310 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1311 | ||
fd062c84 DD |
1312 | #ifdef CONFIG_HUGETLB_PAGE |
1313 | /* | |
1314 | * This is the entry point when | |
1315 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1316 | */ | |
1317 | uasm_l_tlb_huge_update(&l, p); | |
1318 | iPTE_LW(&p, K0, K1); | |
1319 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); | |
1320 | build_tlb_probe_entry(&p); | |
1321 | uasm_i_ori(&p, K0, K0, | |
1322 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1323 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1324 | #endif | |
1325 | ||
e30ec452 TS |
1326 | uasm_l_nopage_tlbs(&l, p); |
1327 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1328 | uasm_i_nop(&p); | |
1da177e4 LT |
1329 | |
1330 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1331 | panic("TLB store handler fastpath space exceeded"); | |
1332 | ||
e30ec452 TS |
1333 | uasm_resolve_relocs(relocs, labels); |
1334 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1335 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1336 | |
92b1e6a6 | 1337 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1338 | } |
1339 | ||
234fcd14 | 1340 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1341 | { |
1342 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1343 | struct uasm_label *l = labels; |
1344 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1345 | |
1346 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1347 | memset(labels, 0, sizeof(labels)); | |
1348 | memset(relocs, 0, sizeof(relocs)); | |
1349 | ||
1350 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1351 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
8df5beac MR |
1352 | if (m4kc_tlbp_war()) |
1353 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1354 | /* Present and writable bits set, set accessed and dirty bits. */ |
1355 | build_make_write(&p, &r, K0, K1); | |
1356 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1357 | ||
fd062c84 DD |
1358 | #ifdef CONFIG_HUGETLB_PAGE |
1359 | /* | |
1360 | * This is the entry point when | |
1361 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1362 | */ | |
1363 | uasm_l_tlb_huge_update(&l, p); | |
1364 | iPTE_LW(&p, K0, K1); | |
1365 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); | |
1366 | build_tlb_probe_entry(&p); | |
1367 | uasm_i_ori(&p, K0, K0, | |
1368 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1369 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1370 | #endif | |
1371 | ||
e30ec452 TS |
1372 | uasm_l_nopage_tlbm(&l, p); |
1373 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1374 | uasm_i_nop(&p); | |
1da177e4 LT |
1375 | |
1376 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1377 | panic("TLB modify handler fastpath space exceeded"); | |
1378 | ||
e30ec452 TS |
1379 | uasm_resolve_relocs(relocs, labels); |
1380 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1381 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1382 | |
92b1e6a6 | 1383 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1384 | } |
1385 | ||
234fcd14 | 1386 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1387 | { |
1388 | /* | |
1389 | * The refill handler is generated per-CPU, multi-node systems | |
1390 | * may have local storage for it. The other handlers are only | |
1391 | * needed once. | |
1392 | */ | |
1393 | static int run_once = 0; | |
1394 | ||
10cc3529 | 1395 | switch (current_cpu_type()) { |
1da177e4 LT |
1396 | case CPU_R2000: |
1397 | case CPU_R3000: | |
1398 | case CPU_R3000A: | |
1399 | case CPU_R3081E: | |
1400 | case CPU_TX3912: | |
1401 | case CPU_TX3922: | |
1402 | case CPU_TX3927: | |
1403 | build_r3000_tlb_refill_handler(); | |
1404 | if (!run_once) { | |
1405 | build_r3000_tlb_load_handler(); | |
1406 | build_r3000_tlb_store_handler(); | |
1407 | build_r3000_tlb_modify_handler(); | |
1408 | run_once++; | |
1409 | } | |
1410 | break; | |
1411 | ||
1412 | case CPU_R6000: | |
1413 | case CPU_R6000A: | |
1414 | panic("No R6000 TLB refill handler yet"); | |
1415 | break; | |
1416 | ||
1417 | case CPU_R8000: | |
1418 | panic("No R8000 TLB refill handler yet"); | |
1419 | break; | |
1420 | ||
1421 | default: | |
1422 | build_r4000_tlb_refill_handler(); | |
1423 | if (!run_once) { | |
1424 | build_r4000_tlb_load_handler(); | |
1425 | build_r4000_tlb_store_handler(); | |
1426 | build_r4000_tlb_modify_handler(); | |
1427 | run_once++; | |
1428 | } | |
1429 | } | |
1430 | } | |
1d40cfcd | 1431 | |
234fcd14 | 1432 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1433 | { |
e0cee3ee | 1434 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1435 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1436 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1437 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1438 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd RB |
1439 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
1440 | } |