[deliverable/linux.git] / arch / parisc / mm / fault.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 *
 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright 1999 Hewlett Packard Co.
 *
 */

#include <linux/mm.h>
#include <linux/ptrace.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/uaccess.h>

#include <asm/traps.h>

/* Various important other fields */
#define bit22set(x)		(x & 0x00000200)
#define bits23_25set(x)		(x & 0x000001c0)
#define isGraphicsFlushRead(x)	((x & 0xfc003fdf) == 0x04001a80)
				/* extended opcode is 0x6a */

#define BITSSET		0x1c0	/* for identifying LDCW */


DEFINE_PER_CPU(struct exception_data, exception_data);

int show_unhandled_signals = 1;

/*
 * parisc_acctyp(unsigned int inst) --
 *    Given a PA-RISC memory access instruction, determine if the
 *    the instruction would perform a memory read or memory write
 *    operation.
 *
 *    This function assumes that the given instruction is a memory access
 *    instruction (i.e. you should really only call it if you know that
 *    the instruction has generated some sort of a memory access fault).
 *
 * Returns:
 *   VM_READ  if read operation
 *   VM_WRITE if write operation
 *   VM_EXEC  if execute operation
 */
static unsigned long
parisc_acctyp(unsigned long code, unsigned int inst)
{
	if (code == 6 || code == 16)
	    return VM_EXEC;

	switch (inst & 0xf0000000) {
	case 0x40000000: /* load */
	case 0x50000000: /* new load */
		return VM_READ;

	case 0x60000000: /* store */
	case 0x70000000: /* new store */
		return VM_WRITE;

	case 0x20000000: /* coproc */
	case 0x30000000: /* coproc2 */
		if (bit22set(inst))
			return VM_WRITE;

	case 0x0: /* indexed/memory management */
		if (bit22set(inst)) {
			/*
			 * Check for the 'Graphics Flush Read' instruction.
			 * It resembles an FDC instruction, except for bits
			 * 20 and 21. Any combination other than zero will
			 * utilize the block mover functionality on some
			 * older PA-RISC platforms.  The case where a block
			 * move is performed from VM to graphics IO space
			 * should be treated as a READ.
			 *
			 * The significance of bits 20,21 in the FDC
			 * instruction is:
			 *
			 *   00  Flush data cache (normal instruction behavior)
			 *   01  Graphics flush write  (IO space -> VM)
			 *   10  Graphics flush read   (VM -> IO space)
			 *   11  Graphics flush read/write (VM <-> IO space)
			 */
			if (isGraphicsFlushRead(inst))
				return VM_READ;
			return VM_WRITE;
		} else {
			/*
			 * Check for LDCWX and LDCWS (semaphore instructions).
			 * If bits 23 through 25 are all 1's it is one of
			 * the above two instructions and is a write.
			 *
			 * Note: With the limited bits we are looking at,
			 * this will also catch PROBEW and PROBEWI. However,
			 * these should never get in here because they don't
			 * generate exceptions of the type:
			 *   Data TLB miss fault/data page fault
			 *   Data memory protection trap
			 */
			if (bits23_25set(inst) == BITSSET)
				return VM_WRITE;
		}
		return VM_READ; /* Default */
	}
	return VM_READ; /* Default */
}

#undef bit22set
#undef bits23_25set
#undef isGraphicsFlushRead
#undef BITSSET


#if 0
/* This is the treewalk to find a vma which is the highest that has
 * a start < addr.  We're using find_vma_prev instead right now, but
 * we might want to use this at some point in the future.  Probably
 * not, but I want it committed to CVS so I don't lose it :-)
 */
			while (tree != vm_avl_empty) {
				if (tree->vm_start > addr) {
					tree = tree->vm_avl_left;
				} else {
					prev = tree;
					if (prev->vm_next == NULL)
						break;
					if (prev->vm_next->vm_start > addr)
						break;
					tree = tree->vm_avl_right;
				}
			}
#endif

int fixup_exception(struct pt_regs *regs)
{
	const struct exception_table_entry *fix;

	fix = search_exception_tables(regs->iaoq[0]);
	if (fix) {
		struct exception_data *d;
		d = this_cpu_ptr(&exception_data);
		d->fault_ip = regs->iaoq[0];
		d->fault_gp = regs->gr[27];
		d->fault_space = regs->isr;
		d->fault_addr = regs->ior;

		regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
		regs->iaoq[0] &= ~3;
		/*
		 * NOTE: In some cases the faulting instruction
		 * may be in the delay slot of a branch. We
		 * don't want to take the branch, so we don't
		 * increment iaoq[1], instead we set it to be
		 * iaoq[0]+4, and clear the B bit in the PSW
		 */
		regs->iaoq[1] = regs->iaoq[0] + 4;
		regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */

		return 1;
	}

	return 0;
}

/*
 * Print out info about fatal segfaults, if the show_unhandled_signals
 * sysctl is set:
 */
static inline void
show_signal_msg(struct pt_regs *regs, unsigned long code,
		unsigned long address, struct task_struct *tsk,
		struct vm_area_struct *vma)
{
	if (!unhandled_signal(tsk, SIGSEGV))
		return;

	if (!printk_ratelimit())
		return;

	pr_warn("\n");
	pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
	    tsk->comm, code, address);
	print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
	if (vma)
		pr_warn(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
				vma->vm_start, vma->vm_end);

	show_regs(regs);
}

void do_page_fault(struct pt_regs *regs, unsigned long code,
			      unsigned long address)
{
	struct vm_area_struct *vma, *prev_vma;
	struct task_struct *tsk;
	struct mm_struct *mm;
	unsigned long acc_type;
	int fault;
	unsigned int flags;

	if (faulthandler_disabled())
		goto no_context;

	tsk = current;
	mm = tsk->mm;
	if (!mm)
		goto no_context;

	flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
	if (user_mode(regs))
		flags |= FAULT_FLAG_USER;

	acc_type = parisc_acctyp(code, regs->iir);
	if (acc_type & VM_WRITE)
		flags |= FAULT_FLAG_WRITE;
retry:
	down_read(&mm->mmap_sem);
	vma = find_vma_prev(mm, address, &prev_vma);
	if (!vma || address < vma->vm_start)
		goto check_expansion;
/*
 * Ok, we have a good vm_area for this memory access. We still need to
 * check the access permissions.
 */

good_area:

	if ((vma->vm_flags & acc_type) != acc_type)
		goto bad_area;

	/*
	 * If for any reason at all we couldn't handle the fault, make
	 * sure we exit gracefully rather than endlessly redo the
	 * fault.
	 */

	fault = handle_mm_fault(mm, vma, address, flags);

	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
		return;

	if (unlikely(fault & VM_FAULT_ERROR)) {
		/*
		 * We hit a shared mapping outside of the file, or some
		 * other thing happened to us that made us unable to
		 * handle the page fault gracefully.
		 */
		if (fault & VM_FAULT_OOM)
			goto out_of_memory;
		else if (fault & VM_FAULT_SIGSEGV)
			goto bad_area;
		else if (fault & VM_FAULT_SIGBUS)
			goto bad_area;
		BUG();
	}
	if (flags & FAULT_FLAG_ALLOW_RETRY) {
		if (fault & VM_FAULT_MAJOR)
			current->maj_flt++;
		else
			current->min_flt++;
		if (fault & VM_FAULT_RETRY) {
			flags &= ~FAULT_FLAG_ALLOW_RETRY;

			/*
			 * No need to up_read(&mm->mmap_sem) as we would
			 * have already released it in __lock_page_or_retry
			 * in mm/filemap.c.
			 */

			goto retry;
		}
	}
	up_read(&mm->mmap_sem);
	return;

check_expansion:
	vma = prev_vma;
	if (vma && (expand_stack(vma, address) == 0))
		goto good_area;

/*
 * Something tried to access memory that isn't in our memory map..
 */
bad_area:
	up_read(&mm->mmap_sem);

	if (user_mode(regs)) {
		struct siginfo si;

		show_signal_msg(regs, code, address, tsk, vma);

		switch (code) {
		case 15:	/* Data TLB miss fault/Data page fault */
			/* send SIGSEGV when outside of vma */
			if (!vma ||
			    address < vma->vm_start || address > vma->vm_end) {
				si.si_signo = SIGSEGV;
				si.si_code = SEGV_MAPERR;
				break;
			}

			/* send SIGSEGV for wrong permissions */
			if ((vma->vm_flags & acc_type) != acc_type) {
				si.si_signo = SIGSEGV;
				si.si_code = SEGV_ACCERR;
				break;
			}

			/* probably address is outside of mapped file */
			/* fall through */
		case 17:	/* NA data TLB miss / page fault */
		case 18:	/* Unaligned access - PCXS only */
			si.si_signo = SIGBUS;
			si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
			break;
		case 16:	/* Non-access instruction TLB miss fault */
		case 26:	/* PCXL: Data memory access rights trap */
		default:
			si.si_signo = SIGSEGV;
			si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
			break;
		}
		si.si_errno = 0;
		si.si_addr = (void __user *) address;
		force_sig_info(si.si_signo, &si, current);
		return;
	}

no_context:

	if (!user_mode(regs) && fixup_exception(regs)) {
		return;
	}

	parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);

  out_of_memory:
	up_read(&mm->mmap_sem);
	if (!user_mode(regs))
		goto no_context;
	pagefault_out_of_memory();
}
Commit	Line	Data
071327ec	1	/*
1da177e4 LT	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	*
	7	* Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
	8	* Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	9	* Copyright 1999 Hewlett Packard Co.
	10	*
	11	*/
	12
	13	#include <linux/mm.h>
	14	#include <linux/ptrace.h>
	15	#include <linux/sched.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/module.h>
70ffdb93	18	#include <linux/uaccess.h>
1da177e4	19
1da177e4 LT	20	#include <asm/traps.h>
1da177e4 LT	21
1da177e4 LT	22	/* Various important other fields */
	23	#define bit22set(x) (x & 0x00000200)
	24	#define bits23_25set(x) (x & 0x000001c0)
	25	#define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
	26	/* extended opcode is 0x6a */
	27
	28	#define BITSSET 0x1c0 /* for identifying LDCW */
	29
	30
	31	DEFINE_PER_CPU(struct exception_data, exception_data);
	32
fef47e2a HD	33	int show_unhandled_signals = 1;
fef47e2a HD	34
1da177e4 LT	35	/*
	36	* parisc_acctyp(unsigned int inst) --
	37	* Given a PA-RISC memory access instruction, determine if the
	38	* the instruction would perform a memory read or memory write
	39	* operation.
	40	*
	41	* This function assumes that the given instruction is a memory access
	42	* instruction (i.e. you should really only call it if you know that
	43	* the instruction has generated some sort of a memory access fault).
	44	*
	45	* Returns:
	46	* VM_READ if read operation
	47	* VM_WRITE if write operation
	48	* VM_EXEC if execute operation
	49	*/
	50	static unsigned long
	51	parisc_acctyp(unsigned long code, unsigned int inst)
	52	{
	53	if (code == 6 \|\| code == 16)
	54	return VM_EXEC;
	55
	56	switch (inst & 0xf0000000) {
	57	case 0x40000000: /* load */
	58	case 0x50000000: /* new load */
	59	return VM_READ;
	60
	61	case 0x60000000: /* store */
	62	case 0x70000000: /* new store */
	63	return VM_WRITE;
	64
	65	case 0x20000000: /* coproc */
	66	case 0x30000000: /* coproc2 */
	67	if (bit22set(inst))
	68	return VM_WRITE;
	69
	70	case 0x0: /* indexed/memory management */
	71	if (bit22set(inst)) {
	72	/*
	73	* Check for the 'Graphics Flush Read' instruction.
	74	* It resembles an FDC instruction, except for bits
	75	* 20 and 21. Any combination other than zero will
	76	* utilize the block mover functionality on some
	77	* older PA-RISC platforms. The case where a block
	78	* move is performed from VM to graphics IO space
	79	* should be treated as a READ.
	80	*
	81	* The significance of bits 20,21 in the FDC
	82	* instruction is:
	83	*
	84	* 00 Flush data cache (normal instruction behavior)
	85	* 01 Graphics flush write (IO space -> VM)
	86	* 10 Graphics flush read (VM -> IO space)
	87	* 11 Graphics flush read/write (VM <-> IO space)
	88	*/
	89	if (isGraphicsFlushRead(inst))
	90	return VM_READ;
	91	return VM_WRITE;
	92	} else {
	93	/*
	94	* Check for LDCWX and LDCWS (semaphore instructions).
	95	* If bits 23 through 25 are all 1's it is one of
	96	* the above two instructions and is a write.
	97	*
	98	* Note: With the limited bits we are looking at,
99	* this will also catch PROBEW and PROBEWI. However,
100	* these should never get in here because they don't
101	* generate exceptions of the type:
102	* Data TLB miss fault/data page fault
103	* Data memory protection trap
104	*/
105	if (bits23_25set(inst) == BITSSET)
106	return VM_WRITE;
107	}
108	return VM_READ; /* Default */
109	}
110	return VM_READ; /* Default */
111	}
112
113	#undef bit22set
114	#undef bits23_25set
115	#undef isGraphicsFlushRead
116	#undef BITSSET
117
118
119	#if 0
120	/* This is the treewalk to find a vma which is the highest that has
121	* a start < addr. We're using find_vma_prev instead right now, but
122	* we might want to use this at some point in the future. Probably
123	* not, but I want it committed to CVS so I don't lose it :-)
124	*/
125	while (tree != vm_avl_empty) {
126	if (tree->vm_start > addr) {
127	tree = tree->vm_avl_left;
128	} else {
129	prev = tree;
130	if (prev->vm_next == NULL)
131	break;
132	if (prev->vm_next->vm_start > addr)
133	break;
134	tree = tree->vm_avl_right;
135	}
136	}
137	#endif
138
c61c25eb KM	139	int fixup_exception(struct pt_regs *regs)
	140	{
	141	const struct exception_table_entry *fix;
	142
	143	fix = search_exception_tables(regs->iaoq[0]);
	144	if (fix) {
	145	struct exception_data *d;
496252f7	146	d = this_cpu_ptr(&exception_data);
c61c25eb	147	d->fault_ip = regs->iaoq[0];
2ef4dfd9	148	d->fault_gp = regs->gr[27];
c61c25eb KM	149	d->fault_space = regs->isr;
	150	d->fault_addr = regs->ior;
	151
0de79858 HD	152	regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
0de79858 HD	153	regs->iaoq[0] &= ~3;
c61c25eb KM	154	/*
	155	* NOTE: In some cases the faulting instruction
	156	* may be in the delay slot of a branch. We
	157	* don't want to take the branch, so we don't
	158	* increment iaoq[1], instead we set it to be
	159	* iaoq[0]+4, and clear the B bit in the PSW
	160	*/
	161	regs->iaoq[1] = regs->iaoq[0] + 4;
	162	regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
	163
	164	return 1;
	165	}
	166
	167	return 0;
	168	}
	169
fef47e2a HD	170	/*
	171	* Print out info about fatal segfaults, if the show_unhandled_signals
	172	* sysctl is set:
	173	*/
	174	static inline void
	175	show_signal_msg(struct pt_regs *regs, unsigned long code,
	176	unsigned long address, struct task_struct *tsk,
	177	struct vm_area_struct *vma)
	178	{
	179	if (!unhandled_signal(tsk, SIGSEGV))
	180	return;
	181
	182	if (!printk_ratelimit())
	183	return;
	184
	185	pr_warn("\n");
	186	pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
	187	tsk->comm, code, address);
	188	print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
	189	if (vma)
	190	pr_warn(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
	191	vma->vm_start, vma->vm_end);
	192
	193	show_regs(regs);
	194	}
	195
1da177e4 LT	196	void do_page_fault(struct pt_regs *regs, unsigned long code,
	197	unsigned long address)
	198	{
	199	struct vm_area_struct vma, prev_vma;
2d8b22de JDA	200	struct task_struct *tsk;
2d8b22de JDA	201	struct mm_struct *mm;
1da177e4	202	unsigned long acc_type;
83c54070	203	int fault;
2d8b22de	204	unsigned int flags;
1da177e4	205
699817c3	206	if (faulthandler_disabled())
1da177e4 LT	207	goto no_context;
1da177e4 LT	208
2d8b22de JDA	209	tsk = current;
	210	mm = tsk->mm;
	211	if (!mm)
	212	goto no_context;
	213
	214	flags = FAULT_FLAG_ALLOW_RETRY \| FAULT_FLAG_KILLABLE;
759496ba JW	215	if (user_mode(regs))
759496ba JW	216	flags \|= FAULT_FLAG_USER;
0772dac1 FP	217
0772dac1 FP	218	acc_type = parisc_acctyp(code, regs->iir);
759496ba JW	219	if (acc_type & VM_WRITE)
759496ba JW	220	flags \|= FAULT_FLAG_WRITE;
38057477	221	retry:
1da177e4 LT	222	down_read(&mm->mmap_sem);
	223	vma = find_vma_prev(mm, address, &prev_vma);
	224	if (!vma \|\| address < vma->vm_start)
	225	goto check_expansion;
	226	/*
	227	* Ok, we have a good vm_area for this memory access. We still need to
	228	* check the access permissions.
	229	*/
	230
	231	good_area:
	232
1da177e4 LT	233	if ((vma->vm_flags & acc_type) != acc_type)
	234	goto bad_area;
	235
	236	/*
	237	* If for any reason at all we couldn't handle the fault, make
	238	* sure we exit gracefully rather than endlessly redo the
	239	* fault.
	240	*/
	241
759496ba	242	fault = handle_mm_fault(mm, vma, address, flags);
38057477 KC	243
	244	if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
	245	return;
	246
83c54070	247	if (unlikely(fault & VM_FAULT_ERROR)) {
1da177e4	248	/*
67a5a59d	249	* We hit a shared mapping outside of the file, or some
6e346228 LT	250	* other thing happened to us that made us unable to
6e346228 LT	251	* handle the page fault gracefully.
1da177e4	252	*/
83c54070 NP	253	if (fault & VM_FAULT_OOM)
83c54070 NP	254	goto out_of_memory;
33692f27 LT	255	else if (fault & VM_FAULT_SIGSEGV)
33692f27 LT	256	goto bad_area;
83c54070 NP	257	else if (fault & VM_FAULT_SIGBUS)
	258	goto bad_area;
	259	BUG();
1da177e4	260	}
38057477 KC	261	if (flags & FAULT_FLAG_ALLOW_RETRY) {
	262	if (fault & VM_FAULT_MAJOR)
	263	current->maj_flt++;
	264	else
	265	current->min_flt++;
	266	if (fault & VM_FAULT_RETRY) {
	267	flags &= ~FAULT_FLAG_ALLOW_RETRY;
	268
	269	/*
	270	* No need to up_read(&mm->mmap_sem) as we would
	271	* have already released it in __lock_page_or_retry
	272	* in mm/filemap.c.
	273	*/
	274
	275	goto retry;
	276	}
	277	}
1da177e4 LT	278	up_read(&mm->mmap_sem);
	279	return;
	280
	281	check_expansion:
	282	vma = prev_vma;
	283	if (vma && (expand_stack(vma, address) == 0))
	284	goto good_area;
	285
	286	/*
	287	* Something tried to access memory that isn't in our memory map..
	288	*/
	289	bad_area:
	290	up_read(&mm->mmap_sem);
	291
	292	if (user_mode(regs)) {
	293	struct siginfo si;
	294
fef47e2a HD	295	show_signal_msg(regs, code, address, tsk, vma);
fef47e2a HD	296
1f2048fd HD	297	switch (code) {
1f2048fd HD	298	case 15: /* Data TLB miss fault/Data page fault */
49d1cb2b HD	299	/* send SIGSEGV when outside of vma */
	300	if (!vma \|\|
	301	address < vma->vm_start \|\| address > vma->vm_end) {
	302	si.si_signo = SIGSEGV;
	303	si.si_code = SEGV_MAPERR;
	304	break;
	305	}
	306
	307	/* send SIGSEGV for wrong permissions */
	308	if ((vma->vm_flags & acc_type) != acc_type) {
	309	si.si_signo = SIGSEGV;
	310	si.si_code = SEGV_ACCERR;
	311	break;
	312	}
	313
	314	/* probably address is outside of mapped file */
	315	/* fall through */
1f2048fd HD	316	case 17: /* NA data TLB miss / page fault */
	317	case 18: /* Unaligned access - PCXS only */
	318	si.si_signo = SIGBUS;
49d1cb2b	319	si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
1f2048fd HD	320	break;
	321	case 16: /* Non-access instruction TLB miss fault */
	322	case 26: /* PCXL: Data memory access rights trap */
	323	default:
	324	si.si_signo = SIGSEGV;
49d1cb2b HD	325	si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
49d1cb2b HD	326	break;
1f2048fd	327	}
1da177e4	328	si.si_errno = 0;
1da177e4	329	si.si_addr = (void __user *) address;
1f2048fd	330	force_sig_info(si.si_signo, &si, current);
1da177e4 LT	331	return;
	332	}
	333
	334	no_context:
	335
c61c25eb KM	336	if (!user_mode(regs) && fixup_exception(regs)) {
c61c25eb KM	337	return;
1da177e4 LT	338	}
	339
	340	parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
	341
	342	out_of_memory:
	343	up_read(&mm->mmap_sem);
53e30d02 NP	344	if (!user_mode(regs))
	345	goto no_context;
	346	pagefault_out_of_memory();
1da177e4	347	}