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98658538 | 1 | /* |
98658538 LY |
2 | * QUICC Engine (QE) Internal Memory Map. |
3 | * The Internal Memory Map for devices with QE on them. This | |
4 | * is the superset of all QE devices (8360, etc.). | |
5 | ||
8a56e1ee | 6 | * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. |
98658538 LY |
7 | * |
8 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
9 | * Li Yang <leoli@freescale.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | #ifndef _ASM_POWERPC_IMMAP_QE_H | |
17 | #define _ASM_POWERPC_IMMAP_QE_H | |
18 | #ifdef __KERNEL__ | |
19 | ||
20 | #include <linux/kernel.h> | |
ab1220d5 | 21 | #include <asm/io.h> |
98658538 LY |
22 | |
23 | #define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ | |
24 | ||
25 | /* QE I-RAM */ | |
26 | struct qe_iram { | |
27 | __be32 iadd; /* I-RAM Address Register */ | |
28 | __be32 idata; /* I-RAM Data Register */ | |
e65650e6 KI |
29 | u8 res0[0x04]; |
30 | __be32 iready; /* I-RAM Ready Register */ | |
31 | u8 res1[0x70]; | |
98658538 LY |
32 | } __attribute__ ((packed)); |
33 | ||
34 | /* QE Interrupt Controller */ | |
35 | struct qe_ic_regs { | |
36 | __be32 qicr; | |
37 | __be32 qivec; | |
38 | __be32 qripnr; | |
39 | __be32 qipnr; | |
40 | __be32 qipxcc; | |
41 | __be32 qipycc; | |
42 | __be32 qipwcc; | |
43 | __be32 qipzcc; | |
44 | __be32 qimr; | |
45 | __be32 qrimr; | |
46 | __be32 qicnr; | |
47 | u8 res0[0x4]; | |
48 | __be32 qiprta; | |
49 | __be32 qiprtb; | |
50 | u8 res1[0x4]; | |
51 | __be32 qricr; | |
52 | u8 res2[0x20]; | |
53 | __be32 qhivec; | |
54 | u8 res3[0x1C]; | |
55 | } __attribute__ ((packed)); | |
56 | ||
57 | /* Communications Processor */ | |
58 | struct cp_qe { | |
59 | __be32 cecr; /* QE command register */ | |
60 | __be32 ceccr; /* QE controller configuration register */ | |
61 | __be32 cecdr; /* QE command data register */ | |
62 | u8 res0[0xA]; | |
63 | __be16 ceter; /* QE timer event register */ | |
64 | u8 res1[0x2]; | |
65 | __be16 cetmr; /* QE timers mask register */ | |
66 | __be32 cetscr; /* QE time-stamp timer control register */ | |
67 | __be32 cetsr1; /* QE time-stamp register 1 */ | |
68 | __be32 cetsr2; /* QE time-stamp register 2 */ | |
69 | u8 res2[0x8]; | |
70 | __be32 cevter; /* QE virtual tasks event register */ | |
71 | __be32 cevtmr; /* QE virtual tasks mask register */ | |
72 | __be16 cercr; /* QE RAM control register */ | |
73 | u8 res3[0x2]; | |
74 | u8 res4[0x24]; | |
75 | __be16 ceexe1; /* QE external request 1 event register */ | |
76 | u8 res5[0x2]; | |
77 | __be16 ceexm1; /* QE external request 1 mask register */ | |
78 | u8 res6[0x2]; | |
79 | __be16 ceexe2; /* QE external request 2 event register */ | |
80 | u8 res7[0x2]; | |
81 | __be16 ceexm2; /* QE external request 2 mask register */ | |
82 | u8 res8[0x2]; | |
83 | __be16 ceexe3; /* QE external request 3 event register */ | |
84 | u8 res9[0x2]; | |
85 | __be16 ceexm3; /* QE external request 3 mask register */ | |
86 | u8 res10[0x2]; | |
87 | __be16 ceexe4; /* QE external request 4 event register */ | |
88 | u8 res11[0x2]; | |
89 | __be16 ceexm4; /* QE external request 4 mask register */ | |
b6927bca EM |
90 | u8 res12[0x3A]; |
91 | __be32 ceurnr; /* QE microcode revision number register */ | |
92 | u8 res13[0x244]; | |
98658538 LY |
93 | } __attribute__ ((packed)); |
94 | ||
95 | /* QE Multiplexer */ | |
96 | struct qe_mux { | |
97 | __be32 cmxgcr; /* CMX general clock route register */ | |
98 | __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ | |
99 | __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ | |
100 | __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ | |
6b0b594b | 101 | __be32 cmxucr[4]; /* CMX UCCx clock route registers */ |
98658538 LY |
102 | __be32 cmxupcr; /* CMX UPC clock route register */ |
103 | u8 res0[0x1C]; | |
104 | } __attribute__ ((packed)); | |
105 | ||
106 | /* QE Timers */ | |
107 | struct qe_timers { | |
108 | u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/ | |
109 | u8 res0[0x3]; | |
110 | u8 gtcfr2; /* Timer 3 and timer 4 global config register*/ | |
111 | u8 res1[0xB]; | |
112 | __be16 gtmdr1; /* Timer 1 mode register */ | |
113 | __be16 gtmdr2; /* Timer 2 mode register */ | |
114 | __be16 gtrfr1; /* Timer 1 reference register */ | |
115 | __be16 gtrfr2; /* Timer 2 reference register */ | |
116 | __be16 gtcpr1; /* Timer 1 capture register */ | |
117 | __be16 gtcpr2; /* Timer 2 capture register */ | |
118 | __be16 gtcnr1; /* Timer 1 counter */ | |
119 | __be16 gtcnr2; /* Timer 2 counter */ | |
120 | __be16 gtmdr3; /* Timer 3 mode register */ | |
121 | __be16 gtmdr4; /* Timer 4 mode register */ | |
122 | __be16 gtrfr3; /* Timer 3 reference register */ | |
123 | __be16 gtrfr4; /* Timer 4 reference register */ | |
124 | __be16 gtcpr3; /* Timer 3 capture register */ | |
125 | __be16 gtcpr4; /* Timer 4 capture register */ | |
126 | __be16 gtcnr3; /* Timer 3 counter */ | |
127 | __be16 gtcnr4; /* Timer 4 counter */ | |
128 | __be16 gtevr1; /* Timer 1 event register */ | |
129 | __be16 gtevr2; /* Timer 2 event register */ | |
130 | __be16 gtevr3; /* Timer 3 event register */ | |
131 | __be16 gtevr4; /* Timer 4 event register */ | |
132 | __be16 gtps; /* Timer 1 prescale register */ | |
133 | u8 res2[0x46]; | |
134 | } __attribute__ ((packed)); | |
135 | ||
136 | /* BRG */ | |
137 | struct qe_brg { | |
fc9e8b4e | 138 | __be32 brgc[16]; /* BRG configuration registers */ |
98658538 LY |
139 | u8 res0[0x40]; |
140 | } __attribute__ ((packed)); | |
141 | ||
142 | /* SPI */ | |
143 | struct spi { | |
144 | u8 res0[0x20]; | |
145 | __be32 spmode; /* SPI mode register */ | |
146 | u8 res1[0x2]; | |
147 | u8 spie; /* SPI event register */ | |
148 | u8 res2[0x1]; | |
149 | u8 res3[0x2]; | |
150 | u8 spim; /* SPI mask register */ | |
151 | u8 res4[0x1]; | |
152 | u8 res5[0x1]; | |
153 | u8 spcom; /* SPI command register */ | |
154 | u8 res6[0x2]; | |
155 | __be32 spitd; /* SPI transmit data register (cpu mode) */ | |
156 | __be32 spird; /* SPI receive data register (cpu mode) */ | |
157 | u8 res7[0x8]; | |
158 | } __attribute__ ((packed)); | |
159 | ||
160 | /* SI */ | |
161 | struct si1 { | |
162 | __be16 siamr1; /* SI1 TDMA mode register */ | |
163 | __be16 sibmr1; /* SI1 TDMB mode register */ | |
164 | __be16 sicmr1; /* SI1 TDMC mode register */ | |
165 | __be16 sidmr1; /* SI1 TDMD mode register */ | |
166 | u8 siglmr1_h; /* SI1 global mode register high */ | |
167 | u8 res0[0x1]; | |
168 | u8 sicmdr1_h; /* SI1 command register high */ | |
169 | u8 res2[0x1]; | |
170 | u8 sistr1_h; /* SI1 status register high */ | |
171 | u8 res3[0x1]; | |
172 | __be16 sirsr1_h; /* SI1 RAM shadow address register high */ | |
173 | u8 sitarc1; /* SI1 RAM counter Tx TDMA */ | |
174 | u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ | |
175 | u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ | |
176 | u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ | |
177 | u8 sirarc1; /* SI1 RAM counter Rx TDMA */ | |
178 | u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ | |
179 | u8 sircrc1; /* SI1 RAM counter Rx TDMC */ | |
180 | u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ | |
181 | u8 res4[0x8]; | |
182 | __be16 siemr1; /* SI1 TDME mode register 16 bits */ | |
183 | __be16 sifmr1; /* SI1 TDMF mode register 16 bits */ | |
184 | __be16 sigmr1; /* SI1 TDMG mode register 16 bits */ | |
185 | __be16 sihmr1; /* SI1 TDMH mode register 16 bits */ | |
186 | u8 siglmg1_l; /* SI1 global mode register low 8 bits */ | |
187 | u8 res5[0x1]; | |
188 | u8 sicmdr1_l; /* SI1 command register low 8 bits */ | |
189 | u8 res6[0x1]; | |
190 | u8 sistr1_l; /* SI1 status register low 8 bits */ | |
191 | u8 res7[0x1]; | |
192 | __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/ | |
193 | u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ | |
194 | u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ | |
195 | u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ | |
196 | u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ | |
197 | u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ | |
198 | u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ | |
199 | u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ | |
200 | u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ | |
201 | u8 res8[0x8]; | |
202 | __be32 siml1; /* SI1 multiframe limit register */ | |
203 | u8 siedm1; /* SI1 extended diagnostic mode register */ | |
204 | u8 res9[0xBB]; | |
205 | } __attribute__ ((packed)); | |
206 | ||
207 | /* SI Routing Tables */ | |
208 | struct sir { | |
209 | u8 tx[0x400]; | |
210 | u8 rx[0x400]; | |
211 | u8 res0[0x800]; | |
212 | } __attribute__ ((packed)); | |
213 | ||
214 | /* USB Controller */ | |
80952988 | 215 | struct qe_usb_ctlr { |
98658538 LY |
216 | u8 usb_usmod; |
217 | u8 usb_usadr; | |
218 | u8 usb_uscom; | |
219 | u8 res1[1]; | |
2b487065 | 220 | __be16 usb_usep[4]; |
98658538 LY |
221 | u8 res2[4]; |
222 | __be16 usb_usber; | |
223 | u8 res3[2]; | |
224 | __be16 usb_usbmr; | |
225 | u8 res4[1]; | |
226 | u8 usb_usbs; | |
227 | __be16 usb_ussft; | |
228 | u8 res5[2]; | |
229 | __be16 usb_usfrn; | |
230 | u8 res6[0x22]; | |
231 | } __attribute__ ((packed)); | |
232 | ||
233 | /* MCC */ | |
80952988 | 234 | struct qe_mcc { |
98658538 LY |
235 | __be32 mcce; /* MCC event register */ |
236 | __be32 mccm; /* MCC mask register */ | |
237 | __be32 mccf; /* MCC configuration register */ | |
238 | __be32 merl; /* MCC emergency request level register */ | |
239 | u8 res0[0xF0]; | |
240 | } __attribute__ ((packed)); | |
241 | ||
242 | /* QE UCC Slow */ | |
243 | struct ucc_slow { | |
244 | __be32 gumr_l; /* UCCx general mode register (low) */ | |
245 | __be32 gumr_h; /* UCCx general mode register (high) */ | |
246 | __be16 upsmr; /* UCCx protocol-specific mode register */ | |
247 | u8 res0[0x2]; | |
248 | __be16 utodr; /* UCCx transmit on demand register */ | |
249 | __be16 udsr; /* UCCx data synchronization register */ | |
250 | __be16 ucce; /* UCCx event register */ | |
251 | u8 res1[0x2]; | |
252 | __be16 uccm; /* UCCx mask register */ | |
253 | u8 res2[0x1]; | |
254 | u8 uccs; /* UCCx status register */ | |
255 | u8 res3[0x24]; | |
256 | __be16 utpt; | |
297640e8 | 257 | u8 res4[0x52]; |
98658538 | 258 | u8 guemr; /* UCC general extended mode register */ |
98658538 LY |
259 | } __attribute__ ((packed)); |
260 | ||
261 | /* QE UCC Fast */ | |
262 | struct ucc_fast { | |
263 | __be32 gumr; /* UCCx general mode register */ | |
264 | __be32 upsmr; /* UCCx protocol-specific mode register */ | |
265 | __be16 utodr; /* UCCx transmit on demand register */ | |
266 | u8 res0[0x2]; | |
267 | __be16 udsr; /* UCCx data synchronization register */ | |
268 | u8 res1[0x2]; | |
269 | __be32 ucce; /* UCCx event register */ | |
270 | __be32 uccm; /* UCCx mask register */ | |
271 | u8 uccs; /* UCCx status register */ | |
272 | u8 res2[0x7]; | |
273 | __be32 urfb; /* UCC receive FIFO base */ | |
274 | __be16 urfs; /* UCC receive FIFO size */ | |
275 | u8 res3[0x2]; | |
276 | __be16 urfet; /* UCC receive FIFO emergency threshold */ | |
277 | __be16 urfset; /* UCC receive FIFO special emergency | |
278 | threshold */ | |
279 | __be32 utfb; /* UCC transmit FIFO base */ | |
280 | __be16 utfs; /* UCC transmit FIFO size */ | |
281 | u8 res4[0x2]; | |
282 | __be16 utfet; /* UCC transmit FIFO emergency threshold */ | |
283 | u8 res5[0x2]; | |
284 | __be16 utftt; /* UCC transmit FIFO transmit threshold */ | |
285 | u8 res6[0x2]; | |
286 | __be16 utpt; /* UCC transmit polling timer */ | |
287 | u8 res7[0x2]; | |
288 | __be32 urtry; /* UCC retry counter register */ | |
289 | u8 res8[0x4C]; | |
290 | u8 guemr; /* UCC general extended mode register */ | |
98658538 LY |
291 | } __attribute__ ((packed)); |
292 | ||
293 | struct ucc { | |
294 | union { | |
295 | struct ucc_slow slow; | |
296 | struct ucc_fast fast; | |
6b0b594b | 297 | u8 res[0x200]; /* UCC blocks are 512 bytes each */ |
98658538 LY |
298 | }; |
299 | } __attribute__ ((packed)); | |
300 | ||
301 | /* MultiPHY UTOPIA POS Controllers (UPC) */ | |
302 | struct upc { | |
303 | __be32 upgcr; /* UTOPIA/POS general configuration register */ | |
304 | __be32 uplpa; /* UTOPIA/POS last PHY address */ | |
305 | __be32 uphec; /* ATM HEC register */ | |
306 | __be32 upuc; /* UTOPIA/POS UCC configuration */ | |
307 | __be32 updc1; /* UTOPIA/POS device 1 configuration */ | |
308 | __be32 updc2; /* UTOPIA/POS device 2 configuration */ | |
309 | __be32 updc3; /* UTOPIA/POS device 3 configuration */ | |
310 | __be32 updc4; /* UTOPIA/POS device 4 configuration */ | |
311 | __be32 upstpa; /* UTOPIA/POS STPA threshold */ | |
312 | u8 res0[0xC]; | |
313 | __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */ | |
314 | __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */ | |
315 | __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */ | |
316 | __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */ | |
317 | __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */ | |
318 | __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */ | |
319 | __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */ | |
320 | __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */ | |
321 | __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */ | |
322 | __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */ | |
323 | __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */ | |
324 | __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */ | |
325 | __be32 upde1; /* UTOPIA/POS device 1 event */ | |
326 | __be32 upde2; /* UTOPIA/POS device 2 event */ | |
327 | __be32 upde3; /* UTOPIA/POS device 3 event */ | |
328 | __be32 upde4; /* UTOPIA/POS device 4 event */ | |
329 | __be16 uprp1; | |
330 | __be16 uprp2; | |
331 | __be16 uprp3; | |
332 | __be16 uprp4; | |
333 | u8 res1[0x8]; | |
334 | __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */ | |
335 | __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */ | |
336 | __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */ | |
337 | __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */ | |
338 | __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */ | |
339 | __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */ | |
340 | __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */ | |
341 | __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */ | |
342 | __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */ | |
343 | __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */ | |
344 | __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */ | |
345 | __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */ | |
346 | __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */ | |
347 | __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */ | |
348 | __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */ | |
349 | __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */ | |
350 | __be32 uper1; /* Device 1 port enable register */ | |
351 | __be32 uper2; /* Device 2 port enable register */ | |
352 | __be32 uper3; /* Device 3 port enable register */ | |
353 | __be32 uper4; /* Device 4 port enable register */ | |
354 | u8 res2[0x150]; | |
355 | } __attribute__ ((packed)); | |
356 | ||
357 | /* SDMA */ | |
358 | struct sdma { | |
359 | __be32 sdsr; /* Serial DMA status register */ | |
360 | __be32 sdmr; /* Serial DMA mode register */ | |
361 | __be32 sdtr1; /* SDMA system bus threshold register */ | |
362 | __be32 sdtr2; /* SDMA secondary bus threshold register */ | |
363 | __be32 sdhy1; /* SDMA system bus hysteresis register */ | |
364 | __be32 sdhy2; /* SDMA secondary bus hysteresis register */ | |
365 | __be32 sdta1; /* SDMA system bus address register */ | |
366 | __be32 sdta2; /* SDMA secondary bus address register */ | |
367 | __be32 sdtm1; /* SDMA system bus MSNUM register */ | |
368 | __be32 sdtm2; /* SDMA secondary bus MSNUM register */ | |
369 | u8 res0[0x10]; | |
370 | __be32 sdaqr; /* SDMA address bus qualify register */ | |
371 | __be32 sdaqmr; /* SDMA address bus qualify mask register */ | |
372 | u8 res1[0x4]; | |
373 | __be32 sdebcr; /* SDMA CAM entries base register */ | |
374 | u8 res2[0x38]; | |
375 | } __attribute__ ((packed)); | |
376 | ||
377 | /* Debug Space */ | |
378 | struct dbg { | |
379 | __be32 bpdcr; /* Breakpoint debug command register */ | |
380 | __be32 bpdsr; /* Breakpoint debug status register */ | |
381 | __be32 bpdmr; /* Breakpoint debug mask register */ | |
382 | __be32 bprmrr0; /* Breakpoint request mode risc register 0 */ | |
383 | __be32 bprmrr1; /* Breakpoint request mode risc register 1 */ | |
384 | u8 res0[0x8]; | |
385 | __be32 bprmtr0; /* Breakpoint request mode trb register 0 */ | |
386 | __be32 bprmtr1; /* Breakpoint request mode trb register 1 */ | |
387 | u8 res1[0x8]; | |
388 | __be32 bprmir; /* Breakpoint request mode immediate register */ | |
389 | __be32 bprmsr; /* Breakpoint request mode serial register */ | |
390 | __be32 bpemr; /* Breakpoint exit mode register */ | |
391 | u8 res2[0x48]; | |
392 | } __attribute__ ((packed)); | |
393 | ||
bc556ba9 TT |
394 | /* |
395 | * RISC Special Registers (Trap and Breakpoint). These are described in | |
396 | * the QE Developer's Handbook. | |
397 | */ | |
98658538 | 398 | struct rsp { |
bc556ba9 TT |
399 | __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ |
400 | u8 res0[64]; | |
401 | __be32 ibcr0; | |
402 | __be32 ibs0; | |
403 | __be32 ibcnr0; | |
404 | u8 res1[4]; | |
405 | __be32 ibcr1; | |
406 | __be32 ibs1; | |
407 | __be32 ibcnr1; | |
408 | __be32 npcr; | |
409 | __be32 dbcr; | |
410 | __be32 dbar; | |
411 | __be32 dbamr; | |
412 | __be32 dbsr; | |
413 | __be32 dbcnr; | |
414 | u8 res2[12]; | |
415 | __be32 dbdr_h; | |
416 | __be32 dbdr_l; | |
417 | __be32 dbdmr_h; | |
418 | __be32 dbdmr_l; | |
419 | __be32 bsr; | |
420 | __be32 bor; | |
421 | __be32 bior; | |
422 | u8 res3[4]; | |
423 | __be32 iatr[4]; | |
424 | __be32 eccr; /* Exception control configuration register */ | |
425 | __be32 eicr; | |
426 | u8 res4[0x100-0xf8]; | |
98658538 LY |
427 | } __attribute__ ((packed)); |
428 | ||
429 | struct qe_immap { | |
430 | struct qe_iram iram; /* I-RAM */ | |
431 | struct qe_ic_regs ic; /* Interrupt Controller */ | |
432 | struct cp_qe cp; /* Communications Processor */ | |
433 | struct qe_mux qmx; /* QE Multiplexer */ | |
434 | struct qe_timers qet; /* QE Timers */ | |
435 | struct spi spi[0x2]; /* spi */ | |
80952988 | 436 | struct qe_mcc mcc; /* mcc */ |
98658538 | 437 | struct qe_brg brg; /* brg */ |
80952988 | 438 | struct qe_usb_ctlr usb; /* USB */ |
98658538 LY |
439 | struct si1 si1; /* SI */ |
440 | u8 res11[0x800]; | |
441 | struct sir sir; /* SI Routing Tables */ | |
442 | struct ucc ucc1; /* ucc1 */ | |
443 | struct ucc ucc3; /* ucc3 */ | |
444 | struct ucc ucc5; /* ucc5 */ | |
445 | struct ucc ucc7; /* ucc7 */ | |
446 | u8 res12[0x600]; | |
447 | struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/ | |
448 | struct ucc ucc2; /* ucc2 */ | |
449 | struct ucc ucc4; /* ucc4 */ | |
450 | struct ucc ucc6; /* ucc6 */ | |
451 | struct ucc ucc8; /* ucc8 */ | |
452 | u8 res13[0x600]; | |
453 | struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ | |
454 | struct sdma sdma; /* SDMA */ | |
6b0b594b TT |
455 | struct dbg dbg; /* 0x104080 - 0x1040FF |
456 | Debug Space */ | |
457 | struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF | |
458 | RISC Special Registers | |
98658538 | 459 | (Trap and Breakpoint) */ |
6b0b594b TT |
460 | u8 res14[0x300]; /* 0x104300 - 0x1045FF */ |
461 | u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ | |
98658538 LY |
462 | u8 res16[0x8000]; /* 0x108000 - 0x110000 */ |
463 | u8 muram[0xC000]; /* 0x110000 - 0x11C000 | |
464 | Multi-user RAM */ | |
465 | u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ | |
466 | u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ | |
467 | } __attribute__ ((packed)); | |
468 | ||
0b51b02e | 469 | extern struct qe_immap __iomem *qe_immr; |
98658538 LY |
470 | extern phys_addr_t get_qe_base(void); |
471 | ||
b49d81de TT |
472 | /* |
473 | * Returns the offset within the QE address space of the given pointer. | |
474 | * | |
475 | * Note that the QE does not support 36-bit physical addresses, so if | |
476 | * get_qe_base() returns a number above 4GB, the caller will probably fail. | |
477 | */ | |
478 | static inline phys_addr_t immrbar_virt_to_phys(void *address) | |
98658538 | 479 | { |
b49d81de TT |
480 | void *q = (void *)qe_immr; |
481 | ||
482 | /* Is it a MURAM address? */ | |
483 | if ((address >= q) && (address < (q + QE_IMMAP_SIZE))) | |
484 | return get_qe_base() + (address - q); | |
485 | ||
486 | /* It's an address returned by kmalloc */ | |
487 | return virt_to_phys(address); | |
98658538 LY |
488 | } |
489 | ||
490 | #endif /* __KERNEL__ */ | |
491 | #endif /* _ASM_POWERPC_IMMAP_QE_H */ |