[deliverable/linux.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2
#else
#define TS_FPRWIDTH 1
#endif

#ifdef CONFIG_PPC64
/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
#define PPR_PRIORITY 3
#ifdef __ASSEMBLY__
#define INIT_PPR (PPR_PRIORITY << 50)
#else
#define INIT_PPR ((u64)PPR_PRIORITY << 50)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */

#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/cache.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/hw_breakpoint.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types. Unused */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

/* Lazy FPU handling on uni-processor */
extern struct task_struct *last_task_used_math;
extern struct task_struct *last_task_used_altivec;
extern struct task_struct *last_task_used_vsx;
extern struct task_struct *last_task_used_spe;

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/* 64-bit user address space is 46-bits (64TB user VM) */
#define TASK_SIZE_USER64 (0x0000400000000000UL)

/* 
 * 32-bit user address space is 4GB - 1 page 
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

#ifdef __powerpc64__

#define STACK_TOP_USER64 TASK_SIZE_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX STACK_TOP_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#define TS_FPR(i) fpr[i][TS_FPROFFSET]
#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	fs;		/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
#endif
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	unsigned long	dbcr0;
	unsigned long	dbcr1;
#ifdef CONFIG_BOOKE
	unsigned long	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	unsigned long	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
	/* FP and VSX 0-31 register set */
	double		fpr[32][TS_FPRWIDTH];
	struct {

		unsigned int pad;
		unsigned int val;	/* Floating point status */
	} fpscr;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_PPC64
	unsigned long	start_tb;	/* Start purr when proc switched in */
	unsigned long	accum_tb;	/* Total accumilated purr for process */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
	unsigned long	trap_nr;	/* last trap # on this thread */
#ifdef CONFIG_ALTIVEC
	/* Complete AltiVec register set */
	vector128	vr[32] __attribute__((aligned(16)));
	/* AltiVec status */
	vector128	vscr __attribute__((aligned(16)));
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used altivec */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	u64		tm_tfhar;	/* Transaction fail handler addr */
	u64		tm_texasr;	/* Transaction exception & summary */
	u64		tm_tfiar;	/* Transaction fail instr address reg */
	unsigned long	tm_orig_msr;	/* Thread's MSR on ctx switch */
	struct pt_regs	ckpt_regs;	/* Checkpointed registers */

	/*
	 * Transactional FP and VSX 0-31 register set.
	 * NOTE: the sense of these is the opposite of the integer ckpt_regs!
	 *
	 * When a transaction is active/signalled/scheduled etc., *regs is the
	 * most recent set of/speculated GPRs with ckpt_regs being the older
	 * checkpointed regs to which we roll back if transaction aborts.
	 *
	 * However, fpr[] is the checkpointed 'base state' of FP regs, and
	 * transact_fpr[] is the new set of transactional values.
	 * VRs work the same way.
	 */
	double		transact_fpr[32][TS_FPRWIDTH];
	struct {
		unsigned int pad;
		unsigned int val;	/* Floating point status */
	} transact_fpscr;
	vector128	transact_vr[32] __attribute__((aligned(16)));
	vector128	transact_vscr __attribute__((aligned(16)));
	unsigned long	transact_vrsave;
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	int		dscr_inherit;
	unsigned long	ppr;	/* used to save/restore SMT priority */
#endif
#ifdef CONFIG_PPC_BOOK3S_64
	unsigned long	tar;
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.fs = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.fs = KERNEL_DS, \
	.fpr = {{0}}, \
	.fpscr = { .val = 0, }, \
	.fpexc_mode = 0, \
	.ppr = INIT_PPR, \
}
#endif

/*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
#define thread_saved_pc(tsk)    \
        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
#else
#define cpu_relax()	barrier()
#endif

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#ifdef CONFIG_PPC64
#define HAVE_ARCH_PICK_MMAP_LAYOUT
#endif

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	unsigned long sp;

	if (is_32)
		sp = regs->gpr[1] & 0x0ffffffffUL;
	else
		sp = regs->gpr[1];

	return sp;
}
#else
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	return regs->gpr[1];
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern void power7_nap(void);

#ifdef CONFIG_PSERIES_IDLE
extern void update_smt_snooze_delay(int cpu, int residency);
#else
static inline void update_smt_snooze_delay(int cpu, int residency) {}
#endif

extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
	16	#define TS_FPRWIDTH 2
	17	#else
9c75a31c	18	#define TS_FPRWIDTH 1
c6e6771b	19	#endif
9c75a31c	20
92779245 HM	21	#ifdef CONFIG_PPC64
	22	/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
	23	#define PPR_PRIORITY 3
	24	#ifdef __ASSEMBLY__
	25	#define INIT_PPR (PPR_PRIORITY << 50)
	26	#else
	27	#define INIT_PPR ((u64)PPR_PRIORITY << 50)
	28	#endif /* __ASSEMBLY__ */
	29	#endif /* CONFIG_PPC64 */
	30
9f04b9e3 PM	31	#ifndef __ASSEMBLY__
9f04b9e3 PM	32	#include <linux/compiler.h>
1325a684	33	#include <linux/cache.h>
1da177e4 LT	34	#include <asm/ptrace.h>
1da177e4 LT	35	#include <asm/types.h>
9422de3e	36	#include <asm/hw_breakpoint.h>
1da177e4	37
799d6046 PM	38	/* We do _not_ want to define new machine types at all, those must die
	39	* in favor of using the device-tree
	40	* -- BenH.
1da177e4	41	*/
1da177e4	42
933ee711	43	/* PREP sub-platform types. Unused */
1da177e4 LT	44	#define _PREP_Motorola 0x01 /* motorola prep */
	45	#define _PREP_Firm 0x02 /* firmworks prep */
	46	#define _PREP_IBM 0x00 /* ibm prep */
	47	#define _PREP_Bull 0x03 /* bull prep */
	48
799d6046	49	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	50	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	51	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	52	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	53	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	54
e8222502 BH	55	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	56
	57	extern int _chrp_type;
799d6046	58
e8222502 BH	59	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	60
9f04b9e3 PM	61	/*
	62	* Default implementation of macro that returns current
	63	* instruction pointer ("program counter").
	64	*/
	65	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	66
	67	/* Macros for adjusting thread priority (hardware multi-threading) */
	68	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	69	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	70	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	71	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	72	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	73	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	74
	75	#ifdef __KERNEL__
	76
1da177e4	77	struct task_struct;
9f04b9e3	78	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	79	void release_thread(struct task_struct *);
1da177e4 LT	80
1da177e4 LT	81	/* Lazy FPU handling on uni-processor */
	82	extern struct task_struct *last_task_used_math;
	83	extern struct task_struct *last_task_used_altivec;
c6e6771b	84	extern struct task_struct *last_task_used_vsx;
1da177e4 LT	85	extern struct task_struct *last_task_used_spe;
1da177e4 LT	86
9f04b9e3	87	#ifdef CONFIG_PPC32
7c4f10b9 RT	88
	89	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	90	#error User TASK_SIZE overlaps with KERNEL_START address
	91	#endif
9f04b9e3 PM	92	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	93
1da177e4 LT	94	/* This decides where the kernel will search for a free chunk of vm
	95	* space during mmap's.
	96	*/
	97	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	98	#endif
	99
	100	#ifdef CONFIG_PPC64
048ee099 AK	101	/* 64-bit user address space is 46-bits (64TB user VM) */
048ee099 AK	102	#define TASK_SIZE_USER64 (0x0000400000000000UL)
9f04b9e3 PM	103
	104	/*
	105	* 32-bit user address space is 4GB - 1 page
	106	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	107	*/
	108	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	109
82455257	110	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	111	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	112	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	113
	114	/* This decides where the kernel will search for a free chunk of vm
	115	* space during mmap's.
	116	*/
	117	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
	118	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
	119
cab175f9	120	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	121	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	122	#endif
1da177e4	123
922a70d3 DH	124	#ifdef __powerpc64__
	125
	126	#define STACK_TOP_USER64 TASK_SIZE_USER64
	127	#define STACK_TOP_USER32 TASK_SIZE_USER32
	128
cab175f9	129	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	130	STACK_TOP_USER32 : STACK_TOP_USER64)
	131
	132	#define STACK_TOP_MAX STACK_TOP_USER64
	133
	134	#else /* __powerpc64__ */
	135
	136	#define STACK_TOP TASK_SIZE
	137	#define STACK_TOP_MAX STACK_TOP
	138
	139	#endif /* __powerpc64__ */
922a70d3	140
1da177e4 LT	141	typedef struct {
	142	unsigned long seg;
	143	} mm_segment_t;
	144
c6e6771b MN	145	#define TS_FPROFFSET 0
	146	#define TS_VSRLOWOFFSET 1
	147	#define TS_FPR(i) fpr[i][TS_FPROFFSET]
8b3c34cf	148	#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]
9c75a31c	149
1da177e4 LT	150	struct thread_struct {
1da177e4 LT	151	unsigned long ksp; /* Kernel stack pointer */
85218827 KG	152	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
85218827 KG	153
9f04b9e3 PM	154	#ifdef CONFIG_PPC64
	155	unsigned long ksp_vsid;
	156	#endif
1da177e4 LT	157	struct pt_regs regs; / Pointer to saved register state */
1da177e4 LT	158	mm_segment_t fs; /* for get_fs() validation */
1325a684 AK	159	#ifdef CONFIG_BOOKE
	160	/* BookE base exception scratch space; align on cacheline */
	161	unsigned long normsave[8] ____cacheline_aligned;
	162	#endif
9f04b9e3	163	#ifdef CONFIG_PPC32
1da177e4	164	void pgdir; / root of page-table tree */
9f04b9e3	165	#endif
99396ac1 DK	166	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	167	/*
	168	* The following help to manage the use of Debug Control Registers
	169	* om the BookE platforms.
	170	*/
	171	unsigned long dbcr0;
1da177e4	172	unsigned long dbcr1;
99396ac1 DK	173	#ifdef CONFIG_BOOKE
	174	unsigned long dbcr2;
	175	#endif
	176	/*
	177	* The stored value of the DBSR register will be the value at the
	178	* last debug interrupt. This register can only be read from the
	179	* user (will never be written to) and has value while helping to
	180	* describe the reason for the last debug trap. Torez
	181	*/
	182	unsigned long dbsr;
	183	/*
	184	* The following will contain addresses used by debug applications
	185	* to help trace and trap on particular address locations.
	186	* The bits in the Debug Control Registers above help define which
	187	* of the following registers will contain valid data and/or addresses.
	188	*/
	189	unsigned long iac1;
	190	unsigned long iac2;
	191	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	192	unsigned long iac3;
	193	unsigned long iac4;
	194	#endif
	195	unsigned long dac1;
	196	unsigned long dac2;
	197	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	198	unsigned long dvc1;
	199	unsigned long dvc2;
	200	#endif
1da177e4	201	#endif
c6e6771b MN	202	/* FP and VSX 0-31 register set */
	203	double fpr[32][TS_FPRWIDTH];
	204	struct {
25c8a78b DG	205
	206	unsigned int pad;
	207	unsigned int val; /* Floating point status */
	208	} fpscr;
9f04b9e3	209	int fpexc_mode; /* floating-point exception mode */
e9370ae1	210	unsigned int align_ctl; /* alignment handling control */
9f04b9e3 PM	211	#ifdef CONFIG_PPC64
	212	unsigned long start_tb; /* Start purr when proc switched in */
	213	unsigned long accum_tb; /* Total accumilated purr for process */
5aae8a53 P	214	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	215	struct perf_event *ptrace_bps[HBP_NUM];
	216	/*
	217	* Helps identify source of single-step exception and subsequent
	218	* hw-breakpoint enablement
	219	*/
	220	struct perf_event *last_hit_ubp;
	221	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9f04b9e3	222	#endif
9422de3e	223	struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
41ab5266	224	unsigned long trap_nr; /* last trap # on this thread */
1da177e4 LT	225	#ifdef CONFIG_ALTIVEC
1da177e4 LT	226	/* Complete AltiVec register set */
fc624eae	227	vector128 vr[32] __attribute__((aligned(16)));
1da177e4	228	/* AltiVec status */
fc624eae	229	vector128 vscr __attribute__((aligned(16)));
1da177e4 LT	230	unsigned long vrsave;
	231	int used_vr; /* set if process has used altivec */
	232	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	233	#ifdef CONFIG_VSX
	234	/* VSR status */
	235	int used_vsr; /* set if process has used altivec */
	236	#endif /* CONFIG_VSX */
1da177e4 LT	237	#ifdef CONFIG_SPE
	238	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	239	u64 acc; /* Accumulator */
	240	unsigned long spefscr; /* SPE & eFP status */
	241	int used_spe; /* set if process has used spe */
	242	#endif /* CONFIG_SPE */
f4c3aff2 MN	243	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	244	u64 tm_tfhar; /* Transaction fail handler addr */
	245	u64 tm_texasr; /* Transaction exception & summary */
	246	u64 tm_tfiar; /* Transaction fail instr address reg */
	247	unsigned long tm_orig_msr; /* Thread's MSR on ctx switch */
	248	struct pt_regs ckpt_regs; /* Checkpointed registers */
	249
	250	/*
	251	* Transactional FP and VSX 0-31 register set.
	252	* NOTE: the sense of these is the opposite of the integer ckpt_regs!
	253	*
	254	* When a transaction is active/signalled/scheduled etc., *regs is the
	255	* most recent set of/speculated GPRs with ckpt_regs being the older
	256	* checkpointed regs to which we roll back if transaction aborts.
	257	*
	258	* However, fpr[] is the checkpointed 'base state' of FP regs, and
	259	* transact_fpr[] is the new set of transactional values.
	260	* VRs work the same way.
	261	*/
	262	double transact_fpr[32][TS_FPRWIDTH];
	263	struct {
	264	unsigned int pad;
	265	unsigned int val; /* Floating point status */
	266	} transact_fpscr;
	267	vector128 transact_vr[32] __attribute__((aligned(16)));
	268	vector128 transact_vscr __attribute__((aligned(16)));
	269	unsigned long transact_vrsave;
	270	#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
97e49255 AG	271	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	272	void* kvm_shadow_vcpu; /* KVM internal data */
	273	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	274	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	275	struct kvm_vcpu *kvm_vcpu;
	276	#endif
efcac658 AK	277	#ifdef CONFIG_PPC64
	278	unsigned long dscr;
	279	int dscr_inherit;
92779245	280	unsigned long ppr; /* used to save/restore SMT priority */
efcac658	281	#endif
2468dcf6 IM	282	#ifdef CONFIG_PPC_BOOK3S_64
	283	unsigned long tar;
	284	#endif
1da177e4 LT	285	};
	286
	287	#define ARCH_MIN_TASKALIGN 16
	288
	289	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	290	#define INIT_SP_LIMIT \
85218827 KG	291	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	292
6a800f36 LY	293	#ifdef CONFIG_SPE
	294	#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
	295	#else
	296	#define SPEFSCR_INIT
	297	#endif
9f04b9e3 PM	298
9f04b9e3 PM	299	#ifdef CONFIG_PPC32
1da177e4 LT	300	#define INIT_THREAD { \
1da177e4 LT	301	.ksp = INIT_SP, \
85218827	302	.ksp_limit = INIT_SP_LIMIT, \
1da177e4 LT	303	.fs = KERNEL_DS, \
	304	.pgdir = swapper_pg_dir, \
	305	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	306	SPEFSCR_INIT \
1da177e4	307	}
9f04b9e3 PM	308	#else
	309	#define INIT_THREAD { \
	310	.ksp = INIT_SP, \
85218827	311	.ksp_limit = INIT_SP_LIMIT, \
9f04b9e3 PM	312	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
9f04b9e3 PM	313	.fs = KERNEL_DS, \
e17a2565	314	.fpr = {{0}}, \
25c8a78b	315	.fpscr = { .val = 0, }, \
ddf5f75a	316	.fpexc_mode = 0, \
92779245	317	.ppr = INIT_PPR, \
9f04b9e3 PM	318	}
9f04b9e3 PM	319	#endif
1da177e4 LT	320
	321	/*
	322	* Return saved PC of a blocked thread. For now, this is the "user" PC
	323	*/
9f04b9e3 PM	324	#define thread_saved_pc(tsk) \
9f04b9e3 PM	325	((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
1da177e4	326
e5093ff0 SD	327	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	328
1da177e4 LT	329	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	330
9f04b9e3 PM	331	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	332	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	333
1da177e4 LT	334	/* Get/set floating-point exception mode */
9f04b9e3 PM	335	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	336	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	337
	338	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	339	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	340
fab5db97 PM	341	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	342	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	343
	344	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	345	extern int set_endian(struct task_struct *tsk, unsigned int val);
	346
e9370ae1 PM	347	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	348	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	349
	350	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	351	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	352
9f04b9e3	353	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	354	{
	355	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	356	}
	357
9f04b9e3	358	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	359	{
	360	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	361	}
	362
9f04b9e3 PM	363	#ifdef CONFIG_PPC64
	364	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
	365	#else
1da177e4	366	#define cpu_relax() barrier()
9f04b9e3	367	#endif
1da177e4	368
2f25194d AB	369	/* Check that a certain kernel stack pointer is valid in task_struct p */
	370	int validate_sp(unsigned long sp, struct task_struct *p,
	371	unsigned long nbytes);
	372
1da177e4 LT	373	/*
	374	* Prefetch macros.
	375	*/
	376	#define ARCH_HAS_PREFETCH
	377	#define ARCH_HAS_PREFETCHW
	378	#define ARCH_HAS_SPINLOCK_PREFETCH
	379
9f04b9e3	380	static inline void prefetch(const void *x)
1da177e4	381	{
9f04b9e3 PM	382	if (unlikely(!x))
	383	return;
	384
	385	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	386	}
1da177e4 LT	387
9f04b9e3	388	static inline void prefetchw(const void *x)
1da177e4	389	{
9f04b9e3 PM	390	if (unlikely(!x))
	391	return;
	392
	393	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	394	}
	395
	396	#define spin_lock_prefetch(x) prefetchw(x)
	397
9f04b9e3 PM	398	#ifdef CONFIG_PPC64
	399	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	400	#endif
1da177e4	401
efbda860 JB	402	#ifdef CONFIG_PPC64
	403	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	404	{
	405	unsigned long sp;
	406
	407	if (is_32)
	408	sp = regs->gpr[1] & 0x0ffffffffUL;
	409	else
	410	sp = regs->gpr[1];
	411
	412	return sp;
	413	}
	414	#else
	415	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	416	{
	417	return regs->gpr[1];
	418	}
	419	#endif
	420
e8bb3e00	421	extern unsigned long cpuidle_disable;
771dae81 DD	422	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	423
ae3a197e	424	extern int powersave_nap; /* set if nap mode can be used in idle loop */
375f561a	425	extern void power7_nap(void);
ae3a197e DH	426
ae3a197e DH	427	#ifdef CONFIG_PSERIES_IDLE
8ea959a1	428	extern void update_smt_snooze_delay(int cpu, int residency);
ae3a197e	429	#else
8ea959a1	430	static inline void update_smt_snooze_delay(int cpu, int residency) {}
ae3a197e DH	431	#endif
	432
	433	extern void flush_instruction_cache(void);
	434	extern void hard_reset_now(void);
	435	extern void poweroff_now(void);
	436	extern int fix_alignment(struct pt_regs *);
	437	extern void cvt_fd(float from, double to);
	438	extern void cvt_df(double from, float to);
	439	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	440
	441	#ifdef CONFIG_PPC64
	442	/*
	443	* We handle most unaligned accesses in hardware. On the other hand
	444	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	445	* powers of 2 writes until it reaches sufficient alignment).
	446	*
	447	* Based on this we disable the IP header alignment in network drivers.
	448	*/
	449	#define NET_IP_ALIGN 0
	450	#endif
	451
1da177e4	452	#endif /* __KERNEL__ */
9f04b9e3 PM	453	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	454	#endif /* _ASM_POWERPC_PROCESSOR_H */