[deliverable/linux.git] / arch / powerpc / include / asm / processor.h

#ifndef _ASM_POWERPC_PROCESSOR_H
#define _ASM_POWERPC_PROCESSOR_H

/*
 * Copyright (C) 2001 PPC 64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/reg.h>

#ifdef CONFIG_VSX
#define TS_FPRWIDTH 2
#else
#define TS_FPRWIDTH 1
#endif

#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <linux/cache.h>
#include <asm/ptrace.h>
#include <asm/types.h>

/* We do _not_ want to define new machine types at all, those must die
 * in favor of using the device-tree
 * -- BenH.
 */

/* PREP sub-platform types see residual.h for these */
#define _PREP_Motorola	0x01	/* motorola prep */
#define _PREP_Firm	0x02	/* firmworks prep */
#define _PREP_IBM	0x00	/* ibm prep */
#define _PREP_Bull	0x03	/* bull prep */

/* CHRP sub-platform types. These are arbitrary */
#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
#define _CHRP_briq	0x07	/* TotalImpact's briQ */

#if defined(__KERNEL__) && defined(CONFIG_PPC32)

extern int _chrp_type;

#ifdef CONFIG_PPC_PREP

/* what kind of prep workstation we are */
extern int _prep_type;

#endif /* CONFIG_PPC_PREP */

#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/* Macros for adjusting thread priority (hardware multi-threading) */
#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")

#ifdef __KERNEL__

struct task_struct;
void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
void release_thread(struct task_struct *);

/* Lazy FPU handling on uni-processor */
extern struct task_struct *last_task_used_math;
extern struct task_struct *last_task_used_altivec;
extern struct task_struct *last_task_used_vsx;
extern struct task_struct *last_task_used_spe;

#ifdef CONFIG_PPC32

#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
#error User TASK_SIZE overlaps with KERNEL_START address
#endif
#define TASK_SIZE	(CONFIG_TASK_SIZE)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
#endif

#ifdef CONFIG_PPC64
/* 64-bit user address space is 46-bits (64TB user VM) */
#define TASK_SIZE_USER64 (0x0000400000000000UL)

/* 
 * 32-bit user address space is 4GB - 1 page 
 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 */
#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))

#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
		TASK_SIZE_USER32 : TASK_SIZE_USER64)
#define TASK_SIZE	  TASK_SIZE_OF(current)

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))

#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif

#ifdef __powerpc64__

#define STACK_TOP_USER64 TASK_SIZE_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32

#define STACK_TOP (is_32bit_task() ? \
		   STACK_TOP_USER32 : STACK_TOP_USER64)

#define STACK_TOP_MAX STACK_TOP_USER64

#else /* __powerpc64__ */

#define STACK_TOP TASK_SIZE
#define STACK_TOP_MAX	STACK_TOP

#endif /* __powerpc64__ */

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define TS_FPROFFSET 0
#define TS_VSRLOWOFFSET 1
#define TS_FPR(i) fpr[i][TS_FPROFFSET]

struct thread_struct {
	unsigned long	ksp;		/* Kernel stack pointer */
	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */

#ifdef CONFIG_PPC64
	unsigned long	ksp_vsid;
#endif
	struct pt_regs	*regs;		/* Pointer to saved register state */
	mm_segment_t	fs;		/* for get_fs() validation */
#ifdef CONFIG_BOOKE
	/* BookE base exception scratch space; align on cacheline */
	unsigned long	normsave[8] ____cacheline_aligned;
#endif
#ifdef CONFIG_PPC32
	void		*pgdir;		/* root of page-table tree */
#endif
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	/*
	 * The following help to manage the use of Debug Control Registers
	 * om the BookE platforms.
	 */
	unsigned long	dbcr0;
	unsigned long	dbcr1;
#ifdef CONFIG_BOOKE
	unsigned long	dbcr2;
#endif
	/*
	 * The stored value of the DBSR register will be the value at the
	 * last debug interrupt. This register can only be read from the
	 * user (will never be written to) and has value while helping to
	 * describe the reason for the last debug trap.  Torez
	 */
	unsigned long	dbsr;
	/*
	 * The following will contain addresses used by debug applications
	 * to help trace and trap on particular address locations.
	 * The bits in the Debug Control Registers above help define which
	 * of the following registers will contain valid data and/or addresses.
	 */
	unsigned long	iac1;
	unsigned long	iac2;
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	unsigned long	iac3;
	unsigned long	iac4;
#endif
	unsigned long	dac1;
	unsigned long	dac2;
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	unsigned long	dvc1;
	unsigned long	dvc2;
#endif
#endif
	/* FP and VSX 0-31 register set */
	double		fpr[32][TS_FPRWIDTH];
	struct {

		unsigned int pad;
		unsigned int val;	/* Floating point status */
	} fpscr;
	int		fpexc_mode;	/* floating-point exception mode */
	unsigned int	align_ctl;	/* alignment handling control */
#ifdef CONFIG_PPC64
	unsigned long	start_tb;	/* Start purr when proc switched in */
	unsigned long	accum_tb;	/* Total accumilated purr for process */
#ifdef CONFIG_HAVE_HW_BREAKPOINT
	struct perf_event *ptrace_bps[HBP_NUM];
	/*
	 * Helps identify source of single-step exception and subsequent
	 * hw-breakpoint enablement
	 */
	struct perf_event *last_hit_ubp;
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
	unsigned long	dabr;		/* Data address breakpoint register */
	unsigned long	dabrx;		/*      ... extension  */
	unsigned long	trap_nr;	/* last trap # on this thread */
#ifdef CONFIG_ALTIVEC
	/* Complete AltiVec register set */
	vector128	vr[32] __attribute__((aligned(16)));
	/* AltiVec status */
	vector128	vscr __attribute__((aligned(16)));
	unsigned long	vrsave;
	int		used_vr;	/* set if process has used altivec */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
	/* VSR status */
	int		used_vsr;	/* set if process has used altivec */
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
	u64		acc;		/* Accumulator */
	unsigned long	spefscr;	/* SPE & eFP status */
	int		used_spe;	/* set if process has used spe */
#endif /* CONFIG_SPE */
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	void*		kvm_shadow_vcpu; /* KVM internal data */
#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	struct kvm_vcpu	*kvm_vcpu;
#endif
#ifdef CONFIG_PPC64
	unsigned long	dscr;
	int		dscr_inherit;
#endif
};

#define ARCH_MIN_TASKALIGN 16

#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
#define INIT_SP_LIMIT \
	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)

#ifdef CONFIG_SPE
#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
#else
#define SPEFSCR_INIT
#endif

#ifdef CONFIG_PPC32
#define INIT_THREAD { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.fs = KERNEL_DS, \
	.pgdir = swapper_pg_dir, \
	.fpexc_mode = MSR_FE0 | MSR_FE1, \
	SPEFSCR_INIT \
}
#else
#define INIT_THREAD  { \
	.ksp = INIT_SP, \
	.ksp_limit = INIT_SP_LIMIT, \
	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
	.fs = KERNEL_DS, \
	.fpr = {{0}}, \
	.fpscr = { .val = 0, }, \
	.fpexc_mode = 0, \
}
#endif

/*
 * Return saved PC of a blocked thread. For now, this is the "user" PC
 */
#define thread_saved_pc(tsk)    \
        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)

#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)

unsigned long get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)

/* Get/set floating-point exception mode */
#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))

extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);

#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))

extern int get_endian(struct task_struct *tsk, unsigned long adr);
extern int set_endian(struct task_struct *tsk, unsigned int val);

#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

static inline unsigned int __unpack_fe01(unsigned long msr_bits)
{
	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
}

static inline unsigned long __pack_fe01(unsigned int fpmode)
{
	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
}

#ifdef CONFIG_PPC64
#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
#else
#define cpu_relax()	barrier()
#endif

/* Check that a certain kernel stack pointer is valid in task_struct p */
int validate_sp(unsigned long sp, struct task_struct *p,
                       unsigned long nbytes);

/*
 * Prefetch macros.
 */
#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

static inline void prefetch(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
}

static inline void prefetchw(const void *x)
{
	if (unlikely(!x))
		return;

	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
}

#define spin_lock_prefetch(x)	prefetchw(x)

#ifdef CONFIG_PPC64
#define HAVE_ARCH_PICK_MMAP_LAYOUT
#endif

#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	unsigned long sp;

	if (is_32)
		sp = regs->gpr[1] & 0x0ffffffffUL;
	else
		sp = regs->gpr[1];

	return sp;
}
#else
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
{
	return regs->gpr[1];
}
#endif

extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};

extern int powersave_nap;	/* set if nap mode can be used in idle loop */
extern void power7_nap(void);

#ifdef CONFIG_PSERIES_IDLE
extern void update_smt_snooze_delay(int cpu, int residency);
#else
static inline void update_smt_snooze_delay(int cpu, int residency) {}
#endif

extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);

#ifdef CONFIG_PPC64
/*
 * We handle most unaligned accesses in hardware. On the other hand 
 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 * powers of 2 writes until it reaches sufficient alignment).
 *
 * Based on this we disable the IP header alignment in network drivers.
 */
#define NET_IP_ALIGN	0
#endif

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PROCESSOR_H */
Commit	Line	Data
9f04b9e3 PM	1	#ifndef _ASM_POWERPC_PROCESSOR_H
9f04b9e3 PM	2	#define _ASM_POWERPC_PROCESSOR_H
1da177e4 LT	3
1da177e4 LT	4	/*
9f04b9e3 PM	5	* Copyright (C) 2001 PPC 64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
1da177e4	11	*/
1da177e4	12
9f04b9e3	13	#include <asm/reg.h>
1da177e4	14
c6e6771b MN	15	#ifdef CONFIG_VSX
	16	#define TS_FPRWIDTH 2
	17	#else
9c75a31c	18	#define TS_FPRWIDTH 1
c6e6771b	19	#endif
9c75a31c	20
9f04b9e3 PM	21	#ifndef __ASSEMBLY__
9f04b9e3 PM	22	#include <linux/compiler.h>
1325a684	23	#include <linux/cache.h>
1da177e4 LT	24	#include <asm/ptrace.h>
1da177e4 LT	25	#include <asm/types.h>
1da177e4	26
799d6046 PM	27	/* We do _not_ want to define new machine types at all, those must die
	28	* in favor of using the device-tree
	29	* -- BenH.
1da177e4	30	*/
1da177e4	31
799d6046	32	/* PREP sub-platform types see residual.h for these */
1da177e4 LT	33	#define _PREP_Motorola 0x01 /* motorola prep */
	34	#define _PREP_Firm 0x02 /* firmworks prep */
	35	#define _PREP_IBM 0x00 /* ibm prep */
	36	#define _PREP_Bull 0x03 /* bull prep */
	37
799d6046	38	/* CHRP sub-platform types. These are arbitrary */
1da177e4 LT	39	#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
	40	#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
	41	#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
26c5032e	42	#define _CHRP_briq 0x07 /* TotalImpact's briQ */
1da177e4	43
e8222502 BH	44	#if defined(__KERNEL__) && defined(CONFIG_PPC32)
	45
	46	extern int _chrp_type;
799d6046	47
0a26b136	48	#ifdef CONFIG_PPC_PREP
799d6046	49
1da177e4 LT	50	/* what kind of prep workstation we are */
1da177e4 LT	51	extern int _prep_type;
1da177e4	52
0a26b136 PM	53	#endif /* CONFIG_PPC_PREP */
0a26b136 PM	54
e8222502 BH	55	#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
e8222502 BH	56
9f04b9e3 PM	57	/*
	58	* Default implementation of macro that returns current
	59	* instruction pointer ("program counter").
	60	*/
	61	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	62
	63	/* Macros for adjusting thread priority (hardware multi-threading) */
	64	#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
	65	#define HMT_low() asm volatile("or 1,1,1 # low priority")
	66	#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
	67	#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
	68	#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
	69	#define HMT_high() asm volatile("or 3,3,3 # high priority")
	70
	71	#ifdef __KERNEL__
	72
1da177e4	73	struct task_struct;
9f04b9e3	74	void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
1da177e4 LT	75	void release_thread(struct task_struct *);
1da177e4 LT	76
1da177e4 LT	77	/* Lazy FPU handling on uni-processor */
	78	extern struct task_struct *last_task_used_math;
	79	extern struct task_struct *last_task_used_altivec;
c6e6771b	80	extern struct task_struct *last_task_used_vsx;
1da177e4 LT	81	extern struct task_struct *last_task_used_spe;
1da177e4 LT	82
9f04b9e3	83	#ifdef CONFIG_PPC32
7c4f10b9 RT	84
	85	#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
	86	#error User TASK_SIZE overlaps with KERNEL_START address
	87	#endif
9f04b9e3 PM	88	#define TASK_SIZE (CONFIG_TASK_SIZE)
9f04b9e3 PM	89
1da177e4 LT	90	/* This decides where the kernel will search for a free chunk of vm
	91	* space during mmap's.
	92	*/
	93	#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
9f04b9e3 PM	94	#endif
	95
	96	#ifdef CONFIG_PPC64
048ee099 AK	97	/* 64-bit user address space is 46-bits (64TB user VM) */
048ee099 AK	98	#define TASK_SIZE_USER64 (0x0000400000000000UL)
9f04b9e3 PM	99
	100	/*
	101	* 32-bit user address space is 4GB - 1 page
	102	* (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
	103	*/
	104	#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
	105
82455257	106	#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
9f04b9e3	107	TASK_SIZE_USER32 : TASK_SIZE_USER64)
82455257	108	#define TASK_SIZE TASK_SIZE_OF(current)
9f04b9e3 PM	109
	110	/* This decides where the kernel will search for a free chunk of vm
	111	* space during mmap's.
	112	*/
	113	#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
	114	#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
	115
cab175f9	116	#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
9f04b9e3 PM	117	TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
9f04b9e3 PM	118	#endif
1da177e4	119
922a70d3 DH	120	#ifdef __powerpc64__
	121
	122	#define STACK_TOP_USER64 TASK_SIZE_USER64
	123	#define STACK_TOP_USER32 TASK_SIZE_USER32
	124
cab175f9	125	#define STACK_TOP (is_32bit_task() ? \
922a70d3 DH	126	STACK_TOP_USER32 : STACK_TOP_USER64)
	127
	128	#define STACK_TOP_MAX STACK_TOP_USER64
	129
	130	#else /* __powerpc64__ */
	131
	132	#define STACK_TOP TASK_SIZE
	133	#define STACK_TOP_MAX STACK_TOP
	134
	135	#endif /* __powerpc64__ */
922a70d3	136
1da177e4 LT	137	typedef struct {
	138	unsigned long seg;
	139	} mm_segment_t;
	140
c6e6771b MN	141	#define TS_FPROFFSET 0
	142	#define TS_VSRLOWOFFSET 1
	143	#define TS_FPR(i) fpr[i][TS_FPROFFSET]
9c75a31c	144
1da177e4 LT	145	struct thread_struct {
1da177e4 LT	146	unsigned long ksp; /* Kernel stack pointer */
85218827 KG	147	unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
85218827 KG	148
9f04b9e3 PM	149	#ifdef CONFIG_PPC64
	150	unsigned long ksp_vsid;
	151	#endif
1da177e4 LT	152	struct pt_regs regs; / Pointer to saved register state */
1da177e4 LT	153	mm_segment_t fs; /* for get_fs() validation */
1325a684 AK	154	#ifdef CONFIG_BOOKE
	155	/* BookE base exception scratch space; align on cacheline */
	156	unsigned long normsave[8] ____cacheline_aligned;
	157	#endif
9f04b9e3	158	#ifdef CONFIG_PPC32
1da177e4	159	void pgdir; / root of page-table tree */
9f04b9e3	160	#endif
99396ac1 DK	161	#ifdef CONFIG_PPC_ADV_DEBUG_REGS
	162	/*
	163	* The following help to manage the use of Debug Control Registers
	164	* om the BookE platforms.
	165	*/
	166	unsigned long dbcr0;
1da177e4	167	unsigned long dbcr1;
99396ac1 DK	168	#ifdef CONFIG_BOOKE
	169	unsigned long dbcr2;
	170	#endif
	171	/*
	172	* The stored value of the DBSR register will be the value at the
	173	* last debug interrupt. This register can only be read from the
	174	* user (will never be written to) and has value while helping to
	175	* describe the reason for the last debug trap. Torez
	176	*/
	177	unsigned long dbsr;
	178	/*
	179	* The following will contain addresses used by debug applications
	180	* to help trace and trap on particular address locations.
	181	* The bits in the Debug Control Registers above help define which
	182	* of the following registers will contain valid data and/or addresses.
	183	*/
	184	unsigned long iac1;
	185	unsigned long iac2;
	186	#if CONFIG_PPC_ADV_DEBUG_IACS > 2
	187	unsigned long iac3;
	188	unsigned long iac4;
	189	#endif
	190	unsigned long dac1;
	191	unsigned long dac2;
	192	#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
	193	unsigned long dvc1;
	194	unsigned long dvc2;
	195	#endif
1da177e4	196	#endif
c6e6771b MN	197	/* FP and VSX 0-31 register set */
	198	double fpr[32][TS_FPRWIDTH];
	199	struct {
25c8a78b DG	200
	201	unsigned int pad;
	202	unsigned int val; /* Floating point status */
	203	} fpscr;
9f04b9e3	204	int fpexc_mode; /* floating-point exception mode */
e9370ae1	205	unsigned int align_ctl; /* alignment handling control */
9f04b9e3 PM	206	#ifdef CONFIG_PPC64
	207	unsigned long start_tb; /* Start purr when proc switched in */
	208	unsigned long accum_tb; /* Total accumilated purr for process */
5aae8a53 P	209	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	210	struct perf_event *ptrace_bps[HBP_NUM];
	211	/*
	212	* Helps identify source of single-step exception and subsequent
	213	* hw-breakpoint enablement
	214	*/
	215	struct perf_event *last_hit_ubp;
	216	#endif /* CONFIG_HAVE_HW_BREAKPOINT */
9f04b9e3 PM	217	#endif
9f04b9e3 PM	218	unsigned long dabr; /* Data address breakpoint register */
4474ef05	219	unsigned long dabrx; /* ... extension */
41ab5266	220	unsigned long trap_nr; /* last trap # on this thread */
1da177e4 LT	221	#ifdef CONFIG_ALTIVEC
1da177e4 LT	222	/* Complete AltiVec register set */
fc624eae	223	vector128 vr[32] __attribute__((aligned(16)));
1da177e4	224	/* AltiVec status */
fc624eae	225	vector128 vscr __attribute__((aligned(16)));
1da177e4 LT	226	unsigned long vrsave;
	227	int used_vr; /* set if process has used altivec */
	228	#endif /* CONFIG_ALTIVEC */
c6e6771b MN	229	#ifdef CONFIG_VSX
	230	/* VSR status */
	231	int used_vsr; /* set if process has used altivec */
	232	#endif /* CONFIG_VSX */
1da177e4 LT	233	#ifdef CONFIG_SPE
	234	unsigned long evr[32]; /* upper 32-bits of SPE regs */
	235	u64 acc; /* Accumulator */
	236	unsigned long spefscr; /* SPE & eFP status */
	237	int used_spe; /* set if process has used spe */
	238	#endif /* CONFIG_SPE */
97e49255 AG	239	#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
	240	void* kvm_shadow_vcpu; /* KVM internal data */
	241	#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
d30f6e48 SW	242	#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
	243	struct kvm_vcpu *kvm_vcpu;
	244	#endif
efcac658 AK	245	#ifdef CONFIG_PPC64
	246	unsigned long dscr;
	247	int dscr_inherit;
	248	#endif
1da177e4 LT	249	};
	250
	251	#define ARCH_MIN_TASKALIGN 16
	252
	253	#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
85218827 KG	254	#define INIT_SP_LIMIT \
85218827 KG	255	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
1da177e4	256
6a800f36 LY	257	#ifdef CONFIG_SPE
	258	#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE \| SPEFSCR_FDBZE \| SPEFSCR_FUNFE \| SPEFSCR_FOVFE,
	259	#else
	260	#define SPEFSCR_INIT
	261	#endif
9f04b9e3 PM	262
9f04b9e3 PM	263	#ifdef CONFIG_PPC32
1da177e4 LT	264	#define INIT_THREAD { \
1da177e4 LT	265	.ksp = INIT_SP, \
85218827	266	.ksp_limit = INIT_SP_LIMIT, \
1da177e4 LT	267	.fs = KERNEL_DS, \
	268	.pgdir = swapper_pg_dir, \
	269	.fpexc_mode = MSR_FE0 \| MSR_FE1, \
6a800f36	270	SPEFSCR_INIT \
1da177e4	271	}
9f04b9e3 PM	272	#else
	273	#define INIT_THREAD { \
	274	.ksp = INIT_SP, \
85218827	275	.ksp_limit = INIT_SP_LIMIT, \
9f04b9e3 PM	276	.regs = (struct pt_regs )INIT_SP - 1, / XXX bogus, I think */ \
9f04b9e3 PM	277	.fs = KERNEL_DS, \
e17a2565	278	.fpr = {{0}}, \
25c8a78b	279	.fpscr = { .val = 0, }, \
ddf5f75a	280	.fpexc_mode = 0, \
9f04b9e3 PM	281	}
9f04b9e3 PM	282	#endif
1da177e4 LT	283
	284	/*
	285	* Return saved PC of a blocked thread. For now, this is the "user" PC
	286	*/
9f04b9e3 PM	287	#define thread_saved_pc(tsk) \
9f04b9e3 PM	288	((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
1da177e4	289
e5093ff0 SD	290	#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
e5093ff0 SD	291
1da177e4 LT	292	unsigned long get_wchan(struct task_struct *p);
1da177e4 LT	293
9f04b9e3 PM	294	#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
9f04b9e3 PM	295	#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
1da177e4 LT	296
1da177e4 LT	297	/* Get/set floating-point exception mode */
9f04b9e3 PM	298	#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
9f04b9e3 PM	299	#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
1da177e4 LT	300
	301	extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
	302	extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
	303
fab5db97 PM	304	#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
	305	#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
	306
	307	extern int get_endian(struct task_struct *tsk, unsigned long adr);
	308	extern int set_endian(struct task_struct *tsk, unsigned int val);
	309
e9370ae1 PM	310	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	311	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	312
	313	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	314	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	315
9f04b9e3	316	static inline unsigned int __unpack_fe01(unsigned long msr_bits)
1da177e4 LT	317	{
	318	return ((msr_bits & MSR_FE0) >> 10) \| ((msr_bits & MSR_FE1) >> 8);
	319	}
	320
9f04b9e3	321	static inline unsigned long __pack_fe01(unsigned int fpmode)
1da177e4 LT	322	{
	323	return ((fpmode << 10) & MSR_FE0) \| ((fpmode << 8) & MSR_FE1);
	324	}
	325
9f04b9e3 PM	326	#ifdef CONFIG_PPC64
	327	#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
	328	#else
1da177e4	329	#define cpu_relax() barrier()
9f04b9e3	330	#endif
1da177e4	331
2f25194d AB	332	/* Check that a certain kernel stack pointer is valid in task_struct p */
	333	int validate_sp(unsigned long sp, struct task_struct *p,
	334	unsigned long nbytes);
	335
1da177e4 LT	336	/*
	337	* Prefetch macros.
	338	*/
	339	#define ARCH_HAS_PREFETCH
	340	#define ARCH_HAS_PREFETCHW
	341	#define ARCH_HAS_SPINLOCK_PREFETCH
	342
9f04b9e3	343	static inline void prefetch(const void *x)
1da177e4	344	{
9f04b9e3 PM	345	if (unlikely(!x))
	346	return;
	347
	348	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
1da177e4 LT	349	}
1da177e4 LT	350
9f04b9e3	351	static inline void prefetchw(const void *x)
1da177e4	352	{
9f04b9e3 PM	353	if (unlikely(!x))
	354	return;
	355
	356	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
1da177e4 LT	357	}
	358
	359	#define spin_lock_prefetch(x) prefetchw(x)
	360
9f04b9e3 PM	361	#ifdef CONFIG_PPC64
	362	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	363	#endif
1da177e4	364
efbda860 JB	365	#ifdef CONFIG_PPC64
	366	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	367	{
	368	unsigned long sp;
	369
	370	if (is_32)
	371	sp = regs->gpr[1] & 0x0ffffffffUL;
	372	else
	373	sp = regs->gpr[1];
	374
	375	return sp;
	376	}
	377	#else
	378	static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
	379	{
	380	return regs->gpr[1];
	381	}
	382	#endif
	383
e8bb3e00	384	extern unsigned long cpuidle_disable;
771dae81 DD	385	enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
771dae81 DD	386
ae3a197e	387	extern int powersave_nap; /* set if nap mode can be used in idle loop */
375f561a	388	extern void power7_nap(void);
ae3a197e DH	389
ae3a197e DH	390	#ifdef CONFIG_PSERIES_IDLE
8ea959a1	391	extern void update_smt_snooze_delay(int cpu, int residency);
ae3a197e	392	#else
8ea959a1	393	static inline void update_smt_snooze_delay(int cpu, int residency) {}
ae3a197e DH	394	#endif
	395
	396	extern void flush_instruction_cache(void);
	397	extern void hard_reset_now(void);
	398	extern void poweroff_now(void);
	399	extern int fix_alignment(struct pt_regs *);
	400	extern void cvt_fd(float from, double to);
	401	extern void cvt_df(double from, float to);
	402	extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
	403
	404	#ifdef CONFIG_PPC64
	405	/*
	406	* We handle most unaligned accesses in hardware. On the other hand
	407	* unaligned DMA can be very expensive on some ppc64 IO chips (it does
	408	* powers of 2 writes until it reaches sufficient alignment).
	409	*
	410	* Based on this we disable the IP header alignment in network drivers.
	411	*/
	412	#define NET_IP_ALIGN 0
	413	#endif
	414
1da177e4	415	#endif /* __KERNEL__ */
9f04b9e3 PM	416	#endif /* __ASSEMBLY__ */
9f04b9e3 PM	417	#endif /* _ASM_POWERPC_PROCESSOR_H */