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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
d92a208d | 23 | #include <linux/delay.h> |
66b15db6 | 24 | #include <linux/export.h> |
22ae782f | 25 | #include <linux/of_address.h> |
04bea68b | 26 | #include <linux/of_pci.h> |
5516b540 KG |
27 | #include <linux/mm.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/syscalls.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 32 | #include <linux/slab.h> |
c2e1d845 | 33 | #include <linux/vgaarb.h> |
5516b540 KG |
34 | |
35 | #include <asm/processor.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/prom.h> | |
38 | #include <asm/pci-bridge.h> | |
39 | #include <asm/byteorder.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/ppc-pci.h> | |
8b8da358 | 42 | #include <asm/eeh.h> |
5516b540 | 43 | |
63a72284 | 44 | /* hose_spinlock protects accesses to the the phb_bitmap. */ |
a4c9e328 | 45 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 46 | LIST_HEAD(hose_list); |
a4c9e328 | 47 | |
63a72284 GP |
48 | /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ |
49 | #define MAX_PHBS 0x10000 | |
50 | ||
51 | /* | |
52 | * For dynamic PHB numbering: used/free PHBs tracking bitmap. | |
53 | * Accesses to this bitmap should be protected by hose_spinlock. | |
54 | */ | |
55 | static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); | |
a4c9e328 | 56 | |
25e81f92 BH |
57 | /* ISA Memory physical address */ |
58 | resource_size_t isa_mem_base; | |
59 | ||
a4c9e328 | 60 | |
45223c54 | 61 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 62 | |
45223c54 | 63 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
64 | { |
65 | pci_dma_ops = dma_ops; | |
66 | } | |
67 | ||
45223c54 | 68 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
69 | { |
70 | return pci_dma_ops; | |
71 | } | |
72 | EXPORT_SYMBOL(get_pci_dma_ops); | |
73 | ||
63a72284 GP |
74 | /* |
75 | * This function should run under locking protection, specifically | |
76 | * hose_spinlock. | |
77 | */ | |
78 | static int get_phb_number(struct device_node *dn) | |
79 | { | |
80 | int ret, phb_id = -1; | |
61e8a0d5 | 81 | u32 prop_32; |
63a72284 GP |
82 | u64 prop; |
83 | ||
84 | /* | |
85 | * Try fixed PHB numbering first, by checking archs and reading | |
86 | * the respective device-tree properties. Firstly, try powernv by | |
87 | * reading "ibm,opal-phbid", only present in OPAL environment. | |
88 | */ | |
89 | ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); | |
61e8a0d5 ME |
90 | if (ret) { |
91 | ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); | |
92 | prop = prop_32; | |
93 | } | |
63a72284 GP |
94 | |
95 | if (!ret) | |
96 | phb_id = (int)(prop & (MAX_PHBS - 1)); | |
97 | ||
98 | /* We need to be sure to not use the same PHB number twice. */ | |
99 | if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) | |
100 | return phb_id; | |
101 | ||
102 | /* | |
103 | * If not pseries nor powernv, or if fixed PHB numbering tried to add | |
104 | * the same PHB number twice, then fallback to dynamic PHB numbering. | |
105 | */ | |
106 | phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); | |
107 | BUG_ON(phb_id >= MAX_PHBS); | |
108 | set_bit(phb_id, phb_bitmap); | |
109 | ||
110 | return phb_id; | |
111 | } | |
112 | ||
e60516e3 | 113 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
114 | { |
115 | struct pci_controller *phb; | |
116 | ||
e60516e3 | 117 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
118 | if (phb == NULL) |
119 | return NULL; | |
e60516e3 | 120 | spin_lock(&hose_spinlock); |
63a72284 | 121 | phb->global_number = get_phb_number(dev); |
e60516e3 SR |
122 | list_add_tail(&phb->list_node, &hose_list); |
123 | spin_unlock(&hose_spinlock); | |
44ef3390 | 124 | phb->dn = dev; |
f691fa10 | 125 | phb->is_dynamic = slab_is_available(); |
a4c9e328 KG |
126 | #ifdef CONFIG_PPC64 |
127 | if (dev) { | |
128 | int nid = of_node_to_nid(dev); | |
129 | ||
130 | if (nid < 0 || !node_online(nid)) | |
131 | nid = -1; | |
132 | ||
133 | PHB_SET_NODE(phb, nid); | |
134 | } | |
135 | #endif | |
136 | return phb; | |
137 | } | |
5b64d2cc | 138 | EXPORT_SYMBOL_GPL(pcibios_alloc_controller); |
a4c9e328 KG |
139 | |
140 | void pcibios_free_controller(struct pci_controller *phb) | |
141 | { | |
142 | spin_lock(&hose_spinlock); | |
63a72284 GP |
143 | |
144 | /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ | |
145 | if (phb->global_number < MAX_PHBS) | |
146 | clear_bit(phb->global_number, phb_bitmap); | |
147 | ||
a4c9e328 KG |
148 | list_del(&phb->list_node); |
149 | spin_unlock(&hose_spinlock); | |
150 | ||
151 | if (phb->is_dynamic) | |
152 | kfree(phb); | |
153 | } | |
6b8b252f | 154 | EXPORT_SYMBOL_GPL(pcibios_free_controller); |
a4c9e328 | 155 | |
2dd9c11b MFO |
156 | /* |
157 | * This function is used to call pcibios_free_controller() | |
158 | * in a deferred manner: a callback from the PCI subsystem. | |
159 | * | |
160 | * _*DO NOT*_ call pcibios_free_controller() explicitly if | |
161 | * this is used (or it may access an invalid *phb pointer). | |
162 | * | |
163 | * The callback occurs when all references to the root bus | |
164 | * are dropped (e.g., child buses/devices and their users). | |
165 | * | |
166 | * It's called as .release_fn() of 'struct pci_host_bridge' | |
167 | * which is associated with the 'struct pci_controller.bus' | |
168 | * (root bus) - it expects .release_data to hold a pointer | |
169 | * to 'struct pci_controller'. | |
170 | * | |
171 | * In order to use it, register .release_fn()/release_data | |
172 | * like this: | |
173 | * | |
174 | * pci_set_host_bridge_release(bridge, | |
175 | * pcibios_free_controller_deferred | |
176 | * (void *) phb); | |
177 | * | |
178 | * e.g. in the pcibios_root_bridge_prepare() callback from | |
179 | * pci_create_root_bus(). | |
180 | */ | |
181 | void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) | |
182 | { | |
183 | struct pci_controller *phb = (struct pci_controller *) | |
184 | bridge->release_data; | |
185 | ||
186 | pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); | |
187 | ||
188 | pcibios_free_controller(phb); | |
189 | } | |
190 | EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); | |
191 | ||
4c2245bb GS |
192 | /* |
193 | * The function is used to return the minimal alignment | |
194 | * for memory or I/O windows of the associated P2P bridge. | |
195 | * By default, 4KiB alignment for I/O windows and 1MiB for | |
196 | * memory windows. | |
197 | */ | |
198 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, | |
199 | unsigned long type) | |
200 | { | |
467efc2e DA |
201 | struct pci_controller *phb = pci_bus_to_host(bus); |
202 | ||
203 | if (phb->controller_ops.window_alignment) | |
204 | return phb->controller_ops.window_alignment(bus, type); | |
205 | ||
206 | /* | |
207 | * PCI core will figure out the default | |
208 | * alignment: 4KiB for I/O and 1MiB for | |
209 | * memory window. | |
210 | */ | |
211 | return 1; | |
4c2245bb GS |
212 | } |
213 | ||
c5fcb29a GS |
214 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) |
215 | { | |
216 | struct pci_controller *hose = pci_bus_to_host(bus); | |
217 | ||
218 | if (hose->controller_ops.setup_bridge) | |
219 | hose->controller_ops.setup_bridge(bus, type); | |
220 | } | |
221 | ||
d92a208d GS |
222 | void pcibios_reset_secondary_bus(struct pci_dev *dev) |
223 | { | |
467efc2e DA |
224 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
225 | ||
226 | if (phb->controller_ops.reset_secondary_bus) { | |
227 | phb->controller_ops.reset_secondary_bus(dev); | |
228 | return; | |
229 | } | |
230 | ||
231 | pci_reset_secondary_bus(dev); | |
d92a208d GS |
232 | } |
233 | ||
5350ab3f WY |
234 | #ifdef CONFIG_PCI_IOV |
235 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) | |
236 | { | |
237 | if (ppc_md.pcibios_iov_resource_alignment) | |
238 | return ppc_md.pcibios_iov_resource_alignment(pdev, resno); | |
239 | ||
240 | return pci_iov_resource_size(pdev, resno); | |
241 | } | |
242 | #endif /* CONFIG_PCI_IOV */ | |
243 | ||
c3bd517d MM |
244 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
245 | { | |
246 | #ifdef CONFIG_PPC64 | |
247 | return hose->pci_io_size; | |
248 | #else | |
28f65c11 | 249 | return resource_size(&hose->io_resource); |
c3bd517d MM |
250 | #endif |
251 | } | |
252 | ||
6dfbde20 BH |
253 | int pcibios_vaddr_is_ioport(void __iomem *address) |
254 | { | |
255 | int ret = 0; | |
256 | struct pci_controller *hose; | |
c3bd517d | 257 | resource_size_t size; |
6dfbde20 BH |
258 | |
259 | spin_lock(&hose_spinlock); | |
260 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 261 | size = pcibios_io_size(hose); |
6dfbde20 BH |
262 | if (address >= hose->io_base_virt && |
263 | address < (hose->io_base_virt + size)) { | |
264 | ret = 1; | |
265 | break; | |
266 | } | |
267 | } | |
268 | spin_unlock(&hose_spinlock); | |
269 | return ret; | |
270 | } | |
271 | ||
c3bd517d MM |
272 | unsigned long pci_address_to_pio(phys_addr_t address) |
273 | { | |
274 | struct pci_controller *hose; | |
275 | resource_size_t size; | |
276 | unsigned long ret = ~0; | |
277 | ||
278 | spin_lock(&hose_spinlock); | |
279 | list_for_each_entry(hose, &hose_list, list_node) { | |
280 | size = pcibios_io_size(hose); | |
281 | if (address >= hose->io_base_phys && | |
282 | address < (hose->io_base_phys + size)) { | |
283 | unsigned long base = | |
284 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
285 | ret = base + (address - hose->io_base_phys); | |
286 | break; | |
287 | } | |
288 | } | |
289 | spin_unlock(&hose_spinlock); | |
290 | ||
291 | return ret; | |
292 | } | |
293 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
294 | ||
5516b540 KG |
295 | /* |
296 | * Return the domain number for this bus. | |
297 | */ | |
298 | int pci_domain_nr(struct pci_bus *bus) | |
299 | { | |
6207e816 | 300 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 301 | |
6207e816 | 302 | return hose->global_number; |
5516b540 | 303 | } |
5516b540 | 304 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 305 | |
a4c9e328 KG |
306 | /* This routine is meant to be used early during boot, when the |
307 | * PCI bus numbers have not yet been assigned, and you need to | |
308 | * issue PCI config cycles to an OF device. | |
309 | * It could also be used to "fix" RTAS config cycles if you want | |
310 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
311 | * config cycles. | |
312 | */ | |
313 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
314 | { | |
a4c9e328 KG |
315 | while(node) { |
316 | struct pci_controller *hose, *tmp; | |
317 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 318 | if (hose->dn == node) |
a4c9e328 KG |
319 | return hose; |
320 | node = node->parent; | |
321 | } | |
322 | return NULL; | |
323 | } | |
324 | ||
58083dad KG |
325 | /* |
326 | * Reads the interrupt pin to determine if interrupt is use by card. | |
327 | * If the interrupt is used, then gets the interrupt line from the | |
328 | * openfirmware and sets it in the pci_dev and pci_config line. | |
329 | */ | |
4666ca2a | 330 | static int pci_read_irq_line(struct pci_dev *pci_dev) |
58083dad | 331 | { |
530210c7 | 332 | struct of_phandle_args oirq; |
58083dad KG |
333 | unsigned int virq; |
334 | ||
b0494bc8 | 335 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
336 | |
337 | #ifdef DEBUG | |
338 | memset(&oirq, 0xff, sizeof(oirq)); | |
339 | #endif | |
340 | /* Try to get a mapping from the device-tree */ | |
0c02c800 | 341 | if (of_irq_parse_pci(pci_dev, &oirq)) { |
58083dad KG |
342 | u8 line, pin; |
343 | ||
344 | /* If that fails, lets fallback to what is in the config | |
345 | * space and map that through the default controller. We | |
346 | * also set the type to level low since that's what PCI | |
347 | * interrupts are. If your platform does differently, then | |
348 | * either provide a proper interrupt tree or don't use this | |
349 | * function. | |
350 | */ | |
351 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
352 | return -1; | |
353 | if (pin == 0) | |
354 | return -1; | |
355 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 356 | line == 0xff || line == 0) { |
58083dad KG |
357 | return -1; |
358 | } | |
b0494bc8 BH |
359 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
360 | line, pin); | |
58083dad KG |
361 | |
362 | virq = irq_create_mapping(NULL, line); | |
363 | if (virq != NO_IRQ) | |
ec775d0e | 364 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 365 | } else { |
b0494bc8 | 366 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
530210c7 GL |
367 | oirq.args_count, oirq.args[0], oirq.args[1], |
368 | of_node_full_name(oirq.np)); | |
58083dad | 369 | |
e6d30ab1 | 370 | virq = irq_create_of_mapping(&oirq); |
58083dad KG |
371 | } |
372 | if(virq == NO_IRQ) { | |
b0494bc8 | 373 | pr_debug(" Failed to map !\n"); |
58083dad KG |
374 | return -1; |
375 | } | |
376 | ||
b0494bc8 | 377 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
378 | |
379 | pci_dev->irq = virq; | |
380 | ||
381 | return 0; | |
382 | } | |
58083dad KG |
383 | |
384 | /* | |
385 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
386 | * modelled on the sparc64 implementation by Dave Miller. | |
387 | * -- paulus. | |
388 | */ | |
389 | ||
390 | /* | |
391 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
392 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
393 | * | |
394 | * Basically, the user finds the base address for his device which he wishes | |
395 | * to mmap. They read the 32-bit value from the config space base register, | |
396 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
397 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
398 | * | |
399 | * Returns negative error code on failure, zero on success. | |
400 | */ | |
401 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
402 | resource_size_t *offset, | |
403 | enum pci_mmap_state mmap_state) | |
404 | { | |
405 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
406 | unsigned long io_offset = 0; | |
407 | int i, res_bit; | |
408 | ||
b0d436c7 | 409 | if (hose == NULL) |
58083dad KG |
410 | return NULL; /* should never happen */ |
411 | ||
412 | /* If memory, add on the PCI bridge address offset */ | |
413 | if (mmap_state == pci_mmap_mem) { | |
414 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
415 | *offset += hose->pci_mem_offset; | |
416 | #endif | |
417 | res_bit = IORESOURCE_MEM; | |
418 | } else { | |
419 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
420 | *offset += io_offset; | |
421 | res_bit = IORESOURCE_IO; | |
422 | } | |
423 | ||
424 | /* | |
425 | * Check that the offset requested corresponds to one of the | |
426 | * resources of the device. | |
427 | */ | |
428 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
429 | struct resource *rp = &dev->resource[i]; | |
430 | int flags = rp->flags; | |
431 | ||
432 | /* treat ROM as memory (should be already) */ | |
433 | if (i == PCI_ROM_RESOURCE) | |
434 | flags |= IORESOURCE_MEM; | |
435 | ||
436 | /* Active and same type? */ | |
437 | if ((flags & res_bit) == 0) | |
438 | continue; | |
439 | ||
440 | /* In the range of this resource? */ | |
441 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
442 | continue; | |
443 | ||
444 | /* found it! construct the final physical address */ | |
445 | if (mmap_state == pci_mmap_io) | |
446 | *offset += hose->io_base_phys - io_offset; | |
447 | return rp; | |
448 | } | |
449 | ||
450 | return NULL; | |
451 | } | |
452 | ||
58083dad KG |
453 | /* |
454 | * This one is used by /dev/mem and fbdev who have no clue about the | |
455 | * PCI device, it tries to find the PCI device first and calls the | |
456 | * above routine | |
457 | */ | |
458 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
459 | unsigned long pfn, | |
460 | unsigned long size, | |
64b3d0e8 | 461 | pgprot_t prot) |
58083dad KG |
462 | { |
463 | struct pci_dev *pdev = NULL; | |
464 | struct resource *found = NULL; | |
7c12d906 | 465 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
466 | int i; |
467 | ||
468 | if (page_is_ram(pfn)) | |
64b3d0e8 | 469 | return prot; |
58083dad | 470 | |
64b3d0e8 | 471 | prot = pgprot_noncached(prot); |
58083dad KG |
472 | for_each_pci_dev(pdev) { |
473 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
474 | struct resource *rp = &pdev->resource[i]; | |
475 | int flags = rp->flags; | |
476 | ||
477 | /* Active and same type? */ | |
478 | if ((flags & IORESOURCE_MEM) == 0) | |
479 | continue; | |
480 | /* In the range of this resource? */ | |
481 | if (offset < (rp->start & PAGE_MASK) || | |
482 | offset > rp->end) | |
483 | continue; | |
484 | found = rp; | |
485 | break; | |
486 | } | |
487 | if (found) | |
488 | break; | |
489 | } | |
490 | if (found) { | |
491 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 492 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
493 | pci_dev_put(pdev); |
494 | } | |
495 | ||
b0494bc8 | 496 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 497 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 498 | |
64b3d0e8 | 499 | return prot; |
58083dad KG |
500 | } |
501 | ||
502 | ||
503 | /* | |
504 | * Perform the actual remap of the pages for a PCI device mapping, as | |
505 | * appropriate for this architecture. The region in the process to map | |
506 | * is described by vm_start and vm_end members of VMA, the base physical | |
507 | * address is found in vm_pgoff. | |
508 | * The pci device structure is provided so that architectures may make mapping | |
509 | * decisions on a per-device or per-bus basis. | |
510 | * | |
511 | * Returns a negative error code on failure, zero on success. | |
512 | */ | |
513 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
514 | enum pci_mmap_state mmap_state, int write_combine) | |
515 | { | |
7c12d906 BH |
516 | resource_size_t offset = |
517 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
518 | struct resource *rp; |
519 | int ret; | |
520 | ||
521 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
522 | if (rp == NULL) | |
523 | return -EINVAL; | |
524 | ||
525 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
1e70cdd6 YL |
526 | if (write_combine) |
527 | vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot); | |
528 | else | |
529 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
58083dad KG |
530 | |
531 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
532 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
e9f82cb7 BH |
537 | /* This provides legacy IO read access on a bus */ |
538 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
539 | { | |
540 | unsigned long offset; | |
541 | struct pci_controller *hose = pci_bus_to_host(bus); | |
542 | struct resource *rp = &hose->io_resource; | |
543 | void __iomem *addr; | |
544 | ||
545 | /* Check if port can be supported by that bus. We only check | |
546 | * the ranges of the PHB though, not the bus itself as the rules | |
547 | * for forwarding legacy cycles down bridges are not our problem | |
548 | * here. So if the host bridge supports it, we do it. | |
549 | */ | |
550 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
551 | offset += port; | |
552 | ||
553 | if (!(rp->flags & IORESOURCE_IO)) | |
554 | return -ENXIO; | |
555 | if (offset < rp->start || (offset + size) > rp->end) | |
556 | return -ENXIO; | |
557 | addr = hose->io_base_virt + port; | |
558 | ||
559 | switch(size) { | |
560 | case 1: | |
561 | *((u8 *)val) = in_8(addr); | |
562 | return 1; | |
563 | case 2: | |
564 | if (port & 1) | |
565 | return -EINVAL; | |
566 | *((u16 *)val) = in_le16(addr); | |
567 | return 2; | |
568 | case 4: | |
569 | if (port & 3) | |
570 | return -EINVAL; | |
571 | *((u32 *)val) = in_le32(addr); | |
572 | return 4; | |
573 | } | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | /* This provides legacy IO write access on a bus */ | |
578 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
579 | { | |
580 | unsigned long offset; | |
581 | struct pci_controller *hose = pci_bus_to_host(bus); | |
582 | struct resource *rp = &hose->io_resource; | |
583 | void __iomem *addr; | |
584 | ||
585 | /* Check if port can be supported by that bus. We only check | |
586 | * the ranges of the PHB though, not the bus itself as the rules | |
587 | * for forwarding legacy cycles down bridges are not our problem | |
588 | * here. So if the host bridge supports it, we do it. | |
589 | */ | |
590 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
591 | offset += port; | |
592 | ||
593 | if (!(rp->flags & IORESOURCE_IO)) | |
594 | return -ENXIO; | |
595 | if (offset < rp->start || (offset + size) > rp->end) | |
596 | return -ENXIO; | |
597 | addr = hose->io_base_virt + port; | |
598 | ||
599 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
600 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
601 | * as a u32, which means that we have to correct the location of | |
602 | * the data read within those 32 bits for size 1 and 2 | |
603 | */ | |
604 | switch(size) { | |
605 | case 1: | |
606 | out_8(addr, val >> 24); | |
607 | return 1; | |
608 | case 2: | |
609 | if (port & 1) | |
610 | return -EINVAL; | |
611 | out_le16(addr, val >> 16); | |
612 | return 2; | |
613 | case 4: | |
614 | if (port & 3) | |
615 | return -EINVAL; | |
616 | out_le32(addr, val); | |
617 | return 4; | |
618 | } | |
619 | return -EINVAL; | |
620 | } | |
621 | ||
622 | /* This provides legacy IO or memory mmap access on a bus */ | |
623 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
624 | struct vm_area_struct *vma, | |
625 | enum pci_mmap_state mmap_state) | |
626 | { | |
627 | struct pci_controller *hose = pci_bus_to_host(bus); | |
628 | resource_size_t offset = | |
629 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
630 | resource_size_t size = vma->vm_end - vma->vm_start; | |
631 | struct resource *rp; | |
632 | ||
633 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
634 | pci_domain_nr(bus), bus->number, | |
635 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
636 | (unsigned long long)offset, | |
637 | (unsigned long long)(offset + size - 1)); | |
638 | ||
639 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
640 | /* Hack alert ! |
641 | * | |
642 | * Because X is lame and can fail starting if it gets an error trying | |
643 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
644 | * access) we fake it here by giving it anonymous memory, effectively | |
645 | * behaving just like /dev/zero | |
646 | */ | |
647 | if ((offset + size) > hose->isa_mem_size) { | |
648 | printk(KERN_DEBUG | |
649 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
650 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
651 | if (vma->vm_flags & VM_SHARED) | |
652 | return shmem_zero_setup(vma); | |
653 | return 0; | |
654 | } | |
e9f82cb7 BH |
655 | offset += hose->isa_mem_phys; |
656 | } else { | |
657 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
658 | unsigned long roffset = offset + io_offset; | |
659 | rp = &hose->io_resource; | |
660 | if (!(rp->flags & IORESOURCE_IO)) | |
661 | return -ENXIO; | |
662 | if (roffset < rp->start || (roffset + size) > rp->end) | |
663 | return -ENXIO; | |
664 | offset += hose->io_base_phys; | |
665 | } | |
666 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
667 | ||
668 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 669 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
670 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
671 | vma->vm_end - vma->vm_start, | |
672 | vma->vm_page_prot); | |
673 | } | |
674 | ||
58083dad KG |
675 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
676 | const struct resource *rsrc, | |
677 | resource_size_t *start, resource_size_t *end) | |
678 | { | |
38301358 | 679 | struct pci_bus_region region; |
58083dad | 680 | |
38301358 BH |
681 | if (rsrc->flags & IORESOURCE_IO) { |
682 | pcibios_resource_to_bus(dev->bus, ®ion, | |
683 | (struct resource *) rsrc); | |
684 | *start = region.start; | |
685 | *end = region.end; | |
58083dad | 686 | return; |
38301358 | 687 | } |
58083dad | 688 | |
38301358 BH |
689 | /* We pass a CPU physical address to userland for MMIO instead of a |
690 | * BAR value because X is lame and expects to be able to use that | |
691 | * to pass to /dev/mem! | |
58083dad | 692 | * |
38301358 BH |
693 | * That means we may have 64-bit values where some apps only expect |
694 | * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). | |
58083dad | 695 | */ |
38301358 BH |
696 | *start = rsrc->start; |
697 | *end = rsrc->end; | |
58083dad | 698 | } |
13dccb9e BH |
699 | |
700 | /** | |
701 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
702 | * @hose: newly allocated pci_controller to be setup | |
703 | * @dev: device node of the host bridge | |
704 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
705 | * | |
706 | * This function will parse the "ranges" property of a PCI host bridge device | |
707 | * node and setup the resource mapping of a pci controller based on its | |
708 | * content. | |
709 | * | |
710 | * Life would be boring if it wasn't for a few issues that we have to deal | |
711 | * with here: | |
712 | * | |
713 | * - We can only cope with one IO space range and up to 3 Memory space | |
714 | * ranges. However, some machines (thanks Apple !) tend to split their | |
715 | * space into lots of small contiguous ranges. So we have to coalesce. | |
716 | * | |
13dccb9e BH |
717 | * - Some busses have IO space not starting at 0, which causes trouble with |
718 | * the way we do our IO resource renumbering. The code somewhat deals with | |
719 | * it for 64 bits but I would expect problems on 32 bits. | |
720 | * | |
721 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
722 | * 32 bits so we need to use 64 bits values for the parsing | |
723 | */ | |
cad5cef6 GKH |
724 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
725 | struct device_node *dev, int primary) | |
13dccb9e | 726 | { |
858957ab | 727 | int memno = 0; |
13dccb9e | 728 | struct resource *res; |
654837e8 AM |
729 | struct of_pci_range range; |
730 | struct of_pci_range_parser parser; | |
13dccb9e BH |
731 | |
732 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
733 | dev->full_name, primary ? "(primary)" : ""); | |
734 | ||
654837e8 AM |
735 | /* Check for ranges property */ |
736 | if (of_pci_range_parser_init(&parser, dev)) | |
13dccb9e BH |
737 | return; |
738 | ||
739 | /* Parse it */ | |
654837e8 | 740 | for_each_of_pci_range(&parser, &range) { |
e9f82cb7 BH |
741 | /* If we failed translation or got a zero-sized region |
742 | * (some FW try to feed us with non sensical zero sized regions | |
743 | * such as power3 which look like some kind of attempt at exposing | |
744 | * the VGA memory hole) | |
745 | */ | |
654837e8 | 746 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
13dccb9e BH |
747 | continue; |
748 | ||
13dccb9e BH |
749 | /* Act based on address space type */ |
750 | res = NULL; | |
654837e8 AM |
751 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
752 | case IORESOURCE_IO: | |
13dccb9e BH |
753 | printk(KERN_INFO |
754 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
654837e8 AM |
755 | range.cpu_addr, range.cpu_addr + range.size - 1, |
756 | range.pci_addr); | |
13dccb9e BH |
757 | |
758 | /* We support only one IO range */ | |
759 | if (hose->pci_io_size) { | |
760 | printk(KERN_INFO | |
761 | " \\--> Skipped (too many) !\n"); | |
762 | continue; | |
763 | } | |
764 | #ifdef CONFIG_PPC32 | |
765 | /* On 32 bits, limit I/O space to 16MB */ | |
654837e8 AM |
766 | if (range.size > 0x01000000) |
767 | range.size = 0x01000000; | |
13dccb9e BH |
768 | |
769 | /* 32 bits needs to map IOs here */ | |
654837e8 AM |
770 | hose->io_base_virt = ioremap(range.cpu_addr, |
771 | range.size); | |
13dccb9e BH |
772 | |
773 | /* Expect trouble if pci_addr is not 0 */ | |
774 | if (primary) | |
775 | isa_io_base = | |
776 | (unsigned long)hose->io_base_virt; | |
777 | #endif /* CONFIG_PPC32 */ | |
778 | /* pci_io_size and io_base_phys always represent IO | |
779 | * space starting at 0 so we factor in pci_addr | |
780 | */ | |
654837e8 AM |
781 | hose->pci_io_size = range.pci_addr + range.size; |
782 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
13dccb9e BH |
783 | |
784 | /* Build resource */ | |
785 | res = &hose->io_resource; | |
654837e8 | 786 | range.cpu_addr = range.pci_addr; |
13dccb9e | 787 | break; |
654837e8 | 788 | case IORESOURCE_MEM: |
13dccb9e BH |
789 | printk(KERN_INFO |
790 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
654837e8 AM |
791 | range.cpu_addr, range.cpu_addr + range.size - 1, |
792 | range.pci_addr, | |
793 | (range.pci_space & 0x40000000) ? | |
794 | "Prefetch" : ""); | |
13dccb9e BH |
795 | |
796 | /* We support only 3 memory ranges */ | |
797 | if (memno >= 3) { | |
798 | printk(KERN_INFO | |
799 | " \\--> Skipped (too many) !\n"); | |
800 | continue; | |
801 | } | |
802 | /* Handles ISA memory hole space here */ | |
654837e8 | 803 | if (range.pci_addr == 0) { |
13dccb9e | 804 | if (primary || isa_mem_base == 0) |
654837e8 AM |
805 | isa_mem_base = range.cpu_addr; |
806 | hose->isa_mem_phys = range.cpu_addr; | |
807 | hose->isa_mem_size = range.size; | |
13dccb9e BH |
808 | } |
809 | ||
13dccb9e | 810 | /* Build resource */ |
654837e8 AM |
811 | hose->mem_offset[memno] = range.cpu_addr - |
812 | range.pci_addr; | |
13dccb9e | 813 | res = &hose->mem_resources[memno++]; |
13dccb9e BH |
814 | break; |
815 | } | |
816 | if (res != NULL) { | |
aeba3731 ME |
817 | res->name = dev->full_name; |
818 | res->flags = range.flags; | |
819 | res->start = range.cpu_addr; | |
820 | res->end = range.cpu_addr + range.size - 1; | |
821 | res->parent = res->child = res->sibling = NULL; | |
13dccb9e BH |
822 | } |
823 | } | |
13dccb9e | 824 | } |
fa462f2d BH |
825 | |
826 | /* Decide whether to display the domain number in /proc */ | |
827 | int pci_proc_domain(struct pci_bus *bus) | |
828 | { | |
829 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 830 | |
0e47ff1c | 831 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 832 | return 0; |
0e47ff1c | 833 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
834 | return hose->global_number != 0; |
835 | return 1; | |
fa462f2d BH |
836 | } |
837 | ||
d82fb31a KSS |
838 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
839 | { | |
840 | if (ppc_md.pcibios_root_bridge_prepare) | |
841 | return ppc_md.pcibios_root_bridge_prepare(bridge); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
bf5e2ba2 BH |
846 | /* This header fixup will do the resource fixup for all devices as they are |
847 | * probed, but not for bridge ranges | |
848 | */ | |
cad5cef6 | 849 | static void pcibios_fixup_resources(struct pci_dev *dev) |
bf5e2ba2 BH |
850 | { |
851 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
852 | int i; | |
853 | ||
854 | if (!hose) { | |
855 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
856 | pci_name(dev)); | |
857 | return; | |
858 | } | |
c3b80fb0 WY |
859 | |
860 | if (dev->is_virtfn) | |
861 | return; | |
862 | ||
bf5e2ba2 BH |
863 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
864 | struct resource *res = dev->resource + i; | |
c5df457f | 865 | struct pci_bus_region reg; |
bf5e2ba2 BH |
866 | if (!res->flags) |
867 | continue; | |
48c2ce97 BH |
868 | |
869 | /* If we're going to re-assign everything, we mark all resources | |
870 | * as unset (and 0-base them). In addition, we mark BARs starting | |
871 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | |
872 | * since in that case, we don't want to re-assign anything | |
7f172890 | 873 | */ |
fc279850 | 874 | pcibios_resource_to_bus(dev->bus, ®, res); |
48c2ce97 | 875 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
c5df457f | 876 | (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { |
48c2ce97 BH |
877 | /* Only print message if not re-assigning */ |
878 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | |
ae2a84b4 KH |
879 | pr_debug("PCI:%s Resource %d %pR is unassigned\n", |
880 | pci_name(dev), i, res); | |
bf5e2ba2 BH |
881 | res->end -= res->start; |
882 | res->start = 0; | |
883 | res->flags |= IORESOURCE_UNSET; | |
884 | continue; | |
885 | } | |
886 | ||
ae2a84b4 | 887 | pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 BH |
888 | } |
889 | ||
890 | /* Call machine specific resource fixup */ | |
891 | if (ppc_md.pcibios_fixup_resources) | |
892 | ppc_md.pcibios_fixup_resources(dev); | |
893 | } | |
894 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
895 | ||
b5561511 BH |
896 | /* This function tries to figure out if a bridge resource has been initialized |
897 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
898 | * things go more smoothly when it gets it right. It should covers cases such | |
899 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
900 | */ | |
cad5cef6 GKH |
901 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
902 | struct resource *res) | |
bf5e2ba2 | 903 | { |
be8cbcd8 | 904 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 905 | struct pci_dev *dev = bus->self; |
b5561511 | 906 | resource_size_t offset; |
3fd47f06 | 907 | struct pci_bus_region region; |
b5561511 BH |
908 | u16 command; |
909 | int i; | |
bf5e2ba2 | 910 | |
b5561511 | 911 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 912 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 913 | return 0; |
bf5e2ba2 | 914 | |
b5561511 BH |
915 | /* Job is a bit different between memory and IO */ |
916 | if (res->flags & IORESOURCE_MEM) { | |
fc279850 | 917 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
3fd47f06 BH |
918 | |
919 | /* If the BAR is non-0 then it's probably been initialized */ | |
920 | if (region.start != 0) | |
b5561511 | 921 | return 0; |
bf5e2ba2 | 922 | |
b5561511 BH |
923 | /* The BAR is 0, let's check if memory decoding is enabled on |
924 | * the bridge. If not, we consider it unassigned | |
925 | */ | |
926 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
927 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
928 | return 1; | |
be8cbcd8 | 929 | |
b5561511 BH |
930 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
931 | * resources covers that starting address (0 then it's good enough for | |
3fd47f06 | 932 | * us for memory space) |
b5561511 BH |
933 | */ |
934 | for (i = 0; i < 3; i++) { | |
935 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
3fd47f06 | 936 | hose->mem_resources[i].start == hose->mem_offset[i]) |
b5561511 BH |
937 | return 0; |
938 | } | |
939 | ||
940 | /* Well, it starts at 0 and we know it will collide so we may as | |
941 | * well consider it as unassigned. That covers the Apple case. | |
942 | */ | |
943 | return 1; | |
944 | } else { | |
945 | /* If the BAR is non-0, then we consider it assigned */ | |
946 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
947 | if (((res->start - offset) & 0xfffffffful) != 0) | |
948 | return 0; | |
949 | ||
950 | /* Here, we are a bit different than memory as typically IO space | |
951 | * starting at low addresses -is- valid. What we do instead if that | |
952 | * we consider as unassigned anything that doesn't have IO enabled | |
953 | * in the PCI command register, and that's it. | |
954 | */ | |
955 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
956 | if (command & PCI_COMMAND_IO) | |
957 | return 0; | |
958 | ||
959 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
960 | * it unassigned | |
961 | */ | |
962 | return 1; | |
963 | } | |
964 | } | |
965 | ||
966 | /* Fixup resources of a PCI<->PCI bridge */ | |
cad5cef6 | 967 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
b5561511 BH |
968 | { |
969 | struct resource *res; | |
970 | int i; | |
971 | ||
972 | struct pci_dev *dev = bus->self; | |
973 | ||
89a74ecc BH |
974 | pci_bus_for_each_resource(bus, res, i) { |
975 | if (!res || !res->flags) | |
b5561511 BH |
976 | continue; |
977 | if (i >= 3 && bus->self->transparent) | |
978 | continue; | |
979 | ||
cf1a4cf8 GS |
980 | /* If we're going to reassign everything, we can |
981 | * shrink the P2P resource to have size as being | |
982 | * of 0 in order to save space. | |
48c2ce97 BH |
983 | */ |
984 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { | |
985 | res->flags |= IORESOURCE_UNSET; | |
48c2ce97 | 986 | res->start = 0; |
cf1a4cf8 | 987 | res->end = -1; |
48c2ce97 BH |
988 | continue; |
989 | } | |
990 | ||
ae2a84b4 | 991 | pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 | 992 | |
b5561511 BH |
993 | /* Try to detect uninitialized P2P bridge resources, |
994 | * and clear them out so they get re-assigned later | |
995 | */ | |
996 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
997 | res->flags = 0; | |
998 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
bf5e2ba2 BH |
999 | } |
1000 | } | |
b5561511 BH |
1001 | } |
1002 | ||
cad5cef6 | 1003 | void pcibios_setup_bus_self(struct pci_bus *bus) |
8b8da358 | 1004 | { |
467efc2e DA |
1005 | struct pci_controller *phb; |
1006 | ||
7eef440a | 1007 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
1008 | if (bus->self != NULL) |
1009 | pcibios_fixup_bridge(bus); | |
1010 | ||
1011 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 1012 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
1013 | */ |
1014 | if (ppc_md.pcibios_fixup_bus) | |
1015 | ppc_md.pcibios_fixup_bus(bus); | |
1016 | ||
1017 | /* Setup bus DMA mappings */ | |
467efc2e DA |
1018 | phb = pci_bus_to_host(bus); |
1019 | if (phb->controller_ops.dma_bus_setup) | |
1020 | phb->controller_ops.dma_bus_setup(bus); | |
8b8da358 BH |
1021 | } |
1022 | ||
7846de40 | 1023 | static void pcibios_setup_device(struct pci_dev *dev) |
37f02195 | 1024 | { |
467efc2e | 1025 | struct pci_controller *phb; |
37f02195 YC |
1026 | /* Fixup NUMA node as it may not be setup yet by the generic |
1027 | * code and is needed by the DMA init | |
1028 | */ | |
1029 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
1030 | ||
1031 | /* Hook up default DMA ops */ | |
1032 | set_dma_ops(&dev->dev, pci_dma_ops); | |
1033 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); | |
1034 | ||
1035 | /* Additional platform DMA/iommu setup */ | |
467efc2e DA |
1036 | phb = pci_bus_to_host(dev->bus); |
1037 | if (phb->controller_ops.dma_dev_setup) | |
1038 | phb->controller_ops.dma_dev_setup(dev); | |
37f02195 YC |
1039 | |
1040 | /* Read default IRQs and fixup if necessary */ | |
1041 | pci_read_irq_line(dev); | |
1042 | if (ppc_md.pci_irq_fixup) | |
1043 | ppc_md.pci_irq_fixup(dev); | |
1044 | } | |
1045 | ||
7846de40 GR |
1046 | int pcibios_add_device(struct pci_dev *dev) |
1047 | { | |
1048 | /* | |
1049 | * We can only call pcibios_setup_device() after bus setup is complete, | |
1050 | * since some of the platform specific DMA setup code depends on it. | |
1051 | */ | |
1052 | if (dev->bus->is_added) | |
1053 | pcibios_setup_device(dev); | |
6e628c7d WY |
1054 | |
1055 | #ifdef CONFIG_PCI_IOV | |
1056 | if (ppc_md.pcibios_fixup_sriov) | |
1057 | ppc_md.pcibios_fixup_sriov(dev); | |
1058 | #endif /* CONFIG_PCI_IOV */ | |
1059 | ||
7846de40 GR |
1060 | return 0; |
1061 | } | |
1062 | ||
cad5cef6 | 1063 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
7eef440a BH |
1064 | { |
1065 | struct pci_dev *dev; | |
1066 | ||
1067 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1068 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1069 | ||
1070 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1071 | /* Cardbus can call us to add new devices to a bus, so ignore |
1072 | * those who are already fully discovered | |
1073 | */ | |
1074 | if (dev->is_added) | |
1075 | continue; | |
1076 | ||
37f02195 | 1077 | pcibios_setup_device(dev); |
7eef440a BH |
1078 | } |
1079 | } | |
1080 | ||
79c8be83 MS |
1081 | void pcibios_set_master(struct pci_dev *dev) |
1082 | { | |
1083 | /* No special bus mastering setup handling */ | |
1084 | } | |
1085 | ||
cad5cef6 | 1086 | void pcibios_fixup_bus(struct pci_bus *bus) |
bf5e2ba2 | 1087 | { |
237865f1 BH |
1088 | /* When called from the generic PCI probe, read PCI<->PCI bridge |
1089 | * bases. This is -not- called when generating the PCI tree from | |
1090 | * the OF device-tree. | |
1091 | */ | |
1092 | pci_read_bridge_bases(bus); | |
1093 | ||
1094 | /* Now fixup the bus bus */ | |
8b8da358 BH |
1095 | pcibios_setup_bus_self(bus); |
1096 | ||
1097 | /* Now fixup devices on that bus */ | |
1098 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1099 | } |
8b8da358 | 1100 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1101 | |
cad5cef6 | 1102 | void pci_fixup_cardbus(struct pci_bus *bus) |
2d1c8618 BH |
1103 | { |
1104 | /* Now fixup devices on that bus */ | |
1105 | pcibios_setup_bus_devices(bus); | |
1106 | } | |
1107 | ||
1108 | ||
3fd94c6b BH |
1109 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1110 | { | |
0e47ff1c | 1111 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1112 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1113 | return 1; | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | /* | |
1118 | * We need to avoid collisions with `mirrored' VGA ports | |
1119 | * and other strange ISA hardware, so we always want the | |
1120 | * addresses to be allocated in the 0x000-0x0ff region | |
1121 | * modulo 0x400. | |
1122 | * | |
1123 | * Why? Because some silly external IO cards only decode | |
1124 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1125 | * is reserved for motherboard devices that decode all 16 | |
1126 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1127 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1128 | * which might have be mirrored at 0x0100-0x03ff.. | |
1129 | */ | |
3b7a17fc | 1130 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1131 | resource_size_t size, resource_size_t align) |
1132 | { | |
1133 | struct pci_dev *dev = data; | |
b26b2d49 | 1134 | resource_size_t start = res->start; |
3fd94c6b BH |
1135 | |
1136 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1137 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1138 | return start; |
1139 | if (start & 0x300) | |
3fd94c6b | 1140 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1141 | } |
b26b2d49 DB |
1142 | |
1143 | return start; | |
3fd94c6b BH |
1144 | } |
1145 | EXPORT_SYMBOL(pcibios_align_resource); | |
1146 | ||
1147 | /* | |
1148 | * Reparent resource children of pr that conflict with res | |
1149 | * under res, and make res replace those children. | |
1150 | */ | |
0f6023d5 | 1151 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1152 | struct resource *res) |
1153 | { | |
1154 | struct resource *p, **pp; | |
1155 | struct resource **firstpp = NULL; | |
1156 | ||
1157 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1158 | if (p->end < res->start) | |
1159 | continue; | |
1160 | if (res->end < p->start) | |
1161 | break; | |
1162 | if (p->start < res->start || p->end > res->end) | |
1163 | return -1; /* not completely contained */ | |
1164 | if (firstpp == NULL) | |
1165 | firstpp = pp; | |
1166 | } | |
1167 | if (firstpp == NULL) | |
1168 | return -1; /* didn't find any conflicting entries? */ | |
1169 | res->parent = parent; | |
1170 | res->child = *firstpp; | |
1171 | res->sibling = *pp; | |
1172 | *firstpp = res; | |
1173 | *pp = NULL; | |
1174 | for (p = res->child; p != NULL; p = p->sibling) { | |
1175 | p->parent = res; | |
ae2a84b4 KH |
1176 | pr_debug("PCI: Reparented %s %pR under %s\n", |
1177 | p->name, p, res->name); | |
3fd94c6b BH |
1178 | } |
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* | |
1183 | * Handle resources of PCI devices. If the world were perfect, we could | |
1184 | * just allocate all the resource regions and do nothing more. It isn't. | |
1185 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1186 | * require us to know lots of host bridge internals. So we attempt to | |
1187 | * keep as much of the original configuration as possible, but tweak it | |
1188 | * when it's found to be wrong. | |
1189 | * | |
1190 | * Known BIOS problems we have to work around: | |
1191 | * - I/O or memory regions not configured | |
1192 | * - regions configured, but not enabled in the command register | |
1193 | * - bogus I/O addresses above 64K used | |
1194 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1195 | * the fact the PCI specs explicitly allow address decoders to be | |
1196 | * shared between expansion ROMs and other resource regions, it's | |
1197 | * at least dangerous) | |
1198 | * | |
1199 | * Our solution: | |
1200 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1201 | * This gives us fixed barriers on where we can allocate. | |
1202 | * (2) Allocate resources for all enabled devices. If there is | |
1203 | * a collision, just mark the resource as unallocated. Also | |
1204 | * disable expansion ROMs during this step. | |
1205 | * (3) Try to allocate resources for disabled devices. If the | |
1206 | * resources were assigned correctly, everything goes well, | |
1207 | * if they weren't, they won't disturb allocation of other | |
1208 | * resources. | |
1209 | * (4) Assign new addresses to resources which were either | |
1210 | * not configured at all or misconfigured. If explicitly | |
1211 | * requested by the user, configure expansion ROM address | |
1212 | * as well. | |
1213 | */ | |
1214 | ||
e51df2c1 | 1215 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1216 | { |
e90a1318 | 1217 | struct pci_bus *b; |
3fd94c6b BH |
1218 | int i; |
1219 | struct resource *res, *pr; | |
1220 | ||
b5ae5f91 BH |
1221 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1222 | pci_domain_nr(bus), bus->number); | |
1223 | ||
89a74ecc BH |
1224 | pci_bus_for_each_resource(bus, res, i) { |
1225 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 | 1226 | continue; |
48c2ce97 BH |
1227 | |
1228 | /* If the resource was left unset at this point, we clear it */ | |
1229 | if (res->flags & IORESOURCE_UNSET) | |
1230 | goto clear_resource; | |
1231 | ||
e90a1318 NF |
1232 | if (bus->parent == NULL) |
1233 | pr = (res->flags & IORESOURCE_IO) ? | |
1234 | &ioport_resource : &iomem_resource; | |
1235 | else { | |
e90a1318 NF |
1236 | pr = pci_find_parent_resource(bus->self, res); |
1237 | if (pr == res) { | |
1238 | /* this happens when the generic PCI | |
1239 | * code (wrongly) decides that this | |
1240 | * bridge is transparent -- paulus | |
3fd94c6b | 1241 | */ |
e90a1318 | 1242 | continue; |
3fd94c6b | 1243 | } |
e90a1318 | 1244 | } |
3fd94c6b | 1245 | |
ae2a84b4 KH |
1246 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", |
1247 | bus->self ? pci_name(bus->self) : "PHB", bus->number, | |
1248 | i, res, pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1249 | |
1250 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
3ebfe46a YL |
1251 | struct pci_dev *dev = bus->self; |
1252 | ||
e90a1318 NF |
1253 | if (request_resource(pr, res) == 0) |
1254 | continue; | |
1255 | /* | |
1256 | * Must be a conflict with an existing entry. | |
1257 | * Move that entry (or entries) under the | |
1258 | * bridge resource and try again. | |
1259 | */ | |
1260 | if (reparent_resources(pr, res) == 0) | |
1261 | continue; | |
3ebfe46a YL |
1262 | |
1263 | if (dev && i < PCI_BRIDGE_RESOURCE_NUM && | |
1264 | pci_claim_bridge_resource(dev, | |
1265 | i + PCI_BRIDGE_RESOURCES) == 0) | |
1266 | continue; | |
3fd94c6b | 1267 | } |
48c2ce97 BH |
1268 | pr_warning("PCI: Cannot allocate resource region " |
1269 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1270 | clear_resource: | |
cf1a4cf8 GS |
1271 | /* The resource might be figured out when doing |
1272 | * reassignment based on the resources required | |
1273 | * by the downstream PCI devices. Here we set | |
1274 | * the size of the resource to be 0 in order to | |
1275 | * save more space. | |
1276 | */ | |
1277 | res->start = 0; | |
1278 | res->end = -1; | |
e90a1318 | 1279 | res->flags = 0; |
3fd94c6b | 1280 | } |
e90a1318 NF |
1281 | |
1282 | list_for_each_entry(b, &bus->children, node) | |
1283 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1284 | } |
1285 | ||
cad5cef6 | 1286 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1287 | { |
1288 | struct resource *pr, *r = &dev->resource[idx]; | |
1289 | ||
ae2a84b4 KH |
1290 | pr_debug("PCI: Allocating %s: Resource %d: %pR\n", |
1291 | pci_name(dev), idx, r); | |
3fd94c6b BH |
1292 | |
1293 | pr = pci_find_parent_resource(dev, r); | |
1294 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1295 | request_resource(pr, r) < 0) { | |
1296 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1297 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1298 | if (pr) | |
ae2a84b4 | 1299 | pr_debug("PCI: parent is %p: %pR\n", pr, pr); |
3fd94c6b BH |
1300 | /* We'll assign a new address later */ |
1301 | r->flags |= IORESOURCE_UNSET; | |
1302 | r->end -= r->start; | |
1303 | r->start = 0; | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | static void __init pcibios_allocate_resources(int pass) | |
1308 | { | |
1309 | struct pci_dev *dev = NULL; | |
1310 | int idx, disabled; | |
1311 | u16 command; | |
1312 | struct resource *r; | |
1313 | ||
1314 | for_each_pci_dev(dev) { | |
1315 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1316 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1317 | r = &dev->resource[idx]; |
1318 | if (r->parent) /* Already allocated */ | |
1319 | continue; | |
1320 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1321 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1322 | /* We only allocate ROMs on pass 1 just in case they |
1323 | * have been screwed up by firmware | |
1324 | */ | |
1325 | if (idx == PCI_ROM_RESOURCE ) | |
1326 | disabled = 1; | |
3fd94c6b BH |
1327 | if (r->flags & IORESOURCE_IO) |
1328 | disabled = !(command & PCI_COMMAND_IO); | |
1329 | else | |
1330 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1331 | if (pass == disabled) |
1332 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1333 | } |
1334 | if (pass) | |
1335 | continue; | |
1336 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1337 | if (r->flags) { |
3fd94c6b BH |
1338 | /* Turn the ROM off, leave the resource region, |
1339 | * but keep it unregistered. | |
1340 | */ | |
1341 | u32 reg; | |
3fd94c6b | 1342 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1343 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1344 | pr_debug("PCI: Switching off ROM of %s\n", | |
1345 | pci_name(dev)); | |
1346 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1347 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1348 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1349 | } | |
3fd94c6b BH |
1350 | } |
1351 | } | |
1352 | } | |
1353 | ||
c1f34302 BH |
1354 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1355 | { | |
1356 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1357 | resource_size_t offset; | |
1358 | struct resource *res, *pres; | |
1359 | int i; | |
1360 | ||
1361 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1362 | ||
1363 | /* Check for IO */ | |
1364 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1365 | goto no_io; | |
1366 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1367 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1368 | BUG_ON(res == NULL); | |
1369 | res->name = "Legacy IO"; | |
1370 | res->flags = IORESOURCE_IO; | |
1371 | res->start = offset; | |
1372 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1373 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1374 | if (request_resource(&hose->io_resource, res)) { | |
1375 | printk(KERN_DEBUG | |
1376 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1377 | pci_domain_nr(bus), bus->number, res); | |
1378 | kfree(res); | |
1379 | } | |
1380 | ||
1381 | no_io: | |
1382 | /* Check for memory */ | |
c1f34302 BH |
1383 | for (i = 0; i < 3; i++) { |
1384 | pres = &hose->mem_resources[i]; | |
3fd47f06 | 1385 | offset = hose->mem_offset[i]; |
c1f34302 BH |
1386 | if (!(pres->flags & IORESOURCE_MEM)) |
1387 | continue; | |
1388 | pr_debug("hose mem res: %pR\n", pres); | |
1389 | if ((pres->start - offset) <= 0xa0000 && | |
1390 | (pres->end - offset) >= 0xbffff) | |
1391 | break; | |
1392 | } | |
1393 | if (i >= 3) | |
1394 | return; | |
1395 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1396 | BUG_ON(res == NULL); | |
1397 | res->name = "Legacy VGA memory"; | |
1398 | res->flags = IORESOURCE_MEM; | |
1399 | res->start = 0xa0000 + offset; | |
1400 | res->end = 0xbffff + offset; | |
1401 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1402 | if (request_resource(pres, res)) { | |
1403 | printk(KERN_DEBUG | |
1404 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1405 | pci_domain_nr(bus), bus->number, res); | |
1406 | kfree(res); | |
1407 | } | |
1408 | } | |
1409 | ||
3fd94c6b BH |
1410 | void __init pcibios_resource_survey(void) |
1411 | { | |
e90a1318 NF |
1412 | struct pci_bus *b; |
1413 | ||
48c2ce97 | 1414 | /* Allocate and assign resources */ |
e90a1318 NF |
1415 | list_for_each_entry(b, &pci_root_buses, node) |
1416 | pcibios_allocate_bus_resources(b); | |
9a1a70ae BH |
1417 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { |
1418 | pcibios_allocate_resources(0); | |
1419 | pcibios_allocate_resources(1); | |
1420 | } | |
3fd94c6b | 1421 | |
c1f34302 BH |
1422 | /* Before we start assigning unassigned resource, we try to reserve |
1423 | * the low IO area and the VGA memory area if they intersect the | |
1424 | * bus available resources to avoid allocating things on top of them | |
1425 | */ | |
0e47ff1c | 1426 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1427 | list_for_each_entry(b, &pci_root_buses, node) |
1428 | pcibios_reserve_legacy_regions(b); | |
1429 | } | |
1430 | ||
1431 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1432 | * we proceed to assigning things that were left unassigned | |
1433 | */ | |
0e47ff1c | 1434 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1435 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1436 | pci_assign_unassigned_resources(); |
1437 | } | |
1438 | ||
1439 | /* Call machine dependent fixup */ | |
1440 | if (ppc_md.pcibios_fixup) | |
1441 | ppc_md.pcibios_fixup(); | |
1442 | } | |
1443 | ||
fd6852c8 | 1444 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1445 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1446 | * rest of the code later, for now, keep it as-is as our main |
1447 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1448 | */ |
baf75b0a | 1449 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1450 | { |
1451 | struct pci_dev *dev; | |
1452 | struct pci_bus *child_bus; | |
1453 | ||
1454 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1455 | int i; | |
1456 | ||
1457 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1458 | struct resource *r = &dev->resource[i]; | |
1459 | ||
1460 | if (r->parent || !r->start || !r->flags) | |
1461 | continue; | |
fd6852c8 | 1462 | |
ae2a84b4 KH |
1463 | pr_debug("PCI: Claiming %s: Resource %d: %pR\n", |
1464 | pci_name(dev), i, r); | |
fd6852c8 | 1465 | |
3ebfe46a YL |
1466 | if (pci_claim_resource(dev, i) == 0) |
1467 | continue; | |
1468 | ||
1469 | pci_claim_bridge_resource(dev, i); | |
3fd94c6b BH |
1470 | } |
1471 | } | |
1472 | ||
1473 | list_for_each_entry(child_bus, &bus->children, node) | |
1474 | pcibios_claim_one_bus(child_bus); | |
1475 | } | |
5b64d2cc | 1476 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); |
fd6852c8 BH |
1477 | |
1478 | ||
1479 | /* pcibios_finish_adding_to_bus | |
1480 | * | |
1481 | * This is to be called by the hotplug code after devices have been | |
1482 | * added to a bus, this include calling it for a PHB that is just | |
1483 | * being added | |
1484 | */ | |
1485 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1486 | { | |
1487 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1488 | pci_domain_nr(bus), bus->number); | |
1489 | ||
1490 | /* Allocate bus and devices resources */ | |
1491 | pcibios_allocate_bus_resources(bus); | |
1492 | pcibios_claim_one_bus(bus); | |
7415c14c GS |
1493 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
1494 | if (bus->self) | |
1495 | pci_assign_unassigned_bridge_resources(bus->self); | |
1496 | else | |
1497 | pci_assign_unassigned_bus_resources(bus); | |
1498 | } | |
fd6852c8 | 1499 | |
6a040ce7 TLSC |
1500 | /* Fixup EEH */ |
1501 | eeh_add_device_tree_late(bus); | |
1502 | ||
fd6852c8 BH |
1503 | /* Add new devices to global lists. Register in proc, sysfs. */ |
1504 | pci_bus_add_devices(bus); | |
1505 | ||
6a040ce7 TLSC |
1506 | /* sysfs files should only be added after devices are added */ |
1507 | eeh_add_sysfs_files(bus); | |
fd6852c8 BH |
1508 | } |
1509 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1510 | ||
549beb9b BH |
1511 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1512 | { | |
467efc2e DA |
1513 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
1514 | ||
1515 | if (phb->controller_ops.enable_device_hook) | |
1516 | if (!phb->controller_ops.enable_device_hook(dev)) | |
1517 | return -EINVAL; | |
549beb9b | 1518 | |
7cfb5f9a | 1519 | return pci_enable_resources(dev, mask); |
549beb9b | 1520 | } |
53280323 | 1521 | |
abeeed6d MN |
1522 | void pcibios_disable_device(struct pci_dev *dev) |
1523 | { | |
1524 | struct pci_controller *phb = pci_bus_to_host(dev->bus); | |
1525 | ||
1526 | if (phb->controller_ops.disable_device) | |
1527 | phb->controller_ops.disable_device(dev); | |
1528 | } | |
1529 | ||
38973ba7 BH |
1530 | resource_size_t pcibios_io_space_offset(struct pci_controller *hose) |
1531 | { | |
1532 | return (unsigned long) hose->io_base_virt - _IO_BASE; | |
1533 | } | |
1534 | ||
cad5cef6 GKH |
1535 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1536 | struct list_head *resources) | |
53280323 | 1537 | { |
53280323 | 1538 | struct resource *res; |
3fd47f06 | 1539 | resource_size_t offset; |
53280323 BH |
1540 | int i; |
1541 | ||
1542 | /* Hookup PHB IO resource */ | |
45a709f8 | 1543 | res = &hose->io_resource; |
53280323 BH |
1544 | |
1545 | if (!res->flags) { | |
cdb1b342 BH |
1546 | pr_debug("PCI: I/O resource not set for host" |
1547 | " bridge %s (domain %d)\n", | |
1548 | hose->dn->full_name, hose->global_number); | |
3fd47f06 BH |
1549 | } else { |
1550 | offset = pcibios_io_space_offset(hose); | |
1551 | ||
ae2a84b4 KH |
1552 | pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", |
1553 | res, (unsigned long long)offset); | |
3fd47f06 | 1554 | pci_add_resource_offset(resources, res, offset); |
a0b8e76f | 1555 | } |
53280323 BH |
1556 | |
1557 | /* Hookup PHB Memory resources */ | |
1558 | for (i = 0; i < 3; ++i) { | |
1559 | res = &hose->mem_resources[i]; | |
1560 | if (!res->flags) { | |
bee7dd9c BH |
1561 | if (i == 0) |
1562 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1563 | "host bridge %s (domain %d)\n", | |
1564 | hose->dn->full_name, hose->global_number); | |
3fd47f06 | 1565 | continue; |
a0b8e76f | 1566 | } |
3fd47f06 | 1567 | offset = hose->mem_offset[i]; |
53280323 | 1568 | |
3fd47f06 | 1569 | |
ae2a84b4 KH |
1570 | pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, |
1571 | res, (unsigned long long)offset); | |
3fd47f06 BH |
1572 | |
1573 | pci_add_resource_offset(resources, res, offset); | |
1574 | } | |
53280323 | 1575 | } |
89c2dd62 KG |
1576 | |
1577 | /* | |
1578 | * Null PCI config access functions, for the case when we can't | |
1579 | * find a hose. | |
1580 | */ | |
1581 | #define NULL_PCI_OP(rw, size, type) \ | |
1582 | static int \ | |
1583 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1584 | { \ | |
1585 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1586 | } | |
1587 | ||
1588 | static int | |
1589 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1590 | int len, u32 *val) | |
1591 | { | |
1592 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1593 | } | |
1594 | ||
1595 | static int | |
1596 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1597 | int len, u32 val) | |
1598 | { | |
1599 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1600 | } | |
1601 | ||
1602 | static struct pci_ops null_pci_ops = | |
1603 | { | |
1604 | .read = null_read_config, | |
1605 | .write = null_write_config, | |
1606 | }; | |
1607 | ||
1608 | /* | |
1609 | * These functions are used early on before PCI scanning is done | |
1610 | * and all of the pci_dev and pci_bus structures have been created. | |
1611 | */ | |
1612 | static struct pci_bus * | |
1613 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1614 | { | |
1615 | static struct pci_bus bus; | |
1616 | ||
b0d436c7 | 1617 | if (hose == NULL) { |
89c2dd62 KG |
1618 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
1619 | } | |
1620 | bus.number = busnr; | |
1621 | bus.sysdata = hose; | |
1622 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1623 | return &bus; | |
1624 | } | |
1625 | ||
1626 | #define EARLY_PCI_OP(rw, size, type) \ | |
1627 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1628 | int devfn, int offset, type value) \ | |
1629 | { \ | |
1630 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1631 | devfn, offset, value); \ | |
1632 | } | |
1633 | ||
1634 | EARLY_PCI_OP(read, byte, u8 *) | |
1635 | EARLY_PCI_OP(read, word, u16 *) | |
1636 | EARLY_PCI_OP(read, dword, u32 *) | |
1637 | EARLY_PCI_OP(write, byte, u8) | |
1638 | EARLY_PCI_OP(write, word, u16) | |
1639 | EARLY_PCI_OP(write, dword, u32) | |
1640 | ||
89c2dd62 KG |
1641 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, |
1642 | int cap) | |
1643 | { | |
1644 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1645 | } | |
0ed2c722 | 1646 | |
98d9f30c BH |
1647 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1648 | { | |
1649 | struct pci_controller *hose = bus->sysdata; | |
1650 | ||
1651 | return of_node_get(hose->dn); | |
1652 | } | |
1653 | ||
0ed2c722 GL |
1654 | /** |
1655 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1656 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1657 | */ |
cad5cef6 | 1658 | void pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 | 1659 | { |
45a709f8 | 1660 | LIST_HEAD(resources); |
0ed2c722 GL |
1661 | struct pci_bus *bus; |
1662 | struct device_node *node = hose->dn; | |
1663 | int mode; | |
1664 | ||
74a7f084 | 1665 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
0ed2c722 | 1666 | |
45a709f8 BH |
1667 | /* Get some IO space for the new PHB */ |
1668 | pcibios_setup_phb_io_space(hose); | |
1669 | ||
1670 | /* Wire up PHB bus resources */ | |
1671 | pcibios_setup_phb_resources(hose, &resources); | |
1672 | ||
be8e60d8 YL |
1673 | hose->busn.start = hose->first_busno; |
1674 | hose->busn.end = hose->last_busno; | |
1675 | hose->busn.flags = IORESOURCE_BUS; | |
1676 | pci_add_resource(&resources, &hose->busn); | |
1677 | ||
0ed2c722 | 1678 | /* Create an empty bus for the toplevel */ |
45a709f8 BH |
1679 | bus = pci_create_root_bus(hose->parent, hose->first_busno, |
1680 | hose->ops, hose, &resources); | |
0ed2c722 GL |
1681 | if (bus == NULL) { |
1682 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1683 | hose->global_number); | |
45a709f8 | 1684 | pci_free_resource_list(&resources); |
0ed2c722 GL |
1685 | return; |
1686 | } | |
0ed2c722 GL |
1687 | hose->bus = bus; |
1688 | ||
0ed2c722 GL |
1689 | /* Get probe mode and perform scan */ |
1690 | mode = PCI_PROBE_NORMAL; | |
467efc2e DA |
1691 | if (node && hose->controller_ops.probe_mode) |
1692 | mode = hose->controller_ops.probe_mode(bus); | |
0ed2c722 | 1693 | pr_debug(" probe mode: %d\n", mode); |
be8e60d8 | 1694 | if (mode == PCI_PROBE_DEVTREE) |
0ed2c722 | 1695 | of_scan_bus(node, bus); |
0ed2c722 | 1696 | |
be8e60d8 YL |
1697 | if (mode == PCI_PROBE_NORMAL) { |
1698 | pci_bus_update_busn_res_end(bus, 255); | |
1699 | hose->last_busno = pci_scan_child_bus(bus); | |
1700 | pci_bus_update_busn_res_end(bus, hose->last_busno); | |
1701 | } | |
781fb7a3 | 1702 | |
491b98c3 BH |
1703 | /* Platform gets a chance to do some global fixups before |
1704 | * we proceed to resource allocation | |
1705 | */ | |
1706 | if (ppc_md.pcibios_fixup_phb) | |
1707 | ppc_md.pcibios_fixup_phb(hose); | |
1708 | ||
781fb7a3 | 1709 | /* Configure PCI Express settings */ |
bb36c445 | 1710 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
781fb7a3 | 1711 | struct pci_bus *child; |
a58674ff BH |
1712 | list_for_each_entry(child, &bus->children, node) |
1713 | pcie_bus_configure_settings(child); | |
781fb7a3 | 1714 | } |
0ed2c722 | 1715 | } |
5b64d2cc | 1716 | EXPORT_SYMBOL_GPL(pcibios_scan_phb); |
c065488f KG |
1717 | |
1718 | static void fixup_hide_host_resource_fsl(struct pci_dev *dev) | |
1719 | { | |
1720 | int i, class = dev->class >> 8; | |
05737c7c JJ |
1721 | /* When configured as agent, programing interface = 1 */ |
1722 | int prog_if = dev->class & 0xf; | |
c065488f KG |
1723 | |
1724 | if ((class == PCI_CLASS_PROCESSOR_POWERPC || | |
1725 | class == PCI_CLASS_BRIDGE_OTHER) && | |
1726 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
05737c7c | 1727 | (prog_if == 0) && |
c065488f KG |
1728 | (dev->bus->parent == NULL)) { |
1729 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1730 | dev->resource[i].start = 0; | |
1731 | dev->resource[i].end = 0; | |
1732 | dev->resource[i].flags = 0; | |
1733 | } | |
1734 | } | |
1735 | } | |
1736 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
1737 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
c2e1d845 BK |
1738 | |
1739 | static void fixup_vga(struct pci_dev *pdev) | |
1740 | { | |
1741 | u16 cmd; | |
1742 | ||
1743 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1744 | if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) | |
1745 | vga_set_default_device(pdev); | |
1746 | ||
1747 | } | |
1748 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, | |
1749 | PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); |