Commit | Line | Data |
---|---|---|
a0ae9c7c AB |
1 | config PPC64 |
2 | bool "64-bit kernel" | |
3 | default n | |
105988c0 | 4 | select PPC_HAVE_PMU_SUPPORT |
a0ae9c7c AB |
5 | help |
6 | This option selects whether a 32-bit or a 64-bit kernel | |
7 | will be built. | |
8 | ||
9 | menu "Processor support" | |
10 | choice | |
11 | prompt "Processor Type" | |
12 | depends on PPC32 | |
a0ae9c7c | 13 | help |
b9fd305d AB |
14 | There are five families of 32 bit PowerPC chips supported. |
15 | The most common ones are the desktop and server CPUs (601, 603, | |
16 | 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their | |
e177edcd | 17 | embedded 512x/52xx/82xx/83xx/86xx counterparts. |
b9fd305d AB |
18 | The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500 |
19 | (85xx) each form a family of their own that is not compatible | |
20 | with the others. | |
21 | ||
22 | If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx. | |
23 | ||
48c93112 | 24 | config PPC_BOOK3S_32 |
e177edcd | 25 | bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx" |
a0ae9c7c AB |
26 | select PPC_FPU |
27 | ||
a0ae9c7c AB |
28 | config PPC_85xx |
29 | bool "Freescale 85xx" | |
30 | select E500 | |
a0ae9c7c | 31 | |
a0ae9c7c AB |
32 | config PPC_8xx |
33 | bool "Freescale 8xx" | |
34 | select FSL_SOC | |
35 | select 8xx | |
1088a209 | 36 | select PPC_LIB_RHEAP |
a0ae9c7c AB |
37 | |
38 | config 40x | |
39 | bool "AMCC 40x" | |
40 | select PPC_DCR_NATIVE | |
9dae8afd | 41 | select PPC_UDBG_16550 |
93173ce2 | 42 | select 4xx_SOC |
b500563b | 43 | select PPC_PCI_CHOICE |
a0ae9c7c AB |
44 | |
45 | config 44x | |
e7f75ad0 | 46 | bool "AMCC 44x, 46x or 47x" |
a0ae9c7c | 47 | select PPC_DCR_NATIVE |
1d5499b5 | 48 | select PPC_UDBG_16550 |
93173ce2 | 49 | select 4xx_SOC |
b500563b | 50 | select PPC_PCI_CHOICE |
4ee7084e | 51 | select PHYS_64BIT |
a0ae9c7c AB |
52 | |
53 | config E200 | |
54 | bool "Freescale e200" | |
55 | ||
56 | endchoice | |
57 | ||
2d27cfd3 BH |
58 | choice |
59 | prompt "Processor Type" | |
5b7c3c91 | 60 | depends on PPC64 |
2d27cfd3 BH |
61 | help |
62 | There are two families of 64 bit PowerPC chips supported. | |
63 | The most common ones are the desktop and server CPUs | |
64 | (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...) | |
65 | ||
66 | The other are the "embedded" processors compliant with the | |
67 | "Book 3E" variant of the architecture | |
68 | ||
69 | config PPC_BOOK3S_64 | |
70 | bool "Server processors" | |
5b7c3c91 BH |
71 | select PPC_FPU |
72 | ||
2d27cfd3 BH |
73 | config PPC_BOOK3E_64 |
74 | bool "Embedded processors" | |
75 | select PPC_FPU # Make it a choice ? | |
1ece355b | 76 | select PPC_SMP_MUXED_IPI |
2d27cfd3 BH |
77 | |
78 | endchoice | |
79 | ||
48c93112 BH |
80 | config PPC_BOOK3S |
81 | def_bool y | |
82 | depends on PPC_BOOK3S_32 || PPC_BOOK3S_64 | |
28794d34 | 83 | |
2d27cfd3 BH |
84 | config PPC_BOOK3E |
85 | def_bool y | |
86 | depends on PPC_BOOK3E_64 | |
87 | ||
a0ae9c7c AB |
88 | config POWER4_ONLY |
89 | bool "Optimize for POWER4" | |
28794d34 | 90 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
91 | default n |
92 | ---help--- | |
93 | Cause the compiler to optimize for POWER4/POWER5/PPC970 processors. | |
94 | The resulting binary will not work on POWER3 or RS64 processors | |
95 | when compiled with binutils 2.15 or later. | |
96 | ||
5b7c3c91 BH |
97 | config 6xx |
98 | def_bool y | |
99 | depends on PPC32 && PPC_BOOK3S | |
7325927e | 100 | select PPC_HAVE_PMU_SUPPORT |
5b7c3c91 | 101 | |
a0ae9c7c AB |
102 | config POWER3 |
103 | bool | |
28794d34 | 104 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
105 | default y if !POWER4_ONLY |
106 | ||
107 | config POWER4 | |
28794d34 | 108 | depends on PPC64 && PPC_BOOK3S |
a0ae9c7c AB |
109 | def_bool y |
110 | ||
76b4eda8 BH |
111 | config PPC_A2 |
112 | bool | |
113 | depends on PPC_BOOK3E_64 | |
114 | ||
3164cccd AB |
115 | config TUNE_CELL |
116 | bool "Optimize for Cell Broadband Engine" | |
28794d34 | 117 | depends on PPC64 && PPC_BOOK3S |
3164cccd AB |
118 | help |
119 | Cause the compiler to optimize for the PPE of the Cell Broadband | |
120 | Engine. This will make the code run considerably faster on Cell | |
121 | but somewhat slower on other machines. This option only changes | |
122 | the scheduling of instructions, not the selection of instructions | |
123 | itself, so the resulting kernel will keep running on all other | |
124 | machines. When building a kernel that is supposed to run only | |
125 | on Cell, you should also select the POWER4_ONLY option. | |
126 | ||
a0ae9c7c AB |
127 | # this is temp to handle compat with arch=ppc |
128 | config 8xx | |
129 | bool | |
130 | ||
a0ae9c7c | 131 | config E500 |
39aef685 | 132 | select FSL_EMB_PERFMON |
4490c06b | 133 | select PPC_FSL_BOOK3E |
a0ae9c7c AB |
134 | bool |
135 | ||
3dfa8773 KG |
136 | config PPC_E500MC |
137 | bool "e500mc Support" | |
138 | select PPC_FPU | |
139 | depends on E500 | |
140 | ||
a0ae9c7c AB |
141 | config PPC_FPU |
142 | bool | |
143 | default y if PPC64 | |
144 | ||
5753c082 KG |
145 | config FSL_EMB_PERFMON |
146 | bool "Freescale Embedded Perfmon" | |
147 | depends on E500 || PPC_83xx | |
148 | help | |
149 | This is the Performance Monitor support found on the e500 core | |
150 | and some e300 cores (c3 and c4). Select this only if your | |
151 | core supports the Embedded Performance Monitor APU | |
152 | ||
a1110654 SW |
153 | config FSL_EMB_PERF_EVENT |
154 | bool | |
155 | depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS | |
156 | default y | |
157 | ||
158 | config FSL_EMB_PERF_EVENT_E500 | |
159 | bool | |
160 | depends on FSL_EMB_PERF_EVENT && E500 | |
161 | default y | |
162 | ||
a0ae9c7c AB |
163 | config 4xx |
164 | bool | |
165 | depends on 40x || 44x | |
166 | default y | |
167 | ||
168 | config BOOKE | |
169 | bool | |
2d27cfd3 | 170 | depends on E200 || E500 || 44x || PPC_BOOK3E |
a0ae9c7c AB |
171 | default y |
172 | ||
173 | config FSL_BOOKE | |
174 | bool | |
4490c06b | 175 | depends on (E200 || E500) && PPC32 |
a0ae9c7c AB |
176 | default y |
177 | ||
4490c06b KG |
178 | # this is for common code between PPC32 & PPC64 FSL BOOKE |
179 | config PPC_FSL_BOOK3E | |
180 | bool | |
181 | select FSL_EMB_PERFMON | |
1ece355b | 182 | select PPC_SMP_MUXED_IPI |
4490c06b | 183 | default y if FSL_BOOKE |
39aef685 | 184 | |
a0ae9c7c AB |
185 | config PTE_64BIT |
186 | bool | |
4ee7084e BB |
187 | depends on 44x || E500 || PPC_86xx |
188 | default y if PHYS_64BIT | |
a0ae9c7c AB |
189 | |
190 | config PHYS_64BIT | |
4ee7084e BB |
191 | bool 'Large physical address support' if E500 || PPC_86xx |
192 | depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx | |
a0ae9c7c AB |
193 | ---help--- |
194 | This option enables kernel support for larger than 32-bit physical | |
4ee7084e BB |
195 | addresses. This feature may not be available on all cores. |
196 | ||
197 | If you have more than 3.5GB of RAM or so, you also need to enable | |
198 | SWIOTLB under Kernel Options for this to work. The actual number | |
199 | is platform-dependent. | |
a0ae9c7c AB |
200 | |
201 | If in doubt, say N here. | |
202 | ||
203 | config ALTIVEC | |
204 | bool "AltiVec Support" | |
28794d34 | 205 | depends on 6xx || POWER4 |
a0ae9c7c AB |
206 | ---help--- |
207 | This option enables kernel support for the Altivec extensions to the | |
208 | PowerPC processor. The kernel currently supports saving and restoring | |
209 | altivec registers, and turning on the 'altivec enable' bit so user | |
210 | processes can execute altivec instructions. | |
211 | ||
212 | This option is only usefully if you have a processor that supports | |
213 | altivec (G4, otherwise known as 74xx series), but does not have | |
214 | any affect on a non-altivec cpu (it does, however add code to the | |
215 | kernel). | |
216 | ||
217 | If in doubt, say Y here. | |
218 | ||
96d5b52c MN |
219 | config VSX |
220 | bool "VSX Support" | |
221 | depends on POWER4 && ALTIVEC && PPC_FPU | |
222 | ---help--- | |
223 | ||
224 | This option enables kernel support for the Vector Scaler extensions | |
225 | to the PowerPC processor. The kernel currently supports saving and | |
226 | restoring VSX registers, and turning on the 'VSX enable' bit so user | |
227 | processes can execute VSX instructions. | |
228 | ||
229 | This option is only useful if you have a processor that supports | |
230 | VSX (P7 and above), but does not have any affect on a non-VSX | |
231 | CPUs (it does, however add code to the kernel). | |
232 | ||
233 | If in doubt, say Y here. | |
234 | ||
851d2e2f THFL |
235 | config PPC_ICSWX |
236 | bool "Support for PowerPC icswx coprocessor instruction" | |
237 | depends on POWER4 | |
238 | default n | |
239 | ---help--- | |
240 | ||
241 | This option enables kernel support for the PowerPC Initiate | |
242 | Coprocessor Store Word (icswx) coprocessor instruction on POWER7 | |
243 | or newer processors. | |
244 | ||
245 | This option is only useful if you have a processor that supports | |
246 | the icswx coprocessor instruction. It does not have any effect | |
247 | on processors without the icswx coprocessor instruction. | |
248 | ||
249 | This option slightly increases kernel memory usage. | |
250 | ||
251 | If in doubt, say N here. | |
252 | ||
a0ae9c7c AB |
253 | config SPE |
254 | bool "SPE Support" | |
3dfa8773 | 255 | depends on E200 || (E500 && !PPC_E500MC) |
a0ae9c7c AB |
256 | default y |
257 | ---help--- | |
258 | This option enables kernel support for the Signal Processing | |
259 | Extensions (SPE) to the PowerPC processor. The kernel currently | |
260 | supports saving and restoring SPE registers, and turning on the | |
261 | 'spe enable' bit so user processes can execute SPE instructions. | |
262 | ||
263 | This option is only useful if you have a processor that supports | |
264 | SPE (e500, otherwise known as 85xx series), but does not have any | |
265 | effect on a non-spe cpu (it does, however add code to the kernel). | |
266 | ||
267 | If in doubt, say Y here. | |
268 | ||
269 | config PPC_STD_MMU | |
5b7c3c91 BH |
270 | def_bool y |
271 | depends on PPC_BOOK3S | |
a0ae9c7c AB |
272 | |
273 | config PPC_STD_MMU_32 | |
274 | def_bool y | |
275 | depends on PPC_STD_MMU && PPC32 | |
276 | ||
5e696617 BH |
277 | config PPC_STD_MMU_64 |
278 | def_bool y | |
279 | depends on PPC_STD_MMU && PPC64 | |
280 | ||
281 | config PPC_MMU_NOHASH | |
282 | def_bool y | |
283 | depends on !PPC_STD_MMU | |
284 | ||
2d27cfd3 BH |
285 | config PPC_MMU_NOHASH_32 |
286 | def_bool y | |
287 | depends on PPC_MMU_NOHASH && PPC32 | |
288 | ||
289 | config PPC_MMU_NOHASH_64 | |
290 | def_bool y | |
291 | depends on PPC_MMU_NOHASH && PPC64 | |
292 | ||
70fe3af8 KG |
293 | config PPC_BOOK3E_MMU |
294 | def_bool y | |
2d27cfd3 | 295 | depends on FSL_BOOKE || PPC_BOOK3E |
70fe3af8 | 296 | |
a0ae9c7c AB |
297 | config PPC_MM_SLICES |
298 | bool | |
ca9153a3 | 299 | default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES) |
a0ae9c7c AB |
300 | default n |
301 | ||
302 | config VIRT_CPU_ACCOUNTING | |
303 | bool "Deterministic task and CPU time accounting" | |
304 | depends on PPC64 | |
305 | default y | |
306 | help | |
307 | Select this option to enable more accurate task and CPU time | |
308 | accounting. This is done by reading a CPU counter on each | |
309 | kernel entry and exit and on transitions within the kernel | |
310 | between system, softirq and hardirq state, so there is a | |
311 | small performance impact. This also enables accounting of | |
312 | stolen time on logically-partitioned systems running on | |
313 | IBM POWER5-based machines. | |
314 | ||
315 | If in doubt, say Y here. | |
316 | ||
105988c0 PM |
317 | config PPC_HAVE_PMU_SUPPORT |
318 | bool | |
319 | ||
320 | config PPC_PERF_CTRS | |
321 | def_bool y | |
cdd6c482 | 322 | depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT |
105988c0 | 323 | help |
cdd6c482 | 324 | This enables the powerpc-specific perf_event back-end. |
105988c0 | 325 | |
a0ae9c7c | 326 | config SMP |
e7f75ad0 | 327 | depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x |
a0ae9c7c AB |
328 | bool "Symmetric multi-processing support" |
329 | ---help--- | |
330 | This enables support for systems with more than one CPU. If you have | |
331 | a system with only one CPU, say N. If you have a system with more | |
332 | than one CPU, say Y. Note that the kernel does not currently | |
333 | support SMP machines with 603/603e/603ev or PPC750 ("G3") processors | |
334 | since they have inadequate hardware support for multiprocessor | |
335 | operation. | |
336 | ||
337 | If you say N here, the kernel will run on single and multiprocessor | |
338 | machines, but will use only one CPU of a multiprocessor machine. If | |
339 | you say Y here, the kernel will run on single-processor machines. | |
340 | On a single-processor machine, the kernel will run faster if you say | |
341 | N here. | |
342 | ||
343 | If you don't know what to do here, say N. | |
344 | ||
345 | config NR_CPUS | |
2d8ae638 MN |
346 | int "Maximum number of CPUs (2-8192)" |
347 | range 2 8192 | |
a0ae9c7c AB |
348 | depends on SMP |
349 | default "32" if PPC64 | |
350 | default "4" | |
351 | ||
352 | config NOT_COHERENT_CACHE | |
353 | bool | |
b91a143b | 354 | depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON |
e7f75ad0 | 355 | default n if PPC_47x |
a0ae9c7c AB |
356 | default y |
357 | ||
f8eb77d6 | 358 | config CHECK_CACHE_COHERENCY |
a0ae9c7c AB |
359 | bool |
360 | ||
361 | endmenu |