projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
parport: disable PC-style parallel port support for s390
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
1da177e4 32#include <asm/bug.h>
b2fa47e6 33#include <asm/page.h>
1da177e4 34
1da177e4
LT		 35extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
36extern void paging_init(void);
2b67fc46 37extern void vmem_map_init(void);
1da177e4
LT		 38
39/*
40 * The S390 doesn't have any external MMU info: the kernel page
41 * tables contain all the necessary information.
42 */
4b3073e1 43#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 44#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 45
46/*
238ec4ef 47 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 48 * for zero-mapped memory areas etc..
49 */
238ec4ef
MS		 50
51extern unsigned long empty_zero_page;
52extern unsigned long zero_page_mask;
53
54#define ZERO_PAGE(vaddr) \
55 (virt_to_page((void *)(empty_zero_page + \
56 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 57#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 58
1da177e4
LT		 59#endif /* !__ASSEMBLY__ */
60
61/*
62 * PMD_SHIFT determines the size of the area a second-level page
63 * table can map
64 * PGDIR_SHIFT determines what a third-level page table entry can map
65 */
f4815ac6 66#ifndef CONFIG_64BIT
146e4b3c
MS		 67# define PMD_SHIFT 20
68# define PUD_SHIFT 20
69# define PGDIR_SHIFT 20
f4815ac6 70#else /* CONFIG_64BIT */
146e4b3c 71# define PMD_SHIFT 20
190a1d72 72# define PUD_SHIFT 31
5a216a20 73# define PGDIR_SHIFT 42
f4815ac6 74#endif /* CONFIG_64BIT */
1da177e4
LT		 75
76#define PMD_SIZE (1UL << PMD_SHIFT)
77#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 78#define PUD_SIZE (1UL << PUD_SHIFT)
79#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 80#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
81#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 82
83/*
84 * entries per page directory level: the S390 is two-level, so
85 * we don't really have any PMD directory physically.
86 * for S390 segment-table entries are combined to one PGD
87 * that leads to 1024 pte per pgd
88 */
146e4b3c 89#define PTRS_PER_PTE 256
f4815ac6 90#ifndef CONFIG_64BIT
146e4b3c 91#define PTRS_PER_PMD 1
5a216a20 92#define PTRS_PER_PUD 1
f4815ac6 93#else /* CONFIG_64BIT */
146e4b3c 94#define PTRS_PER_PMD 2048
5a216a20 95#define PTRS_PER_PUD 2048
f4815ac6 96#endif /* CONFIG_64BIT */
146e4b3c 97#define PTRS_PER_PGD 2048
1da177e4 98
d455a369
HD		 99#define FIRST_USER_ADDRESS 0
100
1da177e4
LT		 101#define pte_ERROR(e) \
102 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
103#define pmd_ERROR(e) \
104 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 105#define pud_ERROR(e) \
106 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 107#define pgd_ERROR(e) \
108 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
109
110#ifndef __ASSEMBLY__
111/*
c972cc60
HC		 112 * The vmalloc and module area will always be on the topmost area of the kernel
113 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
114 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
115 * modules will reside. That makes sure that inter module branches always
116 * happen without trampolines and in addition the placement within a 2GB frame
117 * is branch prediction unit friendly.
8b62bc96 118 */
239a6425 119extern unsigned long VMALLOC_START;
14045ebf
MS		 120extern unsigned long VMALLOC_END;
121extern struct page *vmemmap;
239a6425 122
14045ebf 123#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 124
c972cc60
HC		 125#ifdef CONFIG_64BIT
126extern unsigned long MODULES_VADDR;
127extern unsigned long MODULES_END;
128#define MODULES_VADDR MODULES_VADDR
129#define MODULES_END MODULES_END
130#define MODULES_LEN (1UL << 31)
131#endif
132
1da177e4
LT		 133/*
134 * A 31 bit pagetable entry of S390 has following format:
135 * | PFRA | | OS |
136 * 0 0IP0
137 * 00000000001111111111222222222233
138 * 01234567890123456789012345678901
139 *
140 * I Page-Invalid Bit: Page is not available for address-translation
141 * P Page-Protection Bit: Store access not possible for page
142 *
143 * A 31 bit segmenttable entry of S390 has following format:
144 * | P-table origin | |PTL
145 * 0 IC
146 * 00000000001111111111222222222233
147 * 01234567890123456789012345678901
148 *
149 * I Segment-Invalid Bit: Segment is not available for address-translation
150 * C Common-Segment Bit: Segment is not private (PoP 3-30)
151 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
152 *
153 * The 31 bit segmenttable origin of S390 has following format:
154 *
155 * |S-table origin | | STL |
156 * X **GPS
157 * 00000000001111111111222222222233
158 * 01234567890123456789012345678901
159 *
160 * X Space-Switch event:
161 * G Segment-Invalid Bit: *
162 * P Private-Space Bit: Segment is not private (PoP 3-30)
163 * S Storage-Alteration:
164 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
165 *
166 * A 64 bit pagetable entry of S390 has following format:
6a985c61 167 * | PFRA |0IPC| OS |
1da177e4
LT		 168 * 0000000000111111111122222222223333333333444444444455555555556666
169 * 0123456789012345678901234567890123456789012345678901234567890123
170 *
171 * I Page-Invalid Bit: Page is not available for address-translation
172 * P Page-Protection Bit: Store access not possible for page
6a985c61 173 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 174 *
175 * A 64 bit segmenttable entry of S390 has following format:
176 * | P-table origin | TT
177 * 0000000000111111111122222222223333333333444444444455555555556666
178 * 0123456789012345678901234567890123456789012345678901234567890123
179 *
180 * I Segment-Invalid Bit: Segment is not available for address-translation
181 * C Common-Segment Bit: Segment is not private (PoP 3-30)
182 * P Page-Protection Bit: Store access not possible for page
183 * TT Type 00
184 *
185 * A 64 bit region table entry of S390 has following format:
186 * | S-table origin | TF TTTL
187 * 0000000000111111111122222222223333333333444444444455555555556666
188 * 0123456789012345678901234567890123456789012345678901234567890123
189 *
190 * I Segment-Invalid Bit: Segment is not available for address-translation
191 * TT Type 01
192 * TF
190a1d72 193 * TL Table length
1da177e4
LT		 194 *
195 * The 64 bit regiontable origin of S390 has following format:
196 * | region table origon | DTTL
197 * 0000000000111111111122222222223333333333444444444455555555556666
198 * 0123456789012345678901234567890123456789012345678901234567890123
199 *
200 * X Space-Switch event:
201 * G Segment-Invalid Bit:
202 * P Private-Space Bit:
203 * S Storage-Alteration:
204 * R Real space
205 * TL Table-Length:
206 *
207 * A storage key has the following format:
208 * | ACC |F|R|C|0|
209 * 0 3 4 5 6 7
210 * ACC: access key
211 * F : fetch protection bit
212 * R : referenced bit
213 * C : changed bit
214 */
215
216/* Hardware bits in the page table entry */
6a985c61 217#define _PAGE_CO 0x100 /* HW Change-bit override */
83377484
MS		 218#define _PAGE_RO 0x200 /* HW read-only bit */
219#define _PAGE_INVALID 0x400 /* HW invalid bit */
3610cce8
MS		 220
221/* Software bits in the page table entry */
83377484
MS		 222#define _PAGE_SWT 0x001 /* SW pte type bit t */
223#define _PAGE_SWX 0x002 /* SW pte type bit x */
b2fa47e6
MS		 224#define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
225#define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
226#define _PAGE_SPECIAL 0x010 /* SW associated with special page */
a08cb629 227#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 228
138c9021 229/* Set of bits not changed in pte_modify */
b2fa47e6 230#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
138c9021 231
83377484 232/* Six different types of pages. */
9282ed92
GS		 233#define _PAGE_TYPE_EMPTY 0x400
234#define _PAGE_TYPE_NONE 0x401
83377484
MS		 235#define _PAGE_TYPE_SWAP 0x403
236#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
9282ed92
GS		 237#define _PAGE_TYPE_RO 0x200
238#define _PAGE_TYPE_RW 0x000
1da177e4 239
53492b1d
GS		 240/*
241 * Only four types for huge pages, using the invalid bit and protection bit
242 * of a segment table entry.
243 */
244#define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
245#define _HPAGE_TYPE_NONE 0x220
246#define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
247#define _HPAGE_TYPE_RW 0x000
248
83377484
MS		 249/*
250 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
251 * pte_none and pte_file to find out the pte type WITHOUT holding the page
252 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
253 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
254 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
255 * This change is done while holding the lock, but the intermediate step
256 * of a previously valid pte with the hw invalid bit set can be observed by
257 * handle_pte_fault. That makes it necessary that all valid pte types with
258 * the hw invalid bit set must be distinguishable from the four pte types
259 * empty, none, swap and file.
260 *
261 * irxt ipte irxt
262 * _PAGE_TYPE_EMPTY 1000 -> 1000
263 * _PAGE_TYPE_NONE 1001 -> 1001
264 * _PAGE_TYPE_SWAP 1011 -> 1011
265 * _PAGE_TYPE_FILE 11?1 -> 11?1
266 * _PAGE_TYPE_RO 0100 -> 1100
267 * _PAGE_TYPE_RW 0000 -> 1000
268 *
c1821c2e 269 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
83377484
MS		 270 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
271 * pte_file is true for bits combinations 1101, 1111
c1821c2e 272 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
83377484
MS		 273 */
274
f4815ac6 275#ifndef CONFIG_64BIT
1da177e4 276
3610cce8
MS		 277/* Bits in the segment table address-space-control-element */
278#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
279#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
280#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
281#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
282#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 283
3610cce8
MS		 284/* Bits in the segment table entry */
285#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
80217147 286#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
3610cce8
MS		 287#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
288#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
1da177e4 290
3610cce8
MS		 291#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
292#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
1da177e4 293
6c61cfe9
MS		 294/* Page status table bits for virtualization */
295#define RCP_ACC_BITS 0xf0000000UL
296#define RCP_FP_BIT 0x08000000UL
297#define RCP_PCL_BIT 0x00800000UL
298#define RCP_HR_BIT 0x00400000UL
299#define RCP_HC_BIT 0x00200000UL
300#define RCP_GR_BIT 0x00040000UL
301#define RCP_GC_BIT 0x00020000UL
302
303/* User dirty / referenced bit for KVM's migration feature */
304#define KVM_UR_BIT 0x00008000UL
305#define KVM_UC_BIT 0x00004000UL
306
f4815ac6 307#else /* CONFIG_64BIT */
1da177e4 308
3610cce8
MS		 309/* Bits in the segment/region table address-space-control-element */
310#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
311#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
312#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
313#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
314#define _ASCE_REAL_SPACE 0x20 /* real space control */
315#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
316#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
317#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
318#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
319#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
320#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
321
322/* Bits in the region table entry */
323#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
324#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
325#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
326#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
327#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
328#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
329#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
330
331#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
332#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
333#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
334#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
335#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
336#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
337
18da2369
HC		 338#define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
339
1da177e4 340/* Bits in the segment table entry */
3610cce8
MS		 341#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
342#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
343#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1da177e4 344
3610cce8
MS		 345#define _SEGMENT_ENTRY (0)
346#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
347
53492b1d
GS		 348#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
349#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
75077afb
GS		 350#define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
351#define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT)
53492b1d 352
1ae1c1d0
GS		 353/* Set of bits not changed in pmd_modify */
354#define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
355 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
356
6c61cfe9
MS		 357/* Page status table bits for virtualization */
358#define RCP_ACC_BITS 0xf000000000000000UL
359#define RCP_FP_BIT 0x0800000000000000UL
360#define RCP_PCL_BIT 0x0080000000000000UL
361#define RCP_HR_BIT 0x0040000000000000UL
362#define RCP_HC_BIT 0x0020000000000000UL
363#define RCP_GR_BIT 0x0004000000000000UL
364#define RCP_GC_BIT 0x0002000000000000UL
365
366/* User dirty / referenced bit for KVM's migration feature */
367#define KVM_UR_BIT 0x0000800000000000UL
368#define KVM_UC_BIT 0x0000400000000000UL
369
f4815ac6 370#endif /* CONFIG_64BIT */
1da177e4
LT		 371
372/*
3610cce8
MS		 373 * A user page table pointer has the space-switch-event bit, the
374 * private-space-control bit and the storage-alteration-event-control
375 * bit set. A kernel page table pointer doesn't need them.
1da177e4 376 */
3610cce8
MS		 377#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
378 _ASCE_ALT_EVENT)
1da177e4 379
1da177e4 380/*
9282ed92 381 * Page protection definitions.
1da177e4 382 */
9282ed92
GS		 383#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
384#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
385#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
386
387#define PAGE_KERNEL PAGE_RW
388#define PAGE_COPY PAGE_RO
1da177e4
LT		 389
390/*
043d0708
MS		 391 * On s390 the page table entry has an invalid bit and a read-only bit.
392 * Read permission implies execute permission and write permission
393 * implies read permission.
1da177e4
LT		 394 */
395 /*xwr*/
9282ed92
GS		 396#define __P000 PAGE_NONE
397#define __P001 PAGE_RO
398#define __P010 PAGE_RO
399#define __P011 PAGE_RO
043d0708
MS		 400#define __P100 PAGE_RO
401#define __P101 PAGE_RO
402#define __P110 PAGE_RO
403#define __P111 PAGE_RO
9282ed92
GS		 404
405#define __S000 PAGE_NONE
406#define __S001 PAGE_RO
407#define __S010 PAGE_RW
408#define __S011 PAGE_RW
043d0708
MS		 409#define __S100 PAGE_RO
410#define __S101 PAGE_RO
411#define __S110 PAGE_RW
412#define __S111 PAGE_RW
1da177e4 413
b2fa47e6 414static inline int mm_exclusive(struct mm_struct *mm)
1da177e4 415{
b2fa47e6
MS		 416 return likely(mm == current->active_mm &&
417 atomic_read(&mm->context.attach_count) <= 1);
1da177e4 418}
1da177e4 419
b2fa47e6
MS		 420static inline int mm_has_pgste(struct mm_struct *mm)
421{
422#ifdef CONFIG_PGSTE
423 if (unlikely(mm->context.has_pgste))
424 return 1;
425#endif
426 return 0;
427}
1da177e4
LT		 428/*
429 * pgd/pmd/pte query functions
430 */
f4815ac6 431#ifndef CONFIG_64BIT
1da177e4 432
4448aaf0
AB		 433static inline int pgd_present(pgd_t pgd) { return 1; }
434static inline int pgd_none(pgd_t pgd) { return 0; }
435static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 436
190a1d72
MS		 437static inline int pud_present(pud_t pud) { return 1; }
438static inline int pud_none(pud_t pud) { return 0; }
18da2369 439static inline int pud_large(pud_t pud) { return 0; }
190a1d72
MS		 440static inline int pud_bad(pud_t pud) { return 0; }
441
f4815ac6 442#else /* CONFIG_64BIT */
1da177e4 443
5a216a20
MS		 444static inline int pgd_present(pgd_t pgd)
445{
6252d702
MS		 446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
447 return 1;
5a216a20
MS		 448 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
449}
450
451static inline int pgd_none(pgd_t pgd)
452{
6252d702
MS		 453 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
454 return 0;
5a216a20
MS		 455 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
456}
457
458static inline int pgd_bad(pgd_t pgd)
459{
6252d702
MS		 460 /*
461 * With dynamic page table levels the pgd can be a region table
462 * entry or a segment table entry. Check for the bit that are
463 * invalid for either table entry.
464 */
5a216a20 465 unsigned long mask =
6252d702 466 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 467 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
468 return (pgd_val(pgd) & mask) != 0;
469}
190a1d72
MS		 470
471static inline int pud_present(pud_t pud)
1da177e4 472{
6252d702
MS		 473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
474 return 1;
0d017923 475 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 476}
477
190a1d72 478static inline int pud_none(pud_t pud)
1da177e4 479{
6252d702
MS		 480 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
481 return 0;
0d017923 482 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
1da177e4
LT		 483}
484
18da2369
HC		 485static inline int pud_large(pud_t pud)
486{
487 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
488 return 0;
489 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
490}
491
190a1d72 492static inline int pud_bad(pud_t pud)
1da177e4 493{
6252d702
MS		 494 /*
495 * With dynamic page table levels the pud can be a region table
496 * entry or a segment table entry. Check for the bit that are
497 * invalid for either table entry.
498 */
5a216a20 499 unsigned long mask =
6252d702 500 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 501 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
502 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 503}
504
f4815ac6 505#endif /* CONFIG_64BIT */
3610cce8 506
4448aaf0 507static inline int pmd_present(pmd_t pmd)
1da177e4 508{
d8e7a33d
GS		 509 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO;
510 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE ||
511 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV);
1da177e4
LT		 512}
513
4448aaf0 514static inline int pmd_none(pmd_t pmd)
1da177e4 515{
d8e7a33d
GS		 516 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) &&
517 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO);
1da177e4
LT		 518}
519
378b1e7a
HC		 520static inline int pmd_large(pmd_t pmd)
521{
522#ifdef CONFIG_64BIT
523 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE);
524#else
525 return 0;
526#endif
527}
528
4448aaf0 529static inline int pmd_bad(pmd_t pmd)
1da177e4 530{
3610cce8
MS		 531 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
532 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
1da177e4
LT		 533}
534
75077afb
GS		 535#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
536extern void pmdp_splitting_flush(struct vm_area_struct *vma,
537 unsigned long addr, pmd_t *pmdp);
538
1ae1c1d0
GS		 539#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
540extern int pmdp_set_access_flags(struct vm_area_struct *vma,
541 unsigned long address, pmd_t *pmdp,
542 pmd_t entry, int dirty);
543
544#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
545extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
546 unsigned long address, pmd_t *pmdp);
547
548#define __HAVE_ARCH_PMD_WRITE
549static inline int pmd_write(pmd_t pmd)
550{
551 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0;
552}
553
554static inline int pmd_young(pmd_t pmd)
555{
556 return 0;
557}
558
4448aaf0 559static inline int pte_none(pte_t pte)
1da177e4 560{
83377484 561 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
1da177e4
LT		 562}
563
4448aaf0 564static inline int pte_present(pte_t pte)
1da177e4 565{
83377484
MS		 566 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
567 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
568 (!(pte_val(pte) & _PAGE_INVALID) &&
569 !(pte_val(pte) & _PAGE_SWT));
1da177e4
LT		 570}
571
4448aaf0 572static inline int pte_file(pte_t pte)
1da177e4 573{
83377484
MS		 574 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
575 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
1da177e4
LT		 576}
577
7e675137
NP		 578static inline int pte_special(pte_t pte)
579{
a08cb629 580 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 581}
582
ba8a9229 583#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 584static inline int pte_same(pte_t a, pte_t b)
585{
586 return pte_val(a) == pte_val(b);
587}
1da177e4 588
b2fa47e6 589static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 590{
b2fa47e6 591 unsigned long new = 0;
5b7baf05 592#ifdef CONFIG_PGSTE
b2fa47e6
MS		 593 unsigned long old;
594
5b7baf05 595 preempt_disable();
b2fa47e6
MS		 596 asm(
597 " lg %0,%2\n"
598 "0: lgr %1,%0\n"
599 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
600 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
601 " csg %0,%1,%2\n"
602 " jl 0b\n"
603 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
604 : "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05 605#endif
b2fa47e6 606 return __pgste(new);
5b7baf05
CB		 607}
608
b2fa47e6 609static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 610{
611#ifdef CONFIG_PGSTE
b2fa47e6
MS		 612 asm(
613 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
614 " stg %1,%0\n"
615 : "=Q" (ptep[PTRS_PER_PTE])
616 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05
CB		 617 preempt_enable();
618#endif
619}
620
b2fa47e6 621static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 622{
623#ifdef CONFIG_PGSTE
a43a9d93 624 unsigned long address, bits;
b2fa47e6
MS		 625 unsigned char skey;
626
09b53883
MS		 627 if (!pte_present(*ptep))
628 return pgste;
a43a9d93
HC		 629 address = pte_val(*ptep) & PAGE_MASK;
630 skey = page_get_storage_key(address);
b2fa47e6
MS		 631 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
632 /* Clear page changed & referenced bit in the storage key */
7c81878b
CO		 633 if (bits & _PAGE_CHANGED)
634 page_set_storage_key(address, skey ^ bits, 1);
635 else if (bits)
636 page_reset_referenced(address);
b2fa47e6
MS		 637 /* Transfer page changed & referenced bit to guest bits in pgste */
638 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
639 /* Get host changed & referenced bits from pgste */
640 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
641 /* Clear host bits in pgste. */
642 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
643 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
644 /* Copy page access key and fetch protection bit to pgste */
645 pgste_val(pgste) |=
646 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
647 /* Transfer changed and referenced to kvm user bits */
648 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
649 /* Transfer changed & referenced to pte sofware bits */
650 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */
651#endif
652 return pgste;
653
654}
655
656static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
657{
658#ifdef CONFIG_PGSTE
659 int young;
660
09b53883
MS		 661 if (!pte_present(*ptep))
662 return pgste;
b2fa47e6
MS		 663 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
664 /* Transfer page referenced bit to pte software bit (host view) */
665 if (young || (pgste_val(pgste) & RCP_HR_BIT))
666 pte_val(*ptep) |= _PAGE_SWR;
667 /* Clear host referenced bit in pgste. */
668 pgste_val(pgste) &= ~RCP_HR_BIT;
669 /* Transfer page referenced bit to guest bit in pgste */
670 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
671#endif
672 return pgste;
673
674}
675
09b53883 676static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
b2fa47e6
MS		 677{
678#ifdef CONFIG_PGSTE
a43a9d93 679 unsigned long address;
b2fa47e6
MS		 680 unsigned long okey, nkey;
681
09b53883
MS		 682 if (!pte_present(entry))
683 return;
684 address = pte_val(entry) & PAGE_MASK;
a43a9d93 685 okey = nkey = page_get_storage_key(address);
b2fa47e6
MS		 686 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
687 /* Set page access key and fetch protection bit from pgste */
688 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
689 if (okey != nkey)
a43a9d93 690 page_set_storage_key(address, nkey, 1);
5b7baf05
CB		 691#endif
692}
693
e5992f2e
MS		 694/**
695 * struct gmap_struct - guest address space
696 * @mm: pointer to the parent mm_struct
697 * @table: pointer to the page directory
480e5926 698 * @asce: address space control element for gmap page table
e5992f2e
MS		 699 * @crst_list: list of all crst tables used in the guest address space
700 */
701struct gmap {
702 struct list_head list;
703 struct mm_struct *mm;
704 unsigned long *table;
480e5926 705 unsigned long asce;
e5992f2e
MS		 706 struct list_head crst_list;
707};
708
709/**
710 * struct gmap_rmap - reverse mapping for segment table entries
711 * @next: pointer to the next gmap_rmap structure in the list
712 * @entry: pointer to a segment table entry
713 */
714struct gmap_rmap {
715 struct list_head list;
716 unsigned long *entry;
717};
718
719/**
720 * struct gmap_pgtable - gmap information attached to a page table
721 * @vmaddr: address of the 1MB segment in the process virtual memory
722 * @mapper: list of segment table entries maping a page table
723 */
724struct gmap_pgtable {
725 unsigned long vmaddr;
726 struct list_head mapper;
727};
728
729struct gmap *gmap_alloc(struct mm_struct *mm);
730void gmap_free(struct gmap *gmap);
731void gmap_enable(struct gmap *gmap);
732void gmap_disable(struct gmap *gmap);
733int gmap_map_segment(struct gmap *gmap, unsigned long from,
734 unsigned long to, unsigned long length);
735int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
499069e1 736unsigned long __gmap_fault(unsigned long address, struct gmap *);
e5992f2e 737unsigned long gmap_fault(unsigned long address, struct gmap *);
388186bc 738void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
e5992f2e 739
b2fa47e6
MS		 740/*
741 * Certain architectures need to do special things when PTEs
742 * within a page table are directly modified. Thus, the following
743 * hook is made available.
744 */
745static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
746 pte_t *ptep, pte_t entry)
747{
748 pgste_t pgste;
749
750 if (mm_has_pgste(mm)) {
751 pgste = pgste_get_lock(ptep);
09b53883 752 pgste_set_pte(ptep, pgste, entry);
b2fa47e6
MS		 753 *ptep = entry;
754 pgste_set_unlock(ptep, pgste);
755 } else
756 *ptep = entry;
757}
758
1da177e4
LT		 759/*
760 * query functions pte_write/pte_dirty/pte_young only work if
761 * pte_present() is true. Undefined behaviour if not..
762 */
4448aaf0 763static inline int pte_write(pte_t pte)
1da177e4
LT		 764{
765 return (pte_val(pte) & _PAGE_RO) == 0;
766}
767
4448aaf0 768static inline int pte_dirty(pte_t pte)
1da177e4 769{
b2fa47e6
MS		 770#ifdef CONFIG_PGSTE
771 if (pte_val(pte) & _PAGE_SWC)
772 return 1;
773#endif
1da177e4
LT		 774 return 0;
775}
776
4448aaf0 777static inline int pte_young(pte_t pte)
1da177e4 778{
b2fa47e6
MS		 779#ifdef CONFIG_PGSTE
780 if (pte_val(pte) & _PAGE_SWR)
781 return 1;
782#endif
1da177e4
LT		 783 return 0;
784}
785
1da177e4
LT		 786/*
787 * pgd/pmd/pte modification functions
788 */
789
b2fa47e6 790static inline void pgd_clear(pgd_t *pgd)
5a216a20 791{
f4815ac6 792#ifdef CONFIG_64BIT
6252d702
MS		 793 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
794 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 795#endif
5a216a20
MS		 796}
797
b2fa47e6 798static inline void pud_clear(pud_t *pud)
1da177e4 799{
f4815ac6 800#ifdef CONFIG_64BIT
6252d702
MS		 801 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
802 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 803#endif
1da177e4
LT		 804}
805
b2fa47e6 806static inline void pmd_clear(pmd_t *pmdp)
1da177e4 807{
3610cce8 808 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 809}
810
4448aaf0 811static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 812{
9282ed92 813 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1da177e4
LT		 814}
815
816/*
817 * The following pte modification functions only work if
818 * pte_present() is true. Undefined behaviour if not..
819 */
4448aaf0 820static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 821{
138c9021 822 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4
LT		 823 pte_val(pte) |= pgprot_val(newprot);
824 return pte;
825}
826
4448aaf0 827static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 828{
9282ed92 829 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT		 830 if (!(pte_val(pte) & _PAGE_INVALID))
831 pte_val(pte) |= _PAGE_RO;
832 return pte;
833}
834
4448aaf0 835static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT		 836{
837 pte_val(pte) &= ~_PAGE_RO;
838 return pte;
839}
840
4448aaf0 841static inline pte_t pte_mkclean(pte_t pte)
1da177e4 842{
b2fa47e6
MS		 843#ifdef CONFIG_PGSTE
844 pte_val(pte) &= ~_PAGE_SWC;
845#endif
1da177e4
LT		 846 return pte;
847}
848
4448aaf0 849static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 850{
1da177e4
LT		 851 return pte;
852}
853
4448aaf0 854static inline pte_t pte_mkold(pte_t pte)
1da177e4 855{
b2fa47e6
MS		 856#ifdef CONFIG_PGSTE
857 pte_val(pte) &= ~_PAGE_SWR;
858#endif
1da177e4
LT		 859 return pte;
860}
861
4448aaf0 862static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 863{
1da177e4
LT		 864 return pte;
865}
866
7e675137
NP		 867static inline pte_t pte_mkspecial(pte_t pte)
868{
a08cb629 869 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 870 return pte;
871}
872
84afdcee
HC		 873#ifdef CONFIG_HUGETLB_PAGE
874static inline pte_t pte_mkhuge(pte_t pte)
875{
876 /*
877 * PROT_NONE needs to be remapped from the pte type to the ste type.
878 * The HW invalid bit is also different for pte and ste. The pte
879 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
880 * bit, so we don't have to clear it.
881 */
882 if (pte_val(pte) & _PAGE_INVALID) {
883 if (pte_val(pte) & _PAGE_SWT)
884 pte_val(pte) |= _HPAGE_TYPE_NONE;
885 pte_val(pte) |= _SEGMENT_ENTRY_INV;
886 }
887 /*
888 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
889 * table entry.
890 */
891 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
892 /*
893 * Also set the change-override bit because we don't need dirty bit
894 * tracking for hugetlbfs pages.
895 */
896 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
897 return pte;
898}
899#endif
900
15e86b0c 901/*
b2fa47e6 902 * Get (and clear) the user dirty bit for a pte.
15e86b0c 903 */
b2fa47e6
MS		 904static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
905 pte_t *ptep)
15e86b0c 906{
b2fa47e6
MS		 907 pgste_t pgste;
908 int dirty = 0;
909
910 if (mm_has_pgste(mm)) {
911 pgste = pgste_get_lock(ptep);
912 pgste = pgste_update_all(ptep, pgste);
913 dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
914 pgste_val(pgste) &= ~KVM_UC_BIT;
915 pgste_set_unlock(ptep, pgste);
916 return dirty;
15e86b0c 917 }
15e86b0c
FF		 918 return dirty;
919}
b2fa47e6
MS		 920
921/*
922 * Get (and clear) the user referenced bit for a pte.
923 */
924static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
925 pte_t *ptep)
926{
927 pgste_t pgste;
928 int young = 0;
929
930 if (mm_has_pgste(mm)) {
931 pgste = pgste_get_lock(ptep);
932 pgste = pgste_update_young(ptep, pgste);
933 young = !!(pgste_val(pgste) & KVM_UR_BIT);
934 pgste_val(pgste) &= ~KVM_UR_BIT;
935 pgste_set_unlock(ptep, pgste);
936 }
937 return young;
938}
15e86b0c 939
ba8a9229
MS		 940#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
941static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
942 unsigned long addr, pte_t *ptep)
1da177e4 943{
b2fa47e6
MS		 944 pgste_t pgste;
945 pte_t pte;
946
947 if (mm_has_pgste(vma->vm_mm)) {
948 pgste = pgste_get_lock(ptep);
949 pgste = pgste_update_young(ptep, pgste);
950 pte = *ptep;
951 *ptep = pte_mkold(pte);
952 pgste_set_unlock(ptep, pgste);
953 return pte_young(pte);
954 }
1da177e4
LT		 955 return 0;
956}
957
ba8a9229
MS		 958#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
959static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
960 unsigned long address, pte_t *ptep)
1da177e4 961{
5b7baf05
CB		 962 /* No need to flush TLB
963 * On s390 reference bits are in storage key and never in TLB
964 * With virtualization we handle the reference bit, without we
965 * we can simply return */
5b7baf05 966 return ptep_test_and_clear_young(vma, address, ptep);
1da177e4
LT		 967}
968
9282ed92 969static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 970{
9282ed92 971 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
f4815ac6 972#ifndef CONFIG_64BIT
146e4b3c 973 /* pto must point to the start of the segment table */
1da177e4 974 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 975#else
976 /* ipte in zarch mode can do the math */
977 pte_t *pto = ptep;
978#endif
94c12cc7
MS		 979 asm volatile(
980 " ipte %2,%3"
981 : "=m" (*ptep) : "m" (*ptep),
982 "a" (pto), "a" (address));
1da177e4 983 }
9282ed92
GS		 984}
985
ba8a9229
MS		 986/*
987 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
988 * both clear the TLB for the unmapped pte. The reason is that
989 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
990 * to modify an active pte. The sequence is
991 * 1) ptep_get_and_clear
992 * 2) set_pte_at
993 * 3) flush_tlb_range
994 * On s390 the tlb needs to get flushed with the modification of the pte
995 * if the pte is active. The only way how this can be implemented is to
996 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
997 * is a nop.
998 */
999#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 1000static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1001 unsigned long address, pte_t *ptep)
1002{
1003 pgste_t pgste;
1004 pte_t pte;
1005
1006 mm->context.flush_mm = 1;
1007 if (mm_has_pgste(mm))
1008 pgste = pgste_get_lock(ptep);
1009
1010 pte = *ptep;
1011 if (!mm_exclusive(mm))
1012 __ptep_ipte(address, ptep);
1013 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1014
1015 if (mm_has_pgste(mm)) {
1016 pgste = pgste_update_all(&pte, pgste);
1017 pgste_set_unlock(ptep, pgste);
1018 }
1019 return pte;
1020}
1021
1022#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1023static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1024 unsigned long address,
1025 pte_t *ptep)
1026{
1027 pte_t pte;
1028
1029 mm->context.flush_mm = 1;
1030 if (mm_has_pgste(mm))
1031 pgste_get_lock(ptep);
1032
1033 pte = *ptep;
1034 if (!mm_exclusive(mm))
1035 __ptep_ipte(address, ptep);
1036 return pte;
1037}
1038
1039static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1040 unsigned long address,
1041 pte_t *ptep, pte_t pte)
1042{
1043 *ptep = pte;
1044 if (mm_has_pgste(mm))
1045 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
1046}
ba8a9229
MS		 1047
1048#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 1049static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1050 unsigned long address, pte_t *ptep)
1051{
b2fa47e6
MS		 1052 pgste_t pgste;
1053 pte_t pte;
1054
1055 if (mm_has_pgste(vma->vm_mm))
1056 pgste = pgste_get_lock(ptep);
1057
1058 pte = *ptep;
1059 __ptep_ipte(address, ptep);
1060 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1061
1062 if (mm_has_pgste(vma->vm_mm)) {
1063 pgste = pgste_update_all(&pte, pgste);
1064 pgste_set_unlock(ptep, pgste);
1065 }
1da177e4
LT		 1066 return pte;
1067}
1068
ba8a9229
MS		 1069/*
1070 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1071 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1072 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1073 * cannot be accessed while the batched unmap is running. In this case
1074 * full==1 and a simple pte_clear is enough. See tlb.h.
1075 */
1076#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1077static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1078 unsigned long address,
ba8a9229 1079 pte_t *ptep, int full)
1da177e4 1080{
b2fa47e6
MS		 1081 pgste_t pgste;
1082 pte_t pte;
1083
1084 if (mm_has_pgste(mm))
1085 pgste = pgste_get_lock(ptep);
ba8a9229 1086
b2fa47e6
MS		 1087 pte = *ptep;
1088 if (!full)
1089 __ptep_ipte(address, ptep);
1090 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1091
1092 if (mm_has_pgste(mm)) {
1093 pgste = pgste_update_all(&pte, pgste);
1094 pgste_set_unlock(ptep, pgste);
1095 }
ba8a9229 1096 return pte;
1da177e4
LT		 1097}
1098
ba8a9229 1099#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1100static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1101 unsigned long address, pte_t *ptep)
1102{
1103 pgste_t pgste;
1104 pte_t pte = *ptep;
1105
1106 if (pte_write(pte)) {
1107 mm->context.flush_mm = 1;
1108 if (mm_has_pgste(mm))
1109 pgste = pgste_get_lock(ptep);
1110
1111 if (!mm_exclusive(mm))
1112 __ptep_ipte(address, ptep);
1113 *ptep = pte_wrprotect(pte);
1114
1115 if (mm_has_pgste(mm))
1116 pgste_set_unlock(ptep, pgste);
1117 }
1118 return pte;
1119}
ba8a9229
MS		 1120
1121#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1122static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1123 unsigned long address, pte_t *ptep,
1124 pte_t entry, int dirty)
1125{
1126 pgste_t pgste;
1127
1128 if (pte_same(*ptep, entry))
1129 return 0;
1130 if (mm_has_pgste(vma->vm_mm))
1131 pgste = pgste_get_lock(ptep);
1132
1133 __ptep_ipte(address, ptep);
1134 *ptep = entry;
1135
1136 if (mm_has_pgste(vma->vm_mm))
1137 pgste_set_unlock(ptep, pgste);
1138 return 1;
1139}
1da177e4 1140
1da177e4
LT		 1141/*
1142 * Conversion functions: convert a page and protection to a page entry,
1143 * and a page entry and page directory to the page they refer to.
1144 */
1145static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1146{
1147 pte_t __pte;
1148 pte_val(__pte) = physpage + pgprot_val(pgprot);
1149 return __pte;
1150}
1151
2dcea57a
HC		 1152static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1153{
0b2b6e1d 1154 unsigned long physpage = page_to_phys(page);
1da177e4 1155
2dcea57a
HC		 1156 return mk_pte_phys(physpage, pgprot);
1157}
1158
190a1d72
MS		 1159#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1160#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1161#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1162#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1163
190a1d72
MS		 1164#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1165#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1166
f4815ac6 1167#ifndef CONFIG_64BIT
1da177e4 1168
190a1d72
MS		 1169#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1170#define pud_deref(pmd) ({ BUG(); 0UL; })
1171#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1172
190a1d72
MS		 1173#define pud_offset(pgd, address) ((pud_t *) pgd)
1174#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1175
f4815ac6 1176#else /* CONFIG_64BIT */
1da177e4 1177
190a1d72
MS		 1178#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1179#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1180#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1181
5a216a20
MS		 1182static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1183{
6252d702
MS		 1184 pud_t *pud = (pud_t *) pgd;
1185 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1186 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1187 return pud + pud_index(address);
1188}
1da177e4 1189
190a1d72 1190static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1191{
6252d702
MS		 1192 pmd_t *pmd = (pmd_t *) pud;
1193 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1194 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1195 return pmd + pmd_index(address);
1da177e4
LT		 1196}
1197
f4815ac6 1198#endif /* CONFIG_64BIT */
1da177e4 1199
190a1d72
MS		 1200#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1201#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1202#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1203
190a1d72 1204#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 1205
190a1d72
MS		 1206/* Find an entry in the lowest level page table.. */
1207#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1208#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1209#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1210#define pte_unmap(pte) do { } while (0)
1da177e4 1211
1ae1c1d0
GS		 1212static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1213{
1214 unsigned long sto = (unsigned long) pmdp -
1215 pmd_index(address) * sizeof(pmd_t);
1216
1217 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
1218 asm volatile(
1219 " .insn rrf,0xb98e0000,%2,%3,0,0"
1220 : "=m" (*pmdp)
1221 : "m" (*pmdp), "a" (sto),
1222 "a" ((address & HPAGE_MASK))
1223 : "cc"
1224 );
1225 }
1226}
1227
75077afb 1228#ifdef CONFIG_TRANSPARENT_HUGEPAGE
d8e7a33d
GS		 1229
1230#define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE)
1231#define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO)
1232#define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW)
1233
9501d09f
GS		 1234#define __HAVE_ARCH_PGTABLE_DEPOSIT
1235extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
1236
1237#define __HAVE_ARCH_PGTABLE_WITHDRAW
1238extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
1239
75077afb
GS		 1240static inline int pmd_trans_splitting(pmd_t pmd)
1241{
1242 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1243}
1ae1c1d0
GS		 1244
1245static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1246 pmd_t *pmdp, pmd_t entry)
1247{
1248 *pmdp = entry;
1249}
1250
1251static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1252{
d8e7a33d
GS		 1253 /*
1254 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
1255 * Convert to segment table entry format.
1256 */
1257 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1258 return pgprot_val(SEGMENT_NONE);
1259 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1260 return pgprot_val(SEGMENT_RO);
1261 return pgprot_val(SEGMENT_RW);
1ae1c1d0
GS		 1262}
1263
1264static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1265{
1266 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1267 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1268 return pmd;
1269}
1270
1271static inline pmd_t pmd_mkhuge(pmd_t pmd)
1272{
1273 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1274 return pmd;
1275}
1276
1277static inline pmd_t pmd_mkwrite(pmd_t pmd)
1278{
d8e7a33d
GS		 1279 /* Do not clobber _HPAGE_TYPE_NONE pages! */
1280 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV))
1281 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
1ae1c1d0
GS		 1282 return pmd;
1283}
1284
1285static inline pmd_t pmd_wrprotect(pmd_t pmd)
1286{
1287 pmd_val(pmd) |= _SEGMENT_ENTRY_RO;
1288 return pmd;
1289}
1290
1291static inline pmd_t pmd_mkdirty(pmd_t pmd)
1292{
1293 /* No dirty bit in the segment table entry. */
1294 return pmd;
1295}
1296
1297static inline pmd_t pmd_mkold(pmd_t pmd)
1298{
1299 /* No referenced bit in the segment table entry. */
1300 return pmd;
1301}
1302
1303static inline pmd_t pmd_mkyoung(pmd_t pmd)
1304{
1305 /* No referenced bit in the segment table entry. */
1306 return pmd;
1307}
1308
1309#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1310static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1311 unsigned long address, pmd_t *pmdp)
1312{
1313 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK;
1314 long tmp, rc;
1315 int counter;
1316
1317 rc = 0;
1318 if (MACHINE_HAS_RRBM) {
1319 counter = PTRS_PER_PTE >> 6;
1320 asm volatile(
1321 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */
1322 " ogr %1,%0\n"
1323 " la %3,0(%4,%3)\n"
1324 " brct %2,0b\n"
1325 : "=&d" (tmp), "+&d" (rc), "+d" (counter),
1326 "+a" (pmd_addr)
1327 : "a" (64 * 4096UL) : "cc");
1328 rc = !!rc;
1329 } else {
1330 counter = PTRS_PER_PTE;
1331 asm volatile(
1332 "0: rrbe 0,%2\n"
1333 " la %2,0(%3,%2)\n"
1334 " brc 12,1f\n"
1335 " lhi %0,1\n"
1336 "1: brct %1,0b\n"
1337 : "+d" (rc), "+d" (counter), "+a" (pmd_addr)
1338 : "a" (4096UL) : "cc");
1339 }
1340 return rc;
1341}
1342
1343#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1344static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1345 unsigned long address, pmd_t *pmdp)
1346{
1347 pmd_t pmd = *pmdp;
1348
1349 __pmd_idte(address, pmdp);
1350 pmd_clear(pmdp);
1351 return pmd;
1352}
1353
1354#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1355static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1356 unsigned long address, pmd_t *pmdp)
1357{
1358 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1359}
1360
1361#define __HAVE_ARCH_PMDP_INVALIDATE
1362static inline void pmdp_invalidate(struct vm_area_struct *vma,
1363 unsigned long address, pmd_t *pmdp)
1364{
1365 __pmd_idte(address, pmdp);
1366}
1367
be328650
GS		 1368#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1369static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1370 unsigned long address, pmd_t *pmdp)
1371{
1372 pmd_t pmd = *pmdp;
1373
1374 if (pmd_write(pmd)) {
1375 __pmd_idte(address, pmdp);
1376 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1377 }
1378}
1379
1ae1c1d0
GS		 1380static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1381{
1382 pmd_t __pmd;
1383 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1384 return __pmd;
1385}
1386
1387#define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1388#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1389
1390static inline int pmd_trans_huge(pmd_t pmd)
1391{
1392 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1393}
1394
1395static inline int has_transparent_hugepage(void)
1396{
1397 return MACHINE_HAS_HPAGE ? 1 : 0;
1398}
1399
1400static inline unsigned long pmd_pfn(pmd_t pmd)
1401{
171c4006 1402 return pmd_val(pmd) >> PAGE_SHIFT;
1ae1c1d0 1403}
75077afb
GS		 1404#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1405
1da177e4
LT		 1406/*
1407 * 31 bit swap entry format:
1408 * A page-table entry has some bits we have to treat in a special way.
1409 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1410 * exception will occur instead of a page translation exception. The
1411 * specifiation exception has the bad habit not to store necessary
1412 * information in the lowcore.
1413 * Bit 21 and bit 22 are the page invalid bit and the page protection
1414 * bit. We set both to indicate a swapped page.
1415 * Bit 30 and 31 are used to distinguish the different page types. For
1416 * a swapped page these bits need to be zero.
1417 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1418 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1419 * plus 24 for the offset.
1420 * 0| offset |0110|o|type |00|
1421 * 0 0000000001111111111 2222 2 22222 33
1422 * 0 1234567890123456789 0123 4 56789 01
1423 *
1424 * 64 bit swap entry format:
1425 * A page-table entry has some bits we have to treat in a special way.
1426 * Bits 52 and bit 55 have to be zero, otherwise an specification
1427 * exception will occur instead of a page translation exception. The
1428 * specifiation exception has the bad habit not to store necessary
1429 * information in the lowcore.
1430 * Bit 53 and bit 54 are the page invalid bit and the page protection
1431 * bit. We set both to indicate a swapped page.
1432 * Bit 62 and 63 are used to distinguish the different page types. For
1433 * a swapped page these bits need to be zero.
1434 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1435 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1436 * plus 56 for the offset.
1437 * | offset |0110|o|type |00|
1438 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1439 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1440 */
f4815ac6 1441#ifndef CONFIG_64BIT
1da177e4
LT		 1442#define __SWP_OFFSET_MASK (~0UL >> 12)
1443#else
1444#define __SWP_OFFSET_MASK (~0UL >> 11)
1445#endif
4448aaf0 1446static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1447{
1448 pte_t pte;
1449 offset &= __SWP_OFFSET_MASK;
9282ed92 1450 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT		 1451 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1452 return pte;
1453}
1454
1455#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1456#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1457#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1458
1459#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1460#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1461
f4815ac6 1462#ifndef CONFIG_64BIT
1da177e4 1463# define PTE_FILE_MAX_BITS 26
f4815ac6 1464#else /* CONFIG_64BIT */
1da177e4 1465# define PTE_FILE_MAX_BITS 59
f4815ac6 1466#endif /* CONFIG_64BIT */
1da177e4
LT		 1467
1468#define pte_to_pgoff(__pte) \
1469 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1470
1471#define pgoff_to_pte(__off) \
1472 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 1473 | _PAGE_TYPE_FILE })
1da177e4
LT		 1474
1475#endif /* !__ASSEMBLY__ */
1476
1477#define kern_addr_valid(addr) (1)
1478
17f34580
HC		 1479extern int vmem_add_mapping(unsigned long start, unsigned long size);
1480extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1481extern int s390_enable_sie(void);
f4eb07c1 1482
1da177e4
LT		 1483/*
1484 * No page table caches to initialise
1485 */
1486#define pgtable_cache_init() do { } while (0)
1487
1da177e4
LT		 1488#include <asm-generic/pgtable.h>
1489
1490#endif /* _S390_PAGE_H */
Linux kernel - Deliverables
This page took 0.712355 seconds and 5 git commands to generate.