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thp: make MADV_HUGEPAGE check for mm->def_flags
[deliverable/linux.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
1da177e4 1/*
1da177e4 2 * S390 version
a53c8fab 3 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11#ifndef _ASM_S390_PGTABLE_H
12#define _ASM_S390_PGTABLE_H
13
1da177e4
LT		 14/*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29#ifndef __ASSEMBLY__
9789db08 30#include <linux/sched.h>
2dcea57a 31#include <linux/mm_types.h>
1da177e4 32#include <asm/bug.h>
b2fa47e6 33#include <asm/page.h>
1da177e4 34
1da177e4
LT		 35extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
36extern void paging_init(void);
2b67fc46 37extern void vmem_map_init(void);
92f842ea 38extern void fault_init(void);
1da177e4
LT		 39
40/*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
4b3073e1 44#define update_mmu_cache(vma, address, ptep) do { } while (0)
1da177e4
LT		 45
46/*
238ec4ef 47 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 48 * for zero-mapped memory areas etc..
49 */
238ec4ef
MS		 50
51extern unsigned long empty_zero_page;
52extern unsigned long zero_page_mask;
53
54#define ZERO_PAGE(vaddr) \
55 (virt_to_page((void *)(empty_zero_page + \
56 (((unsigned long)(vaddr)) &zero_page_mask))))
57
58#define is_zero_pfn is_zero_pfn
59static inline int is_zero_pfn(unsigned long pfn)
60{
61 extern unsigned long zero_pfn;
62 unsigned long offset_from_zero_pfn = pfn - zero_pfn;
63 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT);
64}
65
66#define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr))
67
1da177e4
LT		 68#endif /* !__ASSEMBLY__ */
69
70/*
71 * PMD_SHIFT determines the size of the area a second-level page
72 * table can map
73 * PGDIR_SHIFT determines what a third-level page table entry can map
74 */
f4815ac6 75#ifndef CONFIG_64BIT
146e4b3c
MS		 76# define PMD_SHIFT 20
77# define PUD_SHIFT 20
78# define PGDIR_SHIFT 20
f4815ac6 79#else /* CONFIG_64BIT */
146e4b3c 80# define PMD_SHIFT 20
190a1d72 81# define PUD_SHIFT 31
5a216a20 82# define PGDIR_SHIFT 42
f4815ac6 83#endif /* CONFIG_64BIT */
1da177e4
LT		 84
85#define PMD_SIZE (1UL << PMD_SHIFT)
86#define PMD_MASK (~(PMD_SIZE-1))
190a1d72
MS		 87#define PUD_SIZE (1UL << PUD_SHIFT)
88#define PUD_MASK (~(PUD_SIZE-1))
5a216a20
MS		 89#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
90#define PGDIR_MASK (~(PGDIR_SIZE-1))
1da177e4
LT		 91
92/*
93 * entries per page directory level: the S390 is two-level, so
94 * we don't really have any PMD directory physically.
95 * for S390 segment-table entries are combined to one PGD
96 * that leads to 1024 pte per pgd
97 */
146e4b3c 98#define PTRS_PER_PTE 256
f4815ac6 99#ifndef CONFIG_64BIT
146e4b3c 100#define PTRS_PER_PMD 1
5a216a20 101#define PTRS_PER_PUD 1
f4815ac6 102#else /* CONFIG_64BIT */
146e4b3c 103#define PTRS_PER_PMD 2048
5a216a20 104#define PTRS_PER_PUD 2048
f4815ac6 105#endif /* CONFIG_64BIT */
146e4b3c 106#define PTRS_PER_PGD 2048
1da177e4 107
d455a369
HD		 108#define FIRST_USER_ADDRESS 0
109
1da177e4
LT		 110#define pte_ERROR(e) \
111 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
112#define pmd_ERROR(e) \
113 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
190a1d72
MS		 114#define pud_ERROR(e) \
115 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
1da177e4
LT		 116#define pgd_ERROR(e) \
117 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
118
119#ifndef __ASSEMBLY__
120/*
5fd9c6e2 121 * The vmalloc area will always be on the topmost area of the kernel
7d3f661e 122 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc,
5fd9c6e2
CB		 123 * which should be enough for any sane case.
124 * By putting vmalloc at the top, we maximise the gap between physical
125 * memory and vmalloc to catch misplaced memory accesses. As a side
126 * effect, this also makes sure that 64 bit module code cannot be used
127 * as system call address.
8b62bc96 128 */
239a6425 129extern unsigned long VMALLOC_START;
14045ebf
MS		 130extern unsigned long VMALLOC_END;
131extern struct page *vmemmap;
239a6425 132
14045ebf 133#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 134
1da177e4
LT		 135/*
136 * A 31 bit pagetable entry of S390 has following format:
137 * | PFRA | | OS |
138 * 0 0IP0
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
141 *
142 * I Page-Invalid Bit: Page is not available for address-translation
143 * P Page-Protection Bit: Store access not possible for page
144 *
145 * A 31 bit segmenttable entry of S390 has following format:
146 * | P-table origin | |PTL
147 * 0 IC
148 * 00000000001111111111222222222233
149 * 01234567890123456789012345678901
150 *
151 * I Segment-Invalid Bit: Segment is not available for address-translation
152 * C Common-Segment Bit: Segment is not private (PoP 3-30)
153 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
154 *
155 * The 31 bit segmenttable origin of S390 has following format:
156 *
157 * |S-table origin | | STL |
158 * X **GPS
159 * 00000000001111111111222222222233
160 * 01234567890123456789012345678901
161 *
162 * X Space-Switch event:
163 * G Segment-Invalid Bit: *
164 * P Private-Space Bit: Segment is not private (PoP 3-30)
165 * S Storage-Alteration:
166 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
167 *
168 * A 64 bit pagetable entry of S390 has following format:
6a985c61 169 * | PFRA |0IPC| OS |
1da177e4
LT		 170 * 0000000000111111111122222222223333333333444444444455555555556666
171 * 0123456789012345678901234567890123456789012345678901234567890123
172 *
173 * I Page-Invalid Bit: Page is not available for address-translation
174 * P Page-Protection Bit: Store access not possible for page
6a985c61 175 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 176 *
177 * A 64 bit segmenttable entry of S390 has following format:
178 * | P-table origin | TT
179 * 0000000000111111111122222222223333333333444444444455555555556666
180 * 0123456789012345678901234567890123456789012345678901234567890123
181 *
182 * I Segment-Invalid Bit: Segment is not available for address-translation
183 * C Common-Segment Bit: Segment is not private (PoP 3-30)
184 * P Page-Protection Bit: Store access not possible for page
185 * TT Type 00
186 *
187 * A 64 bit region table entry of S390 has following format:
188 * | S-table origin | TF TTTL
189 * 0000000000111111111122222222223333333333444444444455555555556666
190 * 0123456789012345678901234567890123456789012345678901234567890123
191 *
192 * I Segment-Invalid Bit: Segment is not available for address-translation
193 * TT Type 01
194 * TF
190a1d72 195 * TL Table length
1da177e4
LT		 196 *
197 * The 64 bit regiontable origin of S390 has following format:
198 * | region table origon | DTTL
199 * 0000000000111111111122222222223333333333444444444455555555556666
200 * 0123456789012345678901234567890123456789012345678901234567890123
201 *
202 * X Space-Switch event:
203 * G Segment-Invalid Bit:
204 * P Private-Space Bit:
205 * S Storage-Alteration:
206 * R Real space
207 * TL Table-Length:
208 *
209 * A storage key has the following format:
210 * | ACC |F|R|C|0|
211 * 0 3 4 5 6 7
212 * ACC: access key
213 * F : fetch protection bit
214 * R : referenced bit
215 * C : changed bit
216 */
217
218/* Hardware bits in the page table entry */
6a985c61 219#define _PAGE_CO 0x100 /* HW Change-bit override */
83377484
MS		 220#define _PAGE_RO 0x200 /* HW read-only bit */
221#define _PAGE_INVALID 0x400 /* HW invalid bit */
3610cce8
MS		 222
223/* Software bits in the page table entry */
83377484
MS		 224#define _PAGE_SWT 0x001 /* SW pte type bit t */
225#define _PAGE_SWX 0x002 /* SW pte type bit x */
b2fa47e6
MS		 226#define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
227#define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
228#define _PAGE_SPECIAL 0x010 /* SW associated with special page */
a08cb629 229#define __HAVE_ARCH_PTE_SPECIAL
1da177e4 230
138c9021 231/* Set of bits not changed in pte_modify */
b2fa47e6 232#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
138c9021 233
83377484 234/* Six different types of pages. */
9282ed92
GS		 235#define _PAGE_TYPE_EMPTY 0x400
236#define _PAGE_TYPE_NONE 0x401
83377484
MS		 237#define _PAGE_TYPE_SWAP 0x403
238#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
9282ed92
GS		 239#define _PAGE_TYPE_RO 0x200
240#define _PAGE_TYPE_RW 0x000
1da177e4 241
53492b1d
GS		 242/*
243 * Only four types for huge pages, using the invalid bit and protection bit
244 * of a segment table entry.
245 */
246#define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
247#define _HPAGE_TYPE_NONE 0x220
248#define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
249#define _HPAGE_TYPE_RW 0x000
250
83377484
MS		 251/*
252 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
253 * pte_none and pte_file to find out the pte type WITHOUT holding the page
254 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
255 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
256 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
257 * This change is done while holding the lock, but the intermediate step
258 * of a previously valid pte with the hw invalid bit set can be observed by
259 * handle_pte_fault. That makes it necessary that all valid pte types with
260 * the hw invalid bit set must be distinguishable from the four pte types
261 * empty, none, swap and file.
262 *
263 * irxt ipte irxt
264 * _PAGE_TYPE_EMPTY 1000 -> 1000
265 * _PAGE_TYPE_NONE 1001 -> 1001
266 * _PAGE_TYPE_SWAP 1011 -> 1011
267 * _PAGE_TYPE_FILE 11?1 -> 11?1
268 * _PAGE_TYPE_RO 0100 -> 1100
269 * _PAGE_TYPE_RW 0000 -> 1000
270 *
c1821c2e 271 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
83377484
MS		 272 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
273 * pte_file is true for bits combinations 1101, 1111
c1821c2e 274 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
83377484
MS		 275 */
276
f4815ac6 277#ifndef CONFIG_64BIT
1da177e4 278
3610cce8
MS		 279/* Bits in the segment table address-space-control-element */
280#define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
281#define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
282#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
283#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
284#define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
1da177e4 285
3610cce8
MS		 286/* Bits in the segment table entry */
287#define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
80217147 288#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
3610cce8
MS		 289#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
290#define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
291#define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
1da177e4 292
3610cce8
MS		 293#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
294#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
1da177e4 295
6c61cfe9
MS		 296/* Page status table bits for virtualization */
297#define RCP_ACC_BITS 0xf0000000UL
298#define RCP_FP_BIT 0x08000000UL
299#define RCP_PCL_BIT 0x00800000UL
300#define RCP_HR_BIT 0x00400000UL
301#define RCP_HC_BIT 0x00200000UL
302#define RCP_GR_BIT 0x00040000UL
303#define RCP_GC_BIT 0x00020000UL
304
305/* User dirty / referenced bit for KVM's migration feature */
306#define KVM_UR_BIT 0x00008000UL
307#define KVM_UC_BIT 0x00004000UL
308
f4815ac6 309#else /* CONFIG_64BIT */
1da177e4 310
3610cce8
MS		 311/* Bits in the segment/region table address-space-control-element */
312#define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
313#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
314#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
315#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
316#define _ASCE_REAL_SPACE 0x20 /* real space control */
317#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
318#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
319#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
320#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
321#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
322#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
323
324/* Bits in the region table entry */
325#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
326#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
327#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
328#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
329#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
330#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
331#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
332
333#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
334#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
335#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
336#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
337#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
338#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
339
1da177e4 340/* Bits in the segment table entry */
3610cce8
MS		 341#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
342#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
343#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1da177e4 344
3610cce8
MS		 345#define _SEGMENT_ENTRY (0)
346#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
347
53492b1d
GS		 348#define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
349#define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
350
6c61cfe9
MS		 351/* Page status table bits for virtualization */
352#define RCP_ACC_BITS 0xf000000000000000UL
353#define RCP_FP_BIT 0x0800000000000000UL
354#define RCP_PCL_BIT 0x0080000000000000UL
355#define RCP_HR_BIT 0x0040000000000000UL
356#define RCP_HC_BIT 0x0020000000000000UL
357#define RCP_GR_BIT 0x0004000000000000UL
358#define RCP_GC_BIT 0x0002000000000000UL
359
360/* User dirty / referenced bit for KVM's migration feature */
361#define KVM_UR_BIT 0x0000800000000000UL
362#define KVM_UC_BIT 0x0000400000000000UL
363
f4815ac6 364#endif /* CONFIG_64BIT */
1da177e4
LT		 365
366/*
3610cce8
MS		 367 * A user page table pointer has the space-switch-event bit, the
368 * private-space-control bit and the storage-alteration-event-control
369 * bit set. A kernel page table pointer doesn't need them.
1da177e4 370 */
3610cce8
MS		 371#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
372 _ASCE_ALT_EVENT)
1da177e4 373
1da177e4 374/*
9282ed92 375 * Page protection definitions.
1da177e4 376 */
9282ed92
GS		 377#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
378#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
379#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
380
381#define PAGE_KERNEL PAGE_RW
382#define PAGE_COPY PAGE_RO
1da177e4
LT		 383
384/*
043d0708
MS		 385 * On s390 the page table entry has an invalid bit and a read-only bit.
386 * Read permission implies execute permission and write permission
387 * implies read permission.
1da177e4
LT		 388 */
389 /*xwr*/
9282ed92
GS		 390#define __P000 PAGE_NONE
391#define __P001 PAGE_RO
392#define __P010 PAGE_RO
393#define __P011 PAGE_RO
043d0708
MS		 394#define __P100 PAGE_RO
395#define __P101 PAGE_RO
396#define __P110 PAGE_RO
397#define __P111 PAGE_RO
9282ed92
GS		 398
399#define __S000 PAGE_NONE
400#define __S001 PAGE_RO
401#define __S010 PAGE_RW
402#define __S011 PAGE_RW
043d0708
MS		 403#define __S100 PAGE_RO
404#define __S101 PAGE_RO
405#define __S110 PAGE_RW
406#define __S111 PAGE_RW
1da177e4 407
b2fa47e6 408static inline int mm_exclusive(struct mm_struct *mm)
1da177e4 409{
b2fa47e6
MS		 410 return likely(mm == current->active_mm &&
411 atomic_read(&mm->context.attach_count) <= 1);
1da177e4 412}
1da177e4 413
b2fa47e6
MS		 414static inline int mm_has_pgste(struct mm_struct *mm)
415{
416#ifdef CONFIG_PGSTE
417 if (unlikely(mm->context.has_pgste))
418 return 1;
419#endif
420 return 0;
421}
1da177e4
LT		 422/*
423 * pgd/pmd/pte query functions
424 */
f4815ac6 425#ifndef CONFIG_64BIT
1da177e4 426
4448aaf0
AB		 427static inline int pgd_present(pgd_t pgd) { return 1; }
428static inline int pgd_none(pgd_t pgd) { return 0; }
429static inline int pgd_bad(pgd_t pgd) { return 0; }
1da177e4 430
190a1d72
MS		 431static inline int pud_present(pud_t pud) { return 1; }
432static inline int pud_none(pud_t pud) { return 0; }
433static inline int pud_bad(pud_t pud) { return 0; }
434
f4815ac6 435#else /* CONFIG_64BIT */
1da177e4 436
5a216a20
MS		 437static inline int pgd_present(pgd_t pgd)
438{
6252d702
MS		 439 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
440 return 1;
5a216a20
MS		 441 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
442}
443
444static inline int pgd_none(pgd_t pgd)
445{
6252d702
MS		 446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
447 return 0;
5a216a20
MS		 448 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
449}
450
451static inline int pgd_bad(pgd_t pgd)
452{
6252d702
MS		 453 /*
454 * With dynamic page table levels the pgd can be a region table
455 * entry or a segment table entry. Check for the bit that are
456 * invalid for either table entry.
457 */
5a216a20 458 unsigned long mask =
6252d702 459 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 460 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
461 return (pgd_val(pgd) & mask) != 0;
462}
190a1d72
MS		 463
464static inline int pud_present(pud_t pud)
1da177e4 465{
6252d702
MS		 466 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
467 return 1;
0d017923 468 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 469}
470
190a1d72 471static inline int pud_none(pud_t pud)
1da177e4 472{
6252d702
MS		 473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
474 return 0;
0d017923 475 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
1da177e4
LT		 476}
477
190a1d72 478static inline int pud_bad(pud_t pud)
1da177e4 479{
6252d702
MS		 480 /*
481 * With dynamic page table levels the pud can be a region table
482 * entry or a segment table entry. Check for the bit that are
483 * invalid for either table entry.
484 */
5a216a20 485 unsigned long mask =
6252d702 486 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
5a216a20
MS		 487 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
488 return (pud_val(pud) & mask) != 0;
1da177e4
LT		 489}
490
f4815ac6 491#endif /* CONFIG_64BIT */
3610cce8 492
4448aaf0 493static inline int pmd_present(pmd_t pmd)
1da177e4 494{
0d017923 495 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 496}
497
4448aaf0 498static inline int pmd_none(pmd_t pmd)
1da177e4 499{
0d017923 500 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
1da177e4
LT		 501}
502
4448aaf0 503static inline int pmd_bad(pmd_t pmd)
1da177e4 504{
3610cce8
MS		 505 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
506 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
1da177e4
LT		 507}
508
4448aaf0 509static inline int pte_none(pte_t pte)
1da177e4 510{
83377484 511 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
1da177e4
LT		 512}
513
4448aaf0 514static inline int pte_present(pte_t pte)
1da177e4 515{
83377484
MS		 516 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
517 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
518 (!(pte_val(pte) & _PAGE_INVALID) &&
519 !(pte_val(pte) & _PAGE_SWT));
1da177e4
LT		 520}
521
4448aaf0 522static inline int pte_file(pte_t pte)
1da177e4 523{
83377484
MS		 524 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
525 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
1da177e4
LT		 526}
527
7e675137
NP		 528static inline int pte_special(pte_t pte)
529{
a08cb629 530 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 531}
532
ba8a9229 533#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 534static inline int pte_same(pte_t a, pte_t b)
535{
536 return pte_val(a) == pte_val(b);
537}
1da177e4 538
b2fa47e6 539static inline pgste_t pgste_get_lock(pte_t *ptep)
5b7baf05 540{
b2fa47e6 541 unsigned long new = 0;
5b7baf05 542#ifdef CONFIG_PGSTE
b2fa47e6
MS		 543 unsigned long old;
544
5b7baf05 545 preempt_disable();
b2fa47e6
MS		 546 asm(
547 " lg %0,%2\n"
548 "0: lgr %1,%0\n"
549 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
550 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
551 " csg %0,%1,%2\n"
552 " jl 0b\n"
553 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
554 : "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05 555#endif
b2fa47e6 556 return __pgste(new);
5b7baf05
CB		 557}
558
b2fa47e6 559static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 560{
561#ifdef CONFIG_PGSTE
b2fa47e6
MS		 562 asm(
563 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
564 " stg %1,%0\n"
565 : "=Q" (ptep[PTRS_PER_PTE])
566 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
5b7baf05
CB		 567 preempt_enable();
568#endif
569}
570
b2fa47e6 571static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
5b7baf05
CB		 572{
573#ifdef CONFIG_PGSTE
a43a9d93 574 unsigned long address, bits;
b2fa47e6
MS		 575 unsigned char skey;
576
09b53883
MS		 577 if (!pte_present(*ptep))
578 return pgste;
a43a9d93
HC		 579 address = pte_val(*ptep) & PAGE_MASK;
580 skey = page_get_storage_key(address);
b2fa47e6
MS		 581 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
582 /* Clear page changed & referenced bit in the storage key */
7c81878b
CO		 583 if (bits & _PAGE_CHANGED)
584 page_set_storage_key(address, skey ^ bits, 1);
585 else if (bits)
586 page_reset_referenced(address);
b2fa47e6
MS		 587 /* Transfer page changed & referenced bit to guest bits in pgste */
588 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
589 /* Get host changed & referenced bits from pgste */
590 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
591 /* Clear host bits in pgste. */
592 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
593 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
594 /* Copy page access key and fetch protection bit to pgste */
595 pgste_val(pgste) |=
596 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
597 /* Transfer changed and referenced to kvm user bits */
598 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
599 /* Transfer changed & referenced to pte sofware bits */
600 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */
601#endif
602 return pgste;
603
604}
605
606static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
607{
608#ifdef CONFIG_PGSTE
609 int young;
610
09b53883
MS		 611 if (!pte_present(*ptep))
612 return pgste;
b2fa47e6
MS		 613 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
614 /* Transfer page referenced bit to pte software bit (host view) */
615 if (young || (pgste_val(pgste) & RCP_HR_BIT))
616 pte_val(*ptep) |= _PAGE_SWR;
617 /* Clear host referenced bit in pgste. */
618 pgste_val(pgste) &= ~RCP_HR_BIT;
619 /* Transfer page referenced bit to guest bit in pgste */
620 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
621#endif
622 return pgste;
623
624}
625
09b53883 626static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry)
b2fa47e6
MS		 627{
628#ifdef CONFIG_PGSTE
a43a9d93 629 unsigned long address;
b2fa47e6
MS		 630 unsigned long okey, nkey;
631
09b53883
MS		 632 if (!pte_present(entry))
633 return;
634 address = pte_val(entry) & PAGE_MASK;
a43a9d93 635 okey = nkey = page_get_storage_key(address);
b2fa47e6
MS		 636 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
637 /* Set page access key and fetch protection bit from pgste */
638 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
639 if (okey != nkey)
a43a9d93 640 page_set_storage_key(address, nkey, 1);
5b7baf05
CB		 641#endif
642}
643
e5992f2e
MS		 644/**
645 * struct gmap_struct - guest address space
646 * @mm: pointer to the parent mm_struct
647 * @table: pointer to the page directory
480e5926 648 * @asce: address space control element for gmap page table
e5992f2e
MS		 649 * @crst_list: list of all crst tables used in the guest address space
650 */
651struct gmap {
652 struct list_head list;
653 struct mm_struct *mm;
654 unsigned long *table;
480e5926 655 unsigned long asce;
e5992f2e
MS		 656 struct list_head crst_list;
657};
658
659/**
660 * struct gmap_rmap - reverse mapping for segment table entries
661 * @next: pointer to the next gmap_rmap structure in the list
662 * @entry: pointer to a segment table entry
663 */
664struct gmap_rmap {
665 struct list_head list;
666 unsigned long *entry;
667};
668
669/**
670 * struct gmap_pgtable - gmap information attached to a page table
671 * @vmaddr: address of the 1MB segment in the process virtual memory
672 * @mapper: list of segment table entries maping a page table
673 */
674struct gmap_pgtable {
675 unsigned long vmaddr;
676 struct list_head mapper;
677};
678
679struct gmap *gmap_alloc(struct mm_struct *mm);
680void gmap_free(struct gmap *gmap);
681void gmap_enable(struct gmap *gmap);
682void gmap_disable(struct gmap *gmap);
683int gmap_map_segment(struct gmap *gmap, unsigned long from,
684 unsigned long to, unsigned long length);
685int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
499069e1 686unsigned long __gmap_fault(unsigned long address, struct gmap *);
e5992f2e 687unsigned long gmap_fault(unsigned long address, struct gmap *);
388186bc 688void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
e5992f2e 689
b2fa47e6
MS		 690/*
691 * Certain architectures need to do special things when PTEs
692 * within a page table are directly modified. Thus, the following
693 * hook is made available.
694 */
695static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
696 pte_t *ptep, pte_t entry)
697{
698 pgste_t pgste;
699
700 if (mm_has_pgste(mm)) {
701 pgste = pgste_get_lock(ptep);
09b53883 702 pgste_set_pte(ptep, pgste, entry);
b2fa47e6
MS		 703 *ptep = entry;
704 pgste_set_unlock(ptep, pgste);
705 } else
706 *ptep = entry;
707}
708
1da177e4
LT		 709/*
710 * query functions pte_write/pte_dirty/pte_young only work if
711 * pte_present() is true. Undefined behaviour if not..
712 */
4448aaf0 713static inline int pte_write(pte_t pte)
1da177e4
LT		 714{
715 return (pte_val(pte) & _PAGE_RO) == 0;
716}
717
4448aaf0 718static inline int pte_dirty(pte_t pte)
1da177e4 719{
b2fa47e6
MS		 720#ifdef CONFIG_PGSTE
721 if (pte_val(pte) & _PAGE_SWC)
722 return 1;
723#endif
1da177e4
LT		 724 return 0;
725}
726
4448aaf0 727static inline int pte_young(pte_t pte)
1da177e4 728{
b2fa47e6
MS		 729#ifdef CONFIG_PGSTE
730 if (pte_val(pte) & _PAGE_SWR)
731 return 1;
732#endif
1da177e4
LT		 733 return 0;
734}
735
1da177e4
LT		 736/*
737 * pgd/pmd/pte modification functions
738 */
739
b2fa47e6 740static inline void pgd_clear(pgd_t *pgd)
5a216a20 741{
f4815ac6 742#ifdef CONFIG_64BIT
6252d702
MS		 743 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
744 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
b2fa47e6 745#endif
5a216a20
MS		 746}
747
b2fa47e6 748static inline void pud_clear(pud_t *pud)
1da177e4 749{
f4815ac6 750#ifdef CONFIG_64BIT
6252d702
MS		 751 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
752 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
b2fa47e6 753#endif
1da177e4
LT		 754}
755
b2fa47e6 756static inline void pmd_clear(pmd_t *pmdp)
1da177e4 757{
3610cce8 758 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 759}
760
4448aaf0 761static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 762{
9282ed92 763 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1da177e4
LT		 764}
765
766/*
767 * The following pte modification functions only work if
768 * pte_present() is true. Undefined behaviour if not..
769 */
4448aaf0 770static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 771{
138c9021 772 pte_val(pte) &= _PAGE_CHG_MASK;
1da177e4
LT		 773 pte_val(pte) |= pgprot_val(newprot);
774 return pte;
775}
776
4448aaf0 777static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 778{
9282ed92 779 /* Do not clobber _PAGE_TYPE_NONE pages! */
1da177e4
LT		 780 if (!(pte_val(pte) & _PAGE_INVALID))
781 pte_val(pte) |= _PAGE_RO;
782 return pte;
783}
784
4448aaf0 785static inline pte_t pte_mkwrite(pte_t pte)
1da177e4
LT		 786{
787 pte_val(pte) &= ~_PAGE_RO;
788 return pte;
789}
790
4448aaf0 791static inline pte_t pte_mkclean(pte_t pte)
1da177e4 792{
b2fa47e6
MS		 793#ifdef CONFIG_PGSTE
794 pte_val(pte) &= ~_PAGE_SWC;
795#endif
1da177e4
LT		 796 return pte;
797}
798
4448aaf0 799static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 800{
1da177e4
LT		 801 return pte;
802}
803
4448aaf0 804static inline pte_t pte_mkold(pte_t pte)
1da177e4 805{
b2fa47e6
MS		 806#ifdef CONFIG_PGSTE
807 pte_val(pte) &= ~_PAGE_SWR;
808#endif
1da177e4
LT		 809 return pte;
810}
811
4448aaf0 812static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 813{
1da177e4
LT		 814 return pte;
815}
816
7e675137
NP		 817static inline pte_t pte_mkspecial(pte_t pte)
818{
a08cb629 819 pte_val(pte) |= _PAGE_SPECIAL;
7e675137
NP		 820 return pte;
821}
822
84afdcee
HC		 823#ifdef CONFIG_HUGETLB_PAGE
824static inline pte_t pte_mkhuge(pte_t pte)
825{
826 /*
827 * PROT_NONE needs to be remapped from the pte type to the ste type.
828 * The HW invalid bit is also different for pte and ste. The pte
829 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
830 * bit, so we don't have to clear it.
831 */
832 if (pte_val(pte) & _PAGE_INVALID) {
833 if (pte_val(pte) & _PAGE_SWT)
834 pte_val(pte) |= _HPAGE_TYPE_NONE;
835 pte_val(pte) |= _SEGMENT_ENTRY_INV;
836 }
837 /*
838 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
839 * table entry.
840 */
841 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX);
842 /*
843 * Also set the change-override bit because we don't need dirty bit
844 * tracking for hugetlbfs pages.
845 */
846 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
847 return pte;
848}
849#endif
850
15e86b0c 851/*
b2fa47e6 852 * Get (and clear) the user dirty bit for a pte.
15e86b0c 853 */
b2fa47e6
MS		 854static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
855 pte_t *ptep)
15e86b0c 856{
b2fa47e6
MS		 857 pgste_t pgste;
858 int dirty = 0;
859
860 if (mm_has_pgste(mm)) {
861 pgste = pgste_get_lock(ptep);
862 pgste = pgste_update_all(ptep, pgste);
863 dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
864 pgste_val(pgste) &= ~KVM_UC_BIT;
865 pgste_set_unlock(ptep, pgste);
866 return dirty;
15e86b0c 867 }
15e86b0c
FF		 868 return dirty;
869}
b2fa47e6
MS		 870
871/*
872 * Get (and clear) the user referenced bit for a pte.
873 */
874static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
875 pte_t *ptep)
876{
877 pgste_t pgste;
878 int young = 0;
879
880 if (mm_has_pgste(mm)) {
881 pgste = pgste_get_lock(ptep);
882 pgste = pgste_update_young(ptep, pgste);
883 young = !!(pgste_val(pgste) & KVM_UR_BIT);
884 pgste_val(pgste) &= ~KVM_UR_BIT;
885 pgste_set_unlock(ptep, pgste);
886 }
887 return young;
888}
15e86b0c 889
ba8a9229
MS		 890#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
891static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
892 unsigned long addr, pte_t *ptep)
1da177e4 893{
b2fa47e6
MS		 894 pgste_t pgste;
895 pte_t pte;
896
897 if (mm_has_pgste(vma->vm_mm)) {
898 pgste = pgste_get_lock(ptep);
899 pgste = pgste_update_young(ptep, pgste);
900 pte = *ptep;
901 *ptep = pte_mkold(pte);
902 pgste_set_unlock(ptep, pgste);
903 return pte_young(pte);
904 }
1da177e4
LT		 905 return 0;
906}
907
ba8a9229
MS		 908#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
909static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
910 unsigned long address, pte_t *ptep)
1da177e4 911{
5b7baf05
CB		 912 /* No need to flush TLB
913 * On s390 reference bits are in storage key and never in TLB
914 * With virtualization we handle the reference bit, without we
915 * we can simply return */
5b7baf05 916 return ptep_test_and_clear_young(vma, address, ptep);
1da177e4
LT		 917}
918
9282ed92 919static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1da177e4 920{
9282ed92 921 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
f4815ac6 922#ifndef CONFIG_64BIT
146e4b3c 923 /* pto must point to the start of the segment table */
1da177e4 924 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
9282ed92
GS		 925#else
926 /* ipte in zarch mode can do the math */
927 pte_t *pto = ptep;
928#endif
94c12cc7
MS		 929 asm volatile(
930 " ipte %2,%3"
931 : "=m" (*ptep) : "m" (*ptep),
932 "a" (pto), "a" (address));
1da177e4 933 }
9282ed92
GS		 934}
935
ba8a9229
MS		 936/*
937 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
938 * both clear the TLB for the unmapped pte. The reason is that
939 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
940 * to modify an active pte. The sequence is
941 * 1) ptep_get_and_clear
942 * 2) set_pte_at
943 * 3) flush_tlb_range
944 * On s390 the tlb needs to get flushed with the modification of the pte
945 * if the pte is active. The only way how this can be implemented is to
946 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
947 * is a nop.
948 */
949#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6
MS		 950static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
951 unsigned long address, pte_t *ptep)
952{
953 pgste_t pgste;
954 pte_t pte;
955
956 mm->context.flush_mm = 1;
957 if (mm_has_pgste(mm))
958 pgste = pgste_get_lock(ptep);
959
960 pte = *ptep;
961 if (!mm_exclusive(mm))
962 __ptep_ipte(address, ptep);
963 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
964
965 if (mm_has_pgste(mm)) {
966 pgste = pgste_update_all(&pte, pgste);
967 pgste_set_unlock(ptep, pgste);
968 }
969 return pte;
970}
971
972#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
973static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
974 unsigned long address,
975 pte_t *ptep)
976{
977 pte_t pte;
978
979 mm->context.flush_mm = 1;
980 if (mm_has_pgste(mm))
981 pgste_get_lock(ptep);
982
983 pte = *ptep;
984 if (!mm_exclusive(mm))
985 __ptep_ipte(address, ptep);
986 return pte;
987}
988
989static inline void ptep_modify_prot_commit(struct mm_struct *mm,
990 unsigned long address,
991 pte_t *ptep, pte_t pte)
992{
993 *ptep = pte;
994 if (mm_has_pgste(mm))
995 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
996}
ba8a9229
MS		 997
998#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22
MS		 999static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1000 unsigned long address, pte_t *ptep)
1001{
b2fa47e6
MS		 1002 pgste_t pgste;
1003 pte_t pte;
1004
1005 if (mm_has_pgste(vma->vm_mm))
1006 pgste = pgste_get_lock(ptep);
1007
1008 pte = *ptep;
1009 __ptep_ipte(address, ptep);
1010 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1011
1012 if (mm_has_pgste(vma->vm_mm)) {
1013 pgste = pgste_update_all(&pte, pgste);
1014 pgste_set_unlock(ptep, pgste);
1015 }
1da177e4
LT		 1016 return pte;
1017}
1018
ba8a9229
MS		 1019/*
1020 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1021 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1022 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1023 * cannot be accessed while the batched unmap is running. In this case
1024 * full==1 and a simple pte_clear is enough. See tlb.h.
1025 */
1026#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1027static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
b2fa47e6 1028 unsigned long address,
ba8a9229 1029 pte_t *ptep, int full)
1da177e4 1030{
b2fa47e6
MS		 1031 pgste_t pgste;
1032 pte_t pte;
1033
1034 if (mm_has_pgste(mm))
1035 pgste = pgste_get_lock(ptep);
ba8a9229 1036
b2fa47e6
MS		 1037 pte = *ptep;
1038 if (!full)
1039 __ptep_ipte(address, ptep);
1040 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1041
1042 if (mm_has_pgste(mm)) {
1043 pgste = pgste_update_all(&pte, pgste);
1044 pgste_set_unlock(ptep, pgste);
1045 }
ba8a9229 1046 return pte;
1da177e4
LT		 1047}
1048
ba8a9229 1049#define __HAVE_ARCH_PTEP_SET_WRPROTECT
b2fa47e6
MS		 1050static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1051 unsigned long address, pte_t *ptep)
1052{
1053 pgste_t pgste;
1054 pte_t pte = *ptep;
1055
1056 if (pte_write(pte)) {
1057 mm->context.flush_mm = 1;
1058 if (mm_has_pgste(mm))
1059 pgste = pgste_get_lock(ptep);
1060
1061 if (!mm_exclusive(mm))
1062 __ptep_ipte(address, ptep);
1063 *ptep = pte_wrprotect(pte);
1064
1065 if (mm_has_pgste(mm))
1066 pgste_set_unlock(ptep, pgste);
1067 }
1068 return pte;
1069}
ba8a9229
MS		 1070
1071#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6
MS		 1072static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1073 unsigned long address, pte_t *ptep,
1074 pte_t entry, int dirty)
1075{
1076 pgste_t pgste;
1077
1078 if (pte_same(*ptep, entry))
1079 return 0;
1080 if (mm_has_pgste(vma->vm_mm))
1081 pgste = pgste_get_lock(ptep);
1082
1083 __ptep_ipte(address, ptep);
1084 *ptep = entry;
1085
1086 if (mm_has_pgste(vma->vm_mm))
1087 pgste_set_unlock(ptep, pgste);
1088 return 1;
1089}
1da177e4 1090
1da177e4
LT		 1091/*
1092 * Conversion functions: convert a page and protection to a page entry,
1093 * and a page entry and page directory to the page they refer to.
1094 */
1095static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1096{
1097 pte_t __pte;
1098 pte_val(__pte) = physpage + pgprot_val(pgprot);
1099 return __pte;
1100}
1101
2dcea57a
HC		 1102static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1103{
0b2b6e1d 1104 unsigned long physpage = page_to_phys(page);
1da177e4 1105
2dcea57a
HC		 1106 return mk_pte_phys(physpage, pgprot);
1107}
1108
190a1d72
MS		 1109#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1110#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1111#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1112#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1da177e4 1113
190a1d72
MS		 1114#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1115#define pgd_offset_k(address) pgd_offset(&init_mm, address)
1da177e4 1116
f4815ac6 1117#ifndef CONFIG_64BIT
1da177e4 1118
190a1d72
MS		 1119#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1120#define pud_deref(pmd) ({ BUG(); 0UL; })
1121#define pgd_deref(pmd) ({ BUG(); 0UL; })
46a82b2d 1122
190a1d72
MS		 1123#define pud_offset(pgd, address) ((pud_t *) pgd)
1124#define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1da177e4 1125
f4815ac6 1126#else /* CONFIG_64BIT */
1da177e4 1127
190a1d72
MS		 1128#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1129#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
5a216a20 1130#define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1da177e4 1131
5a216a20
MS		 1132static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1133{
6252d702
MS		 1134 pud_t *pud = (pud_t *) pgd;
1135 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1136 pud = (pud_t *) pgd_deref(*pgd);
5a216a20
MS		 1137 return pud + pud_index(address);
1138}
1da177e4 1139
190a1d72 1140static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1da177e4 1141{
6252d702
MS		 1142 pmd_t *pmd = (pmd_t *) pud;
1143 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1144 pmd = (pmd_t *) pud_deref(*pud);
190a1d72 1145 return pmd + pmd_index(address);
1da177e4
LT		 1146}
1147
f4815ac6 1148#endif /* CONFIG_64BIT */
1da177e4 1149
190a1d72
MS		 1150#define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1151#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1152#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1153
190a1d72 1154#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1da177e4 1155
190a1d72
MS		 1156/* Find an entry in the lowest level page table.. */
1157#define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1158#define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1da177e4 1159#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1da177e4 1160#define pte_unmap(pte) do { } while (0)
1da177e4
LT		 1161
1162/*
1163 * 31 bit swap entry format:
1164 * A page-table entry has some bits we have to treat in a special way.
1165 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1166 * exception will occur instead of a page translation exception. The
1167 * specifiation exception has the bad habit not to store necessary
1168 * information in the lowcore.
1169 * Bit 21 and bit 22 are the page invalid bit and the page protection
1170 * bit. We set both to indicate a swapped page.
1171 * Bit 30 and 31 are used to distinguish the different page types. For
1172 * a swapped page these bits need to be zero.
1173 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1174 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1175 * plus 24 for the offset.
1176 * 0| offset |0110|o|type |00|
1177 * 0 0000000001111111111 2222 2 22222 33
1178 * 0 1234567890123456789 0123 4 56789 01
1179 *
1180 * 64 bit swap entry format:
1181 * A page-table entry has some bits we have to treat in a special way.
1182 * Bits 52 and bit 55 have to be zero, otherwise an specification
1183 * exception will occur instead of a page translation exception. The
1184 * specifiation exception has the bad habit not to store necessary
1185 * information in the lowcore.
1186 * Bit 53 and bit 54 are the page invalid bit and the page protection
1187 * bit. We set both to indicate a swapped page.
1188 * Bit 62 and 63 are used to distinguish the different page types. For
1189 * a swapped page these bits need to be zero.
1190 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1191 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1192 * plus 56 for the offset.
1193 * | offset |0110|o|type |00|
1194 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1195 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1196 */
f4815ac6 1197#ifndef CONFIG_64BIT
1da177e4
LT		 1198#define __SWP_OFFSET_MASK (~0UL >> 12)
1199#else
1200#define __SWP_OFFSET_MASK (~0UL >> 11)
1201#endif
4448aaf0 1202static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4
LT		 1203{
1204 pte_t pte;
1205 offset &= __SWP_OFFSET_MASK;
9282ed92 1206 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1da177e4
LT		 1207 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1208 return pte;
1209}
1210
1211#define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1212#define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1213#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1214
1215#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1216#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1217
f4815ac6 1218#ifndef CONFIG_64BIT
1da177e4 1219# define PTE_FILE_MAX_BITS 26
f4815ac6 1220#else /* CONFIG_64BIT */
1da177e4 1221# define PTE_FILE_MAX_BITS 59
f4815ac6 1222#endif /* CONFIG_64BIT */
1da177e4
LT		 1223
1224#define pte_to_pgoff(__pte) \
1225 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1226
1227#define pgoff_to_pte(__off) \
1228 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
9282ed92 1229 | _PAGE_TYPE_FILE })
1da177e4
LT		 1230
1231#endif /* !__ASSEMBLY__ */
1232
1233#define kern_addr_valid(addr) (1)
1234
17f34580
HC		 1235extern int vmem_add_mapping(unsigned long start, unsigned long size);
1236extern int vmem_remove_mapping(unsigned long start, unsigned long size);
402b0862 1237extern int s390_enable_sie(void);
f4eb07c1 1238
1da177e4
LT		 1239/*
1240 * No page table caches to initialise
1241 */
1242#define pgtable_cache_init() do { } while (0)
1243
1da177e4
LT		 1244#include <asm-generic/pgtable.h>
1245
1246#endif /* _S390_PAGE_H */
Linux kernel - Deliverables
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