Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * S390 version |
a53c8fab | 3 | * Copyright IBM Corp. 1999 |
1da177e4 LT |
4 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
5 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
6 | * | |
7 | * Derived from "include/asm-i386/processor.h" | |
8 | * Copyright (C) 1994, Linus Torvalds | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_S390_PROCESSOR_H | |
12 | #define __ASM_S390_PROCESSOR_H | |
13 | ||
d3a73acb MS |
14 | #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ |
15 | #define CIF_ASCE 1 /* user asce needs fixup / uaccess */ | |
fe0f4976 | 16 | #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ |
d3a73acb MS |
17 | |
18 | #define _CIF_MCCK_PENDING (1<<CIF_MCCK_PENDING) | |
19 | #define _CIF_ASCE (1<<CIF_ASCE) | |
fe0f4976 | 20 | #define _CIF_NOHZ_DELAY (1<<CIF_NOHZ_DELAY) |
d3a73acb MS |
21 | |
22 | ||
eb608fb3 HC |
23 | #ifndef __ASSEMBLY__ |
24 | ||
edd53787 | 25 | #include <linux/linkage.h> |
a0616cde | 26 | #include <linux/irqflags.h> |
e86a6ed6 | 27 | #include <asm/cpu.h> |
25097bf1 | 28 | #include <asm/page.h> |
1da177e4 | 29 | #include <asm/ptrace.h> |
25097bf1 | 30 | #include <asm/setup.h> |
e4b8b3f3 | 31 | #include <asm/runtime_instr.h> |
1da177e4 | 32 | |
d3a73acb MS |
33 | static inline void set_cpu_flag(int flag) |
34 | { | |
35 | S390_lowcore.cpu_flags |= (1U << flag); | |
36 | } | |
37 | ||
38 | static inline void clear_cpu_flag(int flag) | |
39 | { | |
40 | S390_lowcore.cpu_flags &= ~(1U << flag); | |
41 | } | |
42 | ||
43 | static inline int test_cpu_flag(int flag) | |
44 | { | |
45 | return !!(S390_lowcore.cpu_flags & (1U << flag)); | |
46 | } | |
47 | ||
fe0f4976 MS |
48 | #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) |
49 | ||
1da177e4 LT |
50 | /* |
51 | * Default implementation of macro that returns current | |
52 | * instruction pointer ("program counter"). | |
53 | */ | |
94c12cc7 | 54 | #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) |
1da177e4 | 55 | |
e86a6ed6 | 56 | static inline void get_cpu_id(struct cpuid *ptr) |
72960a02 | 57 | { |
987bcdac | 58 | asm volatile("stidp %0" : "=Q" (*ptr)); |
72960a02 MH |
59 | } |
60 | ||
31ee4b2f | 61 | extern void s390_adjust_jiffies(void); |
638ad34a MS |
62 | extern const struct seq_operations cpuinfo_op; |
63 | extern int sysctl_ieee_emulation_warnings; | |
65f22a90 | 64 | extern void execve_tail(void); |
1da177e4 | 65 | |
1da177e4 | 66 | /* |
f481bfaf | 67 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
1da177e4 | 68 | */ |
f4815ac6 | 69 | #ifndef CONFIG_64BIT |
1da177e4 | 70 | |
5a216a20 | 71 | #define TASK_SIZE (1UL << 31) |
ee6ee55b | 72 | #define TASK_MAX_SIZE (1UL << 31) |
5a216a20 | 73 | #define TASK_UNMAPPED_BASE (1UL << 30) |
1da177e4 | 74 | |
f4815ac6 | 75 | #else /* CONFIG_64BIT */ |
1da177e4 | 76 | |
f481bfaf | 77 | #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) |
5a216a20 MS |
78 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
79 | (1UL << 30) : (1UL << 41)) | |
80 | #define TASK_SIZE TASK_SIZE_OF(current) | |
ee6ee55b | 81 | #define TASK_MAX_SIZE (1UL << 53) |
1da177e4 | 82 | |
f4815ac6 | 83 | #endif /* CONFIG_64BIT */ |
1da177e4 | 84 | |
f4815ac6 | 85 | #ifndef CONFIG_64BIT |
5a216a20 | 86 | #define STACK_TOP (1UL << 31) |
6252d702 | 87 | #define STACK_TOP_MAX (1UL << 31) |
f4815ac6 | 88 | #else /* CONFIG_64BIT */ |
6252d702 MS |
89 | #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) |
90 | #define STACK_TOP_MAX (1UL << 42) | |
f4815ac6 | 91 | #endif /* CONFIG_64BIT */ |
922a70d3 | 92 | |
1da177e4 LT |
93 | #define HAVE_ARCH_PICK_MMAP_LAYOUT |
94 | ||
95 | typedef struct { | |
96 | __u32 ar4; | |
97 | } mm_segment_t; | |
98 | ||
99 | /* | |
100 | * Thread structure | |
101 | */ | |
102 | struct thread_struct { | |
103 | s390_fp_regs fp_regs; | |
104 | unsigned int acrs[NUM_ACRS]; | |
105 | unsigned long ksp; /* kernel stack pointer */ | |
1da177e4 | 106 | mm_segment_t mm_segment; |
e5992f2e | 107 | unsigned long gmap_addr; /* address of last gmap fault. */ |
24eb3a82 | 108 | unsigned int gmap_pfault; /* signal of a pending guest pfault */ |
5e9a2692 MS |
109 | struct per_regs per_user; /* User specified PER registers */ |
110 | struct per_event per_event; /* Cause of the last PER trap */ | |
d35339a4 | 111 | unsigned long per_flags; /* Flags to control debug behavior */ |
1da177e4 LT |
112 | /* pfault_wait is used to block the process on a pfault event */ |
113 | unsigned long pfault_wait; | |
f2db2e6c | 114 | struct list_head list; |
e4b8b3f3 JG |
115 | /* cpu runtime instrumentation */ |
116 | struct runtime_instr_cb *ri_cb; | |
117 | int ri_signum; | |
d35339a4 MS |
118 | #ifdef CONFIG_64BIT |
119 | unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ | |
120 | #endif | |
1da177e4 LT |
121 | }; |
122 | ||
64597f9d MM |
123 | /* Flag to disable transactions. */ |
124 | #define PER_FLAG_NO_TE 1UL | |
125 | /* Flag to enable random transaction aborts. */ | |
126 | #define PER_FLAG_TE_ABORT_RAND 2UL | |
127 | /* Flag to specify random transaction abort mode: | |
128 | * - abort each transaction at a random instruction before TEND if set. | |
129 | * - abort random transactions at a random instruction if cleared. | |
130 | */ | |
131 | #define PER_FLAG_TE_ABORT_RAND_TEND 4UL | |
d35339a4 | 132 | |
1da177e4 LT |
133 | typedef struct thread_struct thread_struct; |
134 | ||
135 | /* | |
136 | * Stack layout of a C stack frame. | |
137 | */ | |
138 | #ifndef __PACK_STACK | |
139 | struct stack_frame { | |
140 | unsigned long back_chain; | |
141 | unsigned long empty1[5]; | |
142 | unsigned long gprs[10]; | |
143 | unsigned int empty2[8]; | |
144 | }; | |
145 | #else | |
146 | struct stack_frame { | |
147 | unsigned long empty1[5]; | |
148 | unsigned int empty2[8]; | |
149 | unsigned long gprs[10]; | |
150 | unsigned long back_chain; | |
151 | }; | |
152 | #endif | |
153 | ||
154 | #define ARCH_MIN_TASKALIGN 8 | |
155 | ||
6f3fa3f0 MS |
156 | #define INIT_THREAD { \ |
157 | .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ | |
158 | } | |
1da177e4 LT |
159 | |
160 | /* | |
161 | * Do necessary setup to start up a new thread. | |
162 | */ | |
b50511e4 | 163 | #define start_thread(regs, new_psw, new_stackp) do { \ |
e258d719 | 164 | regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ |
b50511e4 MS |
165 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ |
166 | regs->gprs[15] = new_stackp; \ | |
65f22a90 | 167 | execve_tail(); \ |
63506c41 MS |
168 | } while (0) |
169 | ||
b50511e4 | 170 | #define start_thread31(regs, new_psw, new_stackp) do { \ |
e258d719 | 171 | regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ |
b50511e4 MS |
172 | regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ |
173 | regs->gprs[15] = new_stackp; \ | |
174 | crst_table_downgrade(current->mm, 1UL << 31); \ | |
65f22a90 | 175 | execve_tail(); \ |
1da177e4 LT |
176 | } while (0) |
177 | ||
1da177e4 LT |
178 | /* Forward declaration, a strange C thing */ |
179 | struct task_struct; | |
180 | struct mm_struct; | |
df5f8314 | 181 | struct seq_file; |
1da177e4 | 182 | |
6668022c HC |
183 | #ifdef CONFIG_64BIT |
184 | extern void show_cacheinfo(struct seq_file *m); | |
185 | #else | |
186 | static inline void show_cacheinfo(struct seq_file *m) { } | |
187 | #endif | |
188 | ||
1da177e4 LT |
189 | /* Free all resources held by a thread. */ |
190 | extern void release_thread(struct task_struct *); | |
1da177e4 | 191 | |
1da177e4 LT |
192 | /* |
193 | * Return saved PC of a blocked thread. | |
194 | */ | |
195 | extern unsigned long thread_saved_pc(struct task_struct *t); | |
196 | ||
1da177e4 | 197 | unsigned long get_wchan(struct task_struct *p); |
c7584fb6 | 198 | #define task_pt_regs(tsk) ((struct pt_regs *) \ |
30af7120 | 199 | (task_stack_page(tsk) + THREAD_SIZE) - 1) |
c7584fb6 AV |
200 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) |
201 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) | |
1da177e4 | 202 | |
5ebf250d HC |
203 | /* Has task runtime instrumentation enabled ? */ |
204 | #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) | |
205 | ||
a0616cde DH |
206 | static inline unsigned short stap(void) |
207 | { | |
208 | unsigned short cpu_address; | |
209 | ||
210 | asm volatile("stap %0" : "=m" (cpu_address)); | |
211 | return cpu_address; | |
212 | } | |
213 | ||
1da177e4 LT |
214 | /* |
215 | * Give up the time slice of the virtual PU. | |
216 | */ | |
abdba61a HC |
217 | static inline void cpu_relax(void) |
218 | { | |
219 | if (MACHINE_HAS_DIAG44) | |
c48e0913 HC |
220 | asm volatile("diag 0,0,68"); |
221 | barrier(); | |
abdba61a | 222 | } |
1da177e4 | 223 | |
3a6bfbc9 | 224 | #define cpu_relax_lowlatency() barrier() |
083986e8 | 225 | |
dc74d7f9 HC |
226 | static inline void psw_set_key(unsigned int key) |
227 | { | |
228 | asm volatile("spka 0(%0)" : : "d" (key)); | |
229 | } | |
230 | ||
77fa2245 HC |
231 | /* |
232 | * Set PSW to specified value. | |
233 | */ | |
234 | static inline void __load_psw(psw_t psw) | |
235 | { | |
f4815ac6 | 236 | #ifndef CONFIG_64BIT |
987bcdac | 237 | asm volatile("lpsw %0" : : "Q" (psw) : "cc"); |
77fa2245 | 238 | #else |
987bcdac | 239 | asm volatile("lpswe %0" : : "Q" (psw) : "cc"); |
77fa2245 HC |
240 | #endif |
241 | } | |
242 | ||
1da177e4 LT |
243 | /* |
244 | * Set PSW mask to specified value, while leaving the | |
245 | * PSW addr pointing to the next instruction. | |
246 | */ | |
1da177e4 LT |
247 | static inline void __load_psw_mask (unsigned long mask) |
248 | { | |
249 | unsigned long addr; | |
1da177e4 | 250 | psw_t psw; |
77fa2245 | 251 | |
1da177e4 LT |
252 | psw.mask = mask; |
253 | ||
f4815ac6 | 254 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
255 | asm volatile( |
256 | " basr %0,0\n" | |
257 | "0: ahi %0,1f-0b\n" | |
987bcdac MS |
258 | " st %0,%O1+4(%R1)\n" |
259 | " lpsw %1\n" | |
1da177e4 | 260 | "1:" |
987bcdac | 261 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 262 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
263 | asm volatile( |
264 | " larl %0,1f\n" | |
987bcdac MS |
265 | " stg %0,%O1+8(%R1)\n" |
266 | " lpswe %1\n" | |
1da177e4 | 267 | "1:" |
987bcdac | 268 | : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); |
f4815ac6 | 269 | #endif /* CONFIG_64BIT */ |
1da177e4 | 270 | } |
ccf45caf MS |
271 | |
272 | /* | |
273 | * Rewind PSW instruction address by specified number of bytes. | |
274 | */ | |
275 | static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) | |
276 | { | |
f4815ac6 | 277 | #ifndef CONFIG_64BIT |
ccf45caf MS |
278 | if (psw.addr & PSW_ADDR_AMODE) |
279 | /* 31 bit mode */ | |
280 | return (psw.addr - ilc) | PSW_ADDR_AMODE; | |
281 | /* 24 bit mode */ | |
282 | return (psw.addr - ilc) & ((1UL << 24) - 1); | |
283 | #else | |
284 | unsigned long mask; | |
285 | ||
286 | mask = (psw.mask & PSW_MASK_EA) ? -1UL : | |
287 | (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : | |
288 | (1UL << 24) - 1; | |
289 | return (psw.addr - ilc) & mask; | |
290 | #endif | |
291 | } | |
1da177e4 | 292 | |
1da177e4 LT |
293 | /* |
294 | * Function to drop a processor into disabled wait state | |
295 | */ | |
ff2d8b19 | 296 | static inline void __noreturn disabled_wait(unsigned long code) |
1da177e4 | 297 | { |
1da177e4 | 298 | unsigned long ctl_buf; |
77fa2245 | 299 | psw_t dw_psw; |
1da177e4 | 300 | |
b50511e4 | 301 | dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; |
77fa2245 | 302 | dw_psw.addr = code; |
1da177e4 LT |
303 | /* |
304 | * Store status and then load disabled wait psw, | |
305 | * the processor is dead afterwards | |
306 | */ | |
f4815ac6 | 307 | #ifndef CONFIG_64BIT |
94c12cc7 MS |
308 | asm volatile( |
309 | " stctl 0,0,0(%2)\n" | |
310 | " ni 0(%2),0xef\n" /* switch off protection */ | |
311 | " lctl 0,0,0(%2)\n" | |
312 | " stpt 0xd8\n" /* store timer */ | |
313 | " stckc 0xe0\n" /* store clock comparator */ | |
314 | " stpx 0x108\n" /* store prefix register */ | |
315 | " stam 0,15,0x120\n" /* store access registers */ | |
316 | " std 0,0x160\n" /* store f0 */ | |
317 | " std 2,0x168\n" /* store f2 */ | |
318 | " std 4,0x170\n" /* store f4 */ | |
319 | " std 6,0x178\n" /* store f6 */ | |
320 | " stm 0,15,0x180\n" /* store general registers */ | |
321 | " stctl 0,15,0x1c0\n" /* store control registers */ | |
322 | " oi 0x1c0,0x10\n" /* fake protection bit */ | |
323 | " lpsw 0(%1)" | |
324 | : "=m" (ctl_buf) | |
325 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); | |
f4815ac6 | 326 | #else /* CONFIG_64BIT */ |
94c12cc7 MS |
327 | asm volatile( |
328 | " stctg 0,0,0(%2)\n" | |
329 | " ni 4(%2),0xef\n" /* switch off protection */ | |
330 | " lctlg 0,0,0(%2)\n" | |
331 | " lghi 1,0x1000\n" | |
332 | " stpt 0x328(1)\n" /* store timer */ | |
333 | " stckc 0x330(1)\n" /* store clock comparator */ | |
334 | " stpx 0x318(1)\n" /* store prefix register */ | |
335 | " stam 0,15,0x340(1)\n"/* store access registers */ | |
336 | " stfpc 0x31c(1)\n" /* store fpu control */ | |
337 | " std 0,0x200(1)\n" /* store f0 */ | |
338 | " std 1,0x208(1)\n" /* store f1 */ | |
339 | " std 2,0x210(1)\n" /* store f2 */ | |
340 | " std 3,0x218(1)\n" /* store f3 */ | |
341 | " std 4,0x220(1)\n" /* store f4 */ | |
342 | " std 5,0x228(1)\n" /* store f5 */ | |
343 | " std 6,0x230(1)\n" /* store f6 */ | |
344 | " std 7,0x238(1)\n" /* store f7 */ | |
345 | " std 8,0x240(1)\n" /* store f8 */ | |
346 | " std 9,0x248(1)\n" /* store f9 */ | |
347 | " std 10,0x250(1)\n" /* store f10 */ | |
348 | " std 11,0x258(1)\n" /* store f11 */ | |
349 | " std 12,0x260(1)\n" /* store f12 */ | |
350 | " std 13,0x268(1)\n" /* store f13 */ | |
351 | " std 14,0x270(1)\n" /* store f14 */ | |
352 | " std 15,0x278(1)\n" /* store f15 */ | |
353 | " stmg 0,15,0x280(1)\n"/* store general registers */ | |
354 | " stctg 0,15,0x380(1)\n"/* store control registers */ | |
355 | " oi 0x384(1),0x10\n"/* fake protection bit */ | |
356 | " lpswe 0(%1)" | |
357 | : "=m" (ctl_buf) | |
bdd42b28 | 358 | : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); |
f4815ac6 | 359 | #endif /* CONFIG_64BIT */ |
edd53787 | 360 | while (1); |
1da177e4 LT |
361 | } |
362 | ||
a0616cde DH |
363 | /* |
364 | * Use to set psw mask except for the first byte which | |
365 | * won't be changed by this function. | |
366 | */ | |
367 | static inline void | |
368 | __set_psw_mask(unsigned long mask) | |
369 | { | |
370 | __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); | |
371 | } | |
372 | ||
373 | #define local_mcck_enable() \ | |
e258d719 | 374 | __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK) |
a0616cde | 375 | #define local_mcck_disable() \ |
e258d719 | 376 | __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT) |
a0616cde | 377 | |
ab14de6c HC |
378 | /* |
379 | * Basic Machine Check/Program Check Handler. | |
380 | */ | |
381 | ||
382 | extern void s390_base_mcck_handler(void); | |
383 | extern void s390_base_pgm_handler(void); | |
384 | extern void s390_base_ext_handler(void); | |
385 | ||
386 | extern void (*s390_base_mcck_handler_fn)(void); | |
387 | extern void (*s390_base_pgm_handler_fn)(void); | |
388 | extern void (*s390_base_ext_handler_fn)(void); | |
389 | ||
dfd54cbc HC |
390 | #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL |
391 | ||
fbe76568 HC |
392 | extern int memcpy_real(void *, void *, size_t); |
393 | extern void memcpy_absolute(void *, void *, size_t); | |
394 | ||
395 | #define mem_assign_absolute(dest, val) { \ | |
396 | __typeof__(dest) __tmp = (val); \ | |
397 | \ | |
398 | BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ | |
399 | memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ | |
400 | } | |
401 | ||
eb608fb3 HC |
402 | /* |
403 | * Helper macro for exception table entries | |
404 | */ | |
405 | #define EX_TABLE(_fault, _target) \ | |
406 | ".section __ex_table,\"a\"\n" \ | |
407 | ".align 4\n" \ | |
408 | ".long (" #_fault ") - .\n" \ | |
409 | ".long (" #_target ") - .\n" \ | |
410 | ".previous\n" | |
411 | ||
412 | #else /* __ASSEMBLY__ */ | |
413 | ||
414 | #define EX_TABLE(_fault, _target) \ | |
415 | .section __ex_table,"a" ; \ | |
416 | .align 4 ; \ | |
417 | .long (_fault) - . ; \ | |
418 | .long (_target) - . ; \ | |
419 | .previous | |
420 | ||
421 | #endif /* __ASSEMBLY__ */ | |
422 | ||
423 | #endif /* __ASM_S390_PROCESSOR_H */ |