Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
a53c8fab | 2 | * Copyright IBM Corp. 2004, 2011 |
d7b250e2 HC |
3 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, |
4 | * Holger Smolinski <Holger.Smolinski@de.ibm.com>, | |
5 | * Thomas Spatzier <tspat@de.ibm.com>, | |
1da177e4 LT |
6 | * |
7 | * This file contains interrupt related functions. | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/kernel_stat.h> |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/seq_file.h> | |
55dff522 HC |
13 | #include <linux/proc_fs.h> |
14 | #include <linux/profile.h> | |
d7b250e2 HC |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/ftrace.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/cpu.h> | |
257ceab7 | 21 | #include <linux/irq.h> |
d7b250e2 HC |
22 | #include <asm/irq_regs.h> |
23 | #include <asm/cputime.h> | |
24 | #include <asm/lowcore.h> | |
25 | #include <asm/irq.h> | |
1f44a225 | 26 | #include <asm/hw_irq.h> |
d7b250e2 | 27 | #include "entry.h" |
1da177e4 | 28 | |
420f42ec HC |
29 | DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); |
30 | EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); | |
31 | ||
052ff461 | 32 | struct irq_class { |
e2213e04 | 33 | int irq; |
052ff461 HC |
34 | char *name; |
35 | char *desc; | |
36 | }; | |
37 | ||
420f42ec | 38 | /* |
cf2fbdd2 | 39 | * The list of "main" irq classes on s390. This is the list of interrupts |
420f42ec HC |
40 | * that appear both in /proc/stat ("intr" line) and /proc/interrupts. |
41 | * Historically only external and I/O interrupts have been part of /proc/stat. | |
42 | * We can't add the split external and I/O sub classes since the first field | |
43 | * in the "intr" line in /proc/stat is supposed to be the sum of all other | |
44 | * fields. | |
45 | * Since the external and I/O interrupt fields are already sums we would end | |
46 | * up with having a sum which accounts each interrupt twice. | |
47 | */ | |
1f44a225 | 48 | static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { |
e2213e04 HB |
49 | {.irq = EXT_INTERRUPT, .name = "EXT"}, |
50 | {.irq = IO_INTERRUPT, .name = "I/O"}, | |
51 | {.irq = THIN_INTERRUPT, .name = "AIO"}, | |
420f42ec HC |
52 | }; |
53 | ||
54 | /* | |
55 | * The list of split external and I/O interrupts that appear only in | |
56 | * /proc/interrupts. | |
57 | * In addition this list contains non external / I/O events like NMIs. | |
58 | */ | |
57fe1b26 | 59 | static const struct irq_class irqclass_sub_desc[] = { |
e2213e04 HB |
60 | {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, |
61 | {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, | |
62 | {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, | |
63 | {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, | |
64 | {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, | |
65 | {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, | |
66 | {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, | |
67 | {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, | |
68 | {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, | |
69 | {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, | |
70 | {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, | |
71 | {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, | |
8f933b10 | 72 | {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, |
e2213e04 HB |
73 | {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, |
74 | {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"}, | |
75 | {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, | |
76 | {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, | |
77 | {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, | |
78 | {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, | |
79 | {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, | |
80 | {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, | |
e2213e04 HB |
81 | {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, |
82 | {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"}, | |
83 | {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, | |
84 | {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, | |
85 | {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" }, | |
86 | {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" }, | |
87 | {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, | |
88 | {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"}, | |
89 | {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, | |
90 | {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, | |
052ff461 HC |
91 | }; |
92 | ||
1f44a225 MS |
93 | void __init init_IRQ(void) |
94 | { | |
57fe1b26 | 95 | BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); |
1f44a225 MS |
96 | init_cio_interrupts(); |
97 | init_airq_interrupts(); | |
98 | init_ext_interrupts(); | |
99 | } | |
100 | ||
101 | void do_IRQ(struct pt_regs *regs, int irq) | |
102 | { | |
103 | struct pt_regs *old_regs; | |
104 | ||
105 | old_regs = set_irq_regs(regs); | |
106 | irq_enter(); | |
107 | if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) | |
108 | /* Serve timer interrupts first. */ | |
109 | clock_comparator_work(); | |
110 | generic_handle_irq(irq); | |
111 | irq_exit(); | |
112 | set_irq_regs(old_regs); | |
113 | } | |
114 | ||
1da177e4 LT |
115 | /* |
116 | * show_interrupts is needed by /proc/interrupts. | |
117 | */ | |
118 | int show_interrupts(struct seq_file *p, void *v) | |
119 | { | |
e2213e04 HB |
120 | int index = *(loff_t *) v; |
121 | int cpu, irq; | |
1da177e4 | 122 | |
8dd79cb1 | 123 | get_online_cpus(); |
e2213e04 | 124 | if (index == 0) { |
1da177e4 | 125 | seq_puts(p, " "); |
420f42ec HC |
126 | for_each_online_cpu(cpu) |
127 | seq_printf(p, "CPU%d ", cpu); | |
1da177e4 LT |
128 | seq_putc(p, '\n'); |
129 | } | |
e2213e04 HB |
130 | if (index < NR_IRQS) { |
131 | if (index >= NR_IRQS_BASE) | |
1f44a225 | 132 | goto out; |
e2213e04 HB |
133 | seq_printf(p, "%s: ", irqclass_main_desc[index].name); |
134 | irq = irqclass_main_desc[index].irq; | |
420f42ec | 135 | for_each_online_cpu(cpu) |
1f44a225 | 136 | seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); |
420f42ec | 137 | seq_putc(p, '\n'); |
1f44a225 | 138 | goto out; |
420f42ec | 139 | } |
e2213e04 HB |
140 | for (index = 0; index < NR_ARCH_IRQS; index++) { |
141 | seq_printf(p, "%s: ", irqclass_sub_desc[index].name); | |
142 | irq = irqclass_sub_desc[index].irq; | |
420f42ec | 143 | for_each_online_cpu(cpu) |
1f44a225 MS |
144 | seq_printf(p, "%10u ", |
145 | per_cpu(irq_stat, cpu).irqs[irq]); | |
e2213e04 HB |
146 | if (irqclass_sub_desc[index].desc) |
147 | seq_printf(p, " %s", irqclass_sub_desc[index].desc); | |
420f42ec HC |
148 | seq_putc(p, '\n'); |
149 | } | |
1f44a225 | 150 | out: |
8dd79cb1 | 151 | put_online_cpus(); |
420f42ec | 152 | return 0; |
1da177e4 LT |
153 | } |
154 | ||
be403401 TG |
155 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
156 | { | |
afaa7d29 | 157 | return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; |
be403401 TG |
158 | } |
159 | ||
1da177e4 LT |
160 | /* |
161 | * Switch to the asynchronous interrupt stack for softirq execution. | |
162 | */ | |
7d65f4a6 | 163 | void do_softirq_own_stack(void) |
1da177e4 | 164 | { |
7d65f4a6 FW |
165 | unsigned long old, new; |
166 | ||
76737ce1 | 167 | old = current_stack_pointer(); |
7d65f4a6 FW |
168 | /* Check against async. stack address range. */ |
169 | new = S390_lowcore.async_stack; | |
170 | if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) { | |
171 | /* Need to switch to the async. stack. */ | |
172 | new -= STACK_FRAME_OVERHEAD; | |
173 | ((struct stack_frame *) new)->back_chain = old; | |
174 | asm volatile(" la 15,0(%0)\n" | |
175 | " basr 14,%2\n" | |
176 | " la 15,0(%1)\n" | |
177 | : : "a" (new), "a" (old), | |
178 | "a" (__do_softirq) | |
179 | : "0", "1", "2", "3", "4", "5", "14", | |
180 | "cc", "memory" ); | |
181 | } else { | |
182 | /* We are already on the async stack. */ | |
183 | __do_softirq(); | |
1da177e4 | 184 | } |
1da177e4 | 185 | } |
55dff522 | 186 | |
d7b250e2 | 187 | /* |
89c9b66b JG |
188 | * ext_int_hash[index] is the list head for all external interrupts that hash |
189 | * to this index. | |
d7b250e2 | 190 | */ |
9e75c627 | 191 | static struct hlist_head ext_int_hash[32] ____cacheline_aligned; |
d7b250e2 HC |
192 | |
193 | struct ext_int_info { | |
d7b250e2 | 194 | ext_int_handler_t handler; |
50ce749d | 195 | struct hlist_node entry; |
89c9b66b | 196 | struct rcu_head rcu; |
50ce749d | 197 | u16 code; |
d7b250e2 HC |
198 | }; |
199 | ||
89c9b66b | 200 | /* ext_int_hash_lock protects the handler lists for external interrupts */ |
63df41d6 | 201 | static DEFINE_SPINLOCK(ext_int_hash_lock); |
89c9b66b | 202 | |
d7b250e2 HC |
203 | static inline int ext_hash(u16 code) |
204 | { | |
9e75c627 HC |
205 | BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); |
206 | ||
207 | return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); | |
d7b250e2 HC |
208 | } |
209 | ||
1dad093b | 210 | int register_external_irq(u16 code, ext_int_handler_t handler) |
d7b250e2 HC |
211 | { |
212 | struct ext_int_info *p; | |
89c9b66b | 213 | unsigned long flags; |
d7b250e2 HC |
214 | int index; |
215 | ||
216 | p = kmalloc(sizeof(*p), GFP_ATOMIC); | |
217 | if (!p) | |
218 | return -ENOMEM; | |
219 | p->code = code; | |
220 | p->handler = handler; | |
221 | index = ext_hash(code); | |
89c9b66b JG |
222 | |
223 | spin_lock_irqsave(&ext_int_hash_lock, flags); | |
50ce749d | 224 | hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); |
89c9b66b | 225 | spin_unlock_irqrestore(&ext_int_hash_lock, flags); |
d7b250e2 HC |
226 | return 0; |
227 | } | |
1dad093b | 228 | EXPORT_SYMBOL(register_external_irq); |
d7b250e2 | 229 | |
1dad093b | 230 | int unregister_external_irq(u16 code, ext_int_handler_t handler) |
d7b250e2 | 231 | { |
89c9b66b JG |
232 | struct ext_int_info *p; |
233 | unsigned long flags; | |
234 | int index = ext_hash(code); | |
d7b250e2 | 235 | |
89c9b66b | 236 | spin_lock_irqsave(&ext_int_hash_lock, flags); |
50ce749d | 237 | hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { |
89c9b66b | 238 | if (p->code == code && p->handler == handler) { |
50ce749d | 239 | hlist_del_rcu(&p->entry); |
bc399d6e | 240 | kfree_rcu(p, rcu); |
89c9b66b | 241 | } |
7968ca81 | 242 | } |
89c9b66b | 243 | spin_unlock_irqrestore(&ext_int_hash_lock, flags); |
d7b250e2 HC |
244 | return 0; |
245 | } | |
1dad093b | 246 | EXPORT_SYMBOL(unregister_external_irq); |
d7b250e2 | 247 | |
1f44a225 | 248 | static irqreturn_t do_ext_interrupt(int irq, void *dummy) |
d7b250e2 | 249 | { |
1f44a225 | 250 | struct pt_regs *regs = get_irq_regs(); |
48f6b00c | 251 | struct ext_code ext_code; |
d7b250e2 HC |
252 | struct ext_int_info *p; |
253 | int index; | |
254 | ||
48f6b00c | 255 | ext_code = *(struct ext_code *) ®s->int_code; |
1dad093b | 256 | if (ext_code.code != EXT_IRQ_CLK_COMP) |
fe0f4976 | 257 | set_cpu_flag(CIF_NOHZ_DELAY); |
89c9b66b | 258 | |
fde15c3a | 259 | index = ext_hash(ext_code.code); |
89c9b66b | 260 | rcu_read_lock(); |
50ce749d HC |
261 | hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { |
262 | if (unlikely(p->code != ext_code.code)) | |
263 | continue; | |
264 | p->handler(ext_code, regs->int_parm, regs->int_parm_long); | |
265 | } | |
89c9b66b | 266 | rcu_read_unlock(); |
1f44a225 | 267 | return IRQ_HANDLED; |
d7b250e2 HC |
268 | } |
269 | ||
1f44a225 MS |
270 | static struct irqaction external_interrupt = { |
271 | .name = "EXT", | |
272 | .handler = do_ext_interrupt, | |
273 | }; | |
274 | ||
275 | void __init init_ext_interrupts(void) | |
89c9b66b | 276 | { |
1f44a225 MS |
277 | int idx; |
278 | ||
279 | for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) | |
50ce749d | 280 | INIT_HLIST_HEAD(&ext_int_hash[idx]); |
1f44a225 MS |
281 | |
282 | irq_set_chip_and_handler(EXT_INTERRUPT, | |
283 | &dummy_irq_chip, handle_percpu_irq); | |
284 | setup_irq(EXT_INTERRUPT, &external_interrupt); | |
89c9b66b JG |
285 | } |
286 | ||
82003c3e HC |
287 | static DEFINE_SPINLOCK(irq_subclass_lock); |
288 | static unsigned char irq_subclass_refcount[64]; | |
d7b250e2 | 289 | |
82003c3e | 290 | void irq_subclass_register(enum irq_subclass subclass) |
d7b250e2 | 291 | { |
82003c3e HC |
292 | spin_lock(&irq_subclass_lock); |
293 | if (!irq_subclass_refcount[subclass]) | |
294 | ctl_set_bit(0, subclass); | |
295 | irq_subclass_refcount[subclass]++; | |
296 | spin_unlock(&irq_subclass_lock); | |
d7b250e2 | 297 | } |
82003c3e | 298 | EXPORT_SYMBOL(irq_subclass_register); |
d7b250e2 | 299 | |
82003c3e | 300 | void irq_subclass_unregister(enum irq_subclass subclass) |
d7b250e2 | 301 | { |
82003c3e HC |
302 | spin_lock(&irq_subclass_lock); |
303 | irq_subclass_refcount[subclass]--; | |
304 | if (!irq_subclass_refcount[subclass]) | |
305 | ctl_clear_bit(0, subclass); | |
306 | spin_unlock(&irq_subclass_lock); | |
d7b250e2 | 307 | } |
82003c3e | 308 | EXPORT_SYMBOL(irq_subclass_unregister); |