Merge branches 'acpi-soc', 'acpi-misc', 'acpi-pci' and 'device-properties'
[deliverable/linux.git] / arch / s390 / kernel / smp.c
CommitLineData
1da177e4 1/*
8b646bd7 2 * SMP related functions
1da177e4 3 *
a53c8fab 4 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
5 * Author(s): Denis Joseph Barrow,
6 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
7 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 8 *
39ce010d 9 * based on other smp stuff by
1da177e4
LT
10 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
11 * (c) 1998 Ingo Molnar
12 *
8b646bd7
MS
13 * The code outside of smp.c uses logical cpu numbers, only smp.c does
14 * the translation of logical to physical cpu ids. All new code that
15 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
16 */
17
395d31d4
MS
18#define KMSG_COMPONENT "cpu"
19#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
20
f230886b 21#include <linux/workqueue.h>
1da177e4
LT
22#include <linux/module.h>
23#include <linux/init.h>
1da177e4 24#include <linux/mm.h>
4e950f6f 25#include <linux/err.h>
1da177e4
LT
26#include <linux/spinlock.h>
27#include <linux/kernel_stat.h>
1da177e4 28#include <linux/delay.h>
1da177e4 29#include <linux/interrupt.h>
3324e60a 30#include <linux/irqflags.h>
1da177e4 31#include <linux/cpu.h>
5a0e3ad6 32#include <linux/slab.h>
60a0c68d 33#include <linux/crash_dump.h>
1592a8e4 34#include <linux/memblock.h>
cbb870c8 35#include <asm/asm-offsets.h>
1ec2772e 36#include <asm/diag.h>
1e3cab2f
HC
37#include <asm/switch_to.h>
38#include <asm/facility.h>
46b05d26 39#include <asm/ipl.h>
2b67fc46 40#include <asm/setup.h>
1da177e4 41#include <asm/irq.h>
1da177e4 42#include <asm/tlbflush.h>
27f6b416 43#include <asm/vtimer.h>
411ed322 44#include <asm/lowcore.h>
08d07968 45#include <asm/sclp.h>
c742b31c 46#include <asm/vdso.h>
3ab121ab 47#include <asm/debug.h>
4857d4bb 48#include <asm/os_info.h>
a9ae32c3 49#include <asm/sigp.h>
b5f87f15 50#include <asm/idle.h>
a806170e 51#include "entry.h"
1da177e4 52
8b646bd7
MS
53enum {
54 ec_schedule = 0,
8b646bd7
MS
55 ec_call_function_single,
56 ec_stop_cpu,
57};
08d07968 58
8b646bd7 59enum {
08d07968
HC
60 CPU_STATE_STANDBY,
61 CPU_STATE_CONFIGURED,
62};
63
2f859d0d
HC
64static DEFINE_PER_CPU(struct cpu *, cpu_device);
65
8b646bd7 66struct pcpu {
c667aeac 67 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 68 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 69 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
70 signed char state; /* physical cpu state */
71 signed char polarization; /* physical polarization */
8b646bd7
MS
72 u16 address; /* physical cpu address */
73};
74
d08d9430 75static u8 boot_core_type;
8b646bd7
MS
76static struct pcpu pcpu_devices[NR_CPUS];
77
10ad34bc
MS
78unsigned int smp_cpu_mt_shift;
79EXPORT_SYMBOL(smp_cpu_mt_shift);
80
81unsigned int smp_cpu_mtid;
82EXPORT_SYMBOL(smp_cpu_mtid);
83
1a36a39e
MS
84#ifdef CONFIG_CRASH_DUMP
85__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
86#endif
87
10ad34bc
MS
88static unsigned int smp_max_threads __initdata = -1U;
89
90static int __init early_nosmt(char *s)
91{
92 smp_max_threads = 1;
93 return 0;
94}
95early_param("nosmt", early_nosmt);
96
97static int __init early_smt(char *s)
98{
99 get_option(&s, &smp_max_threads);
100 return 0;
101}
102early_param("smt", early_smt);
103
50ab9a9a
HC
104/*
105 * The smp_cpu_state_mutex must be held when changing the state or polarization
106 * member of a pcpu data structure within the pcpu_devices arreay.
107 */
dbd70fb4 108DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 109
8b646bd7
MS
110/*
111 * Signal processor helper functions.
112 */
1a36a39e 113static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 114{
8b646bd7 115 int cc;
5c0b912e 116
8b646bd7 117 while (1) {
c5e3acd6 118 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 119 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
120 return cc;
121 cpu_relax();
5c0b912e 122 }
5c0b912e
HC
123}
124
8b646bd7 125static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 126{
8b646bd7
MS
127 int cc, retry;
128
129 for (retry = 0; ; retry++) {
c5e3acd6 130 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 131 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
132 break;
133 if (retry >= 3)
134 udelay(10);
135 }
136 return cc;
137}
138
139static inline int pcpu_stopped(struct pcpu *pcpu)
140{
41459d36 141 u32 uninitialized_var(status);
c5e3acd6 142
a9ae32c3 143 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 144 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 145 return 0;
c5e3acd6 146 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
147}
148
149static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 150{
a9ae32c3 151 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 152 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 153 return 1;
524b24ad
HC
154 /* Status stored condition code is equivalent to cpu not running. */
155 return 0;
a93b8ec1
HC
156}
157
1943f53c 158/*
8b646bd7 159 * Find struct pcpu by cpu address.
1943f53c 160 */
10ad34bc 161static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
162{
163 int cpu;
164
8b646bd7
MS
165 for_each_cpu(cpu, mask)
166 if (pcpu_devices[cpu].address == address)
167 return pcpu_devices + cpu;
168 return NULL;
169}
170
171static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
172{
173 int order;
174
dea24190
HC
175 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
176 return;
177 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 178 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
179 pcpu_sigp_retry(pcpu, order, 0);
180}
181
2f859d0d
HC
182#define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
183#define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
184
e2741f17 185static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 186{
2f859d0d 187 unsigned long async_stack, panic_stack;
c667aeac 188 struct lowcore *lc;
8b646bd7
MS
189
190 if (pcpu != &pcpu_devices[0]) {
c667aeac 191 pcpu->lowcore = (struct lowcore *)
8b646bd7 192 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
2f859d0d
HC
193 async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
194 panic_stack = __get_free_page(GFP_KERNEL);
195 if (!pcpu->lowcore || !panic_stack || !async_stack)
8b646bd7 196 goto out;
2f859d0d
HC
197 } else {
198 async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET;
199 panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET;
1943f53c 200 }
8b646bd7
MS
201 lc = pcpu->lowcore;
202 memcpy(lc, &S390_lowcore, 512);
203 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
2f859d0d
HC
204 lc->async_stack = async_stack + ASYNC_FRAME_OFFSET;
205 lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET;
8b646bd7 206 lc->cpu_nr = cpu;
6c8cd5bb 207 lc->spinlock_lockval = arch_spin_lockval(cpu);
80703617
MS
208 if (MACHINE_HAS_VX)
209 lc->vector_save_area_addr =
210 (unsigned long) &lc->vector_save_area;
8b646bd7
MS
211 if (vdso_alloc_per_cpu(lc))
212 goto out;
8b646bd7 213 lowcore_ptr[cpu] = lc;
a9ae32c3 214 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7
MS
215 return 0;
216out:
217 if (pcpu != &pcpu_devices[0]) {
2f859d0d
HC
218 free_page(panic_stack);
219 free_pages(async_stack, ASYNC_ORDER);
8b646bd7
MS
220 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
221 }
222 return -ENOMEM;
1943f53c
MH
223}
224
9d0f46af
HC
225#ifdef CONFIG_HOTPLUG_CPU
226
8b646bd7 227static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 228{
a9ae32c3 229 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 230 lowcore_ptr[pcpu - pcpu_devices] = NULL;
8b646bd7 231 vdso_free_per_cpu(pcpu->lowcore);
2f859d0d
HC
232 if (pcpu == &pcpu_devices[0])
233 return;
234 free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET);
235 free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER);
236 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
8b646bd7
MS
237}
238
9d0f46af
HC
239#endif /* CONFIG_HOTPLUG_CPU */
240
8b646bd7
MS
241static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
242{
c667aeac 243 struct lowcore *lc = pcpu->lowcore;
8b646bd7 244
1b948d6c
MS
245 if (MACHINE_HAS_TLB_LC)
246 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
247 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7
MS
248 atomic_inc(&init_mm.context.attach_count);
249 lc->cpu_nr = cpu;
6c8cd5bb 250 lc->spinlock_lockval = arch_spin_lockval(cpu);
8b646bd7
MS
251 lc->percpu_offset = __per_cpu_offset[cpu];
252 lc->kernel_asce = S390_lowcore.kernel_asce;
253 lc->machine_flags = S390_lowcore.machine_flags;
8b646bd7
MS
254 lc->user_timer = lc->system_timer = lc->steal_timer = 0;
255 __ctl_store(lc->cregs_save_area, 0, 15);
256 save_access_regs((unsigned int *) lc->access_regs_save_area);
257 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
258 MAX_FACILITY_BIT/8);
259}
260
261static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
262{
c667aeac 263 struct lowcore *lc = pcpu->lowcore;
8b646bd7
MS
264 struct thread_info *ti = task_thread_info(tsk);
265
dc7ee00d
MS
266 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
267 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7
MS
268 lc->thread_info = (unsigned long) task_thread_info(tsk);
269 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
270 lc->lpp = LPP_MAGIC;
271 lc->current_pid = tsk->pid;
8b646bd7
MS
272 lc->user_timer = ti->user_timer;
273 lc->system_timer = ti->system_timer;
274 lc->steal_timer = 0;
275}
276
277static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
278{
c667aeac 279 struct lowcore *lc = pcpu->lowcore;
8b646bd7
MS
280
281 lc->restart_stack = lc->kernel_stack;
282 lc->restart_fn = (unsigned long) func;
283 lc->restart_data = (unsigned long) data;
284 lc->restart_source = -1UL;
a9ae32c3 285 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
286}
287
288/*
289 * Call function via PSW restart on pcpu and stop the current cpu.
290 */
291static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
292 void *data, unsigned long stack)
293{
c667aeac 294 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 295 unsigned long source_cpu = stap();
8b646bd7 296
e258d719 297 __load_psw_mask(PSW_KERNEL_BITS);
fbe76568 298 if (pcpu->address == source_cpu)
8b646bd7
MS
299 func(data); /* should not return */
300 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 301 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 302 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
303 mem_assign_absolute(lc->restart_stack, stack);
304 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
305 mem_assign_absolute(lc->restart_data, (unsigned long) data);
306 mem_assign_absolute(lc->restart_source, source_cpu);
8b646bd7 307 asm volatile(
eb546195 308 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 309 " brc 2,0b # busy, try again\n"
eb546195 310 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 311 " brc 2,1b # busy, try again\n"
fbe76568 312 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
313 "K" (SIGP_RESTART), "K" (SIGP_STOP)
314 : "0", "1", "cc");
8b646bd7
MS
315 for (;;) ;
316}
317
10ad34bc
MS
318/*
319 * Enable additional logical cpus for multi-threading.
320 */
321static int pcpu_set_smt(unsigned int mtid)
322{
323 register unsigned long reg1 asm ("1") = (unsigned long) mtid;
324 int cc;
325
326 if (smp_cpu_mtid == mtid)
327 return 0;
328 asm volatile(
329 " sigp %1,0,%2 # sigp set multi-threading\n"
330 " ipm %0\n"
331 " srl %0,28\n"
332 : "=d" (cc) : "d" (reg1), "K" (SIGP_SET_MULTI_THREADING)
333 : "cc");
334 if (cc == 0) {
335 smp_cpu_mtid = mtid;
336 smp_cpu_mt_shift = 0;
337 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
338 smp_cpu_mt_shift++;
339 pcpu_devices[0].address = stap();
340 }
341 return cc;
342}
343
8b646bd7
MS
344/*
345 * Call function on an online CPU.
346 */
347void smp_call_online_cpu(void (*func)(void *), void *data)
348{
349 struct pcpu *pcpu;
350
351 /* Use the current cpu if it is online. */
352 pcpu = pcpu_find_address(cpu_online_mask, stap());
353 if (!pcpu)
354 /* Use the first online cpu. */
355 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
356 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
357}
358
359/*
360 * Call function on the ipl CPU.
361 */
362void smp_call_ipl_cpu(void (*func)(void *), void *data)
363{
c6da39f2 364 pcpu_delegate(&pcpu_devices[0], func, data,
2f859d0d
HC
365 pcpu_devices->lowcore->panic_stack -
366 PANIC_FRAME_OFFSET + PAGE_SIZE);
8b646bd7
MS
367}
368
369int smp_find_processor_id(u16 address)
370{
371 int cpu;
372
373 for_each_present_cpu(cpu)
374 if (pcpu_devices[cpu].address == address)
375 return cpu;
376 return -1;
2c2df118
HC
377}
378
8b646bd7 379int smp_vcpu_scheduled(int cpu)
85ac7ca5 380{
8b646bd7
MS
381 return pcpu_running(pcpu_devices + cpu);
382}
383
8b646bd7 384void smp_yield_cpu(int cpu)
85ac7ca5 385{
1ec2772e 386 if (MACHINE_HAS_DIAG9C) {
b5a6b71b 387 diag_stat_inc_norecursion(DIAG_STAT_X09C);
8b646bd7
MS
388 asm volatile("diag %0,0,0x9c"
389 : : "d" (pcpu_devices[cpu].address));
1ec2772e 390 } else if (MACHINE_HAS_DIAG44) {
b5a6b71b 391 diag_stat_inc_norecursion(DIAG_STAT_X044);
8b646bd7 392 asm volatile("diag 0,0,0x44");
1ec2772e 393 }
8b646bd7
MS
394}
395
396/*
397 * Send cpus emergency shutdown signal. This gives the cpus the
398 * opportunity to complete outstanding interrupts.
399 */
63df41d6 400static void smp_emergency_stop(cpumask_t *cpumask)
8b646bd7
MS
401{
402 u64 end;
403 int cpu;
404
1aae0560 405 end = get_tod_clock() + (1000000UL << 12);
8b646bd7
MS
406 for_each_cpu(cpu, cpumask) {
407 struct pcpu *pcpu = pcpu_devices + cpu;
408 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
409 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
410 0, NULL) == SIGP_CC_BUSY &&
1aae0560 411 get_tod_clock() < end)
8b646bd7
MS
412 cpu_relax();
413 }
1aae0560 414 while (get_tod_clock() < end) {
8b646bd7
MS
415 for_each_cpu(cpu, cpumask)
416 if (pcpu_stopped(pcpu_devices + cpu))
417 cpumask_clear_cpu(cpu, cpumask);
418 if (cpumask_empty(cpumask))
419 break;
85ac7ca5 420 cpu_relax();
8b646bd7 421 }
85ac7ca5
MS
422}
423
8b646bd7
MS
424/*
425 * Stop all cpus but the current one.
426 */
677d7623 427void smp_send_stop(void)
1da177e4 428{
85ac7ca5
MS
429 cpumask_t cpumask;
430 int cpu;
1da177e4 431
677d7623 432 /* Disable all interrupts/machine checks */
e258d719 433 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 434 trace_hardirqs_off();
1da177e4 435
3ab121ab 436 debug_set_critical();
85ac7ca5
MS
437 cpumask_copy(&cpumask, cpu_online_mask);
438 cpumask_clear_cpu(smp_processor_id(), &cpumask);
439
8b646bd7
MS
440 if (oops_in_progress)
441 smp_emergency_stop(&cpumask);
1da177e4 442
85ac7ca5
MS
443 /* stop all processors */
444 for_each_cpu(cpu, &cpumask) {
8b646bd7 445 struct pcpu *pcpu = pcpu_devices + cpu;
a9ae32c3 446 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 447 while (!pcpu_stopped(pcpu))
c6b5b847
HC
448 cpu_relax();
449 }
450}
451
1da177e4
LT
452/*
453 * This is the main routine where commands issued by other
454 * cpus are handled.
455 */
9acf73b7 456static void smp_handle_ext_call(void)
1da177e4 457{
39ce010d 458 unsigned long bits;
1da177e4 459
9acf73b7
HC
460 /* handle bit signal external calls */
461 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
462 if (test_bit(ec_stop_cpu, &bits))
463 smp_stop_cpu();
184748cc
PZ
464 if (test_bit(ec_schedule, &bits))
465 scheduler_ipi();
ca9fc75a
HC
466 if (test_bit(ec_call_function_single, &bits))
467 generic_smp_call_function_single_interrupt();
9acf73b7 468}
85ac7ca5 469
9acf73b7
HC
470static void do_ext_call_interrupt(struct ext_code ext_code,
471 unsigned int param32, unsigned long param64)
472{
473 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
474 smp_handle_ext_call();
1da177e4
LT
475}
476
630cd046 477void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
478{
479 int cpu;
480
630cd046 481 for_each_cpu(cpu, mask)
b6ed49e0 482 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
483}
484
485void arch_send_call_function_single_ipi(int cpu)
486{
8b646bd7 487 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
488}
489
1da177e4
LT
490/*
491 * this function sends a 'reschedule' IPI to another CPU.
492 * it goes straight through and wastes no time serializing
493 * anything. Worst case is that we lose a reschedule ...
494 */
495void smp_send_reschedule(int cpu)
496{
8b646bd7 497 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
498}
499
500/*
501 * parameter area for the set/clear control bit callbacks
502 */
94c12cc7 503struct ec_creg_mask_parms {
8b646bd7
MS
504 unsigned long orval;
505 unsigned long andval;
506 int cr;
94c12cc7 507};
1da177e4
LT
508
509/*
510 * callback for setting/clearing control bits
511 */
39ce010d
HC
512static void smp_ctl_bit_callback(void *info)
513{
94c12cc7 514 struct ec_creg_mask_parms *pp = info;
1da177e4 515 unsigned long cregs[16];
39ce010d 516
94c12cc7 517 __ctl_store(cregs, 0, 15);
8b646bd7 518 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 519 __ctl_load(cregs, 0, 15);
1da177e4
LT
520}
521
522/*
523 * Set a bit in a control register of all cpus
524 */
94c12cc7
MS
525void smp_ctl_set_bit(int cr, int bit)
526{
8b646bd7 527 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 528
15c8b6c1 529 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 530}
39ce010d 531EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
532
533/*
534 * Clear a bit in a control register of all cpus
535 */
94c12cc7
MS
536void smp_ctl_clear_bit(int cr, int bit)
537{
8b646bd7 538 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 539
15c8b6c1 540 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 541}
39ce010d 542EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 543
bf28a597 544#ifdef CONFIG_CRASH_DUMP
411ed322 545
1af135a1
HC
546int smp_store_status(int cpu)
547{
1a36a39e
MS
548 struct pcpu *pcpu = pcpu_devices + cpu;
549 unsigned long pa;
1af135a1 550
1a36a39e
MS
551 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
552 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
553 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1
HC
554 return -EIO;
555 if (!MACHINE_HAS_VX)
556 return 0;
1a36a39e
MS
557 pa = __pa(pcpu->lowcore->vector_save_area_addr);
558 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
559 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
560 return -EIO;
1af135a1
HC
561 return 0;
562}
563
10ad34bc
MS
564/*
565 * Collect CPU state of the previous, crashed system.
566 * There are four cases:
567 * 1) standard zfcp dump
568 * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
569 * The state for all CPUs except the boot CPU needs to be collected
570 * with sigp stop-and-store-status. The boot CPU state is located in
571 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 572 * will copy the boot CPU state from the HSA.
10ad34bc
MS
573 * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory)
574 * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP
575 * The state for all CPUs except the boot CPU needs to be collected
576 * with sigp stop-and-store-status. The firmware or the boot-loader
577 * stored the registers of the boot CPU in the absolute lowcore in the
578 * memory of the old system.
579 * 3) kdump and the old kernel did not store the CPU state,
580 * or stand-alone kdump for DASD
581 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
582 * The state for all CPUs except the boot CPU needs to be collected
583 * with sigp stop-and-store-status. The kexec code or the boot-loader
584 * stored the registers of the boot CPU in the memory of the old system.
585 * 4) kdump and the old kernel stored the CPU state
586 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
587 * This case does not exist for s390 anymore, setup_arch explicitly
588 * deactivates the elfcorehdr= kernel parameter
10ad34bc 589 */
1a2c5840 590static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
591 bool is_boot_cpu, unsigned long page)
592{
593 __vector128 *vxrs = (__vector128 *) page;
594
595 if (is_boot_cpu)
596 vxrs = boot_cpu_vector_save_area;
597 else
598 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 599 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
600}
601
1a2c5840 602static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
603 bool is_boot_cpu, unsigned long page)
604{
605 void *regs = (void *) page;
606
607 if (is_boot_cpu)
608 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
609 else
610 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 611 save_area_add_regs(sa, regs);
1a36a39e
MS
612}
613
1592a8e4 614void __init smp_save_dump_cpus(void)
10ad34bc 615{
1a2c5840
MS
616 int addr, boot_cpu_addr, max_cpu_addr;
617 struct save_area *sa;
1a36a39e 618 unsigned long page;
1592a8e4 619 bool is_boot_cpu;
10ad34bc 620
10ad34bc
MS
621 if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP))
622 /* No previous system present, normal boot. */
623 return;
1a36a39e
MS
624 /* Allocate a page as dumping area for the store status sigps */
625 page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31);
10ad34bc 626 /* Set multi-threading state to the previous system. */
37c5f6c8 627 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 628 boot_cpu_addr = stap();
1a2c5840
MS
629 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
630 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 631 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
632 SIGP_CC_NOT_OPERATIONAL)
633 continue;
1592a8e4 634 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
635 /* Allocate save area */
636 sa = save_area_alloc(is_boot_cpu);
637 if (!sa)
638 panic("could not allocate memory for save area\n");
1a36a39e
MS
639 if (MACHINE_HAS_VX)
640 /* Get the vector registers */
1a2c5840 641 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e
MS
642 /*
643 * For a zfcp dump OLDMEM_BASE == NULL and the registers
644 * of the boot CPU are stored in the HSA. To retrieve
645 * these registers an SCLP request is required which is
646 * done by drivers/s390/char/zcore.c:init_cpu_info()
647 */
648 if (!is_boot_cpu || OLDMEM_BASE)
649 /* Get the CPU registers */
1a2c5840 650 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 651 }
1a36a39e 652 memblock_free(page, PAGE_SIZE);
1592a8e4
MH
653 diag308_reset();
654 pcpu_set_smt(0);
1af135a1 655}
1a36a39e 656#endif /* CONFIG_CRASH_DUMP */
08d07968 657
50ab9a9a
HC
658void smp_cpu_set_polarization(int cpu, int val)
659{
660 pcpu_devices[cpu].polarization = val;
661}
662
663int smp_cpu_get_polarization(int cpu)
664{
665 return pcpu_devices[cpu].polarization;
666}
667
d08d9430 668static struct sclp_core_info *smp_get_core_info(void)
08d07968 669{
8b646bd7 670 static int use_sigp_detection;
d08d9430 671 struct sclp_core_info *info;
8b646bd7
MS
672 int address;
673
674 info = kzalloc(sizeof(*info), GFP_KERNEL);
d08d9430 675 if (info && (use_sigp_detection || sclp_get_core_info(info))) {
8b646bd7 676 use_sigp_detection = 1;
e7086eb1 677 for (address = 0;
d08d9430 678 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 679 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 680 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 681 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 682 continue;
d08d9430 683 info->core[info->configured].core_id =
10ad34bc 684 address >> smp_cpu_mt_shift;
8b646bd7
MS
685 info->configured++;
686 }
687 info->combined = info->configured;
08d07968 688 }
8b646bd7 689 return info;
08d07968
HC
690}
691
e2741f17 692static int smp_add_present_cpu(int cpu);
8b646bd7 693
d08d9430 694static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add)
08d07968 695{
8b646bd7 696 struct pcpu *pcpu;
08d07968 697 cpumask_t avail;
10ad34bc
MS
698 int cpu, nr, i, j;
699 u16 address;
08d07968 700
8b646bd7 701 nr = 0;
0f1959f5 702 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
8b646bd7
MS
703 cpu = cpumask_first(&avail);
704 for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
d08d9430 705 if (sclp.has_core_type && info->core[i].type != boot_core_type)
8b646bd7 706 continue;
d08d9430 707 address = info->core[i].core_id << smp_cpu_mt_shift;
10ad34bc
MS
708 for (j = 0; j <= smp_cpu_mtid; j++) {
709 if (pcpu_find_address(cpu_present_mask, address + j))
710 continue;
711 pcpu = pcpu_devices + cpu;
712 pcpu->address = address + j;
713 pcpu->state =
714 (cpu >= info->configured*(smp_cpu_mtid + 1)) ?
715 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
716 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
717 set_cpu_present(cpu, true);
718 if (sysfs_add && smp_add_present_cpu(cpu) != 0)
719 set_cpu_present(cpu, false);
720 else
721 nr++;
722 cpu = cpumask_next(cpu, &avail);
723 if (cpu >= nr_cpu_ids)
724 break;
725 }
8b646bd7
MS
726 }
727 return nr;
1da177e4
LT
728}
729
48483b32
HC
730static void __init smp_detect_cpus(void)
731{
10ad34bc 732 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 733 struct sclp_core_info *info;
10ad34bc 734 u16 address;
48483b32 735
10ad34bc 736 /* Get CPU information */
d08d9430 737 info = smp_get_core_info();
48483b32
HC
738 if (!info)
739 panic("smp_detect_cpus failed to allocate memory\n");
10ad34bc
MS
740
741 /* Find boot CPU type */
d08d9430 742 if (sclp.has_core_type) {
10ad34bc
MS
743 address = stap();
744 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 745 if (info->core[cpu].core_id == address) {
10ad34bc 746 /* The boot cpu dictates the cpu type. */
d08d9430 747 boot_core_type = info->core[cpu].type;
10ad34bc
MS
748 break;
749 }
750 if (cpu >= info->combined)
751 panic("Could not find boot CPU type");
48483b32 752 }
10ad34bc 753
10ad34bc 754 /* Set multi-threading state for the current system */
d08d9430 755 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
756 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
757 pcpu_set_smt(mtid);
758
759 /* Print number of CPUs */
8b646bd7 760 c_cpus = s_cpus = 0;
48483b32 761 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
762 if (sclp.has_core_type &&
763 info->core[cpu].type != boot_core_type)
48483b32 764 continue;
10ad34bc
MS
765 if (cpu < info->configured)
766 c_cpus += smp_cpu_mtid + 1;
767 else
768 s_cpus += smp_cpu_mtid + 1;
48483b32 769 }
395d31d4 770 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
771
772 /* Add CPUs present at boot */
9d40d2e3 773 get_online_cpus();
8b646bd7 774 __smp_rescan_cpus(info, 0);
9d40d2e3 775 put_online_cpus();
8b646bd7 776 kfree(info);
48483b32
HC
777}
778
1da177e4 779/*
39ce010d 780 * Activate a secondary processor.
1da177e4 781 */
e2741f17 782static void smp_start_secondary(void *cpuvoid)
1da177e4 783{
1aae0560 784 S390_lowcore.last_update_clock = get_tod_clock();
8b646bd7
MS
785 S390_lowcore.restart_stack = (unsigned long) restart_stack;
786 S390_lowcore.restart_fn = (unsigned long) do_restart;
787 S390_lowcore.restart_data = 0;
788 S390_lowcore.restart_source = -1UL;
789 restore_access_regs(S390_lowcore.access_regs_save_area);
790 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
e258d719 791 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
39ce010d 792 cpu_init();
5bfb5d69 793 preempt_disable();
39ce010d 794 init_cpu_timer();
b5f87f15 795 vtime_init();
29b08d2b 796 pfault_init();
e545a614 797 notify_cpu_starting(smp_processor_id());
0f1959f5 798 set_cpu_online(smp_processor_id(), true);
93f3b2ee 799 inc_irq_stat(CPU_RST);
1da177e4 800 local_irq_enable();
fc6d73d6 801 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
802}
803
1da177e4 804/* Upping and downing of CPUs */
e2741f17 805int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 806{
8b646bd7 807 struct pcpu *pcpu;
10ad34bc 808 int base, i, rc;
1da177e4 809
8b646bd7
MS
810 pcpu = pcpu_devices + cpu;
811 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 812 return -EIO;
10ad34bc
MS
813 base = cpu - (cpu % (smp_cpu_mtid + 1));
814 for (i = 0; i <= smp_cpu_mtid; i++) {
815 if (base + i < nr_cpu_ids)
816 if (cpu_online(base + i))
817 break;
818 }
819 /*
820 * If this is the first CPU of the core to get online
821 * do an initial CPU reset.
822 */
823 if (i > smp_cpu_mtid &&
824 pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 825 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 826 return -EIO;
e80e7813 827
8b646bd7
MS
828 rc = pcpu_alloc_lowcore(pcpu, cpu);
829 if (rc)
830 return rc;
831 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 832 pcpu_attach_task(pcpu, tidle);
8b646bd7 833 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba
HC
834 /* Wait until cpu puts itself in the online & active maps */
835 while (!cpu_online(cpu) || !cpu_active(cpu))
1da177e4
LT
836 cpu_relax();
837 return 0;
838}
839
d80512f8 840static unsigned int setup_possible_cpus __initdata;
255acee7 841
d80512f8
HC
842static int __init _setup_possible_cpus(char *s)
843{
844 get_option(&s, &setup_possible_cpus);
37a33026
HC
845 return 0;
846}
d80512f8 847early_param("possible_cpus", _setup_possible_cpus);
37a33026 848
48483b32
HC
849#ifdef CONFIG_HOTPLUG_CPU
850
39ce010d 851int __cpu_disable(void)
1da177e4 852{
8b646bd7 853 unsigned long cregs[16];
1da177e4 854
9acf73b7
HC
855 /* Handle possible pending IPIs */
856 smp_handle_ext_call();
8b646bd7
MS
857 set_cpu_online(smp_processor_id(), false);
858 /* Disable pseudo page faults on this cpu. */
29b08d2b 859 pfault_fini();
8b646bd7
MS
860 /* Disable interrupt sources via control register. */
861 __ctl_store(cregs, 0, 15);
862 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
863 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
864 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
865 __ctl_load(cregs, 0, 15);
fe0f4976 866 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
867 return 0;
868}
869
39ce010d 870void __cpu_die(unsigned int cpu)
1da177e4 871{
8b646bd7
MS
872 struct pcpu *pcpu;
873
1da177e4 874 /* Wait until target cpu is down */
8b646bd7
MS
875 pcpu = pcpu_devices + cpu;
876 while (!pcpu_stopped(pcpu))
1da177e4 877 cpu_relax();
8b646bd7 878 pcpu_free_lowcore(pcpu);
050eef36 879 atomic_dec(&init_mm.context.attach_count);
1b948d6c
MS
880 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
881 if (MACHINE_HAS_TLB_LC)
882 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
883}
884
b456d94a 885void __noreturn cpu_die(void)
1da177e4
LT
886{
887 idle_task_exit();
a9ae32c3 888 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 889 for (;;) ;
1da177e4
LT
890}
891
255acee7
HC
892#endif /* CONFIG_HOTPLUG_CPU */
893
d80512f8
HC
894void __init smp_fill_possible_mask(void)
895{
9747bc47 896 unsigned int possible, sclp_max, cpu;
d80512f8 897
3a9f3fe6
DH
898 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
899 sclp_max = min(smp_max_threads, sclp_max);
d08d9430 900 sclp_max = sclp.max_cores * sclp_max ?: nr_cpu_ids;
cf813db0 901 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 902 possible = min(possible, sclp_max);
d80512f8
HC
903 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
904 set_cpu_possible(cpu, true);
905}
906
1da177e4
LT
907void __init smp_prepare_cpus(unsigned int max_cpus)
908{
39ce010d 909 /* request the 0x1201 emergency signal external interrupt */
1dad093b 910 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 911 panic("Couldn't request external interrupt 0x1201");
d98e19cc 912 /* request the 0x1202 external call external interrupt */
1dad093b 913 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 914 panic("Couldn't request external interrupt 0x1202");
8b646bd7 915 smp_detect_cpus();
1da177e4
LT
916}
917
ea1f4eec 918void __init smp_prepare_boot_cpu(void)
1da177e4 919{
8b646bd7
MS
920 struct pcpu *pcpu = pcpu_devices;
921
8b646bd7 922 pcpu->state = CPU_STATE_CONFIGURED;
10ad34bc 923 pcpu->address = stap();
c667aeac 924 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 925 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 926 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
8b646bd7
MS
927 set_cpu_present(0, true);
928 set_cpu_online(0, true);
1da177e4
LT
929}
930
ea1f4eec 931void __init smp_cpus_done(unsigned int max_cpus)
1da177e4 932{
1da177e4
LT
933}
934
02beaccc
HC
935void __init smp_setup_processor_id(void)
936{
937 S390_lowcore.cpu_nr = 0;
6c8cd5bb 938 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
02beaccc
HC
939}
940
1da177e4
LT
941/*
942 * the frequency of the profiling timer can be changed
943 * by writing a multiplier value into /proc/profile.
944 *
945 * usually you want to run this on all CPUs ;)
946 */
947int setup_profiling_timer(unsigned int multiplier)
948{
39ce010d 949 return 0;
1da177e4
LT
950}
951
08d07968 952#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 953static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 954 struct device_attribute *attr, char *buf)
08d07968
HC
955{
956 ssize_t count;
957
958 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 959 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
960 mutex_unlock(&smp_cpu_state_mutex);
961 return count;
962}
963
8a25a2fd 964static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
965 struct device_attribute *attr,
966 const char *buf, size_t count)
08d07968 967{
8b646bd7 968 struct pcpu *pcpu;
10ad34bc 969 int cpu, val, rc, i;
08d07968
HC
970 char delim;
971
972 if (sscanf(buf, "%d %c", &val, &delim) != 1)
973 return -EINVAL;
974 if (val != 0 && val != 1)
975 return -EINVAL;
9d40d2e3 976 get_online_cpus();
0b18d318 977 mutex_lock(&smp_cpu_state_mutex);
08d07968 978 rc = -EBUSY;
2c2df118 979 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 980 cpu = dev->id;
10ad34bc
MS
981 cpu -= cpu % (smp_cpu_mtid + 1);
982 if (cpu == 0)
08d07968 983 goto out;
10ad34bc
MS
984 for (i = 0; i <= smp_cpu_mtid; i++)
985 if (cpu_online(cpu + i))
986 goto out;
8b646bd7 987 pcpu = pcpu_devices + cpu;
08d07968
HC
988 rc = 0;
989 switch (val) {
990 case 0:
8b646bd7
MS
991 if (pcpu->state != CPU_STATE_CONFIGURED)
992 break;
d08d9430 993 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
994 if (rc)
995 break;
10ad34bc
MS
996 for (i = 0; i <= smp_cpu_mtid; i++) {
997 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
998 continue;
999 pcpu[i].state = CPU_STATE_STANDBY;
1000 smp_cpu_set_polarization(cpu + i,
1001 POLARIZATION_UNKNOWN);
1002 }
8b646bd7 1003 topology_expect_change();
08d07968
HC
1004 break;
1005 case 1:
8b646bd7
MS
1006 if (pcpu->state != CPU_STATE_STANDBY)
1007 break;
d08d9430 1008 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1009 if (rc)
1010 break;
10ad34bc
MS
1011 for (i = 0; i <= smp_cpu_mtid; i++) {
1012 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1013 continue;
1014 pcpu[i].state = CPU_STATE_CONFIGURED;
1015 smp_cpu_set_polarization(cpu + i,
1016 POLARIZATION_UNKNOWN);
1017 }
8b646bd7 1018 topology_expect_change();
08d07968
HC
1019 break;
1020 default:
1021 break;
1022 }
1023out:
08d07968 1024 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1025 put_online_cpus();
08d07968
HC
1026 return rc ? rc : count;
1027}
8a25a2fd 1028static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968
HC
1029#endif /* CONFIG_HOTPLUG_CPU */
1030
8a25a2fd
KS
1031static ssize_t show_cpu_address(struct device *dev,
1032 struct device_attribute *attr, char *buf)
08d07968 1033{
8b646bd7 1034 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1035}
8a25a2fd 1036static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1037
08d07968
HC
1038static struct attribute *cpu_common_attrs[] = {
1039#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1040 &dev_attr_configure.attr,
08d07968 1041#endif
8a25a2fd 1042 &dev_attr_address.attr,
08d07968
HC
1043 NULL,
1044};
1045
1046static struct attribute_group cpu_common_attr_group = {
1047 .attrs = cpu_common_attrs,
1048};
1da177e4 1049
08d07968 1050static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1051 &dev_attr_idle_count.attr,
1052 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1053 NULL,
1054};
1055
08d07968
HC
1056static struct attribute_group cpu_online_attr_group = {
1057 .attrs = cpu_online_attrs,
fae8b22d
HC
1058};
1059
e2741f17
PG
1060static int smp_cpu_notify(struct notifier_block *self, unsigned long action,
1061 void *hcpu)
2fc2d1e9
HC
1062{
1063 unsigned int cpu = (unsigned int)(long)hcpu;
2f859d0d 1064 struct device *s = &per_cpu(cpu_device, cpu)->dev;
d882ba69 1065 int err = 0;
2fc2d1e9 1066
1c725922 1067 switch (action & ~CPU_TASKS_FROZEN) {
2fc2d1e9 1068 case CPU_ONLINE:
d882ba69 1069 err = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
2fc2d1e9
HC
1070 break;
1071 case CPU_DEAD:
08d07968 1072 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
2fc2d1e9
HC
1073 break;
1074 }
d882ba69 1075 return notifier_from_errno(err);
2fc2d1e9
HC
1076}
1077
e2741f17 1078static int smp_add_present_cpu(int cpu)
08d07968 1079{
96619fc1
HC
1080 struct device *s;
1081 struct cpu *c;
08d07968
HC
1082 int rc;
1083
96619fc1
HC
1084 c = kzalloc(sizeof(*c), GFP_KERNEL);
1085 if (!c)
1086 return -ENOMEM;
2f859d0d 1087 per_cpu(cpu_device, cpu) = c;
96619fc1 1088 s = &c->dev;
08d07968
HC
1089 c->hotpluggable = 1;
1090 rc = register_cpu(c, cpu);
1091 if (rc)
1092 goto out;
1093 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1094 if (rc)
1095 goto out_cpu;
83a24e32
HC
1096 if (cpu_online(cpu)) {
1097 rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1098 if (rc)
1099 goto out_online;
1100 }
1101 rc = topology_cpu_init(c);
1102 if (rc)
1103 goto out_topology;
1104 return 0;
1105
1106out_topology:
1107 if (cpu_online(cpu))
1108 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1109out_online:
08d07968
HC
1110 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1111out_cpu:
1112#ifdef CONFIG_HOTPLUG_CPU
1113 unregister_cpu(c);
1114#endif
1115out:
1116 return rc;
1117}
1118
1119#ifdef CONFIG_HOTPLUG_CPU
1e489518 1120
67060d9c 1121int __ref smp_rescan_cpus(void)
08d07968 1122{
d08d9430 1123 struct sclp_core_info *info;
8b646bd7 1124 int nr;
08d07968 1125
d08d9430 1126 info = smp_get_core_info();
8b646bd7
MS
1127 if (!info)
1128 return -ENOMEM;
9d40d2e3 1129 get_online_cpus();
0b18d318 1130 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1131 nr = __smp_rescan_cpus(info, 1);
08d07968 1132 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1133 put_online_cpus();
8b646bd7
MS
1134 kfree(info);
1135 if (nr)
c10fde0d 1136 topology_schedule_update();
8b646bd7 1137 return 0;
1e489518
HC
1138}
1139
8a25a2fd
KS
1140static ssize_t __ref rescan_store(struct device *dev,
1141 struct device_attribute *attr,
c9be0a36 1142 const char *buf,
1e489518
HC
1143 size_t count)
1144{
1145 int rc;
1146
1147 rc = smp_rescan_cpus();
08d07968
HC
1148 return rc ? rc : count;
1149}
8a25a2fd 1150static DEVICE_ATTR(rescan, 0200, NULL, rescan_store);
08d07968
HC
1151#endif /* CONFIG_HOTPLUG_CPU */
1152
83a24e32 1153static int __init s390_smp_init(void)
1da177e4 1154{
f4edbcd5 1155 int cpu, rc = 0;
2fc2d1e9 1156
08d07968 1157#ifdef CONFIG_HOTPLUG_CPU
8a25a2fd 1158 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1159 if (rc)
1160 return rc;
1161#endif
f4edbcd5 1162 cpu_notifier_register_begin();
08d07968
HC
1163 for_each_present_cpu(cpu) {
1164 rc = smp_add_present_cpu(cpu);
fae8b22d 1165 if (rc)
f4edbcd5 1166 goto out;
1da177e4 1167 }
f4edbcd5
SB
1168
1169 __hotcpu_notifier(smp_cpu_notify, 0);
1170
1171out:
1172 cpu_notifier_register_done();
1173 return rc;
1da177e4 1174}
83a24e32 1175subsys_initcall(s390_smp_init);
This page took 0.768856 seconds and 5 git commands to generate.