Commit | Line | Data |
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4c5107e4 PM |
1 | /* |
2 | * New-style PCI core. | |
3 | * | |
4c5107e4 | 4 | * Copyright (c) 2004 - 2009 Paul Mundt |
35bcfffd PM |
5 | * Copyright (c) 2002 M. R. Brown |
6 | * | |
7 | * Modelled after arch/mips/pci/pci.c: | |
8 | * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) | |
4c5107e4 PM |
9 | * |
10 | * This file is subject to the terms and conditions of the GNU General Public | |
11 | * License. See the file "COPYING" in the main directory of this archive | |
12 | * for more details. | |
13 | */ | |
14 | #include <linux/kernel.h> | |
35bcfffd | 15 | #include <linux/mm.h> |
4c5107e4 PM |
16 | #include <linux/pci.h> |
17 | #include <linux/init.h> | |
35bcfffd | 18 | #include <linux/types.h> |
4c5107e4 PM |
19 | #include <linux/dma-debug.h> |
20 | #include <linux/io.h> | |
e79066a6 | 21 | #include <linux/mutex.h> |
39a90865 | 22 | #include <linux/spinlock.h> |
4c5107e4 | 23 | |
35bcfffd PM |
24 | unsigned long PCIBIOS_MIN_IO = 0x0000; |
25 | unsigned long PCIBIOS_MIN_MEM = 0; | |
26 | ||
e79066a6 PM |
27 | /* |
28 | * The PCI controller list. | |
29 | */ | |
30 | static struct pci_channel *hose_head, **hose_tail = &hose_head; | |
31 | ||
32 | static int pci_initialized; | |
33 | ||
34 | static void __devinit pcibios_scanbus(struct pci_channel *hose) | |
4c5107e4 | 35 | { |
e79066a6 | 36 | static int next_busno; |
320e68da | 37 | static int need_domain_info; |
4c5107e4 | 38 | struct pci_bus *bus; |
e79066a6 | 39 | |
e79066a6 | 40 | bus = pci_scan_bus(next_busno, hose->pci_ops, hose); |
320e68da PM |
41 | hose->bus = bus; |
42 | ||
43 | need_domain_info = need_domain_info || hose->index; | |
44 | hose->need_domain_info = need_domain_info; | |
e79066a6 PM |
45 | if (bus) { |
46 | next_busno = bus->subordinate + 1; | |
47 | /* Don't allow 8-bit bus number overflow inside the hose - | |
48 | reserve some space for bridges. */ | |
320e68da | 49 | if (next_busno > 224) { |
e79066a6 | 50 | next_busno = 0; |
320e68da PM |
51 | need_domain_info = 1; |
52 | } | |
e79066a6 PM |
53 | |
54 | pci_bus_size_bridges(bus); | |
55 | pci_bus_assign_resources(bus); | |
56 | pci_enable_bridges(bus); | |
4c5107e4 | 57 | } |
e79066a6 | 58 | } |
4c5107e4 | 59 | |
39a90865 PM |
60 | /* |
61 | * This interrupt-safe spinlock protects all accesses to PCI | |
62 | * configuration space. | |
63 | */ | |
64 | DEFINE_RAW_SPINLOCK(pci_config_lock); | |
e79066a6 | 65 | static DEFINE_MUTEX(pci_scan_mutex); |
4c5107e4 | 66 | |
bcf39352 | 67 | int __devinit register_pci_controller(struct pci_channel *hose) |
e79066a6 | 68 | { |
b6c58b1d PM |
69 | int i; |
70 | ||
71 | for (i = 0; i < hose->nr_resources; i++) { | |
72 | struct resource *res = hose->resources + i; | |
73 | ||
74 | if (res->flags & IORESOURCE_IO) { | |
75 | if (request_resource(&ioport_resource, res) < 0) | |
76 | goto out; | |
77 | } else { | |
78 | if (request_resource(&iomem_resource, res) < 0) | |
79 | goto out; | |
80 | } | |
ac8ab54a | 81 | } |
e79066a6 PM |
82 | |
83 | *hose_tail = hose; | |
84 | hose_tail = &hose->next; | |
85 | ||
86 | /* | |
25985edc | 87 | * Do not panic here but later - this might happen before console init. |
e79066a6 PM |
88 | */ |
89 | if (!hose->io_map_base) { | |
90 | printk(KERN_WARNING | |
91 | "registering PCI controller with io_map_base unset\n"); | |
92 | } | |
93 | ||
ef407bee PM |
94 | /* |
95 | * Setup the ERR/PERR and SERR timers, if available. | |
96 | */ | |
97 | pcibios_enable_timers(hose); | |
98 | ||
e79066a6 PM |
99 | /* |
100 | * Scan the bus if it is register after the PCI subsystem | |
101 | * initialization. | |
102 | */ | |
103 | if (pci_initialized) { | |
104 | mutex_lock(&pci_scan_mutex); | |
105 | pcibios_scanbus(hose); | |
106 | mutex_unlock(&pci_scan_mutex); | |
4c5107e4 | 107 | } |
ac8ab54a | 108 | |
bcf39352 | 109 | return 0; |
85b59f5b | 110 | |
ac8ab54a | 111 | out: |
b6c58b1d PM |
112 | for (--i; i >= 0; i--) |
113 | release_resource(&hose->resources[i]); | |
114 | ||
ac8ab54a | 115 | printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); |
bcf39352 | 116 | return -1; |
e79066a6 PM |
117 | } |
118 | ||
119 | static int __init pcibios_init(void) | |
120 | { | |
121 | struct pci_channel *hose; | |
122 | ||
123 | /* Scan all of the recorded PCI controllers. */ | |
124 | for (hose = hose_head; hose; hose = hose->next) | |
125 | pcibios_scanbus(hose); | |
126 | ||
4c5107e4 PM |
127 | pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); |
128 | ||
129 | dma_debug_add_bus(&pci_bus_type); | |
130 | ||
e79066a6 PM |
131 | pci_initialized = 1; |
132 | ||
4c5107e4 PM |
133 | return 0; |
134 | } | |
135 | subsys_initcall(pcibios_init); | |
136 | ||
137 | static void pcibios_fixup_device_resources(struct pci_dev *dev, | |
138 | struct pci_bus *bus) | |
139 | { | |
140 | /* Update device resources. */ | |
09cfeb13 | 141 | struct pci_channel *hose = bus->sysdata; |
4c5107e4 PM |
142 | unsigned long offset = 0; |
143 | int i; | |
144 | ||
145 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
146 | if (!dev->resource[i].start) | |
147 | continue; | |
4c5107e4 | 148 | if (dev->resource[i].flags & IORESOURCE_IO) |
09cfeb13 | 149 | offset = hose->io_offset; |
4c5107e4 | 150 | else if (dev->resource[i].flags & IORESOURCE_MEM) |
09cfeb13 | 151 | offset = hose->mem_offset; |
4c5107e4 PM |
152 | |
153 | dev->resource[i].start += offset; | |
154 | dev->resource[i].end += offset; | |
155 | } | |
156 | } | |
157 | ||
4c5107e4 PM |
158 | /* |
159 | * Called after each bus is probed, but before its children | |
160 | * are examined. | |
161 | */ | |
35bcfffd | 162 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
4c5107e4 PM |
163 | { |
164 | struct pci_dev *dev = bus->self; | |
165 | struct list_head *ln; | |
b6c58b1d | 166 | struct pci_channel *hose = bus->sysdata; |
4c5107e4 PM |
167 | |
168 | if (!dev) { | |
b6c58b1d PM |
169 | int i; |
170 | ||
171 | for (i = 0; i < hose->nr_resources; i++) | |
172 | bus->resource[i] = hose->resources + i; | |
4c5107e4 PM |
173 | } |
174 | ||
175 | for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { | |
176 | dev = pci_dev_b(ln); | |
177 | ||
178 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
179 | pcibios_fixup_device_resources(dev, bus); | |
180 | } | |
181 | } | |
35bcfffd PM |
182 | |
183 | /* | |
184 | * We need to avoid collisions with `mirrored' VGA ports | |
185 | * and other strange ISA hardware, so we always want the | |
186 | * addresses to be allocated in the 0x000-0x0ff region | |
187 | * modulo 0x400. | |
188 | */ | |
3b7a17fc | 189 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
b26b2d49 | 190 | resource_size_t size, resource_size_t align) |
35bcfffd PM |
191 | { |
192 | struct pci_dev *dev = data; | |
b6c58b1d | 193 | struct pci_channel *hose = dev->sysdata; |
35bcfffd PM |
194 | resource_size_t start = res->start; |
195 | ||
196 | if (res->flags & IORESOURCE_IO) { | |
b6c58b1d PM |
197 | if (start < PCIBIOS_MIN_IO + hose->resources[0].start) |
198 | start = PCIBIOS_MIN_IO + hose->resources[0].start; | |
35bcfffd PM |
199 | |
200 | /* | |
201 | * Put everything into 0x00-0xff region modulo 0x400. | |
202 | */ | |
84959359 | 203 | if (start & 0x300) |
35bcfffd | 204 | start = (start + 0x3ff) & ~0x3ff; |
35bcfffd PM |
205 | } |
206 | ||
b26b2d49 | 207 | return start; |
35bcfffd PM |
208 | } |
209 | ||
210 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
9ad62ec4 | 211 | struct resource *res) |
35bcfffd PM |
212 | { |
213 | struct pci_channel *hose = dev->sysdata; | |
214 | unsigned long offset = 0; | |
215 | ||
216 | if (res->flags & IORESOURCE_IO) | |
217 | offset = hose->io_offset; | |
218 | else if (res->flags & IORESOURCE_MEM) | |
219 | offset = hose->mem_offset; | |
220 | ||
221 | region->start = res->start - offset; | |
222 | region->end = res->end - offset; | |
223 | } | |
224 | ||
9ad62ec4 PM |
225 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
226 | struct pci_bus_region *region) | |
35bcfffd PM |
227 | { |
228 | struct pci_channel *hose = dev->sysdata; | |
229 | unsigned long offset = 0; | |
230 | ||
231 | if (res->flags & IORESOURCE_IO) | |
232 | offset = hose->io_offset; | |
233 | else if (res->flags & IORESOURCE_MEM) | |
234 | offset = hose->mem_offset; | |
235 | ||
236 | res->start = region->start + offset; | |
237 | res->end = region->end + offset; | |
238 | } | |
239 | ||
240 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
241 | { | |
c62e3fae | 242 | return pci_enable_resources(dev, mask); |
35bcfffd PM |
243 | } |
244 | ||
245 | /* | |
246 | * If we set up a device for bus mastering, we need to check and set | |
247 | * the latency timer as it may not be properly set. | |
248 | */ | |
249 | static unsigned int pcibios_max_latency = 255; | |
250 | ||
251 | void pcibios_set_master(struct pci_dev *dev) | |
252 | { | |
253 | u8 lat; | |
254 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
255 | if (lat < 16) | |
256 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
257 | else if (lat > pcibios_max_latency) | |
258 | lat = pcibios_max_latency; | |
259 | else | |
260 | return; | |
261 | printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", | |
262 | pci_name(dev), lat); | |
263 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
264 | } | |
265 | ||
266 | void __init pcibios_update_irq(struct pci_dev *dev, int irq) | |
267 | { | |
268 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
269 | } | |
270 | ||
61a46766 | 271 | char * __devinit __weak pcibios_setup(char *str) |
35bcfffd PM |
272 | { |
273 | return str; | |
274 | } | |
275 | ||
9ad62ec4 PM |
276 | static void __init |
277 | pcibios_bus_report_status_early(struct pci_channel *hose, | |
278 | int top_bus, int current_bus, | |
279 | unsigned int status_mask, int warn) | |
280 | { | |
281 | unsigned int pci_devfn; | |
282 | u16 status; | |
283 | int ret; | |
284 | ||
285 | for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { | |
286 | if (PCI_FUNC(pci_devfn)) | |
287 | continue; | |
288 | ret = early_read_config_word(hose, top_bus, current_bus, | |
289 | pci_devfn, PCI_STATUS, &status); | |
290 | if (ret != PCIBIOS_SUCCESSFUL) | |
291 | continue; | |
292 | if (status == 0xffff) | |
293 | continue; | |
294 | ||
295 | early_write_config_word(hose, top_bus, current_bus, | |
296 | pci_devfn, PCI_STATUS, | |
297 | status & status_mask); | |
298 | if (warn) | |
299 | printk("(%02x:%02x: %04X) ", current_bus, | |
300 | pci_devfn, status); | |
301 | } | |
302 | } | |
303 | ||
ef407bee PM |
304 | /* |
305 | * We can't use pci_find_device() here since we are | |
306 | * called from interrupt context. | |
307 | */ | |
9ad62ec4 PM |
308 | static void __init_refok |
309 | pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, | |
310 | int warn) | |
ef407bee PM |
311 | { |
312 | struct pci_dev *dev; | |
313 | ||
314 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
315 | u16 status; | |
316 | ||
317 | /* | |
318 | * ignore host bridge - we handle | |
319 | * that separately | |
320 | */ | |
321 | if (dev->bus->number == 0 && dev->devfn == 0) | |
322 | continue; | |
323 | ||
324 | pci_read_config_word(dev, PCI_STATUS, &status); | |
325 | if (status == 0xffff) | |
326 | continue; | |
327 | ||
328 | if ((status & status_mask) == 0) | |
329 | continue; | |
330 | ||
331 | /* clear the status errors */ | |
332 | pci_write_config_word(dev, PCI_STATUS, status & status_mask); | |
333 | ||
334 | if (warn) | |
335 | printk("(%s: %04X) ", pci_name(dev), status); | |
336 | } | |
337 | ||
338 | list_for_each_entry(dev, &bus->devices, bus_list) | |
339 | if (dev->subordinate) | |
340 | pcibios_bus_report_status(dev->subordinate, status_mask, warn); | |
341 | } | |
342 | ||
9ad62ec4 | 343 | void __init_refok pcibios_report_status(unsigned int status_mask, int warn) |
ef407bee PM |
344 | { |
345 | struct pci_channel *hose; | |
346 | ||
9ad62ec4 PM |
347 | for (hose = hose_head; hose; hose = hose->next) { |
348 | if (unlikely(!hose->bus)) | |
349 | pcibios_bus_report_status_early(hose, hose_head->index, | |
350 | hose->index, status_mask, warn); | |
351 | else | |
352 | pcibios_bus_report_status(hose->bus, status_mask, warn); | |
353 | } | |
ef407bee PM |
354 | } |
355 | ||
35bcfffd PM |
356 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
357 | enum pci_mmap_state mmap_state, int write_combine) | |
358 | { | |
359 | /* | |
360 | * I/O space can be accessed via normal processor loads and stores on | |
361 | * this platform but for now we elect not to do this and portable | |
362 | * drivers should not do this anyway. | |
363 | */ | |
364 | if (mmap_state == pci_mmap_io) | |
365 | return -EINVAL; | |
366 | ||
367 | /* | |
368 | * Ignore write-combine; for now only return uncached mappings. | |
369 | */ | |
370 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
371 | ||
372 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
373 | vma->vm_end - vma->vm_start, | |
374 | vma->vm_page_prot); | |
375 | } | |
376 | ||
15444a89 DM |
377 | #ifndef CONFIG_GENERIC_IOMAP |
378 | ||
35bcfffd PM |
379 | static void __iomem *ioport_map_pci(struct pci_dev *dev, |
380 | unsigned long port, unsigned int nr) | |
381 | { | |
382 | struct pci_channel *chan = dev->sysdata; | |
383 | ||
320e68da | 384 | if (unlikely(!chan->io_map_base)) { |
37b7a978 | 385 | chan->io_map_base = sh_io_port_base; |
35bcfffd | 386 | |
320e68da PM |
387 | if (pci_domains_supported) |
388 | panic("To avoid data corruption io_map_base MUST be " | |
389 | "set with multiple PCI domains."); | |
390 | } | |
391 | ||
35bcfffd PM |
392 | return (void __iomem *)(chan->io_map_base + port); |
393 | } | |
394 | ||
395 | void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) | |
396 | { | |
397 | resource_size_t start = pci_resource_start(dev, bar); | |
398 | resource_size_t len = pci_resource_len(dev, bar); | |
399 | unsigned long flags = pci_resource_flags(dev, bar); | |
400 | ||
401 | if (unlikely(!len || !start)) | |
402 | return NULL; | |
403 | if (maxlen && len > maxlen) | |
404 | len = maxlen; | |
405 | ||
406 | if (flags & IORESOURCE_IO) | |
407 | return ioport_map_pci(dev, start, len); | |
35bcfffd PM |
408 | if (flags & IORESOURCE_MEM) { |
409 | if (flags & IORESOURCE_CACHEABLE) | |
410 | return ioremap(start, len); | |
35bcfffd PM |
411 | return ioremap_nocache(start, len); |
412 | } | |
413 | ||
414 | return NULL; | |
415 | } | |
416 | EXPORT_SYMBOL(pci_iomap); | |
417 | ||
418 | void pci_iounmap(struct pci_dev *dev, void __iomem *addr) | |
419 | { | |
420 | iounmap(addr); | |
421 | } | |
422 | EXPORT_SYMBOL(pci_iounmap); | |
423 | ||
15444a89 DM |
424 | #endif /* CONFIG_GENERIC_IOMAP */ |
425 | ||
35bcfffd PM |
426 | #ifdef CONFIG_HOTPLUG |
427 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
428 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
429 | EXPORT_SYMBOL(PCIBIOS_MIN_IO); | |
430 | EXPORT_SYMBOL(PCIBIOS_MIN_MEM); | |
431 | #endif |