Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * arch/sparc64/mm/init.c |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
1da177e4 LT |
16 | #include <linux/initrd.h> |
17 | #include <linux/swap.h> | |
18 | #include <linux/pagemap.h> | |
c9cf5528 | 19 | #include <linux/poison.h> |
1da177e4 LT |
20 | #include <linux/fs.h> |
21 | #include <linux/seq_file.h> | |
05e14cb3 | 22 | #include <linux/kprobes.h> |
1ac4f5eb | 23 | #include <linux/cache.h> |
13edad7a | 24 | #include <linux/sort.h> |
f6d4fb5c | 25 | #include <linux/ioport.h> |
5cbc3073 | 26 | #include <linux/percpu.h> |
95f72d1e | 27 | #include <linux/memblock.h> |
919ee677 | 28 | #include <linux/mmzone.h> |
5a0e3ad6 | 29 | #include <linux/gfp.h> |
1da177e4 LT |
30 | |
31 | #include <asm/head.h> | |
1da177e4 LT |
32 | #include <asm/page.h> |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/dma.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/tlb.h> | |
44 | #include <asm/spitfire.h> | |
45 | #include <asm/sections.h> | |
517af332 | 46 | #include <asm/tsb.h> |
481295f9 | 47 | #include <asm/hypervisor.h> |
372b07bb | 48 | #include <asm/prom.h> |
5cbc3073 | 49 | #include <asm/mdesc.h> |
3d5ae6b6 | 50 | #include <asm/cpudata.h> |
59dec13b | 51 | #include <asm/setup.h> |
4f70f7a9 | 52 | #include <asm/irq.h> |
1da177e4 | 53 | |
27137e52 | 54 | #include "init_64.h" |
9cc3a1ac | 55 | |
4f93d21d | 56 | unsigned long kern_linear_pte_xor[4] __read_mostly; |
494e5b6f | 57 | static unsigned long page_cache4v_flag; |
9cc3a1ac | 58 | |
4f93d21d DM |
59 | /* A bitmap, two bits for every 256MB of physical memory. These two |
60 | * bits determine what page size we use for kernel linear | |
61 | * translations. They form an index into kern_linear_pte_xor[]. The | |
62 | * value in the indexed slot is XOR'd with the TLB miss virtual | |
63 | * address to form the resulting TTE. The mapping is: | |
64 | * | |
65 | * 0 ==> 4MB | |
66 | * 1 ==> 256MB | |
67 | * 2 ==> 2GB | |
68 | * 3 ==> 16GB | |
69 | * | |
70 | * All sun4v chips support 256MB pages. Only SPARC-T4 and later | |
71 | * support 2GB pages, and hopefully future cpus will support the 16GB | |
72 | * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there | |
73 | * if these larger page sizes are not supported by the cpu. | |
74 | * | |
75 | * It would be nice to determine this from the machine description | |
76 | * 'cpu' properties, but we need to have this table setup before the | |
77 | * MDESC is initialized. | |
9cc3a1ac | 78 | */ |
9cc3a1ac | 79 | |
d1acb421 | 80 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d DM |
81 | /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. |
82 | * Space is allocated for this right after the trap table in | |
83 | * arch/sparc64/kernel/head.S | |
2d9e2763 DM |
84 | */ |
85 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 86 | #endif |
0dd5b7b0 | 87 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
d7744a09 | 88 | |
ce33fdc5 DM |
89 | static unsigned long cpu_pgsz_mask; |
90 | ||
d195b71b | 91 | #define MAX_BANKS 1024 |
13edad7a | 92 | |
7c9503b8 GKH |
93 | static struct linux_prom64_registers pavail[MAX_BANKS]; |
94 | static int pavail_ents; | |
13edad7a | 95 | |
52708d69 NG |
96 | u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; |
97 | ||
13edad7a DM |
98 | static int cmp_p64(const void *a, const void *b) |
99 | { | |
100 | const struct linux_prom64_registers *x = a, *y = b; | |
101 | ||
102 | if (x->phys_addr > y->phys_addr) | |
103 | return 1; | |
104 | if (x->phys_addr < y->phys_addr) | |
105 | return -1; | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static void __init read_obp_memory(const char *property, | |
110 | struct linux_prom64_registers *regs, | |
111 | int *num_ents) | |
112 | { | |
8d125562 | 113 | phandle node = prom_finddevice("/memory"); |
13edad7a DM |
114 | int prop_size = prom_getproplen(node, property); |
115 | int ents, ret, i; | |
116 | ||
117 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
118 | if (ents > MAX_BANKS) { | |
119 | prom_printf("The machine has more %s property entries than " | |
120 | "this kernel can support (%d).\n", | |
121 | property, MAX_BANKS); | |
122 | prom_halt(); | |
123 | } | |
124 | ||
125 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
126 | if (ret == -1) { | |
5da444aa AM |
127 | prom_printf("Couldn't get %s property from /memory.\n", |
128 | property); | |
13edad7a DM |
129 | prom_halt(); |
130 | } | |
131 | ||
13edad7a DM |
132 | /* Sanitize what we got from the firmware, by page aligning |
133 | * everything. | |
134 | */ | |
135 | for (i = 0; i < ents; i++) { | |
136 | unsigned long base, size; | |
137 | ||
138 | base = regs[i].phys_addr; | |
139 | size = regs[i].reg_size; | |
10147570 | 140 | |
13edad7a DM |
141 | size &= PAGE_MASK; |
142 | if (base & ~PAGE_MASK) { | |
143 | unsigned long new_base = PAGE_ALIGN(base); | |
144 | ||
145 | size -= new_base - base; | |
146 | if ((long) size < 0L) | |
147 | size = 0UL; | |
148 | base = new_base; | |
149 | } | |
0015d3d6 DM |
150 | if (size == 0UL) { |
151 | /* If it is empty, simply get rid of it. | |
152 | * This simplifies the logic of the other | |
153 | * functions that process these arrays. | |
154 | */ | |
155 | memmove(®s[i], ®s[i + 1], | |
156 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 157 | i--; |
0015d3d6 DM |
158 | ents--; |
159 | continue; | |
486ad10a | 160 | } |
0015d3d6 DM |
161 | regs[i].phys_addr = base; |
162 | regs[i].reg_size = size; | |
486ad10a DM |
163 | } |
164 | ||
165 | *num_ents = ents; | |
166 | ||
c9c10830 | 167 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
168 | cmp_p64, NULL); |
169 | } | |
1da177e4 | 170 | |
d1112018 | 171 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
172 | unsigned long kern_base __read_mostly; |
173 | unsigned long kern_size __read_mostly; | |
1da177e4 | 174 | |
1da177e4 LT |
175 | /* Initial ramdisk setup */ |
176 | extern unsigned long sparc_ramdisk_image64; | |
177 | extern unsigned int sparc_ramdisk_image; | |
178 | extern unsigned int sparc_ramdisk_size; | |
179 | ||
1ac4f5eb | 180 | struct page *mem_map_zero __read_mostly; |
35802c0b | 181 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 182 | |
0835ae0f DM |
183 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
184 | ||
185 | unsigned long sparc64_kern_pri_context __read_mostly; | |
186 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
187 | unsigned long sparc64_kern_sec_context __read_mostly; | |
188 | ||
64658743 | 189 | int num_kernel_image_mappings; |
1da177e4 | 190 | |
1da177e4 LT |
191 | #ifdef CONFIG_DEBUG_DCFLUSH |
192 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
193 | #ifdef CONFIG_SMP | |
194 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
195 | #endif | |
196 | #endif | |
197 | ||
7a591cfe | 198 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 199 | { |
7a591cfe | 200 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
201 | #ifdef CONFIG_DEBUG_DCFLUSH |
202 | atomic_inc(&dcpage_flushes); | |
203 | #endif | |
204 | ||
205 | #ifdef DCACHE_ALIASING_POSSIBLE | |
206 | __flush_dcache_page(page_address(page), | |
207 | ((tlb_type == spitfire) && | |
208 | page_mapping(page) != NULL)); | |
209 | #else | |
210 | if (page_mapping(page) != NULL && | |
211 | tlb_type == spitfire) | |
212 | __flush_icache_page(__pa(page_address(page))); | |
213 | #endif | |
214 | } | |
215 | ||
216 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
217 | #define PG_dcache_cpu_shift 32UL |
218 | #define PG_dcache_cpu_mask \ | |
219 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
220 | |
221 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 222 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 223 | |
d979f179 | 224 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
225 | { |
226 | unsigned long mask = this_cpu; | |
48b0e548 DM |
227 | unsigned long non_cpu_bits; |
228 | ||
229 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
230 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
231 | ||
1da177e4 LT |
232 | __asm__ __volatile__("1:\n\t" |
233 | "ldx [%2], %%g7\n\t" | |
234 | "and %%g7, %1, %%g1\n\t" | |
235 | "or %%g1, %0, %%g1\n\t" | |
236 | "casx [%2], %%g7, %%g1\n\t" | |
237 | "cmp %%g7, %%g1\n\t" | |
238 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 239 | " nop" |
1da177e4 LT |
240 | : /* no outputs */ |
241 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
242 | : "g1", "g7"); | |
243 | } | |
244 | ||
d979f179 | 245 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
246 | { |
247 | unsigned long mask = (1UL << PG_dcache_dirty); | |
248 | ||
249 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
250 | "1:\n\t" | |
251 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 252 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
253 | "and %%g1, %3, %%g1\n\t" |
254 | "cmp %%g1, %0\n\t" | |
255 | "bne,pn %%icc, 2f\n\t" | |
256 | " andn %%g7, %1, %%g1\n\t" | |
257 | "casx [%2], %%g7, %%g1\n\t" | |
258 | "cmp %%g7, %%g1\n\t" | |
259 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 260 | " nop\n" |
1da177e4 LT |
261 | "2:" |
262 | : /* no outputs */ | |
263 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
264 | "i" (PG_dcache_cpu_mask), |
265 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
266 | : "g1", "g7"); |
267 | } | |
268 | ||
517af332 DM |
269 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
270 | { | |
271 | unsigned long tsb_addr = (unsigned long) ent; | |
272 | ||
3b3ab2eb | 273 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
274 | tsb_addr = __pa(tsb_addr); |
275 | ||
276 | __tsb_insert(tsb_addr, tag, pte); | |
277 | } | |
278 | ||
c4bce90e | 279 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
c4bce90e | 280 | |
ff9aefbf | 281 | static void flush_dcache(unsigned long pfn) |
1da177e4 | 282 | { |
ff9aefbf | 283 | struct page *page; |
7a591cfe | 284 | |
ff9aefbf | 285 | page = pfn_to_page(pfn); |
1a78cedb | 286 | if (page) { |
7a591cfe | 287 | unsigned long pg_flags; |
7a591cfe | 288 | |
ff9aefbf SR |
289 | pg_flags = page->flags; |
290 | if (pg_flags & (1UL << PG_dcache_dirty)) { | |
7a591cfe DM |
291 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & |
292 | PG_dcache_cpu_mask); | |
293 | int this_cpu = get_cpu(); | |
294 | ||
295 | /* This is just to optimize away some function calls | |
296 | * in the SMP case. | |
297 | */ | |
298 | if (cpu == this_cpu) | |
299 | flush_dcache_page_impl(page); | |
300 | else | |
301 | smp_flush_dcache_page_impl(page, cpu); | |
302 | ||
303 | clear_dcache_dirty_cpu(page, cpu); | |
304 | ||
305 | put_cpu(); | |
306 | } | |
1da177e4 | 307 | } |
ff9aefbf SR |
308 | } |
309 | ||
9e695d2e DM |
310 | /* mm->context.lock must be held */ |
311 | static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, | |
312 | unsigned long tsb_hash_shift, unsigned long address, | |
313 | unsigned long tte) | |
314 | { | |
315 | struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; | |
316 | unsigned long tag; | |
317 | ||
bcd896ba DM |
318 | if (unlikely(!tsb)) |
319 | return; | |
320 | ||
9e695d2e DM |
321 | tsb += ((address >> tsb_hash_shift) & |
322 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
323 | tag = (address >> 22UL); | |
324 | tsb_insert(tsb, tag, tte); | |
325 | } | |
326 | ||
4b3073e1 | 327 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
ff9aefbf SR |
328 | { |
329 | struct mm_struct *mm; | |
bcd896ba | 330 | unsigned long flags; |
4b3073e1 | 331 | pte_t pte = *ptep; |
ff9aefbf SR |
332 | |
333 | if (tlb_type != hypervisor) { | |
334 | unsigned long pfn = pte_pfn(pte); | |
335 | ||
336 | if (pfn_valid(pfn)) | |
337 | flush_dcache(pfn); | |
338 | } | |
bd40791e DM |
339 | |
340 | mm = vma->vm_mm; | |
7a1ac526 | 341 | |
18f38132 DM |
342 | /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ |
343 | if (!pte_accessible(mm, pte)) | |
344 | return; | |
345 | ||
7a1ac526 DM |
346 | spin_lock_irqsave(&mm->context.lock, flags); |
347 | ||
9e695d2e | 348 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
af1b1a9b | 349 | if ((mm->context.hugetlb_pte_count || mm->context.thp_pte_count) && |
7bc3777c NG |
350 | is_hugetlb_pte(pte)) { |
351 | /* We are fabricating 8MB pages using 4MB real hw pages. */ | |
352 | pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); | |
37b3a8ff | 353 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, |
bcd896ba | 354 | address, pte_val(pte)); |
7bc3777c | 355 | } else |
dcc1e8dd | 356 | #endif |
bcd896ba DM |
357 | __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, |
358 | address, pte_val(pte)); | |
7a1ac526 DM |
359 | |
360 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
361 | } |
362 | ||
363 | void flush_dcache_page(struct page *page) | |
364 | { | |
a9546f59 DM |
365 | struct address_space *mapping; |
366 | int this_cpu; | |
1da177e4 | 367 | |
7a591cfe DM |
368 | if (tlb_type == hypervisor) |
369 | return; | |
370 | ||
a9546f59 DM |
371 | /* Do not bother with the expensive D-cache flush if it |
372 | * is merely the zero page. The 'bigcore' testcase in GDB | |
373 | * causes this case to run millions of times. | |
374 | */ | |
375 | if (page == ZERO_PAGE(0)) | |
376 | return; | |
377 | ||
378 | this_cpu = get_cpu(); | |
379 | ||
380 | mapping = page_mapping(page); | |
1da177e4 | 381 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 382 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 383 | if (dirty) { |
a9546f59 DM |
384 | int dirty_cpu = dcache_dirty_cpu(page); |
385 | ||
1da177e4 LT |
386 | if (dirty_cpu == this_cpu) |
387 | goto out; | |
388 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
389 | } | |
390 | set_dcache_dirty(page, this_cpu); | |
391 | } else { | |
392 | /* We could delay the flush for the !page_mapping | |
393 | * case too. But that case is for exec env/arg | |
394 | * pages and those are %99 certainly going to get | |
395 | * faulted into the tlb (and thus flushed) anyways. | |
396 | */ | |
397 | flush_dcache_page_impl(page); | |
398 | } | |
399 | ||
400 | out: | |
401 | put_cpu(); | |
402 | } | |
917c3660 | 403 | EXPORT_SYMBOL(flush_dcache_page); |
1da177e4 | 404 | |
05e14cb3 | 405 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 406 | { |
a43fe0e7 | 407 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
408 | if (tlb_type == spitfire) { |
409 | unsigned long kaddr; | |
410 | ||
a94aa253 DM |
411 | /* This code only runs on Spitfire cpus so this is |
412 | * why we can assume _PAGE_PADDR_4U. | |
413 | */ | |
414 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
415 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
416 | ||
417 | if (kaddr >= PAGE_OFFSET) | |
418 | paddr = kaddr & mask; | |
419 | else { | |
420 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
421 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
422 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
423 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
424 | ||
425 | paddr = pte_val(*ptep) & mask; | |
426 | } | |
427 | __flush_icache_page(paddr); | |
428 | } | |
1da177e4 LT |
429 | } |
430 | } | |
917c3660 | 431 | EXPORT_SYMBOL(flush_icache_range); |
1da177e4 | 432 | |
1da177e4 LT |
433 | void mmu_info(struct seq_file *m) |
434 | { | |
ce33fdc5 DM |
435 | static const char *pgsz_strings[] = { |
436 | "8K", "64K", "512K", "4MB", "32MB", | |
437 | "256MB", "2GB", "16GB", | |
438 | }; | |
439 | int i, printed; | |
440 | ||
1da177e4 LT |
441 | if (tlb_type == cheetah) |
442 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
443 | else if (tlb_type == cheetah_plus) | |
444 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
445 | else if (tlb_type == spitfire) | |
446 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
447 | else if (tlb_type == hypervisor) |
448 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
449 | else |
450 | seq_printf(m, "MMU Type\t: ???\n"); | |
451 | ||
ce33fdc5 DM |
452 | seq_printf(m, "MMU PGSZs\t: "); |
453 | printed = 0; | |
454 | for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { | |
455 | if (cpu_pgsz_mask & (1UL << i)) { | |
456 | seq_printf(m, "%s%s", | |
457 | printed ? "," : "", pgsz_strings[i]); | |
458 | printed++; | |
459 | } | |
460 | } | |
461 | seq_putc(m, '\n'); | |
462 | ||
1da177e4 LT |
463 | #ifdef CONFIG_DEBUG_DCFLUSH |
464 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
465 | atomic_read(&dcpage_flushes)); | |
466 | #ifdef CONFIG_SMP | |
467 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
468 | atomic_read(&dcpage_flushes_xcall)); | |
469 | #endif /* CONFIG_SMP */ | |
470 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
471 | } | |
472 | ||
a94aa253 DM |
473 | struct linux_prom_translation prom_trans[512] __read_mostly; |
474 | unsigned int prom_trans_ents __read_mostly; | |
475 | ||
1da177e4 LT |
476 | unsigned long kern_locked_tte_data; |
477 | ||
c9c10830 DM |
478 | /* The obp translations are saved based on 8k pagesize, since obp can |
479 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 480 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 481 | */ |
5085b4a5 DM |
482 | static inline int in_obp_range(unsigned long vaddr) |
483 | { | |
484 | return (vaddr >= LOW_OBP_ADDRESS && | |
485 | vaddr < HI_OBP_ADDRESS); | |
486 | } | |
487 | ||
c9c10830 | 488 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 489 | { |
c9c10830 | 490 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 491 | |
c9c10830 DM |
492 | if (x->virt > y->virt) |
493 | return 1; | |
494 | if (x->virt < y->virt) | |
495 | return -1; | |
496 | return 0; | |
405599bd DM |
497 | } |
498 | ||
c9c10830 | 499 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 500 | static void __init read_obp_translations(void) |
405599bd | 501 | { |
c9c10830 | 502 | int n, node, ents, first, last, i; |
1da177e4 LT |
503 | |
504 | node = prom_finddevice("/virtual-memory"); | |
505 | n = prom_getproplen(node, "translations"); | |
405599bd | 506 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 507 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
508 | prom_halt(); |
509 | } | |
405599bd | 510 | if (unlikely(n > sizeof(prom_trans))) { |
5da444aa | 511 | prom_printf("prom_mappings: Size %d is too big.\n", n); |
1da177e4 LT |
512 | prom_halt(); |
513 | } | |
405599bd | 514 | |
b206fc4c | 515 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
516 | (char *)&prom_trans[0], |
517 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 518 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
519 | prom_halt(); |
520 | } | |
9ad98c5b | 521 | |
b206fc4c | 522 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 523 | |
c9c10830 DM |
524 | ents = n; |
525 | ||
526 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
527 | cmp_ptrans, NULL); | |
528 | ||
529 | /* Now kick out all the non-OBP entries. */ | |
530 | for (i = 0; i < ents; i++) { | |
531 | if (in_obp_range(prom_trans[i].virt)) | |
532 | break; | |
533 | } | |
534 | first = i; | |
535 | for (; i < ents; i++) { | |
536 | if (!in_obp_range(prom_trans[i].virt)) | |
537 | break; | |
538 | } | |
539 | last = i; | |
540 | ||
541 | for (i = 0; i < (last - first); i++) { | |
542 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
543 | struct linux_prom_translation *dest = &prom_trans[i]; | |
544 | ||
545 | *dest = *src; | |
546 | } | |
547 | for (; i < ents; i++) { | |
548 | struct linux_prom_translation *dest = &prom_trans[i]; | |
549 | dest->virt = dest->size = dest->data = 0x0UL; | |
550 | } | |
551 | ||
552 | prom_trans_ents = last - first; | |
553 | ||
554 | if (tlb_type == spitfire) { | |
555 | /* Clear diag TTE bits. */ | |
556 | for (i = 0; i < prom_trans_ents; i++) | |
557 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
558 | } | |
f4142cba DM |
559 | |
560 | /* Force execute bit on. */ | |
561 | for (i = 0; i < prom_trans_ents; i++) | |
562 | prom_trans[i].data |= (tlb_type == hypervisor ? | |
563 | _PAGE_EXEC_4V : _PAGE_EXEC_4U); | |
405599bd | 564 | } |
1da177e4 | 565 | |
d82ace7d DM |
566 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
567 | unsigned long pte, | |
568 | unsigned long mmu) | |
569 | { | |
7db35f31 DM |
570 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
571 | ||
572 | if (ret != 0) { | |
5da444aa | 573 | prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " |
7db35f31 | 574 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
575 | prom_halt(); |
576 | } | |
d82ace7d DM |
577 | } |
578 | ||
c4bce90e DM |
579 | static unsigned long kern_large_tte(unsigned long paddr); |
580 | ||
898cf0ec | 581 | static void __init remap_kernel(void) |
405599bd DM |
582 | { |
583 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 584 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 585 | |
1da177e4 | 586 | tte_vaddr = (unsigned long) KERNBASE; |
0eef331a | 587 | phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
c4bce90e | 588 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
589 | |
590 | kern_locked_tte_data = tte_data; | |
591 | ||
d82ace7d DM |
592 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
593 | if (tlb_type == hypervisor) { | |
64658743 | 594 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
595 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
596 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
597 | tte_vaddr += 0x400000; |
598 | tte_data += 0x400000; | |
d82ace7d DM |
599 | } |
600 | } else { | |
64658743 DM |
601 | for (i = 0; i < num_kernel_image_mappings; i++) { |
602 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
603 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
604 | tte_vaddr += 0x400000; | |
605 | tte_data += 0x400000; | |
d82ace7d | 606 | } |
64658743 | 607 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 608 | } |
0835ae0f DM |
609 | if (tlb_type == cheetah_plus) { |
610 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
611 | CTX_CHEETAH_PLUS_NUC); | |
612 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
613 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
614 | } | |
405599bd | 615 | } |
1da177e4 | 616 | |
405599bd | 617 | |
c9c10830 | 618 | static void __init inherit_prom_mappings(void) |
9ad98c5b | 619 | { |
405599bd | 620 | /* Now fixup OBP's idea about where we really are mapped. */ |
3c62a2d3 | 621 | printk("Remapping the kernel... "); |
405599bd | 622 | remap_kernel(); |
3c62a2d3 | 623 | printk("done.\n"); |
1da177e4 LT |
624 | } |
625 | ||
1da177e4 LT |
626 | void prom_world(int enter) |
627 | { | |
1da177e4 | 628 | if (!enter) |
dff933da | 629 | set_fs(get_fs()); |
1da177e4 | 630 | |
3487d1d4 | 631 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
632 | } |
633 | ||
1da177e4 LT |
634 | void __flush_dcache_range(unsigned long start, unsigned long end) |
635 | { | |
636 | unsigned long va; | |
637 | ||
638 | if (tlb_type == spitfire) { | |
639 | int n = 0; | |
640 | ||
641 | for (va = start; va < end; va += 32) { | |
642 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
643 | if (++n >= 512) | |
644 | break; | |
645 | } | |
a43fe0e7 | 646 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
647 | start = __pa(start); |
648 | end = __pa(end); | |
649 | for (va = start; va < end; va += 32) | |
650 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
651 | "membar #Sync" | |
652 | : /* no outputs */ | |
653 | : "r" (va), | |
654 | "i" (ASI_DCACHE_INVALIDATE)); | |
655 | } | |
656 | } | |
917c3660 | 657 | EXPORT_SYMBOL(__flush_dcache_range); |
1da177e4 | 658 | |
85f1e1f6 DM |
659 | /* get_new_mmu_context() uses "cache + 1". */ |
660 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
661 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
662 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) | |
663 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
664 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
665 | ||
1da177e4 LT |
666 | /* Caller does TLB context flushing on local CPU if necessary. |
667 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
668 | * | |
669 | * We must be careful about boundary cases so that we never | |
670 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
671 | * version of zero (and thus NO_CONTEXT would not be caught | |
672 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
673 | * |
674 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
675 | */ |
676 | void get_new_mmu_context(struct mm_struct *mm) | |
677 | { | |
678 | unsigned long ctx, new_ctx; | |
679 | unsigned long orig_pgsz_bits; | |
a0663a79 | 680 | int new_version; |
1da177e4 | 681 | |
07df8418 | 682 | spin_lock(&ctx_alloc_lock); |
1da177e4 LT |
683 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
684 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
685 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 686 | new_version = 0; |
1da177e4 LT |
687 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
688 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
689 | if (new_ctx >= ctx) { | |
690 | int i; | |
691 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
692 | CTX_FIRST_VERSION; | |
693 | if (new_ctx == 1) | |
694 | new_ctx = CTX_FIRST_VERSION; | |
695 | ||
696 | /* Don't call memset, for 16 entries that's just | |
697 | * plain silly... | |
698 | */ | |
699 | mmu_context_bmap[0] = 3; | |
700 | mmu_context_bmap[1] = 0; | |
701 | mmu_context_bmap[2] = 0; | |
702 | mmu_context_bmap[3] = 0; | |
703 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
704 | mmu_context_bmap[i + 0] = 0; | |
705 | mmu_context_bmap[i + 1] = 0; | |
706 | mmu_context_bmap[i + 2] = 0; | |
707 | mmu_context_bmap[i + 3] = 0; | |
708 | } | |
a0663a79 | 709 | new_version = 1; |
1da177e4 LT |
710 | goto out; |
711 | } | |
712 | } | |
713 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
714 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
715 | out: | |
716 | tlb_context_cache = new_ctx; | |
717 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
07df8418 | 718 | spin_unlock(&ctx_alloc_lock); |
a0663a79 DM |
719 | |
720 | if (unlikely(new_version)) | |
721 | smp_new_mmu_context_version(); | |
1da177e4 LT |
722 | } |
723 | ||
919ee677 DM |
724 | static int numa_enabled = 1; |
725 | static int numa_debug; | |
726 | ||
727 | static int __init early_numa(char *p) | |
1da177e4 | 728 | { |
919ee677 DM |
729 | if (!p) |
730 | return 0; | |
731 | ||
732 | if (strstr(p, "off")) | |
733 | numa_enabled = 0; | |
d1112018 | 734 | |
919ee677 DM |
735 | if (strstr(p, "debug")) |
736 | numa_debug = 1; | |
d1112018 | 737 | |
919ee677 | 738 | return 0; |
d1112018 | 739 | } |
919ee677 DM |
740 | early_param("numa", early_numa); |
741 | ||
742 | #define numadbg(f, a...) \ | |
743 | do { if (numa_debug) \ | |
744 | printk(KERN_INFO f, ## a); \ | |
745 | } while (0) | |
d1112018 | 746 | |
4e82c9a6 DM |
747 | static void __init find_ramdisk(unsigned long phys_base) |
748 | { | |
749 | #ifdef CONFIG_BLK_DEV_INITRD | |
750 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
751 | unsigned long ramdisk_image; | |
752 | ||
753 | /* Older versions of the bootloader only supported a | |
754 | * 32-bit physical address for the ramdisk image | |
755 | * location, stored at sparc_ramdisk_image. Newer | |
756 | * SILO versions set sparc_ramdisk_image to zero and | |
757 | * provide a full 64-bit physical address at | |
758 | * sparc_ramdisk_image64. | |
759 | */ | |
760 | ramdisk_image = sparc_ramdisk_image; | |
761 | if (!ramdisk_image) | |
762 | ramdisk_image = sparc_ramdisk_image64; | |
763 | ||
764 | /* Another bootloader quirk. The bootloader normalizes | |
765 | * the physical address to KERNBASE, so we have to | |
766 | * factor that back out and add in the lowest valid | |
767 | * physical page address to get the true physical address. | |
768 | */ | |
769 | ramdisk_image -= KERNBASE; | |
770 | ramdisk_image += phys_base; | |
771 | ||
919ee677 DM |
772 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
773 | ramdisk_image, sparc_ramdisk_size); | |
774 | ||
4e82c9a6 DM |
775 | initrd_start = ramdisk_image; |
776 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 | 777 | |
95f72d1e | 778 | memblock_reserve(initrd_start, sparc_ramdisk_size); |
d45100f7 DM |
779 | |
780 | initrd_start += PAGE_OFFSET; | |
781 | initrd_end += PAGE_OFFSET; | |
4e82c9a6 DM |
782 | } |
783 | #endif | |
784 | } | |
785 | ||
919ee677 DM |
786 | struct node_mem_mask { |
787 | unsigned long mask; | |
788 | unsigned long val; | |
919ee677 DM |
789 | }; |
790 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
791 | static int num_node_masks; | |
792 | ||
48d37216 SR |
793 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
794 | ||
919ee677 DM |
795 | int numa_cpu_lookup_table[NR_CPUS]; |
796 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
797 | ||
919ee677 DM |
798 | struct mdesc_mblock { |
799 | u64 base; | |
800 | u64 size; | |
801 | u64 offset; /* RA-to-PA */ | |
802 | }; | |
803 | static struct mdesc_mblock *mblocks; | |
804 | static int num_mblocks; | |
805 | ||
806 | static unsigned long ra_to_pa(unsigned long addr) | |
807 | { | |
808 | int i; | |
809 | ||
810 | for (i = 0; i < num_mblocks; i++) { | |
811 | struct mdesc_mblock *m = &mblocks[i]; | |
812 | ||
813 | if (addr >= m->base && | |
814 | addr < (m->base + m->size)) { | |
815 | addr += m->offset; | |
816 | break; | |
817 | } | |
818 | } | |
819 | return addr; | |
820 | } | |
821 | ||
822 | static int find_node(unsigned long addr) | |
823 | { | |
824 | int i; | |
825 | ||
826 | addr = ra_to_pa(addr); | |
827 | for (i = 0; i < num_node_masks; i++) { | |
828 | struct node_mem_mask *p = &node_masks[i]; | |
829 | ||
830 | if ((addr & p->mask) == p->val) | |
831 | return i; | |
832 | } | |
3dee9df5 | 833 | /* The following condition has been observed on LDOM guests.*/ |
834 | WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node" | |
835 | " rule. Some physical memory will be owned by node 0."); | |
836 | return 0; | |
919ee677 DM |
837 | } |
838 | ||
f9b18db3 | 839 | static u64 memblock_nid_range(u64 start, u64 end, int *nid) |
919ee677 DM |
840 | { |
841 | *nid = find_node(start); | |
842 | start += PAGE_SIZE; | |
843 | while (start < end) { | |
844 | int n = find_node(start); | |
845 | ||
846 | if (n != *nid) | |
847 | break; | |
848 | start += PAGE_SIZE; | |
849 | } | |
850 | ||
c918dcce DM |
851 | if (start > end) |
852 | start = end; | |
853 | ||
919ee677 DM |
854 | return start; |
855 | } | |
919ee677 DM |
856 | #endif |
857 | ||
858 | /* This must be invoked after performing all of the necessary | |
2a4814df | 859 | * memblock_set_node() calls for 'nid'. We need to be able to get |
919ee677 | 860 | * correct data from get_pfn_range_for_nid(). |
f1cfdb55 | 861 | */ |
919ee677 DM |
862 | static void __init allocate_node_data(int nid) |
863 | { | |
919ee677 | 864 | struct pglist_data *p; |
aa6f0790 | 865 | unsigned long start_pfn, end_pfn; |
919ee677 | 866 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
aa6f0790 PG |
867 | unsigned long paddr; |
868 | ||
9d1e2492 | 869 | paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); |
919ee677 DM |
870 | if (!paddr) { |
871 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
872 | prom_halt(); | |
873 | } | |
874 | NODE_DATA(nid) = __va(paddr); | |
875 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
876 | ||
625d693e | 877 | NODE_DATA(nid)->node_id = nid; |
919ee677 DM |
878 | #endif |
879 | ||
880 | p = NODE_DATA(nid); | |
881 | ||
882 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
883 | p->node_start_pfn = start_pfn; | |
884 | p->node_spanned_pages = end_pfn - start_pfn; | |
919ee677 DM |
885 | } |
886 | ||
887 | static void init_node_masks_nonnuma(void) | |
d1112018 | 888 | { |
48d37216 | 889 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
1da177e4 | 890 | int i; |
48d37216 | 891 | #endif |
1da177e4 | 892 | |
919ee677 | 893 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 894 | |
919ee677 DM |
895 | node_masks[0].mask = node_masks[0].val = 0; |
896 | num_node_masks = 1; | |
d1112018 | 897 | |
48d37216 | 898 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
919ee677 DM |
899 | for (i = 0; i < NR_CPUS; i++) |
900 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 901 | |
fb1fece5 | 902 | cpumask_setall(&numa_cpumask_lookup_table[0]); |
48d37216 | 903 | #endif |
919ee677 DM |
904 | } |
905 | ||
906 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
907 | struct pglist_data *node_data[MAX_NUMNODES]; | |
908 | ||
909 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
910 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
911 | EXPORT_SYMBOL(node_data); | |
912 | ||
913 | struct mdesc_mlgroup { | |
914 | u64 node; | |
915 | u64 latency; | |
916 | u64 match; | |
917 | u64 mask; | |
918 | }; | |
919 | static struct mdesc_mlgroup *mlgroups; | |
920 | static int num_mlgroups; | |
921 | ||
922 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, | |
923 | u32 cfg_handle) | |
924 | { | |
925 | u64 arc; | |
926 | ||
927 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
928 | u64 target = mdesc_arc_target(md, arc); | |
929 | const u64 *val; | |
930 | ||
931 | val = mdesc_get_property(md, target, | |
932 | "cfg-handle", NULL); | |
933 | if (val && *val == cfg_handle) | |
934 | return 0; | |
935 | } | |
936 | return -ENODEV; | |
937 | } | |
938 | ||
939 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
940 | u32 cfg_handle) | |
941 | { | |
942 | u64 arc, candidate, best_latency = ~(u64)0; | |
943 | ||
944 | candidate = MDESC_NODE_NULL; | |
945 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
946 | u64 target = mdesc_arc_target(md, arc); | |
947 | const char *name = mdesc_node_name(md, target); | |
948 | const u64 *val; | |
949 | ||
950 | if (strcmp(name, "pio-latency-group")) | |
951 | continue; | |
952 | ||
953 | val = mdesc_get_property(md, target, "latency", NULL); | |
954 | if (!val) | |
955 | continue; | |
956 | ||
957 | if (*val < best_latency) { | |
958 | candidate = target; | |
959 | best_latency = *val; | |
960 | } | |
961 | } | |
962 | ||
963 | if (candidate == MDESC_NODE_NULL) | |
964 | return -ENODEV; | |
965 | ||
966 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
967 | } | |
968 | ||
969 | int of_node_to_nid(struct device_node *dp) | |
970 | { | |
971 | const struct linux_prom64_registers *regs; | |
972 | struct mdesc_handle *md; | |
973 | u32 cfg_handle; | |
974 | int count, nid; | |
975 | u64 grp; | |
976 | ||
072bd413 DM |
977 | /* This is the right thing to do on currently supported |
978 | * SUN4U NUMA platforms as well, as the PCI controller does | |
979 | * not sit behind any particular memory controller. | |
980 | */ | |
919ee677 DM |
981 | if (!mlgroups) |
982 | return -1; | |
983 | ||
984 | regs = of_get_property(dp, "reg", NULL); | |
985 | if (!regs) | |
986 | return -1; | |
987 | ||
988 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
989 | ||
990 | md = mdesc_grab(); | |
991 | ||
992 | count = 0; | |
993 | nid = -1; | |
994 | mdesc_for_each_node_by_name(md, grp, "group") { | |
995 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
996 | nid = count; | |
997 | break; | |
998 | } | |
999 | count++; | |
1000 | } | |
1001 | ||
1002 | mdesc_release(md); | |
1003 | ||
1004 | return nid; | |
1005 | } | |
1006 | ||
01c45381 | 1007 | static void __init add_node_ranges(void) |
919ee677 | 1008 | { |
08b84798 | 1009 | struct memblock_region *reg; |
919ee677 | 1010 | |
08b84798 BH |
1011 | for_each_memblock(memory, reg) { |
1012 | unsigned long size = reg->size; | |
919ee677 DM |
1013 | unsigned long start, end; |
1014 | ||
08b84798 | 1015 | start = reg->base; |
919ee677 DM |
1016 | end = start + size; |
1017 | while (start < end) { | |
1018 | unsigned long this_end; | |
1019 | int nid; | |
1020 | ||
35a1f0bd | 1021 | this_end = memblock_nid_range(start, end, &nid); |
919ee677 | 1022 | |
2a4814df | 1023 | numadbg("Setting memblock NUMA node nid[%d] " |
919ee677 DM |
1024 | "start[%lx] end[%lx]\n", |
1025 | nid, start, this_end); | |
1026 | ||
e7e8de59 TC |
1027 | memblock_set_node(start, this_end - start, |
1028 | &memblock.memory, nid); | |
919ee677 DM |
1029 | start = this_end; |
1030 | } | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
1035 | { | |
1036 | unsigned long paddr; | |
1037 | int count = 0; | |
1038 | u64 node; | |
1039 | ||
1040 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
1041 | count++; | |
1042 | if (!count) | |
1043 | return -ENOENT; | |
1044 | ||
95f72d1e | 1045 | paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), |
919ee677 DM |
1046 | SMP_CACHE_BYTES); |
1047 | if (!paddr) | |
1048 | return -ENOMEM; | |
1049 | ||
1050 | mlgroups = __va(paddr); | |
1051 | num_mlgroups = count; | |
1052 | ||
1053 | count = 0; | |
1054 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1055 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1056 | const u64 *val; | |
1057 | ||
1058 | m->node = node; | |
1059 | ||
1060 | val = mdesc_get_property(md, node, "latency", NULL); | |
1061 | m->latency = *val; | |
1062 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1063 | m->match = *val; | |
1064 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1065 | m->mask = *val; | |
1066 | ||
90181136 SR |
1067 | numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " |
1068 | "match[%llx] mask[%llx]\n", | |
919ee677 DM |
1069 | count - 1, m->node, m->latency, m->match, m->mask); |
1070 | } | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1076 | { | |
1077 | unsigned long paddr; | |
1078 | int count = 0; | |
1079 | u64 node; | |
1080 | ||
1081 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1082 | count++; | |
1083 | if (!count) | |
1084 | return -ENOENT; | |
1085 | ||
95f72d1e | 1086 | paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), |
919ee677 DM |
1087 | SMP_CACHE_BYTES); |
1088 | if (!paddr) | |
1089 | return -ENOMEM; | |
1090 | ||
1091 | mblocks = __va(paddr); | |
1092 | num_mblocks = count; | |
1093 | ||
1094 | count = 0; | |
1095 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1096 | struct mdesc_mblock *m = &mblocks[count++]; | |
1097 | const u64 *val; | |
1098 | ||
1099 | val = mdesc_get_property(md, node, "base", NULL); | |
1100 | m->base = *val; | |
1101 | val = mdesc_get_property(md, node, "size", NULL); | |
1102 | m->size = *val; | |
1103 | val = mdesc_get_property(md, node, | |
1104 | "address-congruence-offset", NULL); | |
771a37ff | 1105 | |
1106 | /* The address-congruence-offset property is optional. | |
1107 | * Explicity zero it be identifty this. | |
1108 | */ | |
1109 | if (val) | |
1110 | m->offset = *val; | |
1111 | else | |
1112 | m->offset = 0UL; | |
919ee677 | 1113 | |
90181136 | 1114 | numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", |
919ee677 DM |
1115 | count - 1, m->base, m->size, m->offset); |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1122 | u64 grp, cpumask_t *mask) | |
1123 | { | |
1124 | u64 arc; | |
1125 | ||
fb1fece5 | 1126 | cpumask_clear(mask); |
919ee677 DM |
1127 | |
1128 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1129 | u64 target = mdesc_arc_target(md, arc); | |
1130 | const char *name = mdesc_node_name(md, target); | |
1131 | const u64 *id; | |
1132 | ||
1133 | if (strcmp(name, "cpu")) | |
1134 | continue; | |
1135 | id = mdesc_get_property(md, target, "id", NULL); | |
e305cb8f | 1136 | if (*id < nr_cpu_ids) |
fb1fece5 | 1137 | cpumask_set_cpu(*id, mask); |
919ee677 DM |
1138 | } |
1139 | } | |
1140 | ||
1141 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1142 | { | |
1143 | int i; | |
1144 | ||
1145 | for (i = 0; i < num_mlgroups; i++) { | |
1146 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1147 | if (m->node == node) | |
1148 | return m; | |
1149 | } | |
1150 | return NULL; | |
1151 | } | |
1152 | ||
52708d69 NG |
1153 | int __node_distance(int from, int to) |
1154 | { | |
1155 | if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { | |
1156 | pr_warn("Returning default NUMA distance value for %d->%d\n", | |
1157 | from, to); | |
1158 | return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; | |
1159 | } | |
1160 | return numa_latency[from][to]; | |
1161 | } | |
1162 | ||
bdf2f59e | 1163 | static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) |
52708d69 NG |
1164 | { |
1165 | int i; | |
1166 | ||
1167 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1168 | struct node_mem_mask *n = &node_masks[i]; | |
1169 | ||
1170 | if ((grp->mask == n->mask) && (grp->match == n->val)) | |
1171 | break; | |
1172 | } | |
1173 | return i; | |
1174 | } | |
1175 | ||
bdf2f59e PG |
1176 | static void __init find_numa_latencies_for_group(struct mdesc_handle *md, |
1177 | u64 grp, int index) | |
52708d69 NG |
1178 | { |
1179 | u64 arc; | |
1180 | ||
1181 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1182 | int tnode; | |
1183 | u64 target = mdesc_arc_target(md, arc); | |
1184 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1185 | ||
1186 | if (!m) | |
1187 | continue; | |
1188 | tnode = find_best_numa_node_for_mlgroup(m); | |
1189 | if (tnode == MAX_NUMNODES) | |
1190 | continue; | |
1191 | numa_latency[index][tnode] = m->latency; | |
1192 | } | |
1193 | } | |
1194 | ||
919ee677 DM |
1195 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, |
1196 | int index) | |
1197 | { | |
1198 | struct mdesc_mlgroup *candidate = NULL; | |
1199 | u64 arc, best_latency = ~(u64)0; | |
1200 | struct node_mem_mask *n; | |
1201 | ||
1202 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1203 | u64 target = mdesc_arc_target(md, arc); | |
1204 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1205 | if (!m) | |
1206 | continue; | |
1207 | if (m->latency < best_latency) { | |
1208 | candidate = m; | |
1209 | best_latency = m->latency; | |
1210 | } | |
1211 | } | |
1212 | if (!candidate) | |
1213 | return -ENOENT; | |
1214 | ||
1215 | if (num_node_masks != index) { | |
1216 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1217 | "index[%d] != num_node_masks[%d]\n", | |
1218 | index, num_node_masks); | |
1219 | return -EINVAL; | |
1220 | } | |
1221 | ||
1222 | n = &node_masks[num_node_masks++]; | |
1223 | ||
1224 | n->mask = candidate->mask; | |
1225 | n->val = candidate->match; | |
1da177e4 | 1226 | |
90181136 | 1227 | numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n", |
919ee677 | 1228 | index, n->mask, n->val, candidate->latency); |
1da177e4 | 1229 | |
919ee677 DM |
1230 | return 0; |
1231 | } | |
1232 | ||
1233 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1234 | int index) | |
1235 | { | |
1236 | cpumask_t mask; | |
1237 | int cpu; | |
1238 | ||
1239 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1240 | ||
fb1fece5 | 1241 | for_each_cpu(cpu, &mask) |
919ee677 | 1242 | numa_cpu_lookup_table[cpu] = index; |
fb1fece5 | 1243 | cpumask_copy(&numa_cpumask_lookup_table[index], &mask); |
919ee677 DM |
1244 | |
1245 | if (numa_debug) { | |
1246 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
fb1fece5 | 1247 | for_each_cpu(cpu, &mask) |
919ee677 DM |
1248 | printk("%d ", cpu); |
1249 | printk("]\n"); | |
1250 | } | |
1251 | ||
1252 | return numa_attach_mlgroup(md, grp, index); | |
1253 | } | |
1254 | ||
1255 | static int __init numa_parse_mdesc(void) | |
1256 | { | |
1257 | struct mdesc_handle *md = mdesc_grab(); | |
52708d69 | 1258 | int i, j, err, count; |
919ee677 DM |
1259 | u64 node; |
1260 | ||
1261 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1262 | if (node == MDESC_NODE_NULL) { | |
1263 | mdesc_release(md); | |
1264 | return -ENOENT; | |
1265 | } | |
1266 | ||
1267 | err = grab_mblocks(md); | |
1268 | if (err < 0) | |
1269 | goto out; | |
1270 | ||
1271 | err = grab_mlgroups(md); | |
1272 | if (err < 0) | |
1273 | goto out; | |
1274 | ||
1275 | count = 0; | |
1276 | mdesc_for_each_node_by_name(md, node, "group") { | |
1277 | err = numa_parse_mdesc_group(md, node, count); | |
1278 | if (err < 0) | |
1279 | break; | |
1280 | count++; | |
1281 | } | |
1282 | ||
52708d69 NG |
1283 | count = 0; |
1284 | mdesc_for_each_node_by_name(md, node, "group") { | |
1285 | find_numa_latencies_for_group(md, node, count); | |
1286 | count++; | |
1287 | } | |
1288 | ||
1289 | /* Normalize numa latency matrix according to ACPI SLIT spec. */ | |
1290 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1291 | u64 self_latency = numa_latency[i][i]; | |
1292 | ||
1293 | for (j = 0; j < MAX_NUMNODES; j++) { | |
1294 | numa_latency[i][j] = | |
1295 | (numa_latency[i][j] * LOCAL_DISTANCE) / | |
1296 | self_latency; | |
1297 | } | |
1298 | } | |
1299 | ||
919ee677 DM |
1300 | add_node_ranges(); |
1301 | ||
1302 | for (i = 0; i < num_node_masks; i++) { | |
1303 | allocate_node_data(i); | |
1304 | node_set_online(i); | |
1305 | } | |
1306 | ||
1307 | err = 0; | |
1308 | out: | |
1309 | mdesc_release(md); | |
1310 | return err; | |
1311 | } | |
1312 | ||
072bd413 DM |
1313 | static int __init numa_parse_jbus(void) |
1314 | { | |
1315 | unsigned long cpu, index; | |
1316 | ||
1317 | /* NUMA node id is encoded in bits 36 and higher, and there is | |
1318 | * a 1-to-1 mapping from CPU ID to NUMA node ID. | |
1319 | */ | |
1320 | index = 0; | |
1321 | for_each_present_cpu(cpu) { | |
1322 | numa_cpu_lookup_table[cpu] = index; | |
fb1fece5 | 1323 | cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); |
072bd413 DM |
1324 | node_masks[index].mask = ~((1UL << 36UL) - 1UL); |
1325 | node_masks[index].val = cpu << 36UL; | |
1326 | ||
1327 | index++; | |
1328 | } | |
1329 | num_node_masks = index; | |
1330 | ||
1331 | add_node_ranges(); | |
1332 | ||
1333 | for (index = 0; index < num_node_masks; index++) { | |
1334 | allocate_node_data(index); | |
1335 | node_set_online(index); | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
919ee677 DM |
1341 | static int __init numa_parse_sun4u(void) |
1342 | { | |
072bd413 DM |
1343 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1344 | unsigned long ver; | |
1345 | ||
1346 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
1347 | if ((ver >> 32UL) == __JALAPENO_ID || | |
1348 | (ver >> 32UL) == __SERRANO_ID) | |
1349 | return numa_parse_jbus(); | |
1350 | } | |
919ee677 DM |
1351 | return -1; |
1352 | } | |
1353 | ||
1354 | static int __init bootmem_init_numa(void) | |
1355 | { | |
36beca65 | 1356 | int i, j; |
919ee677 DM |
1357 | int err = -1; |
1358 | ||
1359 | numadbg("bootmem_init_numa()\n"); | |
1360 | ||
36beca65 NG |
1361 | /* Some sane defaults for numa latency values */ |
1362 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1363 | for (j = 0; j < MAX_NUMNODES; j++) | |
1364 | numa_latency[i][j] = (i == j) ? | |
1365 | LOCAL_DISTANCE : REMOTE_DISTANCE; | |
1366 | } | |
1367 | ||
919ee677 DM |
1368 | if (numa_enabled) { |
1369 | if (tlb_type == hypervisor) | |
1370 | err = numa_parse_mdesc(); | |
1371 | else | |
1372 | err = numa_parse_sun4u(); | |
1373 | } | |
1374 | return err; | |
1375 | } | |
1376 | ||
1377 | #else | |
1da177e4 | 1378 | |
919ee677 DM |
1379 | static int bootmem_init_numa(void) |
1380 | { | |
1381 | return -1; | |
1382 | } | |
1383 | ||
1384 | #endif | |
1385 | ||
1386 | static void __init bootmem_init_nonnuma(void) | |
1387 | { | |
95f72d1e YL |
1388 | unsigned long top_of_ram = memblock_end_of_DRAM(); |
1389 | unsigned long total_ram = memblock_phys_mem_size(); | |
919ee677 DM |
1390 | |
1391 | numadbg("bootmem_init_nonnuma()\n"); | |
1392 | ||
1393 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1394 | top_of_ram, total_ram); | |
1395 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1396 | (top_of_ram - total_ram) >> 20); | |
1397 | ||
1398 | init_node_masks_nonnuma(); | |
e7e8de59 | 1399 | memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0); |
919ee677 | 1400 | allocate_node_data(0); |
919ee677 DM |
1401 | node_set_online(0); |
1402 | } | |
1403 | ||
919ee677 DM |
1404 | static unsigned long __init bootmem_init(unsigned long phys_base) |
1405 | { | |
1406 | unsigned long end_pfn; | |
919ee677 | 1407 | |
95f72d1e | 1408 | end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; |
919ee677 DM |
1409 | max_pfn = max_low_pfn = end_pfn; |
1410 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1411 | ||
1412 | if (bootmem_init_numa() < 0) | |
1413 | bootmem_init_nonnuma(); | |
1414 | ||
625d693e DM |
1415 | /* Dump memblock with node info. */ |
1416 | memblock_dump_all(); | |
919ee677 | 1417 | |
625d693e | 1418 | /* XXX cpu notifier XXX */ |
d1112018 | 1419 | |
625d693e | 1420 | sparse_memory_present_with_active_regions(MAX_NUMNODES); |
d1112018 DM |
1421 | sparse_init(); |
1422 | ||
1da177e4 LT |
1423 | return end_pfn; |
1424 | } | |
1425 | ||
9cc3a1ac DM |
1426 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1427 | static int pall_ents __initdata; | |
1428 | ||
0dd5b7b0 DM |
1429 | static unsigned long max_phys_bits = 40; |
1430 | ||
1431 | bool kern_addr_valid(unsigned long addr) | |
1432 | { | |
0dd5b7b0 DM |
1433 | pgd_t *pgd; |
1434 | pud_t *pud; | |
1435 | pmd_t *pmd; | |
1436 | pte_t *pte; | |
1437 | ||
bb4e6e85 | 1438 | if ((long)addr < 0L) { |
0dd5b7b0 DM |
1439 | unsigned long pa = __pa(addr); |
1440 | ||
bb4e6e85 DM |
1441 | if ((addr >> max_phys_bits) != 0UL) |
1442 | return false; | |
1443 | ||
0dd5b7b0 DM |
1444 | return pfn_valid(pa >> PAGE_SHIFT); |
1445 | } | |
1446 | ||
bb4e6e85 DM |
1447 | if (addr >= (unsigned long) KERNBASE && |
1448 | addr < (unsigned long)&_end) | |
1449 | return true; | |
1450 | ||
0dd5b7b0 DM |
1451 | pgd = pgd_offset_k(addr); |
1452 | if (pgd_none(*pgd)) | |
1453 | return 0; | |
1454 | ||
1455 | pud = pud_offset(pgd, addr); | |
1456 | if (pud_none(*pud)) | |
1457 | return 0; | |
1458 | ||
1459 | if (pud_large(*pud)) | |
1460 | return pfn_valid(pud_pfn(*pud)); | |
1461 | ||
1462 | pmd = pmd_offset(pud, addr); | |
1463 | if (pmd_none(*pmd)) | |
1464 | return 0; | |
1465 | ||
1466 | if (pmd_large(*pmd)) | |
1467 | return pfn_valid(pmd_pfn(*pmd)); | |
1468 | ||
1469 | pte = pte_offset_kernel(pmd, addr); | |
1470 | if (pte_none(*pte)) | |
1471 | return 0; | |
1472 | ||
1473 | return pfn_valid(pte_pfn(*pte)); | |
1474 | } | |
1475 | EXPORT_SYMBOL(kern_addr_valid); | |
1476 | ||
1477 | static unsigned long __ref kernel_map_hugepud(unsigned long vstart, | |
1478 | unsigned long vend, | |
1479 | pud_t *pud) | |
1480 | { | |
1481 | const unsigned long mask16gb = (1UL << 34) - 1UL; | |
1482 | u64 pte_val = vstart; | |
1483 | ||
1484 | /* Each PUD is 8GB */ | |
1485 | if ((vstart & mask16gb) || | |
1486 | (vend - vstart <= mask16gb)) { | |
1487 | pte_val ^= kern_linear_pte_xor[2]; | |
1488 | pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; | |
1489 | ||
1490 | return vstart + PUD_SIZE; | |
1491 | } | |
1492 | ||
1493 | pte_val ^= kern_linear_pte_xor[3]; | |
1494 | pte_val |= _PAGE_PUD_HUGE; | |
1495 | ||
1496 | vend = vstart + mask16gb + 1UL; | |
1497 | while (vstart < vend) { | |
1498 | pud_val(*pud) = pte_val; | |
1499 | ||
1500 | pte_val += PUD_SIZE; | |
1501 | vstart += PUD_SIZE; | |
1502 | pud++; | |
1503 | } | |
1504 | return vstart; | |
1505 | } | |
1506 | ||
1507 | static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, | |
1508 | bool guard) | |
1509 | { | |
1510 | if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) | |
1511 | return true; | |
1512 | ||
1513 | return false; | |
1514 | } | |
1515 | ||
1516 | static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, | |
1517 | unsigned long vend, | |
1518 | pmd_t *pmd) | |
1519 | { | |
1520 | const unsigned long mask256mb = (1UL << 28) - 1UL; | |
1521 | const unsigned long mask2gb = (1UL << 31) - 1UL; | |
1522 | u64 pte_val = vstart; | |
1523 | ||
1524 | /* Each PMD is 8MB */ | |
1525 | if ((vstart & mask256mb) || | |
1526 | (vend - vstart <= mask256mb)) { | |
1527 | pte_val ^= kern_linear_pte_xor[0]; | |
1528 | pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; | |
1529 | ||
1530 | return vstart + PMD_SIZE; | |
1531 | } | |
1532 | ||
1533 | if ((vstart & mask2gb) || | |
1534 | (vend - vstart <= mask2gb)) { | |
1535 | pte_val ^= kern_linear_pte_xor[1]; | |
1536 | pte_val |= _PAGE_PMD_HUGE; | |
1537 | vend = vstart + mask256mb + 1UL; | |
1538 | } else { | |
1539 | pte_val ^= kern_linear_pte_xor[2]; | |
1540 | pte_val |= _PAGE_PMD_HUGE; | |
1541 | vend = vstart + mask2gb + 1UL; | |
1542 | } | |
1543 | ||
1544 | while (vstart < vend) { | |
1545 | pmd_val(*pmd) = pte_val; | |
1546 | ||
1547 | pte_val += PMD_SIZE; | |
1548 | vstart += PMD_SIZE; | |
1549 | pmd++; | |
1550 | } | |
1551 | ||
1552 | return vstart; | |
1553 | } | |
1554 | ||
1555 | static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, | |
1556 | bool guard) | |
1557 | { | |
1558 | if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) | |
1559 | return true; | |
1560 | ||
1561 | return false; | |
1562 | } | |
1563 | ||
896aef43 | 1564 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
0dd5b7b0 DM |
1565 | unsigned long pend, pgprot_t prot, |
1566 | bool use_huge) | |
56425306 DM |
1567 | { |
1568 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1569 | unsigned long vend = PAGE_OFFSET + pend; | |
1570 | unsigned long alloc_bytes = 0UL; | |
1571 | ||
1572 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1573 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1574 | vstart, vend); |
1575 | prom_halt(); | |
1576 | } | |
1577 | ||
1578 | while (vstart < vend) { | |
1579 | unsigned long this_end, paddr = __pa(vstart); | |
1580 | pgd_t *pgd = pgd_offset_k(vstart); | |
1581 | pud_t *pud; | |
1582 | pmd_t *pmd; | |
1583 | pte_t *pte; | |
1584 | ||
ac55c768 DM |
1585 | if (pgd_none(*pgd)) { |
1586 | pud_t *new; | |
1587 | ||
1588 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1589 | alloc_bytes += PAGE_SIZE; | |
1590 | pgd_populate(&init_mm, pgd, new); | |
1591 | } | |
56425306 DM |
1592 | pud = pud_offset(pgd, vstart); |
1593 | if (pud_none(*pud)) { | |
1594 | pmd_t *new; | |
1595 | ||
0dd5b7b0 DM |
1596 | if (kernel_can_map_hugepud(vstart, vend, use_huge)) { |
1597 | vstart = kernel_map_hugepud(vstart, vend, pud); | |
1598 | continue; | |
1599 | } | |
56425306 DM |
1600 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); |
1601 | alloc_bytes += PAGE_SIZE; | |
1602 | pud_populate(&init_mm, pud, new); | |
1603 | } | |
1604 | ||
1605 | pmd = pmd_offset(pud, vstart); | |
0dd5b7b0 | 1606 | if (pmd_none(*pmd)) { |
56425306 DM |
1607 | pte_t *new; |
1608 | ||
0dd5b7b0 DM |
1609 | if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { |
1610 | vstart = kernel_map_hugepmd(vstart, vend, pmd); | |
1611 | continue; | |
1612 | } | |
56425306 DM |
1613 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); |
1614 | alloc_bytes += PAGE_SIZE; | |
1615 | pmd_populate_kernel(&init_mm, pmd, new); | |
1616 | } | |
1617 | ||
1618 | pte = pte_offset_kernel(pmd, vstart); | |
1619 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1620 | if (this_end > vend) | |
1621 | this_end = vend; | |
1622 | ||
1623 | while (vstart < this_end) { | |
1624 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1625 | ||
1626 | vstart += PAGE_SIZE; | |
1627 | paddr += PAGE_SIZE; | |
1628 | pte++; | |
1629 | } | |
1630 | } | |
1631 | ||
1632 | return alloc_bytes; | |
1633 | } | |
1634 | ||
0dd5b7b0 | 1635 | static void __init flush_all_kernel_tsbs(void) |
4f93d21d | 1636 | { |
0dd5b7b0 | 1637 | int i; |
4f93d21d | 1638 | |
0dd5b7b0 DM |
1639 | for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { |
1640 | struct tsb *ent = &swapper_tsb[i]; | |
4f93d21d | 1641 | |
0dd5b7b0 | 1642 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
4f93d21d | 1643 | } |
0dd5b7b0 DM |
1644 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1645 | for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { | |
1646 | struct tsb *ent = &swapper_4m_tsb[i]; | |
4f93d21d | 1647 | |
0dd5b7b0 | 1648 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
9cc3a1ac | 1649 | } |
0dd5b7b0 | 1650 | #endif |
9cc3a1ac | 1651 | } |
56425306 | 1652 | |
0dd5b7b0 | 1653 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac | 1654 | |
8f361453 DM |
1655 | static void __init kernel_physical_mapping_init(void) |
1656 | { | |
8f361453 | 1657 | unsigned long i, mem_alloced = 0UL; |
0dd5b7b0 | 1658 | bool use_huge = true; |
8f361453 | 1659 | |
0dd5b7b0 DM |
1660 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1661 | use_huge = false; | |
1662 | #endif | |
8f361453 DM |
1663 | for (i = 0; i < pall_ents; i++) { |
1664 | unsigned long phys_start, phys_end; | |
1665 | ||
1666 | phys_start = pall[i].phys_addr; | |
1667 | phys_end = phys_start + pall[i].reg_size; | |
1668 | ||
56425306 | 1669 | mem_alloced += kernel_map_range(phys_start, phys_end, |
0dd5b7b0 | 1670 | PAGE_KERNEL, use_huge); |
56425306 DM |
1671 | } |
1672 | ||
1673 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1674 | mem_alloced); | |
1675 | ||
1676 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1677 | flushi(&kvmap_linear_patch[0]); | |
1678 | ||
0dd5b7b0 DM |
1679 | flush_all_kernel_tsbs(); |
1680 | ||
56425306 DM |
1681 | __flush_tlb_all(); |
1682 | } | |
1683 | ||
9cc3a1ac | 1684 | #ifdef CONFIG_DEBUG_PAGEALLOC |
031bc574 | 1685 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
56425306 DM |
1686 | { |
1687 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1688 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1689 | ||
1690 | kernel_map_range(phys_start, phys_end, | |
0dd5b7b0 | 1691 | (enable ? PAGE_KERNEL : __pgprot(0)), false); |
56425306 | 1692 | |
74bf4312 DM |
1693 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1694 | PAGE_OFFSET + phys_end); | |
1695 | ||
56425306 DM |
1696 | /* we should perform an IPI and flush all tlbs, |
1697 | * but that can deadlock->flush only current cpu. | |
1698 | */ | |
1699 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1700 | PAGE_OFFSET + phys_end); | |
1701 | } | |
1702 | #endif | |
1703 | ||
10147570 DM |
1704 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1705 | { | |
0836a0eb DM |
1706 | int i; |
1707 | ||
13edad7a DM |
1708 | for (i = 0; i < pavail_ents; i++) { |
1709 | if (pavail[i].reg_size >= size) | |
1710 | return pavail[i].phys_addr; | |
0836a0eb DM |
1711 | } |
1712 | ||
13edad7a | 1713 | return ~0UL; |
0836a0eb DM |
1714 | } |
1715 | ||
b2d43834 DM |
1716 | unsigned long PAGE_OFFSET; |
1717 | EXPORT_SYMBOL(PAGE_OFFSET); | |
1718 | ||
bb4e6e85 DM |
1719 | unsigned long VMALLOC_END = 0x0000010000000000UL; |
1720 | EXPORT_SYMBOL(VMALLOC_END); | |
1721 | ||
4397bed0 DM |
1722 | unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; |
1723 | unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; | |
1724 | ||
b2d43834 DM |
1725 | static void __init setup_page_offset(void) |
1726 | { | |
b2d43834 | 1727 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
4397bed0 DM |
1728 | /* Cheetah/Panther support a full 64-bit virtual |
1729 | * address, so we can use all that our page tables | |
1730 | * support. | |
1731 | */ | |
1732 | sparc64_va_hole_top = 0xfff0000000000000UL; | |
1733 | sparc64_va_hole_bottom = 0x0010000000000000UL; | |
1734 | ||
b2d43834 DM |
1735 | max_phys_bits = 42; |
1736 | } else if (tlb_type == hypervisor) { | |
1737 | switch (sun4v_chip_type) { | |
1738 | case SUN4V_CHIP_NIAGARA1: | |
1739 | case SUN4V_CHIP_NIAGARA2: | |
4397bed0 DM |
1740 | /* T1 and T2 support 48-bit virtual addresses. */ |
1741 | sparc64_va_hole_top = 0xffff800000000000UL; | |
1742 | sparc64_va_hole_bottom = 0x0000800000000000UL; | |
1743 | ||
b2d43834 DM |
1744 | max_phys_bits = 39; |
1745 | break; | |
1746 | case SUN4V_CHIP_NIAGARA3: | |
4397bed0 DM |
1747 | /* T3 supports 48-bit virtual addresses. */ |
1748 | sparc64_va_hole_top = 0xffff800000000000UL; | |
1749 | sparc64_va_hole_bottom = 0x0000800000000000UL; | |
1750 | ||
b2d43834 DM |
1751 | max_phys_bits = 43; |
1752 | break; | |
1753 | case SUN4V_CHIP_NIAGARA4: | |
1754 | case SUN4V_CHIP_NIAGARA5: | |
1755 | case SUN4V_CHIP_SPARC64X: | |
7c0fa0f2 | 1756 | case SUN4V_CHIP_SPARC_M6: |
4397bed0 DM |
1757 | /* T4 and later support 52-bit virtual addresses. */ |
1758 | sparc64_va_hole_top = 0xfff8000000000000UL; | |
1759 | sparc64_va_hole_bottom = 0x0008000000000000UL; | |
b2d43834 DM |
1760 | max_phys_bits = 47; |
1761 | break; | |
7c0fa0f2 | 1762 | case SUN4V_CHIP_SPARC_M7: |
c5b8b5be | 1763 | case SUN4V_CHIP_SPARC_SN: |
7c0fa0f2 DM |
1764 | default: |
1765 | /* M7 and later support 52-bit virtual addresses. */ | |
1766 | sparc64_va_hole_top = 0xfff8000000000000UL; | |
1767 | sparc64_va_hole_bottom = 0x0008000000000000UL; | |
1768 | max_phys_bits = 49; | |
1769 | break; | |
b2d43834 DM |
1770 | } |
1771 | } | |
1772 | ||
1773 | if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { | |
1774 | prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", | |
1775 | max_phys_bits); | |
1776 | prom_halt(); | |
1777 | } | |
1778 | ||
bb4e6e85 DM |
1779 | PAGE_OFFSET = sparc64_va_hole_top; |
1780 | VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + | |
1781 | (sparc64_va_hole_bottom >> 2)); | |
b2d43834 | 1782 | |
bb4e6e85 | 1783 | pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", |
b2d43834 | 1784 | PAGE_OFFSET, max_phys_bits); |
bb4e6e85 DM |
1785 | pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", |
1786 | VMALLOC_START, VMALLOC_END); | |
1787 | pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", | |
1788 | VMEMMAP_BASE, VMEMMAP_BASE << 1); | |
b2d43834 DM |
1789 | } |
1790 | ||
517af332 DM |
1791 | static void __init tsb_phys_patch(void) |
1792 | { | |
d257d5da | 1793 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1794 | struct tsb_phys_patch_entry *p; |
1795 | ||
d257d5da DM |
1796 | pquad = &__tsb_ldquad_phys_patch; |
1797 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1798 | unsigned long addr = pquad->addr; | |
1799 | ||
1800 | if (tlb_type == hypervisor) | |
1801 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1802 | else | |
1803 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1804 | wmb(); | |
1805 | __asm__ __volatile__("flush %0" | |
1806 | : /* no outputs */ | |
1807 | : "r" (addr)); | |
1808 | ||
1809 | pquad++; | |
1810 | } | |
1811 | ||
517af332 DM |
1812 | p = &__tsb_phys_patch; |
1813 | while (p < &__tsb_phys_patch_end) { | |
1814 | unsigned long addr = p->addr; | |
1815 | ||
1816 | *(unsigned int *) addr = p->insn; | |
1817 | wmb(); | |
1818 | __asm__ __volatile__("flush %0" | |
1819 | : /* no outputs */ | |
1820 | : "r" (addr)); | |
1821 | ||
1822 | p++; | |
1823 | } | |
1824 | } | |
1825 | ||
490384e7 | 1826 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1827 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1828 | #define NUM_KTSB_DESCR 2 | |
1829 | #else | |
1830 | #define NUM_KTSB_DESCR 1 | |
1831 | #endif | |
1832 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 | 1833 | |
8c82dc0e DM |
1834 | /* The swapper TSBs are loaded with a base sequence of: |
1835 | * | |
1836 | * sethi %uhi(SYMBOL), REG1 | |
1837 | * sethi %hi(SYMBOL), REG2 | |
1838 | * or REG1, %ulo(SYMBOL), REG1 | |
1839 | * or REG2, %lo(SYMBOL), REG2 | |
1840 | * sllx REG1, 32, REG1 | |
1841 | * or REG1, REG2, REG1 | |
1842 | * | |
1843 | * When we use physical addressing for the TSB accesses, we patch the | |
1844 | * first four instructions in the above sequence. | |
1845 | */ | |
1846 | ||
9076d0e7 DM |
1847 | static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) |
1848 | { | |
8c82dc0e DM |
1849 | unsigned long high_bits, low_bits; |
1850 | ||
1851 | high_bits = (pa >> 32) & 0xffffffff; | |
1852 | low_bits = (pa >> 0) & 0xffffffff; | |
9076d0e7 DM |
1853 | |
1854 | while (start < end) { | |
1855 | unsigned int *ia = (unsigned int *)(unsigned long)*start; | |
1856 | ||
8c82dc0e | 1857 | ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); |
9076d0e7 DM |
1858 | __asm__ __volatile__("flush %0" : : "r" (ia)); |
1859 | ||
8c82dc0e | 1860 | ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); |
9076d0e7 DM |
1861 | __asm__ __volatile__("flush %0" : : "r" (ia + 1)); |
1862 | ||
8c82dc0e DM |
1863 | ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); |
1864 | __asm__ __volatile__("flush %0" : : "r" (ia + 2)); | |
1865 | ||
1866 | ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); | |
1867 | __asm__ __volatile__("flush %0" : : "r" (ia + 3)); | |
1868 | ||
9076d0e7 DM |
1869 | start++; |
1870 | } | |
1871 | } | |
1872 | ||
1873 | static void ktsb_phys_patch(void) | |
1874 | { | |
1875 | extern unsigned int __swapper_tsb_phys_patch; | |
1876 | extern unsigned int __swapper_tsb_phys_patch_end; | |
9076d0e7 DM |
1877 | unsigned long ktsb_pa; |
1878 | ||
1879 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); | |
1880 | patch_one_ktsb_phys(&__swapper_tsb_phys_patch, | |
1881 | &__swapper_tsb_phys_patch_end, ktsb_pa); | |
1882 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
0785a8e8 DM |
1883 | { |
1884 | extern unsigned int __swapper_4m_tsb_phys_patch; | |
1885 | extern unsigned int __swapper_4m_tsb_phys_patch_end; | |
9076d0e7 DM |
1886 | ktsb_pa = (kern_base + |
1887 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1888 | patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, | |
1889 | &__swapper_4m_tsb_phys_patch_end, ktsb_pa); | |
0785a8e8 | 1890 | } |
9076d0e7 DM |
1891 | #endif |
1892 | } | |
1893 | ||
490384e7 DM |
1894 | static void __init sun4v_ktsb_init(void) |
1895 | { | |
1896 | unsigned long ktsb_pa; | |
1897 | ||
d7744a09 | 1898 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1899 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1900 | ||
1901 | switch (PAGE_SIZE) { | |
1902 | case 8 * 1024: | |
1903 | default: | |
1904 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1905 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1906 | break; | |
1907 | ||
1908 | case 64 * 1024: | |
1909 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1910 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1911 | break; | |
1912 | ||
1913 | case 512 * 1024: | |
1914 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1915 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1916 | break; | |
1917 | ||
1918 | case 4 * 1024 * 1024: | |
1919 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1920 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1921 | break; | |
6cb79b3f | 1922 | } |
490384e7 | 1923 | |
3f19a84e | 1924 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1925 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1926 | ktsb_descr[0].ctx_idx = 0; | |
1927 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1928 | ktsb_descr[0].resv = 0; | |
1929 | ||
d1acb421 | 1930 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d | 1931 | /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ |
d7744a09 DM |
1932 | ktsb_pa = (kern_base + |
1933 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1934 | ||
1935 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
c69ad0a3 DM |
1936 | ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | |
1937 | HV_PGSZ_MASK_256MB | | |
1938 | HV_PGSZ_MASK_2GB | | |
1939 | HV_PGSZ_MASK_16GB) & | |
1940 | cpu_pgsz_mask); | |
d7744a09 DM |
1941 | ktsb_descr[1].assoc = 1; |
1942 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1943 | ktsb_descr[1].ctx_idx = 0; | |
1944 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1945 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1946 | #endif |
490384e7 DM |
1947 | } |
1948 | ||
2066aadd | 1949 | void sun4v_ktsb_register(void) |
490384e7 | 1950 | { |
7db35f31 | 1951 | unsigned long pa, ret; |
490384e7 DM |
1952 | |
1953 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1954 | ||
7db35f31 DM |
1955 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
1956 | if (ret != 0) { | |
1957 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
1958 | "errors with %lx\n", pa, ret); | |
1959 | prom_halt(); | |
1960 | } | |
490384e7 DM |
1961 | } |
1962 | ||
c69ad0a3 DM |
1963 | static void __init sun4u_linear_pte_xor_finalize(void) |
1964 | { | |
1965 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
1966 | /* This is where we would add Panther support for | |
1967 | * 32MB and 256MB pages. | |
1968 | */ | |
1969 | #endif | |
1970 | } | |
1971 | ||
1972 | static void __init sun4v_linear_pte_xor_finalize(void) | |
1973 | { | |
494e5b6f KA |
1974 | unsigned long pagecv_flag; |
1975 | ||
1976 | /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead | |
1977 | * enables MCD error. Do not set bit 9 on M7 processor. | |
1978 | */ | |
1979 | switch (sun4v_chip_type) { | |
1980 | case SUN4V_CHIP_SPARC_M7: | |
c5b8b5be | 1981 | case SUN4V_CHIP_SPARC_SN: |
494e5b6f KA |
1982 | pagecv_flag = 0x00; |
1983 | break; | |
1984 | default: | |
1985 | pagecv_flag = _PAGE_CV_4V; | |
1986 | break; | |
1987 | } | |
c69ad0a3 DM |
1988 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1989 | if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { | |
1990 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ | |
922631b9 | 1991 | PAGE_OFFSET; |
494e5b6f | 1992 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
1993 | _PAGE_P_4V | _PAGE_W_4V); |
1994 | } else { | |
1995 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
1996 | } | |
1997 | ||
1998 | if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { | |
1999 | kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ | |
922631b9 | 2000 | PAGE_OFFSET; |
494e5b6f | 2001 | kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
2002 | _PAGE_P_4V | _PAGE_W_4V); |
2003 | } else { | |
2004 | kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; | |
2005 | } | |
2006 | ||
2007 | if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { | |
2008 | kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ | |
922631b9 | 2009 | PAGE_OFFSET; |
494e5b6f | 2010 | kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
2011 | _PAGE_P_4V | _PAGE_W_4V); |
2012 | } else { | |
2013 | kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; | |
2014 | } | |
2015 | #endif | |
2016 | } | |
2017 | ||
1da177e4 LT |
2018 | /* paging_init() sets up the page tables */ |
2019 | ||
1da177e4 | 2020 | static unsigned long last_valid_pfn; |
ac55c768 | 2021 | |
c4bce90e DM |
2022 | static void sun4u_pgprot_init(void); |
2023 | static void sun4v_pgprot_init(void); | |
2024 | ||
7c21d533 | 2025 | static phys_addr_t __init available_memory(void) |
2026 | { | |
2027 | phys_addr_t available = 0ULL; | |
2028 | phys_addr_t pa_start, pa_end; | |
2029 | u64 i; | |
2030 | ||
fc6daaf9 TL |
2031 | for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, |
2032 | &pa_end, NULL) | |
7c21d533 | 2033 | available = available + (pa_end - pa_start); |
2034 | ||
2035 | return available; | |
2036 | } | |
2037 | ||
494e5b6f KA |
2038 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
2039 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
2040 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
2041 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
2042 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2043 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2044 | ||
7c21d533 | 2045 | /* We need to exclude reserved regions. This exclusion will include |
2046 | * vmlinux and initrd. To be more precise the initrd size could be used to | |
2047 | * compute a new lower limit because it is freed later during initialization. | |
2048 | */ | |
2049 | static void __init reduce_memory(phys_addr_t limit_ram) | |
2050 | { | |
2051 | phys_addr_t avail_ram = available_memory(); | |
2052 | phys_addr_t pa_start, pa_end; | |
2053 | u64 i; | |
2054 | ||
2055 | if (limit_ram >= avail_ram) | |
2056 | return; | |
2057 | ||
fc6daaf9 TL |
2058 | for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, |
2059 | &pa_end, NULL) { | |
7c21d533 | 2060 | phys_addr_t region_size = pa_end - pa_start; |
2061 | phys_addr_t clip_start = pa_start; | |
2062 | ||
2063 | avail_ram = avail_ram - region_size; | |
2064 | /* Are we consuming too much? */ | |
2065 | if (avail_ram < limit_ram) { | |
2066 | phys_addr_t give_back = limit_ram - avail_ram; | |
2067 | ||
2068 | region_size = region_size - give_back; | |
2069 | clip_start = clip_start + give_back; | |
2070 | } | |
2071 | ||
2072 | memblock_remove(clip_start, region_size); | |
2073 | ||
2074 | if (avail_ram <= limit_ram) | |
2075 | break; | |
2076 | i = 0UL; | |
2077 | } | |
2078 | } | |
2079 | ||
1da177e4 LT |
2080 | void __init paging_init(void) |
2081 | { | |
919ee677 | 2082 | unsigned long end_pfn, shift, phys_base; |
0836a0eb DM |
2083 | unsigned long real_end, i; |
2084 | ||
b2d43834 DM |
2085 | setup_page_offset(); |
2086 | ||
22adb358 DM |
2087 | /* These build time checkes make sure that the dcache_dirty_cpu() |
2088 | * page->flags usage will work. | |
2089 | * | |
2090 | * When a page gets marked as dcache-dirty, we store the | |
2091 | * cpu number starting at bit 32 in the page->flags. Also, | |
2092 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
2093 | * in 13-bit signed-immediate instruction fields. | |
2094 | */ | |
9223b419 CL |
2095 | |
2096 | /* | |
2097 | * Page flags must not reach into upper 32 bits that are used | |
2098 | * for the cpu number | |
2099 | */ | |
2100 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
2101 | ||
2102 | /* | |
2103 | * The bit fields placed in the high range must not reach below | |
2104 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
2105 | * at the 32 bit boundary. | |
2106 | */ | |
22adb358 | 2107 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
2108 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
2109 | ||
22adb358 DM |
2110 | BUILD_BUG_ON(NR_CPUS > 4096); |
2111 | ||
0eef331a | 2112 | kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
481295f9 DM |
2113 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; |
2114 | ||
d7744a09 | 2115 | /* Invalidate both kernel TSBs. */ |
8b234274 | 2116 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 2117 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 2118 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 2119 | #endif |
8b234274 | 2120 | |
494e5b6f KA |
2121 | /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde |
2122 | * bit on M7 processor. This is a conflicting usage of the same | |
2123 | * bit. Enabling TTE.cv on M7 would turn on Memory Corruption | |
2124 | * Detection error on all pages and this will lead to problems | |
2125 | * later. Kernel does not run with MCD enabled and hence rest | |
2126 | * of the required steps to fully configure memory corruption | |
2127 | * detection are not taken. We need to ensure TTE.mcde is not | |
2128 | * set on M7 processor. Compute the value of cacheability | |
2129 | * flag for use later taking this into consideration. | |
2130 | */ | |
2131 | switch (sun4v_chip_type) { | |
2132 | case SUN4V_CHIP_SPARC_M7: | |
c5b8b5be | 2133 | case SUN4V_CHIP_SPARC_SN: |
494e5b6f KA |
2134 | page_cache4v_flag = _PAGE_CP_4V; |
2135 | break; | |
2136 | default: | |
2137 | page_cache4v_flag = _PAGE_CACHE_4V; | |
2138 | break; | |
2139 | } | |
2140 | ||
c4bce90e DM |
2141 | if (tlb_type == hypervisor) |
2142 | sun4v_pgprot_init(); | |
2143 | else | |
2144 | sun4u_pgprot_init(); | |
2145 | ||
d257d5da | 2146 | if (tlb_type == cheetah_plus || |
9076d0e7 | 2147 | tlb_type == hypervisor) { |
517af332 | 2148 | tsb_phys_patch(); |
9076d0e7 DM |
2149 | ktsb_phys_patch(); |
2150 | } | |
517af332 | 2151 | |
c69ad0a3 | 2152 | if (tlb_type == hypervisor) |
d257d5da DM |
2153 | sun4v_patch_tlb_handlers(); |
2154 | ||
a94a172d DM |
2155 | /* Find available physical memory... |
2156 | * | |
2157 | * Read it twice in order to work around a bug in openfirmware. | |
2158 | * The call to grab this table itself can cause openfirmware to | |
2159 | * allocate memory, which in turn can take away some space from | |
2160 | * the list of available memory. Reading it twice makes sure | |
2161 | * we really do get the final value. | |
2162 | */ | |
2163 | read_obp_translations(); | |
2164 | read_obp_memory("reg", &pall[0], &pall_ents); | |
2165 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
13edad7a | 2166 | read_obp_memory("available", &pavail[0], &pavail_ents); |
0836a0eb DM |
2167 | |
2168 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 2169 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 2170 | phys_base = min(phys_base, pavail[i].phys_addr); |
95f72d1e | 2171 | memblock_add(pavail[i].phys_addr, pavail[i].reg_size); |
3b2a7e23 DM |
2172 | } |
2173 | ||
95f72d1e | 2174 | memblock_reserve(kern_base, kern_size); |
0836a0eb | 2175 | |
4e82c9a6 DM |
2176 | find_ramdisk(phys_base); |
2177 | ||
7c21d533 | 2178 | if (cmdline_memory_size) |
2179 | reduce_memory(cmdline_memory_size); | |
25b0c659 | 2180 | |
1aadc056 | 2181 | memblock_allow_resize(); |
95f72d1e | 2182 | memblock_dump_all(); |
3b2a7e23 | 2183 | |
1da177e4 LT |
2184 | set_bit(0, mmu_context_bmap); |
2185 | ||
2bdb3cb2 DM |
2186 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
2187 | ||
1da177e4 | 2188 | real_end = (unsigned long)_end; |
0eef331a | 2189 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); |
64658743 DM |
2190 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", |
2191 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
2192 | |
2193 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
2194 | * work. |
2195 | */ | |
2196 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
2197 | ||
d195b71b | 2198 | memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); |
0dd5b7b0 | 2199 | |
c9c10830 | 2200 | inherit_prom_mappings(); |
5085b4a5 | 2201 | |
a8b900d8 DM |
2202 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
2203 | setup_tba(); | |
1da177e4 | 2204 | |
c9c10830 | 2205 | __flush_tlb_all(); |
9ad98c5b | 2206 | |
ad072004 | 2207 | prom_build_devicetree(); |
b696fdc2 | 2208 | of_populate_present_mask(); |
b99c6ebe DM |
2209 | #ifndef CONFIG_SMP |
2210 | of_fill_in_cpu_data(); | |
2211 | #endif | |
ad072004 | 2212 | |
890db403 | 2213 | if (tlb_type == hypervisor) { |
4a283339 | 2214 | sun4v_mdesc_init(); |
6ac5c610 | 2215 | mdesc_populate_present_mask(cpu_all_mask); |
b99c6ebe DM |
2216 | #ifndef CONFIG_SMP |
2217 | mdesc_fill_in_cpu_data(cpu_all_mask); | |
2218 | #endif | |
ce33fdc5 | 2219 | mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); |
c69ad0a3 DM |
2220 | |
2221 | sun4v_linear_pte_xor_finalize(); | |
2222 | ||
2223 | sun4v_ktsb_init(); | |
2224 | sun4v_ktsb_register(); | |
ce33fdc5 DM |
2225 | } else { |
2226 | unsigned long impl, ver; | |
2227 | ||
2228 | cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | | |
2229 | HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); | |
2230 | ||
2231 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
2232 | impl = ((ver >> 32) & 0xffff); | |
2233 | if (impl == PANTHER_IMPL) | |
2234 | cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | | |
2235 | HV_PGSZ_MASK_256MB); | |
c69ad0a3 DM |
2236 | |
2237 | sun4u_linear_pte_xor_finalize(); | |
890db403 | 2238 | } |
4a283339 | 2239 | |
c69ad0a3 DM |
2240 | /* Flush the TLBs and the 4M TSB so that the updated linear |
2241 | * pte XOR settings are realized for all mappings. | |
2242 | */ | |
2243 | __flush_tlb_all(); | |
2244 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
2245 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); | |
2246 | #endif | |
2247 | __flush_tlb_all(); | |
2248 | ||
5ed56f1a DM |
2249 | /* Setup bootmem... */ |
2250 | last_valid_pfn = end_pfn = bootmem_init(phys_base); | |
2251 | ||
56425306 | 2252 | kernel_physical_mapping_init(); |
56425306 | 2253 | |
1da177e4 | 2254 | { |
919ee677 | 2255 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 2256 | |
919ee677 | 2257 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 2258 | |
919ee677 | 2259 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 2260 | |
919ee677 | 2261 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
2262 | } |
2263 | ||
3c62a2d3 | 2264 | printk("Booting Linux...\n"); |
1da177e4 LT |
2265 | } |
2266 | ||
7c9503b8 | 2267 | int page_in_phys_avail(unsigned long paddr) |
919ee677 DM |
2268 | { |
2269 | int i; | |
2270 | ||
2271 | paddr &= PAGE_MASK; | |
2272 | ||
2273 | for (i = 0; i < pavail_ents; i++) { | |
2274 | unsigned long start, end; | |
2275 | ||
2276 | start = pavail[i].phys_addr; | |
2277 | end = start + pavail[i].reg_size; | |
2278 | ||
2279 | if (paddr >= start && paddr < end) | |
2280 | return 1; | |
2281 | } | |
2282 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
2283 | return 1; | |
2284 | #ifdef CONFIG_BLK_DEV_INITRD | |
2285 | if (paddr >= __pa(initrd_start) && | |
2286 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
2287 | return 1; | |
2288 | #endif | |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
961f8fa0 YL |
2293 | static void __init register_page_bootmem_info(void) |
2294 | { | |
2295 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
2296 | int i; | |
2297 | ||
2298 | for_each_online_node(i) | |
2299 | if (NODE_DATA(i)->node_spanned_pages) | |
2300 | register_page_bootmem_info_node(NODE_DATA(i)); | |
2301 | #endif | |
2302 | } | |
1da177e4 LT |
2303 | void __init mem_init(void) |
2304 | { | |
1da177e4 LT |
2305 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
2306 | ||
961f8fa0 | 2307 | register_page_bootmem_info(); |
0c988534 | 2308 | free_all_bootmem(); |
919ee677 | 2309 | |
1da177e4 LT |
2310 | /* |
2311 | * Set up the zero page, mark it reserved, so that page count | |
2312 | * is not manipulated when freeing the page from user ptes. | |
2313 | */ | |
2314 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
2315 | if (mem_map_zero == NULL) { | |
2316 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
2317 | prom_halt(); | |
2318 | } | |
70affe45 | 2319 | mark_page_reserved(mem_map_zero); |
1da177e4 | 2320 | |
dceccbe9 | 2321 | mem_init_print_info(NULL); |
1da177e4 LT |
2322 | |
2323 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
2324 | cheetah_ecache_flush_init(); | |
2325 | } | |
2326 | ||
898cf0ec | 2327 | void free_initmem(void) |
1da177e4 LT |
2328 | { |
2329 | unsigned long addr, initend; | |
f2b60794 DM |
2330 | int do_free = 1; |
2331 | ||
2332 | /* If the physical memory maps were trimmed by kernel command | |
2333 | * line options, don't even try freeing this initmem stuff up. | |
2334 | * The kernel image could have been in the trimmed out region | |
2335 | * and if so the freeing below will free invalid page structs. | |
2336 | */ | |
2337 | if (cmdline_memory_size) | |
2338 | do_free = 0; | |
1da177e4 LT |
2339 | |
2340 | /* | |
2341 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
2342 | */ | |
2343 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
2344 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
2345 | for (; addr < initend; addr += PAGE_SIZE) { | |
2346 | unsigned long page; | |
1da177e4 LT |
2347 | |
2348 | page = (addr + | |
2349 | ((unsigned long) __va(kern_base)) - | |
2350 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 2351 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 | 2352 | |
70affe45 JL |
2353 | if (do_free) |
2354 | free_reserved_page(virt_to_page(page)); | |
1da177e4 LT |
2355 | } |
2356 | } | |
2357 | ||
2358 | #ifdef CONFIG_BLK_DEV_INITRD | |
2359 | void free_initrd_mem(unsigned long start, unsigned long end) | |
2360 | { | |
dceccbe9 JL |
2361 | free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, |
2362 | "initrd"); | |
1da177e4 LT |
2363 | } |
2364 | #endif | |
c4bce90e | 2365 | |
c4bce90e DM |
2366 | pgprot_t PAGE_KERNEL __read_mostly; |
2367 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2368 | ||
2369 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2370 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2371 | |
2372 | pgprot_t PAGE_SHARED __read_mostly; | |
2373 | EXPORT_SYMBOL(PAGE_SHARED); | |
2374 | ||
c4bce90e DM |
2375 | unsigned long pg_iobits __read_mostly; |
2376 | ||
2377 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2378 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2379 | |
c4bce90e | 2380 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2381 | EXPORT_SYMBOL(_PAGE_E); |
2382 | ||
c4bce90e | 2383 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2384 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2385 | |
46644c24 | 2386 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
0aad818b JW |
2387 | int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, |
2388 | int node) | |
46644c24 | 2389 | { |
46644c24 DM |
2390 | unsigned long pte_base; |
2391 | ||
2392 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2393 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2394 | _PAGE_P_4U | _PAGE_W_4U); | |
2395 | if (tlb_type == hypervisor) | |
2396 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
494e5b6f | 2397 | page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); |
46644c24 | 2398 | |
c06240c7 | 2399 | pte_base |= _PAGE_PMD_HUGE; |
46644c24 | 2400 | |
c06240c7 DM |
2401 | vstart = vstart & PMD_MASK; |
2402 | vend = ALIGN(vend, PMD_SIZE); | |
2403 | for (; vstart < vend; vstart += PMD_SIZE) { | |
2404 | pgd_t *pgd = pgd_offset_k(vstart); | |
2405 | unsigned long pte; | |
2406 | pud_t *pud; | |
2407 | pmd_t *pmd; | |
2408 | ||
2409 | if (pgd_none(*pgd)) { | |
2410 | pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node); | |
2411 | ||
2412 | if (!new) | |
46644c24 | 2413 | return -ENOMEM; |
c06240c7 DM |
2414 | pgd_populate(&init_mm, pgd, new); |
2415 | } | |
46644c24 | 2416 | |
c06240c7 DM |
2417 | pud = pud_offset(pgd, vstart); |
2418 | if (pud_none(*pud)) { | |
2419 | pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node); | |
46644c24 | 2420 | |
c06240c7 DM |
2421 | if (!new) |
2422 | return -ENOMEM; | |
2423 | pud_populate(&init_mm, pud, new); | |
46644c24 | 2424 | } |
2856cc2e | 2425 | |
c06240c7 DM |
2426 | pmd = pmd_offset(pud, vstart); |
2427 | ||
2428 | pte = pmd_val(*pmd); | |
2429 | if (!(pte & _PAGE_VALID)) { | |
2430 | void *block = vmemmap_alloc_block(PMD_SIZE, node); | |
2431 | ||
2432 | if (!block) | |
2433 | return -ENOMEM; | |
2434 | ||
2435 | pmd_val(*pmd) = pte_base | __pa(block); | |
2436 | } | |
2856cc2e | 2437 | } |
c06240c7 DM |
2438 | |
2439 | return 0; | |
2856cc2e | 2440 | } |
46723bfa | 2441 | |
0aad818b | 2442 | void vmemmap_free(unsigned long start, unsigned long end) |
0197518c TC |
2443 | { |
2444 | } | |
46644c24 DM |
2445 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ |
2446 | ||
c4bce90e DM |
2447 | static void prot_init_common(unsigned long page_none, |
2448 | unsigned long page_shared, | |
2449 | unsigned long page_copy, | |
2450 | unsigned long page_readonly, | |
2451 | unsigned long page_exec_bit) | |
2452 | { | |
2453 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2454 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2455 | |
2456 | protection_map[0x0] = __pgprot(page_none); | |
2457 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2458 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2459 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2460 | protection_map[0x4] = __pgprot(page_readonly); | |
2461 | protection_map[0x5] = __pgprot(page_readonly); | |
2462 | protection_map[0x6] = __pgprot(page_copy); | |
2463 | protection_map[0x7] = __pgprot(page_copy); | |
2464 | protection_map[0x8] = __pgprot(page_none); | |
2465 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2466 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2467 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2468 | protection_map[0xc] = __pgprot(page_readonly); | |
2469 | protection_map[0xd] = __pgprot(page_readonly); | |
2470 | protection_map[0xe] = __pgprot(page_shared); | |
2471 | protection_map[0xf] = __pgprot(page_shared); | |
2472 | } | |
2473 | ||
2474 | static void __init sun4u_pgprot_init(void) | |
2475 | { | |
2476 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2477 | unsigned long page_exec_bit; | |
4f93d21d | 2478 | int i; |
c4bce90e DM |
2479 | |
2480 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2481 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2482 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2483 | _PAGE_EXEC_4U); | |
2484 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2485 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2486 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2487 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
c4bce90e DM |
2488 | |
2489 | _PAGE_IE = _PAGE_IE_4U; | |
2490 | _PAGE_E = _PAGE_E_4U; | |
2491 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2492 | ||
2493 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2494 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2495 | ||
d1acb421 | 2496 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2497 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2498 | #else |
9cc3a1ac | 2499 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
922631b9 | 2500 | PAGE_OFFSET; |
d1acb421 | 2501 | #endif |
9cc3a1ac DM |
2502 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2503 | _PAGE_P_4U | _PAGE_W_4U); | |
2504 | ||
4f93d21d DM |
2505 | for (i = 1; i < 4; i++) |
2506 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
c4bce90e | 2507 | |
c4bce90e DM |
2508 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | |
2509 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2510 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2511 | ||
2512 | ||
2513 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2514 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2515 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2516 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2517 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2518 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2519 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2520 | ||
2521 | page_exec_bit = _PAGE_EXEC_4U; | |
2522 | ||
2523 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2524 | page_exec_bit); | |
2525 | } | |
2526 | ||
2527 | static void __init sun4v_pgprot_init(void) | |
2528 | { | |
2529 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2530 | unsigned long page_exec_bit; | |
4f93d21d | 2531 | int i; |
c4bce90e DM |
2532 | |
2533 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
494e5b6f | 2534 | page_cache4v_flag | _PAGE_P_4V | |
c4bce90e DM |
2535 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | |
2536 | _PAGE_EXEC_4V); | |
2537 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
c4bce90e DM |
2538 | |
2539 | _PAGE_IE = _PAGE_IE_4V; | |
2540 | _PAGE_E = _PAGE_E_4V; | |
494e5b6f | 2541 | _PAGE_CACHE = page_cache4v_flag; |
c4bce90e | 2542 | |
d1acb421 | 2543 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2544 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2545 | #else |
9cc3a1ac | 2546 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
922631b9 | 2547 | PAGE_OFFSET; |
d1acb421 | 2548 | #endif |
494e5b6f KA |
2549 | kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | |
2550 | _PAGE_W_4V); | |
9cc3a1ac | 2551 | |
c69ad0a3 DM |
2552 | for (i = 1; i < 4; i++) |
2553 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
4f93d21d | 2554 | |
c4bce90e DM |
2555 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | |
2556 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2557 | ||
c4bce90e DM |
2558 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | |
2559 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2560 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2561 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2562 | ||
494e5b6f KA |
2563 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; |
2564 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | | |
c4bce90e | 2565 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); |
494e5b6f | 2566 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | |
c4bce90e | 2567 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); |
494e5b6f | 2568 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | |
c4bce90e DM |
2569 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); |
2570 | ||
2571 | page_exec_bit = _PAGE_EXEC_4V; | |
2572 | ||
2573 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2574 | page_exec_bit); | |
2575 | } | |
2576 | ||
2577 | unsigned long pte_sz_bits(unsigned long sz) | |
2578 | { | |
2579 | if (tlb_type == hypervisor) { | |
2580 | switch (sz) { | |
2581 | case 8 * 1024: | |
2582 | default: | |
2583 | return _PAGE_SZ8K_4V; | |
2584 | case 64 * 1024: | |
2585 | return _PAGE_SZ64K_4V; | |
2586 | case 512 * 1024: | |
2587 | return _PAGE_SZ512K_4V; | |
2588 | case 4 * 1024 * 1024: | |
2589 | return _PAGE_SZ4MB_4V; | |
6cb79b3f | 2590 | } |
c4bce90e DM |
2591 | } else { |
2592 | switch (sz) { | |
2593 | case 8 * 1024: | |
2594 | default: | |
2595 | return _PAGE_SZ8K_4U; | |
2596 | case 64 * 1024: | |
2597 | return _PAGE_SZ64K_4U; | |
2598 | case 512 * 1024: | |
2599 | return _PAGE_SZ512K_4U; | |
2600 | case 4 * 1024 * 1024: | |
2601 | return _PAGE_SZ4MB_4U; | |
6cb79b3f | 2602 | } |
c4bce90e DM |
2603 | } |
2604 | } | |
2605 | ||
2606 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2607 | { | |
2608 | pte_t pte; | |
cf627156 DM |
2609 | |
2610 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2611 | pte_val(pte) |= (((unsigned long)space) << 32); |
2612 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2613 | |
cf627156 | 2614 | return pte; |
c4bce90e DM |
2615 | } |
2616 | ||
2617 | static unsigned long kern_large_tte(unsigned long paddr) | |
2618 | { | |
2619 | unsigned long val; | |
2620 | ||
2621 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2622 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2623 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2624 | if (tlb_type == hypervisor) | |
2625 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
494e5b6f | 2626 | page_cache4v_flag | _PAGE_P_4V | |
c4bce90e DM |
2627 | _PAGE_EXEC_4V | _PAGE_W_4V); |
2628 | ||
2629 | return val | paddr; | |
2630 | } | |
2631 | ||
c4bce90e DM |
2632 | /* If not locked, zap it. */ |
2633 | void __flush_tlb_all(void) | |
2634 | { | |
2635 | unsigned long pstate; | |
2636 | int i; | |
2637 | ||
2638 | __asm__ __volatile__("flushw\n\t" | |
2639 | "rdpr %%pstate, %0\n\t" | |
2640 | "wrpr %0, %1, %%pstate" | |
2641 | : "=r" (pstate) | |
2642 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2643 | if (tlb_type == hypervisor) { |
2644 | sun4v_mmu_demap_all(); | |
2645 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2646 | for (i = 0; i < 64; i++) { |
2647 | /* Spitfire Errata #32 workaround */ | |
2648 | /* NOTE: Always runs on spitfire, so no | |
2649 | * cheetah+ page size encodings. | |
2650 | */ | |
2651 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2652 | "flush %%g6" | |
2653 | : /* No outputs */ | |
2654 | : "r" (0), | |
2655 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2656 | ||
2657 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2658 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2659 | "membar #Sync" | |
2660 | : /* no outputs */ | |
2661 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2662 | spitfire_put_dtlb_data(i, 0x0UL); | |
2663 | } | |
2664 | ||
2665 | /* Spitfire Errata #32 workaround */ | |
2666 | /* NOTE: Always runs on spitfire, so no | |
2667 | * cheetah+ page size encodings. | |
2668 | */ | |
2669 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2670 | "flush %%g6" | |
2671 | : /* No outputs */ | |
2672 | : "r" (0), | |
2673 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2674 | ||
2675 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2676 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2677 | "membar #Sync" | |
2678 | : /* no outputs */ | |
2679 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2680 | spitfire_put_itlb_data(i, 0x0UL); | |
2681 | } | |
2682 | } | |
2683 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2684 | cheetah_flush_dtlb_all(); | |
2685 | cheetah_flush_itlb_all(); | |
2686 | } | |
2687 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2688 | : : "r" (pstate)); | |
2689 | } | |
c460bec7 | 2690 | |
c460bec7 DM |
2691 | pte_t *pte_alloc_one_kernel(struct mm_struct *mm, |
2692 | unsigned long address) | |
2693 | { | |
32d6bd90 | 2694 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); |
37b3a8ff | 2695 | pte_t *pte = NULL; |
c460bec7 | 2696 | |
c460bec7 DM |
2697 | if (page) |
2698 | pte = (pte_t *) page_address(page); | |
2699 | ||
2700 | return pte; | |
2701 | } | |
2702 | ||
2703 | pgtable_t pte_alloc_one(struct mm_struct *mm, | |
2704 | unsigned long address) | |
2705 | { | |
32d6bd90 | 2706 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); |
1ae9ae5f KS |
2707 | if (!page) |
2708 | return NULL; | |
2709 | if (!pgtable_page_ctor(page)) { | |
2710 | free_hot_cold_page(page, 0); | |
2711 | return NULL; | |
c460bec7 | 2712 | } |
1ae9ae5f | 2713 | return (pte_t *) page_address(page); |
c460bec7 DM |
2714 | } |
2715 | ||
2716 | void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |
2717 | { | |
37b3a8ff | 2718 | free_page((unsigned long)pte); |
c460bec7 DM |
2719 | } |
2720 | ||
2721 | static void __pte_free(pgtable_t pte) | |
2722 | { | |
2723 | struct page *page = virt_to_page(pte); | |
37b3a8ff DM |
2724 | |
2725 | pgtable_page_dtor(page); | |
2726 | __free_page(page); | |
c460bec7 DM |
2727 | } |
2728 | ||
2729 | void pte_free(struct mm_struct *mm, pgtable_t pte) | |
2730 | { | |
2731 | __pte_free(pte); | |
2732 | } | |
2733 | ||
2734 | void pgtable_free(void *table, bool is_page) | |
2735 | { | |
2736 | if (is_page) | |
2737 | __pte_free(table); | |
2738 | else | |
2739 | kmem_cache_free(pgtable_cache, table); | |
2740 | } | |
9e695d2e DM |
2741 | |
2742 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
9e695d2e DM |
2743 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, |
2744 | pmd_t *pmd) | |
2745 | { | |
2746 | unsigned long pte, flags; | |
2747 | struct mm_struct *mm; | |
2748 | pmd_t entry = *pmd; | |
9e695d2e DM |
2749 | |
2750 | if (!pmd_large(entry) || !pmd_young(entry)) | |
2751 | return; | |
2752 | ||
a7b9403f | 2753 | pte = pmd_val(entry); |
9e695d2e | 2754 | |
18f38132 DM |
2755 | /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ |
2756 | if (!(pte & _PAGE_VALID)) | |
2757 | return; | |
2758 | ||
37b3a8ff DM |
2759 | /* We are fabricating 8MB pages using 4MB real hw pages. */ |
2760 | pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); | |
9e695d2e DM |
2761 | |
2762 | mm = vma->vm_mm; | |
2763 | ||
2764 | spin_lock_irqsave(&mm->context.lock, flags); | |
2765 | ||
2766 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) | |
37b3a8ff | 2767 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, |
9e695d2e DM |
2768 | addr, pte); |
2769 | ||
2770 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
2771 | } | |
2772 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
2773 | ||
2774 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
2775 | static void context_reload(void *__data) | |
2776 | { | |
2777 | struct mm_struct *mm = __data; | |
2778 | ||
2779 | if (mm == current->mm) | |
2780 | load_secondary_context(mm); | |
2781 | } | |
2782 | ||
0fbebed6 | 2783 | void hugetlb_setup(struct pt_regs *regs) |
9e695d2e | 2784 | { |
0fbebed6 DM |
2785 | struct mm_struct *mm = current->mm; |
2786 | struct tsb_config *tp; | |
9e695d2e | 2787 | |
70ffdb93 | 2788 | if (faulthandler_disabled() || !mm) { |
0fbebed6 DM |
2789 | const struct exception_table_entry *entry; |
2790 | ||
2791 | entry = search_exception_tables(regs->tpc); | |
2792 | if (entry) { | |
2793 | regs->tpc = entry->fixup; | |
2794 | regs->tnpc = regs->tpc + 4; | |
2795 | return; | |
2796 | } | |
2797 | pr_alert("Unexpected HugeTLB setup in atomic context.\n"); | |
2798 | die_if_kernel("HugeTSB in atomic", regs); | |
2799 | } | |
2800 | ||
2801 | tp = &mm->context.tsb_block[MM_TSB_HUGE]; | |
2802 | if (likely(tp->tsb == NULL)) | |
2803 | tsb_grow(mm, MM_TSB_HUGE, 0); | |
9e695d2e | 2804 | |
9e695d2e DM |
2805 | tsb_context_switch(mm); |
2806 | smp_tsb_sync(mm); | |
2807 | ||
2808 | /* On UltraSPARC-III+ and later, configure the second half of | |
2809 | * the Data-TLB for huge pages. | |
2810 | */ | |
2811 | if (tlb_type == cheetah_plus) { | |
9ea46abe | 2812 | bool need_context_reload = false; |
9e695d2e DM |
2813 | unsigned long ctx; |
2814 | ||
9ea46abe | 2815 | spin_lock_irq(&ctx_alloc_lock); |
9e695d2e DM |
2816 | ctx = mm->context.sparc64_ctx_val; |
2817 | ctx &= ~CTX_PGSZ_MASK; | |
2818 | ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; | |
2819 | ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; | |
2820 | ||
2821 | if (ctx != mm->context.sparc64_ctx_val) { | |
2822 | /* When changing the page size fields, we | |
2823 | * must perform a context flush so that no | |
2824 | * stale entries match. This flush must | |
2825 | * occur with the original context register | |
2826 | * settings. | |
2827 | */ | |
2828 | do_flush_tlb_mm(mm); | |
2829 | ||
2830 | /* Reload the context register of all processors | |
2831 | * also executing in this address space. | |
2832 | */ | |
2833 | mm->context.sparc64_ctx_val = ctx; | |
9ea46abe | 2834 | need_context_reload = true; |
9e695d2e | 2835 | } |
9ea46abe DM |
2836 | spin_unlock_irq(&ctx_alloc_lock); |
2837 | ||
2838 | if (need_context_reload) | |
2839 | on_each_cpu(context_reload, mm, 0); | |
9e695d2e DM |
2840 | } |
2841 | } | |
2842 | #endif | |
f6d4fb5c | 2843 | |
2844 | static struct resource code_resource = { | |
2845 | .name = "Kernel code", | |
35d98e93 | 2846 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 2847 | }; |
2848 | ||
2849 | static struct resource data_resource = { | |
2850 | .name = "Kernel data", | |
35d98e93 | 2851 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 2852 | }; |
2853 | ||
2854 | static struct resource bss_resource = { | |
2855 | .name = "Kernel bss", | |
35d98e93 | 2856 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 2857 | }; |
2858 | ||
2859 | static inline resource_size_t compute_kern_paddr(void *addr) | |
2860 | { | |
2861 | return (resource_size_t) (addr - KERNBASE + kern_base); | |
2862 | } | |
2863 | ||
2864 | static void __init kernel_lds_init(void) | |
2865 | { | |
2866 | code_resource.start = compute_kern_paddr(_text); | |
2867 | code_resource.end = compute_kern_paddr(_etext - 1); | |
2868 | data_resource.start = compute_kern_paddr(_etext); | |
2869 | data_resource.end = compute_kern_paddr(_edata - 1); | |
2870 | bss_resource.start = compute_kern_paddr(__bss_start); | |
2871 | bss_resource.end = compute_kern_paddr(_end - 1); | |
2872 | } | |
2873 | ||
2874 | static int __init report_memory(void) | |
2875 | { | |
2876 | int i; | |
2877 | struct resource *res; | |
2878 | ||
2879 | kernel_lds_init(); | |
2880 | ||
2881 | for (i = 0; i < pavail_ents; i++) { | |
2882 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
2883 | ||
2884 | if (!res) { | |
2885 | pr_warn("Failed to allocate source.\n"); | |
2886 | break; | |
2887 | } | |
2888 | ||
2889 | res->name = "System RAM"; | |
2890 | res->start = pavail[i].phys_addr; | |
2891 | res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; | |
35d98e93 | 2892 | res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; |
f6d4fb5c | 2893 | |
2894 | if (insert_resource(&iomem_resource, res) < 0) { | |
2895 | pr_warn("Resource insertion failed.\n"); | |
2896 | break; | |
2897 | } | |
2898 | ||
2899 | insert_resource(res, &code_resource); | |
2900 | insert_resource(res, &data_resource); | |
2901 | insert_resource(res, &bss_resource); | |
2902 | } | |
2903 | ||
2904 | return 0; | |
2905 | } | |
3c08158e | 2906 | arch_initcall(report_memory); |
e9011d08 | 2907 | |
4ca9a237 DM |
2908 | #ifdef CONFIG_SMP |
2909 | #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range | |
2910 | #else | |
2911 | #define do_flush_tlb_kernel_range __flush_tlb_kernel_range | |
2912 | #endif | |
2913 | ||
2914 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
2915 | { | |
2916 | if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { | |
2917 | if (start < LOW_OBP_ADDRESS) { | |
2918 | flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); | |
2919 | do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); | |
2920 | } | |
2921 | if (end > HI_OBP_ADDRESS) { | |
473ad7f4 DM |
2922 | flush_tsb_kernel_range(HI_OBP_ADDRESS, end); |
2923 | do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); | |
4ca9a237 DM |
2924 | } |
2925 | } else { | |
2926 | flush_tsb_kernel_range(start, end); | |
2927 | do_flush_tlb_kernel_range(start, end); | |
2928 | } | |
2929 | } |