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[SPARC64]: Fix obppath pci device sysfs creation.
[deliverable/linux.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/smp_lock.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
23#include <asm/pbm.h>
24#include <asm/pgtable.h>
25#include <asm/irq.h>
26#include <asm/ebus.h>
27#include <asm/isa.h>
e87dc350 28#include <asm/prom.h>
1da177e4 29
1e8a8cc5
DM		 30#include "pci_impl.h"
31
1da177e4
LT		 32unsigned long pci_memspace_mask = 0xffffffffUL;
33
34#ifndef CONFIG_PCI
35/* A "nop" PCI implementation. */
36asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
38 unsigned char *buf)
39{
40 return 0;
41}
42asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
43 unsigned long off, unsigned long len,
44 unsigned char *buf)
45{
46 return 0;
47}
48#else
49
50/* List of all PCI controllers found in the system. */
51struct pci_controller_info *pci_controller_root = NULL;
52
53/* Each PCI controller found gets a unique index. */
54int pci_num_controllers = 0;
55
1da177e4
LT		 56volatile int pci_poke_in_progress;
57volatile int pci_poke_cpu = -1;
58volatile int pci_poke_faulted;
59
60static DEFINE_SPINLOCK(pci_poke_lock);
61
62void pci_config_read8(u8 *addr, u8 *ret)
63{
64 unsigned long flags;
65 u8 byte;
66
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
70 pci_poke_faulted = 0;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
73 "membar #Sync"
74 : "=r" (byte)
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 : "memory");
77 pci_poke_in_progress = 0;
78 pci_poke_cpu = -1;
79 if (!pci_poke_faulted)
80 *ret = byte;
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
82}
83
84void pci_config_read16(u16 *addr, u16 *ret)
85{
86 unsigned long flags;
87 u16 word;
88
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
92 pci_poke_faulted = 0;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
95 "membar #Sync"
96 : "=r" (word)
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
98 : "memory");
99 pci_poke_in_progress = 0;
100 pci_poke_cpu = -1;
101 if (!pci_poke_faulted)
102 *ret = word;
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
104}
105
106void pci_config_read32(u32 *addr, u32 *ret)
107{
108 unsigned long flags;
109 u32 dword;
110
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
117 "membar #Sync"
118 : "=r" (dword)
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
120 : "memory");
121 pci_poke_in_progress = 0;
122 pci_poke_cpu = -1;
123 if (!pci_poke_faulted)
124 *ret = dword;
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
126}
127
128void pci_config_write8(u8 *addr, u8 val)
129{
130 unsigned long flags;
131
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
138 "membar #Sync"
139 : /* no outputs */
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
141 : "memory");
142 pci_poke_in_progress = 0;
143 pci_poke_cpu = -1;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
145}
146
147void pci_config_write16(u16 *addr, u16 val)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
157 "membar #Sync"
158 : /* no outputs */
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
160 : "memory");
161 pci_poke_in_progress = 0;
162 pci_poke_cpu = -1;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
164}
165
166void pci_config_write32(u32 *addr, u32 val)
167{
168 unsigned long flags;
169
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
176 "membar #Sync"
177 : /* no outputs */
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 : "memory");
180 pci_poke_in_progress = 0;
181 pci_poke_cpu = -1;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
183}
184
185/* Probe for all PCI controllers in the system. */
e87dc350
DM		 186extern void sabre_init(struct device_node *, const char *);
187extern void psycho_init(struct device_node *, const char *);
188extern void schizo_init(struct device_node *, const char *);
189extern void schizo_plus_init(struct device_node *, const char *);
190extern void tomatillo_init(struct device_node *, const char *);
191extern void sun4v_pci_init(struct device_node *, const char *);
1da177e4
LT		 192
193static struct {
194 char *model_name;
e87dc350 195 void (*init)(struct device_node *, const char *);
1da177e4
LT		 196} pci_controller_table[] __initdata = {
197 { "SUNW,sabre", sabre_init },
198 { "pci108e,a000", sabre_init },
199 { "pci108e,a001", sabre_init },
200 { "SUNW,psycho", psycho_init },
201 { "pci108e,8000", psycho_init },
202 { "SUNW,schizo", schizo_init },
203 { "pci108e,8001", schizo_init },
204 { "SUNW,schizo+", schizo_plus_init },
205 { "pci108e,8002", schizo_plus_init },
206 { "SUNW,tomatillo", tomatillo_init },
207 { "pci108e,a801", tomatillo_init },
8f6a93a1 208 { "SUNW,sun4v-pci", sun4v_pci_init },
1da177e4
LT		 209};
210#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
211 sizeof(pci_controller_table[0]))
212
e87dc350 213static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 214{
215 int i;
216
217 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
218 if (!strncmp(model_name,
219 pci_controller_table[i].model_name,
220 namelen)) {
e87dc350 221 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 222 return 1;
223 }
224 }
1da177e4
LT		 225
226 return 0;
227}
228
e87dc350 229static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 230{
231 int i;
232
233 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
234 if (!strncmp(model_name,
235 pci_controller_table[i].model_name,
236 namelen)) {
237 return 1;
238 }
239 }
240 return 0;
241}
242
e87dc350 243static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 244{
e87dc350 245 struct device_node *dp;
1da177e4
LT		 246 int count = 0;
247
e87dc350
DM		 248 for_each_node_by_name(dp, "pci") {
249 struct property *prop;
1da177e4
LT		 250 int len;
251
e87dc350
DM		 252 prop = of_find_property(dp, "model", &len);
253 if (!prop)
254 prop = of_find_property(dp, "compatible", &len);
255
256 if (prop) {
257 const char *model = prop->value;
1da177e4
LT		 258 int item_len = 0;
259
260 /* Our value may be a multi-valued string in the
261 * case of some compatible properties. For sanity,
e87dc350
DM		 262 * only try the first one.
263 */
264 while (model[item_len] && len) {
1da177e4
LT		 265 len--;
266 item_len++;
267 }
268
e87dc350 269 if (handler(model, item_len, dp))
1da177e4
LT		 270 count++;
271 }
1da177e4
LT		 272 }
273
274 return count;
275}
276
277
278/* Is there some PCI controller in the system? */
279int __init pcic_present(void)
280{
281 return pci_controller_scan(pci_is_controller);
282}
283
8f6a93a1
DM		 284struct pci_iommu_ops *pci_iommu_ops;
285EXPORT_SYMBOL(pci_iommu_ops);
286
287extern struct pci_iommu_ops pci_sun4u_iommu_ops,
288 pci_sun4v_iommu_ops;
289
1da177e4
LT		 290/* Find each controller in the system, attach and initialize
291 * software state structure for each and link into the
292 * pci_controller_root. Setup the controller enough such
293 * that bus scanning can be done.
294 */
295static void __init pci_controller_probe(void)
296{
8f6a93a1
DM		 297 if (tlb_type == hypervisor)
298 pci_iommu_ops = &pci_sun4v_iommu_ops;
299 else
300 pci_iommu_ops = &pci_sun4u_iommu_ops;
301
1da177e4
LT		 302 printk("PCI: Probing for controllers.\n");
303
304 pci_controller_scan(pci_controller_init);
305}
306
a2fb23af
DM		 307static unsigned long pci_parse_of_flags(u32 addr0)
308{
309 unsigned long flags = 0;
310
311 if (addr0 & 0x02000000) {
312 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
313 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
314 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
315 if (addr0 & 0x40000000)
316 flags |= IORESOURCE_PREFETCH
317 | PCI_BASE_ADDRESS_MEM_PREFETCH;
318 } else if (addr0 & 0x01000000)
319 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
320 return flags;
321}
322
323/* The of_device layer has translated all of the assigned-address properties
324 * into physical address resources, we only have to figure out the register
325 * mapping.
326 */
327static void pci_parse_of_addrs(struct of_device *op,
328 struct device_node *node,
329 struct pci_dev *dev)
330{
331 struct resource *op_res;
332 const u32 *addrs;
333 int proplen;
334
335 addrs = of_get_property(node, "assigned-addresses", &proplen);
336 if (!addrs)
337 return;
338 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
339 op_res = &op->resource[0];
340 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
341 struct resource *res;
342 unsigned long flags;
343 int i;
344
345 flags = pci_parse_of_flags(addrs[0]);
346 if (!flags)
347 continue;
348 i = addrs[0] & 0xff;
349 printk(" start: %lx, end: %lx, i: %x\n",
350 op_res->start, op_res->end, i);
351
352 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
353 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
354 } else if (i == dev->rom_base_reg) {
355 res = &dev->resource[PCI_ROM_RESOURCE];
356 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
357 } else {
358 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
359 continue;
360 }
361 res->start = op_res->start;
362 res->end = op_res->end;
363 res->flags = flags;
364 res->name = pci_name(dev);
365 }
366}
367
368struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
369 struct device_node *node,
370 struct pci_bus *bus, int devfn)
371{
372 struct dev_archdata *sd;
373 struct pci_dev *dev;
374 const char *type;
375
376 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
377 if (!dev)
378 return NULL;
379
380 sd = &dev->dev.archdata;
381 sd->iommu = pbm->iommu;
382 sd->stc = &pbm->stc;
383 sd->host_controller = pbm;
384 sd->prom_node = node;
385 sd->op = of_find_device_by_node(node);
386 sd->msi_num = 0xffffffff;
387
388 type = of_get_property(node, "device_type", NULL);
389 if (type == NULL)
390 type = "";
391
392 printk(" create device, devfn: %x, type: %s\n", devfn, type);
393
394 dev->bus = bus;
395 dev->sysdata = node;
396 dev->dev.parent = bus->bridge;
397 dev->dev.bus = &pci_bus_type;
398 dev->devfn = devfn;
399 dev->multifunction = 0; /* maybe a lie? */
400
401 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
402 dev->device = of_getintprop_default(node, "device-id", 0xffff);
403 dev->subsystem_vendor =
404 of_getintprop_default(node, "subsystem-vendor-id", 0);
405 dev->subsystem_device =
406 of_getintprop_default(node, "subsystem-id", 0);
407
408 dev->cfg_size = pci_cfg_space_size(dev);
409
410 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
411 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
412 dev->class = of_getintprop_default(node, "class-code", 0);
413
414 printk(" class: 0x%x\n", dev->class);
415
416 dev->current_state = 4; /* unknown power state */
417 dev->error_state = pci_channel_io_normal;
418
419 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
420 /* a PCI-PCI bridge */
421 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
422 dev->rom_base_reg = PCI_ROM_ADDRESS1;
423 } else if (!strcmp(type, "cardbus")) {
424 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
425 } else {
426 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
427 dev->rom_base_reg = PCI_ROM_ADDRESS;
428
429 dev->irq = sd->op->irqs[0];
430 if (dev->irq == 0xffffffff)
431 dev->irq = PCI_IRQ_NONE;
432 }
433
434 pci_parse_of_addrs(sd->op, node, dev);
435
436 printk(" adding to system ...\n");
437
438 pci_device_add(dev, bus);
439
440 return dev;
441}
442
443static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
444 struct device_node *node,
445 struct pci_bus *bus);
446
447#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
448
449void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
450 struct device_node *node,
451 struct pci_dev *dev)
452{
453 struct pci_bus *bus;
454 const u32 *busrange, *ranges;
455 int len, i;
456 struct resource *res;
457 unsigned int flags;
458 u64 size;
459
460 printk("of_scan_pci_bridge(%s)\n", node->full_name);
461
462 /* parse bus-range property */
463 busrange = of_get_property(node, "bus-range", &len);
464 if (busrange == NULL || len != 8) {
465 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
466 node->full_name);
467 return;
468 }
469 ranges = of_get_property(node, "ranges", &len);
470 if (ranges == NULL) {
471 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
472 node->full_name);
473 return;
474 }
475
476 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
477 if (!bus) {
478 printk(KERN_ERR "Failed to create pci bus for %s\n",
479 node->full_name);
480 return;
481 }
482
483 bus->primary = dev->bus->number;
484 bus->subordinate = busrange[1];
485 bus->bridge_ctl = 0;
486
487 /* parse ranges property */
488 /* PCI #address-cells == 3 and #size-cells == 2 always */
489 res = &dev->resource[PCI_BRIDGE_RESOURCES];
490 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
491 res->flags = 0;
492 bus->resource[i] = res;
493 ++res;
494 }
495 i = 1;
496 for (; len >= 32; len -= 32, ranges += 8) {
497 struct resource *root;
498
499 flags = pci_parse_of_flags(ranges[0]);
500 size = GET_64BIT(ranges, 6);
501 if (flags == 0 || size == 0)
502 continue;
503 if (flags & IORESOURCE_IO) {
504 res = bus->resource[0];
505 if (res->flags) {
506 printk(KERN_ERR "PCI: ignoring extra I/O range"
507 " for bridge %s\n", node->full_name);
508 continue;
509 }
510 root = &pbm->io_space;
511 } else {
512 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
513 printk(KERN_ERR "PCI: too many memory ranges"
514 " for bridge %s\n", node->full_name);
515 continue;
516 }
517 res = bus->resource[i];
518 ++i;
519 root = &pbm->mem_space;
520 }
521
522 res->start = GET_64BIT(ranges, 1);
523 res->end = res->start + size - 1;
524 res->flags = flags;
525
526 /* Another way to implement this would be to add an of_device
527 * layer routine that can calculate a resource for a given
528 * range property value in a PCI device.
529 */
530 pbm->parent->resource_adjust(dev, res, root);
531 }
532 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
533 bus->number);
534 printk(" bus name: %s\n", bus->name);
535
536 pci_of_scan_bus(pbm, node, bus);
537}
538
539static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
540 struct device_node *node,
541 struct pci_bus *bus)
542{
543 struct device_node *child;
544 const u32 *reg;
545 int reglen, devfn;
546 struct pci_dev *dev;
547
548 printk("PCI: scan_bus[%s] bus no %d\n",
549 node->full_name, bus->number);
550
551 child = NULL;
552 while ((child = of_get_next_child(node, child)) != NULL) {
553 printk(" * %s\n", child->full_name);
554 reg = of_get_property(child, "reg", &reglen);
555 if (reg == NULL || reglen < 20)
556 continue;
557 devfn = (reg[0] >> 8) & 0xff;
558
559 /* create a new pci_dev for this device */
560 dev = of_create_pci_dev(pbm, child, bus, devfn);
561 if (!dev)
562 continue;
563 printk("PCI: dev header type: %x\n", dev->hdr_type);
564
565 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
566 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
567 of_scan_pci_bridge(pbm, child, dev);
568 }
569}
570
571static ssize_t
572show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
573{
574 struct pci_dev *pdev;
575 struct device_node *dp;
576
577 pdev = to_pci_dev(dev);
578 dp = pdev->dev.archdata.prom_node;
579
580 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
581}
582
583static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
584
585static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
586{
587 struct pci_dev *dev;
a378fd0e 588 struct pci_bus *child_bus;
a2fb23af
DM		 589 int err;
590
591 list_for_each_entry(dev, &bus->devices, bus_list) {
592 /* we don't really care if we can create this file or
593 * not, but we need to assign the result of the call
594 * or the world will fall under alien invasion and
595 * everybody will be frozen on a spaceship ready to be
596 * eaten on alpha centauri by some green and jelly
597 * humanoid.
598 */
599 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
600 }
a378fd0e
DM		 601 list_for_each_entry(child_bus, &bus->children, node)
602 pci_bus_register_of_sysfs(child_bus);
a2fb23af
DM		 603}
604
605struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
606{
607 struct pci_controller_info *p = pbm->parent;
608 struct device_node *node = pbm->prom_node;
609 struct pci_bus *bus;
610
611 printk("PCI: Scanning PBM %s\n", node->full_name);
612
613 /* XXX parent device? XXX */
614 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
615 if (!bus) {
616 printk(KERN_ERR "Failed to create bus for %s\n",
617 node->full_name);
618 return NULL;
619 }
620 bus->secondary = pbm->pci_first_busno;
621 bus->subordinate = pbm->pci_last_busno;
622
623 bus->resource[0] = &pbm->io_space;
624 bus->resource[1] = &pbm->mem_space;
625
626 pci_of_scan_bus(pbm, node, bus);
627 pci_bus_add_devices(bus);
628 pci_bus_register_of_sysfs(bus);
629
630 return bus;
631}
632
1da177e4
LT		 633static void __init pci_scan_each_controller_bus(void)
634{
635 struct pci_controller_info *p;
636
637 for (p = pci_controller_root; p; p = p->next)
638 p->scan_bus(p);
639}
640
1da177e4
LT		 641extern void power_init(void);
642
643static int __init pcibios_init(void)
644{
645 pci_controller_probe();
646 if (pci_controller_root == NULL)
647 return 0;
648
649 pci_scan_each_controller_bus();
650
1da177e4
LT		 651 isa_init();
652 ebus_init();
1da177e4
LT		 653 power_init();
654
655 return 0;
656}
657
658subsys_initcall(pcibios_init);
659
f6b45da1 660void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 661{
662 struct pci_pbm_info *pbm = pbus->sysdata;
663
664 /* Generic PCI bus probing sets these to point at
665 * &io{port,mem}_resouce which is wrong for us.
666 */
667 pbus->resource[0] = &pbm->io_space;
668 pbus->resource[1] = &pbm->mem_space;
669}
670
085ae41f 671struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 672{
673 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 674 struct resource *root = NULL;
1da177e4 675
085ae41f 676 if (r->flags & IORESOURCE_IO)
1da177e4 677 root = &pbm->io_space;
085ae41f 678 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 679 root = &pbm->mem_space;
680
085ae41f 681 return root;
1da177e4
LT		 682}
683
684void pcibios_update_irq(struct pci_dev *pdev, int irq)
685{
686}
687
688void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 689 resource_size_t size, resource_size_t align)
1da177e4
LT		 690{
691}
692
a2fb23af 693int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 694{
a2fb23af
DM		 695 u16 cmd, oldcmd;
696 int i;
697
698 pci_read_config_word(dev, PCI_COMMAND, &cmd);
699 oldcmd = cmd;
700
701 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
702 struct resource *res = &dev->resource[i];
703
704 /* Only set up the requested stuff */
705 if (!(mask & (1<<i)))
706 continue;
707
708 if (res->flags & IORESOURCE_IO)
709 cmd |= PCI_COMMAND_IO;
710 if (res->flags & IORESOURCE_MEM)
711 cmd |= PCI_COMMAND_MEMORY;
712 }
713
714 if (cmd != oldcmd) {
715 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
716 pci_name(dev), cmd);
717 /* Enable the appropriate bits in the PCI command register. */
718 pci_write_config_word(dev, PCI_COMMAND, cmd);
719 }
1da177e4
LT		 720 return 0;
721}
722
723void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
724 struct resource *res)
725{
726 struct pci_pbm_info *pbm = pdev->bus->sysdata;
727 struct resource zero_res, *root;
728
729 zero_res.start = 0;
730 zero_res.end = 0;
731 zero_res.flags = res->flags;
732
733 if (res->flags & IORESOURCE_IO)
734 root = &pbm->io_space;
735 else
736 root = &pbm->mem_space;
737
738 pbm->parent->resource_adjust(pdev, &zero_res, root);
739
740 region->start = res->start - zero_res.start;
741 region->end = res->end - zero_res.start;
742}
5fdfd42e 743EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 744
745void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
746 struct pci_bus_region *region)
747{
748 struct pci_pbm_info *pbm = pdev->bus->sysdata;
749 struct resource *root;
750
751 res->start = region->start;
752 res->end = region->end;
753
754 if (res->flags & IORESOURCE_IO)
755 root = &pbm->io_space;
756 else
757 root = &pbm->mem_space;
758
759 pbm->parent->resource_adjust(pdev, res, root);
760}
41290c14 761EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 762
f6b45da1 763char * __devinit pcibios_setup(char *str)
1da177e4 764{
1da177e4
LT		 765 return str;
766}
767
768/* Platform support for /proc/bus/pci/X/Y mmap()s. */
769
770/* If the user uses a host-bridge as the PCI device, he may use
771 * this to perform a raw mmap() of the I/O or MEM space behind
772 * that controller.
773 *
774 * This can be useful for execution of x86 PCI bios initialization code
775 * on a PCI card, like the xfree86 int10 stuff does.
776 */
777static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
778 enum pci_mmap_state mmap_state)
779{
a2fb23af 780 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 781 struct pci_controller_info *p;
782 unsigned long space_size, user_offset, user_size;
783
1da177e4
LT		 784 p = pbm->parent;
785 if (p->pbms_same_domain) {
786 unsigned long lowest, highest;
787
788 lowest = ~0UL; highest = 0UL;
789 if (mmap_state == pci_mmap_io) {
790 if (p->pbm_A.io_space.flags) {
791 lowest = p->pbm_A.io_space.start;
792 highest = p->pbm_A.io_space.end + 1;
793 }
794 if (p->pbm_B.io_space.flags) {
795 if (lowest > p->pbm_B.io_space.start)
796 lowest = p->pbm_B.io_space.start;
797 if (highest < p->pbm_B.io_space.end + 1)
798 highest = p->pbm_B.io_space.end + 1;
799 }
800 space_size = highest - lowest;
801 } else {
802 if (p->pbm_A.mem_space.flags) {
803 lowest = p->pbm_A.mem_space.start;
804 highest = p->pbm_A.mem_space.end + 1;
805 }
806 if (p->pbm_B.mem_space.flags) {
807 if (lowest > p->pbm_B.mem_space.start)
808 lowest = p->pbm_B.mem_space.start;
809 if (highest < p->pbm_B.mem_space.end + 1)
810 highest = p->pbm_B.mem_space.end + 1;
811 }
812 space_size = highest - lowest;
813 }
814 } else {
815 if (mmap_state == pci_mmap_io) {
816 space_size = (pbm->io_space.end -
817 pbm->io_space.start) + 1;
818 } else {
819 space_size = (pbm->mem_space.end -
820 pbm->mem_space.start) + 1;
821 }
822 }
823
824 /* Make sure the request is in range. */
825 user_offset = vma->vm_pgoff << PAGE_SHIFT;
826 user_size = vma->vm_end - vma->vm_start;
827
828 if (user_offset >= space_size ||
829 (user_offset + user_size) > space_size)
830 return -EINVAL;
831
832 if (p->pbms_same_domain) {
833 unsigned long lowest = ~0UL;
834
835 if (mmap_state == pci_mmap_io) {
836 if (p->pbm_A.io_space.flags)
837 lowest = p->pbm_A.io_space.start;
838 if (p->pbm_B.io_space.flags &&
839 lowest > p->pbm_B.io_space.start)
840 lowest = p->pbm_B.io_space.start;
841 } else {
842 if (p->pbm_A.mem_space.flags)
843 lowest = p->pbm_A.mem_space.start;
844 if (p->pbm_B.mem_space.flags &&
845 lowest > p->pbm_B.mem_space.start)
846 lowest = p->pbm_B.mem_space.start;
847 }
848 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
849 } else {
850 if (mmap_state == pci_mmap_io) {
851 vma->vm_pgoff = (pbm->io_space.start +
852 user_offset) >> PAGE_SHIFT;
853 } else {
854 vma->vm_pgoff = (pbm->mem_space.start +
855 user_offset) >> PAGE_SHIFT;
856 }
857 }
858
859 return 0;
860}
861
862/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
863 * to the 32-bit pci bus offset for DEV requested by the user.
864 *
865 * Basically, the user finds the base address for his device which he wishes
866 * to mmap. They read the 32-bit value from the config space base register,
867 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
868 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
869 *
870 * Returns negative error code on failure, zero on success.
871 */
872static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
873 enum pci_mmap_state mmap_state)
874{
875 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
876 unsigned long user32 = user_offset & pci_memspace_mask;
877 unsigned long largest_base, this_base, addr32;
878 int i;
879
880 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
881 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
882
883 /* Figure out which base address this is for. */
884 largest_base = 0UL;
885 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
886 struct resource *rp = &dev->resource[i];
887
888 /* Active? */
889 if (!rp->flags)
890 continue;
891
892 /* Same type? */
893 if (i == PCI_ROM_RESOURCE) {
894 if (mmap_state != pci_mmap_mem)
895 continue;
896 } else {
897 if ((mmap_state == pci_mmap_io &&
898 (rp->flags & IORESOURCE_IO) == 0) ||
899 (mmap_state == pci_mmap_mem &&
900 (rp->flags & IORESOURCE_MEM) == 0))
901 continue;
902 }
903
904 this_base = rp->start;
905
906 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
907
908 if (mmap_state == pci_mmap_io)
909 addr32 &= 0xffffff;
910
911 if (addr32 <= user32 && this_base > largest_base)
912 largest_base = this_base;
913 }
914
915 if (largest_base == 0UL)
916 return -EINVAL;
917
918 /* Now construct the final physical address. */
919 if (mmap_state == pci_mmap_io)
920 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
921 else
922 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
923
924 return 0;
925}
926
927/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
928 * mapping.
929 */
930static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
931 enum pci_mmap_state mmap_state)
932{
933 vma->vm_flags |= (VM_IO | VM_RESERVED);
934}
935
936/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
937 * device mapping.
938 */
939static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
940 enum pci_mmap_state mmap_state)
941{
a7a6cac2 942 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 943}
944
945/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
946 * for this architecture. The region in the process to map is described by vm_start
947 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
948 * The pci device structure is provided so that architectures may make mapping
949 * decisions on a per-device or per-bus basis.
950 *
951 * Returns a negative error code on failure, zero on success.
952 */
953int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
954 enum pci_mmap_state mmap_state,
955 int write_combine)
956{
957 int ret;
958
959 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
960 if (ret < 0)
961 return ret;
962
963 __pci_mmap_set_flags(dev, vma, mmap_state);
964 __pci_mmap_set_pgprot(dev, vma, mmap_state);
965
14778d90 966 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 967 ret = io_remap_pfn_range(vma, vma->vm_start,
968 vma->vm_pgoff,
969 vma->vm_end - vma->vm_start,
970 vma->vm_page_prot);
971 if (ret)
972 return ret;
973
1da177e4
LT		 974 return 0;
975}
976
977/* Return the domain nuber for this pci bus */
978
979int pci_domain_nr(struct pci_bus *pbus)
980{
981 struct pci_pbm_info *pbm = pbus->sysdata;
982 int ret;
983
984 if (pbm == NULL || pbm->parent == NULL) {
985 ret = -ENXIO;
986 } else {
987 struct pci_controller_info *p = pbm->parent;
988
989 ret = p->index;
990 if (p->pbms_same_domain == 0)
991 ret = ((ret << 1) +
992 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
993 }
994
995 return ret;
996}
997EXPORT_SYMBOL(pci_domain_nr);
998
35a17eb6
DM		 999#ifdef CONFIG_PCI_MSI
1000int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1001{
a2fb23af 1002 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1003 struct pci_controller_info *p = pbm->parent;
1004 int virt_irq, err;
1005
1006 if (!pbm->msi_num || !p->setup_msi_irq)
1007 return -EINVAL;
1008
1009 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1010 if (err < 0)
1011 return err;
1012
1013 return virt_irq;
1014}
1015
1016void arch_teardown_msi_irq(unsigned int virt_irq)
1017{
abfd336c 1018 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1019 struct pci_dev *pdev = entry->dev;
a2fb23af 1020 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1021 struct pci_controller_info *p = pbm->parent;
1022
1023 if (!pbm->msi_num || !p->setup_msi_irq)
1024 return;
1025
1026 return p->teardown_msi_irq(virt_irq, pdev);
1027}
1028#endif /* !(CONFIG_PCI_MSI) */
1029
f6d0f9ea
DM		 1030struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1031{
a2fb23af 1032 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1033}
1034EXPORT_SYMBOL(pci_device_to_OF_node);
1035
1da177e4 1036#endif /* !(CONFIG_PCI) */
Linux kernel - Deliverables
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