Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | ||
22 | #include <asm/uaccess.h> | |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/irq.h> | |
25 | #include <asm/ebus.h> | |
e87dc350 | 26 | #include <asm/prom.h> |
01f94c4a | 27 | #include <asm/apb.h> |
1da177e4 | 28 | |
1e8a8cc5 DM |
29 | #include "pci_impl.h" |
30 | ||
1da177e4 | 31 | /* List of all PCI controllers found in the system. */ |
34768bc8 | 32 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 33 | |
6c108f12 DM |
34 | /* Each PBM found gets a unique index. */ |
35 | int pci_num_pbms = 0; | |
1da177e4 | 36 | |
1da177e4 LT |
37 | volatile int pci_poke_in_progress; |
38 | volatile int pci_poke_cpu = -1; | |
39 | volatile int pci_poke_faulted; | |
40 | ||
41 | static DEFINE_SPINLOCK(pci_poke_lock); | |
42 | ||
43 | void pci_config_read8(u8 *addr, u8 *ret) | |
44 | { | |
45 | unsigned long flags; | |
46 | u8 byte; | |
47 | ||
48 | spin_lock_irqsave(&pci_poke_lock, flags); | |
49 | pci_poke_cpu = smp_processor_id(); | |
50 | pci_poke_in_progress = 1; | |
51 | pci_poke_faulted = 0; | |
52 | __asm__ __volatile__("membar #Sync\n\t" | |
53 | "lduba [%1] %2, %0\n\t" | |
54 | "membar #Sync" | |
55 | : "=r" (byte) | |
56 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
57 | : "memory"); | |
58 | pci_poke_in_progress = 0; | |
59 | pci_poke_cpu = -1; | |
60 | if (!pci_poke_faulted) | |
61 | *ret = byte; | |
62 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
63 | } | |
64 | ||
65 | void pci_config_read16(u16 *addr, u16 *ret) | |
66 | { | |
67 | unsigned long flags; | |
68 | u16 word; | |
69 | ||
70 | spin_lock_irqsave(&pci_poke_lock, flags); | |
71 | pci_poke_cpu = smp_processor_id(); | |
72 | pci_poke_in_progress = 1; | |
73 | pci_poke_faulted = 0; | |
74 | __asm__ __volatile__("membar #Sync\n\t" | |
75 | "lduha [%1] %2, %0\n\t" | |
76 | "membar #Sync" | |
77 | : "=r" (word) | |
78 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
79 | : "memory"); | |
80 | pci_poke_in_progress = 0; | |
81 | pci_poke_cpu = -1; | |
82 | if (!pci_poke_faulted) | |
83 | *ret = word; | |
84 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
85 | } | |
86 | ||
87 | void pci_config_read32(u32 *addr, u32 *ret) | |
88 | { | |
89 | unsigned long flags; | |
90 | u32 dword; | |
91 | ||
92 | spin_lock_irqsave(&pci_poke_lock, flags); | |
93 | pci_poke_cpu = smp_processor_id(); | |
94 | pci_poke_in_progress = 1; | |
95 | pci_poke_faulted = 0; | |
96 | __asm__ __volatile__("membar #Sync\n\t" | |
97 | "lduwa [%1] %2, %0\n\t" | |
98 | "membar #Sync" | |
99 | : "=r" (dword) | |
100 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
101 | : "memory"); | |
102 | pci_poke_in_progress = 0; | |
103 | pci_poke_cpu = -1; | |
104 | if (!pci_poke_faulted) | |
105 | *ret = dword; | |
106 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
107 | } | |
108 | ||
109 | void pci_config_write8(u8 *addr, u8 val) | |
110 | { | |
111 | unsigned long flags; | |
112 | ||
113 | spin_lock_irqsave(&pci_poke_lock, flags); | |
114 | pci_poke_cpu = smp_processor_id(); | |
115 | pci_poke_in_progress = 1; | |
116 | pci_poke_faulted = 0; | |
117 | __asm__ __volatile__("membar #Sync\n\t" | |
118 | "stba %0, [%1] %2\n\t" | |
119 | "membar #Sync" | |
120 | : /* no outputs */ | |
121 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
122 | : "memory"); | |
123 | pci_poke_in_progress = 0; | |
124 | pci_poke_cpu = -1; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write16(u16 *addr, u16 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stha %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write32(u32 *addr, u32 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stwa %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
167 | extern void sabre_init(struct device_node *, const char *); |
168 | extern void psycho_init(struct device_node *, const char *); | |
169 | extern void schizo_init(struct device_node *, const char *); | |
170 | extern void schizo_plus_init(struct device_node *, const char *); | |
171 | extern void tomatillo_init(struct device_node *, const char *); | |
172 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 173 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
174 | |
175 | static struct { | |
176 | char *model_name; | |
e87dc350 | 177 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
178 | } pci_controller_table[] __initdata = { |
179 | { "SUNW,sabre", sabre_init }, | |
180 | { "pci108e,a000", sabre_init }, | |
181 | { "pci108e,a001", sabre_init }, | |
182 | { "SUNW,psycho", psycho_init }, | |
183 | { "pci108e,8000", psycho_init }, | |
184 | { "SUNW,schizo", schizo_init }, | |
185 | { "pci108e,8001", schizo_init }, | |
186 | { "SUNW,schizo+", schizo_plus_init }, | |
187 | { "pci108e,8002", schizo_plus_init }, | |
188 | { "SUNW,tomatillo", tomatillo_init }, | |
189 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 190 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 191 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 | 192 | }; |
29f139ce | 193 | #define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table) |
1da177e4 | 194 | |
e87dc350 | 195 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
196 | { |
197 | int i; | |
198 | ||
199 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
200 | if (!strncmp(model_name, | |
201 | pci_controller_table[i].model_name, | |
202 | namelen)) { | |
e87dc350 | 203 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
204 | return 1; |
205 | } | |
206 | } | |
1da177e4 LT |
207 | |
208 | return 0; | |
209 | } | |
210 | ||
e87dc350 | 211 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 212 | { |
e87dc350 | 213 | struct device_node *dp; |
1da177e4 LT |
214 | int count = 0; |
215 | ||
e87dc350 DM |
216 | for_each_node_by_name(dp, "pci") { |
217 | struct property *prop; | |
1da177e4 LT |
218 | int len; |
219 | ||
e87dc350 DM |
220 | prop = of_find_property(dp, "model", &len); |
221 | if (!prop) | |
222 | prop = of_find_property(dp, "compatible", &len); | |
223 | ||
224 | if (prop) { | |
225 | const char *model = prop->value; | |
1da177e4 LT |
226 | int item_len = 0; |
227 | ||
228 | /* Our value may be a multi-valued string in the | |
229 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
230 | * only try the first one. |
231 | */ | |
232 | while (model[item_len] && len) { | |
1da177e4 LT |
233 | len--; |
234 | item_len++; | |
235 | } | |
236 | ||
e87dc350 | 237 | if (handler(model, item_len, dp)) |
1da177e4 LT |
238 | count++; |
239 | } | |
1da177e4 LT |
240 | } |
241 | ||
242 | return count; | |
243 | } | |
244 | ||
1da177e4 LT |
245 | /* Find each controller in the system, attach and initialize |
246 | * software state structure for each and link into the | |
34768bc8 | 247 | * pci_pbm_root. Setup the controller enough such |
1da177e4 LT |
248 | * that bus scanning can be done. |
249 | */ | |
250 | static void __init pci_controller_probe(void) | |
251 | { | |
252 | printk("PCI: Probing for controllers.\n"); | |
253 | ||
254 | pci_controller_scan(pci_controller_init); | |
255 | } | |
256 | ||
5840fc66 DM |
257 | static int ofpci_verbose; |
258 | ||
259 | static int __init ofpci_debug(char *str) | |
260 | { | |
261 | int val = 0; | |
262 | ||
263 | get_option(&str, &val); | |
264 | if (val) | |
265 | ofpci_verbose = 1; | |
266 | return 1; | |
267 | } | |
268 | ||
269 | __setup("ofpci_debug=", ofpci_debug); | |
270 | ||
a2fb23af DM |
271 | static unsigned long pci_parse_of_flags(u32 addr0) |
272 | { | |
273 | unsigned long flags = 0; | |
274 | ||
275 | if (addr0 & 0x02000000) { | |
276 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
277 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
278 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
279 | if (addr0 & 0x40000000) | |
280 | flags |= IORESOURCE_PREFETCH | |
281 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
282 | } else if (addr0 & 0x01000000) | |
283 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
284 | return flags; | |
285 | } | |
286 | ||
287 | /* The of_device layer has translated all of the assigned-address properties | |
288 | * into physical address resources, we only have to figure out the register | |
289 | * mapping. | |
290 | */ | |
291 | static void pci_parse_of_addrs(struct of_device *op, | |
292 | struct device_node *node, | |
293 | struct pci_dev *dev) | |
294 | { | |
295 | struct resource *op_res; | |
296 | const u32 *addrs; | |
297 | int proplen; | |
298 | ||
299 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
300 | if (!addrs) | |
301 | return; | |
5840fc66 DM |
302 | if (ofpci_verbose) |
303 | printk(" parse addresses (%d bytes) @ %p\n", | |
304 | proplen, addrs); | |
a2fb23af DM |
305 | op_res = &op->resource[0]; |
306 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
307 | struct resource *res; | |
308 | unsigned long flags; | |
309 | int i; | |
310 | ||
311 | flags = pci_parse_of_flags(addrs[0]); | |
312 | if (!flags) | |
313 | continue; | |
314 | i = addrs[0] & 0xff; | |
5840fc66 DM |
315 | if (ofpci_verbose) |
316 | printk(" start: %lx, end: %lx, i: %x\n", | |
317 | op_res->start, op_res->end, i); | |
a2fb23af DM |
318 | |
319 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
320 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
321 | } else if (i == dev->rom_base_reg) { | |
322 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
323 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
324 | } else { | |
325 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
326 | continue; | |
327 | } | |
328 | res->start = op_res->start; | |
329 | res->end = op_res->end; | |
330 | res->flags = flags; | |
331 | res->name = pci_name(dev); | |
332 | } | |
333 | } | |
334 | ||
335 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
336 | struct device_node *node, | |
c26d3c01 | 337 | struct pci_bus *bus, int devfn) |
a2fb23af DM |
338 | { |
339 | struct dev_archdata *sd; | |
340 | struct pci_dev *dev; | |
341 | const char *type; | |
01f94c4a | 342 | u32 class; |
a2fb23af | 343 | |
26e6385f | 344 | dev = alloc_pci_dev(); |
a2fb23af DM |
345 | if (!dev) |
346 | return NULL; | |
347 | ||
348 | sd = &dev->dev.archdata; | |
349 | sd->iommu = pbm->iommu; | |
350 | sd->stc = &pbm->stc; | |
351 | sd->host_controller = pbm; | |
352 | sd->prom_node = node; | |
353 | sd->op = of_find_device_by_node(node); | |
c1b1a5f1 | 354 | sd->numa_node = pbm->numa_node; |
a2fb23af | 355 | |
ad7ad57c DM |
356 | sd = &sd->op->dev.archdata; |
357 | sd->iommu = pbm->iommu; | |
358 | sd->stc = &pbm->stc; | |
c1b1a5f1 | 359 | sd->numa_node = pbm->numa_node; |
ad7ad57c | 360 | |
a2fb23af DM |
361 | type = of_get_property(node, "device_type", NULL); |
362 | if (type == NULL) | |
363 | type = ""; | |
364 | ||
5840fc66 DM |
365 | if (ofpci_verbose) |
366 | printk(" create device, devfn: %x, type: %s\n", | |
367 | devfn, type); | |
a2fb23af DM |
368 | |
369 | dev->bus = bus; | |
370 | dev->sysdata = node; | |
371 | dev->dev.parent = bus->bridge; | |
372 | dev->dev.bus = &pci_bus_type; | |
373 | dev->devfn = devfn; | |
374 | dev->multifunction = 0; /* maybe a lie? */ | |
375 | ||
c26d3c01 DM |
376 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); |
377 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
378 | dev->subsystem_vendor = | |
379 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
380 | dev->subsystem_device = | |
381 | of_getintprop_default(node, "subsystem-id", 0); | |
382 | ||
383 | dev->cfg_size = pci_cfg_space_size(dev); | |
384 | ||
385 | /* We can't actually use the firmware value, we have | |
386 | * to read what is in the register right now. One | |
387 | * reason is that in the case of IDE interfaces the | |
388 | * firmware can sample the value before the the IDE | |
389 | * interface is programmed into native mode. | |
390 | */ | |
391 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
392 | dev->class = class >> 8; | |
393 | dev->revision = class & 0xff; | |
394 | ||
2222c313 | 395 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), |
c26d3c01 | 396 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
28f57e77 | 397 | |
5840fc66 DM |
398 | if (ofpci_verbose) |
399 | printk(" class: 0x%x device name: %s\n", | |
400 | dev->class, pci_name(dev)); | |
a2fb23af | 401 | |
861fe906 DM |
402 | /* I have seen IDE devices which will not respond to |
403 | * the bmdma simplex check reads if bus mastering is | |
404 | * disabled. | |
405 | */ | |
406 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
407 | pci_set_master(dev); | |
408 | ||
a2fb23af DM |
409 | dev->current_state = 4; /* unknown power state */ |
410 | dev->error_state = pci_channel_io_normal; | |
411 | ||
c26d3c01 DM |
412 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
413 | /* a PCI-PCI bridge */ | |
a2fb23af DM |
414 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
415 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
c26d3c01 DM |
416 | } else if (!strcmp(type, "cardbus")) { |
417 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
a2fb23af | 418 | } else { |
c26d3c01 DM |
419 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; |
420 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 421 | |
c26d3c01 DM |
422 | dev->irq = sd->op->irqs[0]; |
423 | if (dev->irq == 0xffffffff) | |
424 | dev->irq = PCI_IRQ_NONE; | |
a2fb23af | 425 | } |
c26d3c01 | 426 | |
a2fb23af DM |
427 | pci_parse_of_addrs(sd->op, node, dev); |
428 | ||
5840fc66 DM |
429 | if (ofpci_verbose) |
430 | printk(" adding to system ...\n"); | |
a2fb23af DM |
431 | |
432 | pci_device_add(dev, bus); | |
433 | ||
434 | return dev; | |
435 | } | |
436 | ||
a6009dda | 437 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
438 | { |
439 | u32 idx, first, last; | |
440 | ||
441 | first = 8; | |
442 | last = 0; | |
443 | for (idx = 0; idx < 8; idx++) { | |
444 | if ((map & (1 << idx)) != 0) { | |
445 | if (first > idx) | |
446 | first = idx; | |
447 | if (last < idx) | |
448 | last = idx; | |
449 | } | |
450 | } | |
451 | ||
452 | *first_p = first; | |
453 | *last_p = last; | |
454 | } | |
455 | ||
f16537ba DM |
456 | static void pci_resource_adjust(struct resource *res, |
457 | struct resource *root) | |
0bae5f81 DM |
458 | { |
459 | res->start += root->start; | |
460 | res->end += root->start; | |
461 | } | |
462 | ||
8c2786cf DM |
463 | /* For PCI bus devices which lack a 'ranges' property we interrogate |
464 | * the config space values to set the resources, just like the generic | |
465 | * Linux PCI probing code does. | |
466 | */ | |
467 | static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, | |
468 | struct pci_bus *bus, | |
469 | struct pci_pbm_info *pbm) | |
470 | { | |
471 | struct resource *res; | |
472 | u8 io_base_lo, io_limit_lo; | |
473 | u16 mem_base_lo, mem_limit_lo; | |
474 | unsigned long base, limit; | |
475 | ||
476 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
477 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
478 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
479 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
480 | ||
481 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
482 | u16 io_base_hi, io_limit_hi; | |
483 | ||
484 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
485 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
486 | base |= (io_base_hi << 16); | |
487 | limit |= (io_limit_hi << 16); | |
488 | } | |
489 | ||
490 | res = bus->resource[0]; | |
491 | if (base <= limit) { | |
492 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
493 | if (!res->start) | |
494 | res->start = base; | |
495 | if (!res->end) | |
496 | res->end = limit + 0xfff; | |
497 | pci_resource_adjust(res, &pbm->io_space); | |
498 | } | |
499 | ||
500 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
501 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
502 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
503 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
504 | ||
505 | res = bus->resource[1]; | |
506 | if (base <= limit) { | |
507 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
508 | IORESOURCE_MEM); | |
509 | res->start = base; | |
510 | res->end = limit + 0xfffff; | |
511 | pci_resource_adjust(res, &pbm->mem_space); | |
512 | } | |
513 | ||
514 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
515 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
516 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
517 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
518 | ||
519 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
520 | u32 mem_base_hi, mem_limit_hi; | |
521 | ||
522 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
523 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
524 | ||
525 | /* | |
526 | * Some bridges set the base > limit by default, and some | |
527 | * (broken) BIOSes do not initialize them. If we find | |
528 | * this, just assume they are not being used. | |
529 | */ | |
530 | if (mem_base_hi <= mem_limit_hi) { | |
531 | base |= ((long) mem_base_hi) << 32; | |
532 | limit |= ((long) mem_limit_hi) << 32; | |
533 | } | |
534 | } | |
535 | ||
536 | res = bus->resource[2]; | |
537 | if (base <= limit) { | |
538 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
539 | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
540 | res->start = base; | |
541 | res->end = limit + 0xfffff; | |
542 | pci_resource_adjust(res, &pbm->mem_space); | |
543 | } | |
544 | } | |
545 | ||
01f94c4a DM |
546 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
547 | * a proper 'ranges' property. | |
548 | */ | |
a6009dda DM |
549 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
550 | struct pci_bus *bus, | |
551 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
552 | { |
553 | struct resource *res; | |
554 | u32 first, last; | |
555 | u8 map; | |
556 | ||
557 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
558 | apb_calc_first_last(map, &first, &last); | |
559 | res = bus->resource[0]; | |
560 | res->start = (first << 21); | |
561 | res->end = (last << 21) + ((1 << 21) - 1); | |
562 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 563 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
564 | |
565 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
566 | apb_calc_first_last(map, &first, &last); | |
567 | res = bus->resource[1]; | |
568 | res->start = (first << 21); | |
569 | res->end = (last << 21) + ((1 << 21) - 1); | |
570 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 571 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
572 | } |
573 | ||
a6009dda DM |
574 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
575 | struct device_node *node, | |
576 | struct pci_bus *bus); | |
a2fb23af DM |
577 | |
578 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
579 | ||
a6009dda DM |
580 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
581 | struct device_node *node, | |
582 | struct pci_dev *dev) | |
a2fb23af DM |
583 | { |
584 | struct pci_bus *bus; | |
585 | const u32 *busrange, *ranges; | |
01f94c4a | 586 | int len, i, simba; |
a2fb23af DM |
587 | struct resource *res; |
588 | unsigned int flags; | |
589 | u64 size; | |
590 | ||
5840fc66 DM |
591 | if (ofpci_verbose) |
592 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
593 | |
594 | /* parse bus-range property */ | |
595 | busrange = of_get_property(node, "bus-range", &len); | |
596 | if (busrange == NULL || len != 8) { | |
597 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
598 | node->full_name); | |
599 | return; | |
600 | } | |
601 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 602 | simba = 0; |
a2fb23af | 603 | if (ranges == NULL) { |
a165b420 | 604 | const char *model = of_get_property(node, "model", NULL); |
8c2786cf | 605 | if (model && !strcmp(model, "SUNW,simba")) |
01f94c4a | 606 | simba = 1; |
a2fb23af DM |
607 | } |
608 | ||
609 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
610 | if (!bus) { | |
611 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
612 | node->full_name); | |
613 | return; | |
614 | } | |
615 | ||
616 | bus->primary = dev->bus->number; | |
617 | bus->subordinate = busrange[1]; | |
618 | bus->bridge_ctl = 0; | |
619 | ||
01f94c4a | 620 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
621 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
622 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
623 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
624 | res->flags = 0; | |
625 | bus->resource[i] = res; | |
626 | ++res; | |
627 | } | |
01f94c4a DM |
628 | if (simba) { |
629 | apb_fake_ranges(dev, bus, pbm); | |
8c2786cf DM |
630 | goto after_ranges; |
631 | } else if (ranges == NULL) { | |
632 | pci_cfg_fake_ranges(dev, bus, pbm); | |
633 | goto after_ranges; | |
01f94c4a | 634 | } |
a2fb23af DM |
635 | i = 1; |
636 | for (; len >= 32; len -= 32, ranges += 8) { | |
637 | struct resource *root; | |
638 | ||
639 | flags = pci_parse_of_flags(ranges[0]); | |
640 | size = GET_64BIT(ranges, 6); | |
641 | if (flags == 0 || size == 0) | |
642 | continue; | |
643 | if (flags & IORESOURCE_IO) { | |
644 | res = bus->resource[0]; | |
645 | if (res->flags) { | |
646 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
647 | " for bridge %s\n", node->full_name); | |
648 | continue; | |
649 | } | |
650 | root = &pbm->io_space; | |
651 | } else { | |
652 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
653 | printk(KERN_ERR "PCI: too many memory ranges" | |
654 | " for bridge %s\n", node->full_name); | |
655 | continue; | |
656 | } | |
657 | res = bus->resource[i]; | |
658 | ++i; | |
659 | root = &pbm->mem_space; | |
660 | } | |
661 | ||
662 | res->start = GET_64BIT(ranges, 1); | |
663 | res->end = res->start + size - 1; | |
664 | res->flags = flags; | |
665 | ||
666 | /* Another way to implement this would be to add an of_device | |
667 | * layer routine that can calculate a resource for a given | |
668 | * range property value in a PCI device. | |
669 | */ | |
0bae5f81 | 670 | pci_resource_adjust(res, root); |
a2fb23af | 671 | } |
8c2786cf | 672 | after_ranges: |
a2fb23af DM |
673 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
674 | bus->number); | |
5840fc66 DM |
675 | if (ofpci_verbose) |
676 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
677 | |
678 | pci_of_scan_bus(pbm, node, bus); | |
679 | } | |
680 | ||
a6009dda DM |
681 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
682 | struct device_node *node, | |
683 | struct pci_bus *bus) | |
a2fb23af DM |
684 | { |
685 | struct device_node *child; | |
686 | const u32 *reg; | |
2cc7345f | 687 | int reglen, devfn, prev_devfn; |
a2fb23af DM |
688 | struct pci_dev *dev; |
689 | ||
5840fc66 DM |
690 | if (ofpci_verbose) |
691 | printk("PCI: scan_bus[%s] bus no %d\n", | |
692 | node->full_name, bus->number); | |
a2fb23af DM |
693 | |
694 | child = NULL; | |
2cc7345f | 695 | prev_devfn = -1; |
a2fb23af | 696 | while ((child = of_get_next_child(node, child)) != NULL) { |
5840fc66 DM |
697 | if (ofpci_verbose) |
698 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
699 | reg = of_get_property(child, "reg", ®len); |
700 | if (reg == NULL || reglen < 20) | |
701 | continue; | |
2cc7345f | 702 | |
a2fb23af DM |
703 | devfn = (reg[0] >> 8) & 0xff; |
704 | ||
2cc7345f DM |
705 | /* This is a workaround for some device trees |
706 | * which list PCI devices twice. On the V100 | |
707 | * for example, device number 3 is listed twice. | |
708 | * Once as "pm" and once again as "lomp". | |
709 | */ | |
710 | if (devfn == prev_devfn) | |
711 | continue; | |
712 | prev_devfn = devfn; | |
713 | ||
a2fb23af | 714 | /* create a new pci_dev for this device */ |
c26d3c01 | 715 | dev = of_create_pci_dev(pbm, child, bus, devfn); |
a2fb23af DM |
716 | if (!dev) |
717 | continue; | |
5840fc66 DM |
718 | if (ofpci_verbose) |
719 | printk("PCI: dev header type: %x\n", | |
720 | dev->hdr_type); | |
a2fb23af DM |
721 | |
722 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
723 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
724 | of_scan_pci_bridge(pbm, child, dev); | |
725 | } | |
726 | } | |
727 | ||
728 | static ssize_t | |
729 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
730 | { | |
731 | struct pci_dev *pdev; | |
732 | struct device_node *dp; | |
733 | ||
734 | pdev = to_pci_dev(dev); | |
735 | dp = pdev->dev.archdata.prom_node; | |
736 | ||
737 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
738 | } | |
739 | ||
740 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
741 | ||
742 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
743 | { | |
744 | struct pci_dev *dev; | |
a378fd0e | 745 | struct pci_bus *child_bus; |
a2fb23af DM |
746 | int err; |
747 | ||
748 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
749 | /* we don't really care if we can create this file or | |
750 | * not, but we need to assign the result of the call | |
751 | * or the world will fall under alien invasion and | |
752 | * everybody will be frozen on a spaceship ready to be | |
753 | * eaten on alpha centauri by some green and jelly | |
754 | * humanoid. | |
755 | */ | |
756 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
757 | } | |
a378fd0e DM |
758 | list_for_each_entry(child_bus, &bus->children, node) |
759 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
760 | } |
761 | ||
a6009dda | 762 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) |
a2fb23af | 763 | { |
a2fb23af DM |
764 | struct device_node *node = pbm->prom_node; |
765 | struct pci_bus *bus; | |
766 | ||
767 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
768 | ||
769 | /* XXX parent device? XXX */ | |
f1cd8de2 | 770 | bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
771 | if (!bus) { |
772 | printk(KERN_ERR "Failed to create bus for %s\n", | |
773 | node->full_name); | |
774 | return NULL; | |
775 | } | |
776 | bus->secondary = pbm->pci_first_busno; | |
777 | bus->subordinate = pbm->pci_last_busno; | |
778 | ||
779 | bus->resource[0] = &pbm->io_space; | |
780 | bus->resource[1] = &pbm->mem_space; | |
781 | ||
782 | pci_of_scan_bus(pbm, node, bus); | |
783 | pci_bus_add_devices(bus); | |
784 | pci_bus_register_of_sysfs(bus); | |
785 | ||
786 | return bus; | |
787 | } | |
788 | ||
1da177e4 LT |
789 | static void __init pci_scan_each_controller_bus(void) |
790 | { | |
34768bc8 | 791 | struct pci_pbm_info *pbm; |
1da177e4 | 792 | |
34768bc8 DM |
793 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) |
794 | pbm->scan_bus(pbm); | |
1da177e4 LT |
795 | } |
796 | ||
1da177e4 LT |
797 | extern void power_init(void); |
798 | ||
799 | static int __init pcibios_init(void) | |
800 | { | |
801 | pci_controller_probe(); | |
34768bc8 | 802 | if (pci_pbm_root == NULL) |
1da177e4 LT |
803 | return 0; |
804 | ||
805 | pci_scan_each_controller_bus(); | |
806 | ||
1da177e4 | 807 | ebus_init(); |
1da177e4 LT |
808 | power_init(); |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | subsys_initcall(pcibios_init); | |
814 | ||
f6b45da1 | 815 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
816 | { |
817 | struct pci_pbm_info *pbm = pbus->sysdata; | |
818 | ||
819 | /* Generic PCI bus probing sets these to point at | |
820 | * &io{port,mem}_resouce which is wrong for us. | |
821 | */ | |
822 | pbus->resource[0] = &pbm->io_space; | |
823 | pbus->resource[1] = &pbm->mem_space; | |
824 | } | |
825 | ||
085ae41f | 826 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
827 | { |
828 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 829 | struct resource *root = NULL; |
1da177e4 | 830 | |
085ae41f | 831 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 832 | root = &pbm->io_space; |
085ae41f | 833 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
834 | root = &pbm->mem_space; |
835 | ||
085ae41f | 836 | return root; |
1da177e4 LT |
837 | } |
838 | ||
839 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
840 | { | |
841 | } | |
842 | ||
843 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 844 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
845 | { |
846 | } | |
847 | ||
a2fb23af | 848 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 849 | { |
a2fb23af DM |
850 | u16 cmd, oldcmd; |
851 | int i; | |
852 | ||
853 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
854 | oldcmd = cmd; | |
855 | ||
856 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
857 | struct resource *res = &dev->resource[i]; | |
858 | ||
859 | /* Only set up the requested stuff */ | |
860 | if (!(mask & (1<<i))) | |
861 | continue; | |
862 | ||
863 | if (res->flags & IORESOURCE_IO) | |
864 | cmd |= PCI_COMMAND_IO; | |
865 | if (res->flags & IORESOURCE_MEM) | |
866 | cmd |= PCI_COMMAND_MEMORY; | |
867 | } | |
868 | ||
869 | if (cmd != oldcmd) { | |
870 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
871 | pci_name(dev), cmd); | |
872 | /* Enable the appropriate bits in the PCI command register. */ | |
873 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
874 | } | |
1da177e4 LT |
875 | return 0; |
876 | } | |
877 | ||
878 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
879 | struct resource *res) | |
880 | { | |
881 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
882 | struct resource zero_res, *root; | |
883 | ||
884 | zero_res.start = 0; | |
885 | zero_res.end = 0; | |
886 | zero_res.flags = res->flags; | |
887 | ||
888 | if (res->flags & IORESOURCE_IO) | |
889 | root = &pbm->io_space; | |
890 | else | |
891 | root = &pbm->mem_space; | |
892 | ||
0bae5f81 | 893 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
894 | |
895 | region->start = res->start - zero_res.start; | |
896 | region->end = res->end - zero_res.start; | |
897 | } | |
5fdfd42e | 898 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
899 | |
900 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
901 | struct pci_bus_region *region) | |
902 | { | |
903 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
904 | struct resource *root; | |
905 | ||
906 | res->start = region->start; | |
907 | res->end = region->end; | |
908 | ||
909 | if (res->flags & IORESOURCE_IO) | |
910 | root = &pbm->io_space; | |
911 | else | |
912 | root = &pbm->mem_space; | |
913 | ||
0bae5f81 | 914 | pci_resource_adjust(res, root); |
1da177e4 | 915 | } |
41290c14 | 916 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 917 | |
f6b45da1 | 918 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 919 | { |
1da177e4 LT |
920 | return str; |
921 | } | |
922 | ||
923 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
924 | ||
925 | /* If the user uses a host-bridge as the PCI device, he may use | |
926 | * this to perform a raw mmap() of the I/O or MEM space behind | |
927 | * that controller. | |
928 | * | |
929 | * This can be useful for execution of x86 PCI bios initialization code | |
930 | * on a PCI card, like the xfree86 int10 stuff does. | |
931 | */ | |
932 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
933 | enum pci_mmap_state mmap_state) | |
934 | { | |
a2fb23af | 935 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
936 | unsigned long space_size, user_offset, user_size; |
937 | ||
3875c5c0 DM |
938 | if (mmap_state == pci_mmap_io) { |
939 | space_size = (pbm->io_space.end - | |
940 | pbm->io_space.start) + 1; | |
1da177e4 | 941 | } else { |
3875c5c0 DM |
942 | space_size = (pbm->mem_space.end - |
943 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
944 | } |
945 | ||
946 | /* Make sure the request is in range. */ | |
947 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
948 | user_size = vma->vm_end - vma->vm_start; | |
949 | ||
950 | if (user_offset >= space_size || | |
951 | (user_offset + user_size) > space_size) | |
952 | return -EINVAL; | |
953 | ||
3875c5c0 DM |
954 | if (mmap_state == pci_mmap_io) { |
955 | vma->vm_pgoff = (pbm->io_space.start + | |
956 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 957 | } else { |
3875c5c0 DM |
958 | vma->vm_pgoff = (pbm->mem_space.start + |
959 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
960 | } |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
bbe0b5eb DM |
965 | /* Adjust vm_pgoff of VMA such that it is the physical page offset |
966 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
1da177e4 LT |
967 | * |
968 | * Basically, the user finds the base address for his device which he wishes | |
969 | * to mmap. They read the 32-bit value from the config space base register, | |
970 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
971 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
972 | * | |
973 | * Returns negative error code on failure, zero on success. | |
974 | */ | |
bbe0b5eb DM |
975 | static int __pci_mmap_make_offset(struct pci_dev *pdev, |
976 | struct vm_area_struct *vma, | |
1da177e4 LT |
977 | enum pci_mmap_state mmap_state) |
978 | { | |
bbe0b5eb DM |
979 | unsigned long user_paddr, user_size; |
980 | int i, err; | |
1da177e4 | 981 | |
bbe0b5eb DM |
982 | /* First compute the physical address in vma->vm_pgoff, |
983 | * making sure the user offset is within range in the | |
984 | * appropriate PCI space. | |
985 | */ | |
986 | err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); | |
987 | if (err) | |
988 | return err; | |
989 | ||
990 | /* If this is a mapping on a host bridge, any address | |
991 | * is OK. | |
992 | */ | |
993 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
994 | return err; | |
995 | ||
996 | /* Otherwise make sure it's in the range for one of the | |
997 | * device's resources. | |
998 | */ | |
999 | user_paddr = vma->vm_pgoff << PAGE_SHIFT; | |
1000 | user_size = vma->vm_end - vma->vm_start; | |
1da177e4 | 1001 | |
1da177e4 | 1002 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
bbe0b5eb | 1003 | struct resource *rp = &pdev->resource[i]; |
1da177e4 LT |
1004 | |
1005 | /* Active? */ | |
1006 | if (!rp->flags) | |
1007 | continue; | |
1008 | ||
1009 | /* Same type? */ | |
1010 | if (i == PCI_ROM_RESOURCE) { | |
1011 | if (mmap_state != pci_mmap_mem) | |
1012 | continue; | |
1013 | } else { | |
1014 | if ((mmap_state == pci_mmap_io && | |
1015 | (rp->flags & IORESOURCE_IO) == 0) || | |
1016 | (mmap_state == pci_mmap_mem && | |
1017 | (rp->flags & IORESOURCE_MEM) == 0)) | |
1018 | continue; | |
1019 | } | |
1020 | ||
bbe0b5eb DM |
1021 | if ((rp->start <= user_paddr) && |
1022 | (user_paddr + user_size) <= (rp->end + 1UL)) | |
1023 | break; | |
1da177e4 LT |
1024 | } |
1025 | ||
bbe0b5eb | 1026 | if (i > PCI_ROM_RESOURCE) |
1da177e4 LT |
1027 | return -EINVAL; |
1028 | ||
1da177e4 LT |
1029 | return 0; |
1030 | } | |
1031 | ||
1032 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1033 | * mapping. | |
1034 | */ | |
1035 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1036 | enum pci_mmap_state mmap_state) | |
1037 | { | |
1038 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1039 | } | |
1040 | ||
1041 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1042 | * device mapping. | |
1043 | */ | |
1044 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1045 | enum pci_mmap_state mmap_state) | |
1046 | { | |
a7a6cac2 | 1047 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1048 | } |
1049 | ||
1050 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1051 | * for this architecture. The region in the process to map is described by vm_start | |
1052 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1053 | * The pci device structure is provided so that architectures may make mapping | |
1054 | * decisions on a per-device or per-bus basis. | |
1055 | * | |
1056 | * Returns a negative error code on failure, zero on success. | |
1057 | */ | |
1058 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1059 | enum pci_mmap_state mmap_state, | |
1060 | int write_combine) | |
1061 | { | |
1062 | int ret; | |
1063 | ||
1064 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1065 | if (ret < 0) | |
1066 | return ret; | |
1067 | ||
1068 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1069 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1070 | ||
14778d90 | 1071 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1072 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1073 | vma->vm_pgoff, | |
1074 | vma->vm_end - vma->vm_start, | |
1075 | vma->vm_page_prot); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
1da177e4 LT |
1079 | return 0; |
1080 | } | |
1081 | ||
c1b1a5f1 DM |
1082 | #ifdef CONFIG_NUMA |
1083 | int pcibus_to_node(struct pci_bus *pbus) | |
1084 | { | |
1085 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1086 | ||
1087 | return pbm->numa_node; | |
1088 | } | |
1089 | EXPORT_SYMBOL(pcibus_to_node); | |
1090 | #endif | |
1091 | ||
1da177e4 LT |
1092 | /* Return the domain nuber for this pci bus */ |
1093 | ||
1094 | int pci_domain_nr(struct pci_bus *pbus) | |
1095 | { | |
1096 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1097 | int ret; | |
1098 | ||
1099 | if (pbm == NULL || pbm->parent == NULL) { | |
1100 | ret = -ENXIO; | |
1101 | } else { | |
6c108f12 | 1102 | ret = pbm->index; |
1da177e4 LT |
1103 | } |
1104 | ||
1105 | return ret; | |
1106 | } | |
1107 | EXPORT_SYMBOL(pci_domain_nr); | |
1108 | ||
35a17eb6 DM |
1109 | #ifdef CONFIG_PCI_MSI |
1110 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1111 | { | |
a2fb23af | 1112 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
e9870c4c | 1113 | int virt_irq; |
35a17eb6 | 1114 | |
e9870c4c | 1115 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
1116 | return -EINVAL; |
1117 | ||
e9870c4c | 1118 | return pbm->setup_msi_irq(&virt_irq, pdev, desc); |
35a17eb6 DM |
1119 | } |
1120 | ||
1121 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1122 | { | |
abfd336c | 1123 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1124 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1125 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 1126 | |
e9870c4c | 1127 | if (!pbm->teardown_msi_irq) |
35a17eb6 DM |
1128 | return; |
1129 | ||
e9870c4c | 1130 | return pbm->teardown_msi_irq(virt_irq, pdev); |
35a17eb6 DM |
1131 | } |
1132 | #endif /* !(CONFIG_PCI_MSI) */ | |
1133 | ||
f6d0f9ea DM |
1134 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1135 | { | |
a2fb23af | 1136 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1137 | } |
1138 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1139 | ||
ad7ad57c DM |
1140 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
1141 | { | |
1142 | struct pci_dev *ali_isa_bridge; | |
1143 | u8 val; | |
1144 | ||
1145 | /* ALI sound chips generate 31-bits of DMA, a special register | |
1146 | * determines what bit 31 is emitted as. | |
1147 | */ | |
1148 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
1149 | PCI_DEVICE_ID_AL_M1533, | |
1150 | NULL); | |
1151 | ||
1152 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
1153 | if (set_bit) | |
1154 | val |= 0x01; | |
1155 | else | |
1156 | val &= ~0x01; | |
1157 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
1158 | pci_dev_put(ali_isa_bridge); | |
1159 | } | |
1160 | ||
1161 | int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) | |
1162 | { | |
1163 | u64 dma_addr_mask; | |
1164 | ||
1165 | if (pdev == NULL) { | |
1166 | dma_addr_mask = 0xffffffff; | |
1167 | } else { | |
1168 | struct iommu *iommu = pdev->dev.archdata.iommu; | |
1169 | ||
1170 | dma_addr_mask = iommu->dma_addr_mask; | |
1171 | ||
1172 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
1173 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
1174 | device_mask == 0x7fffffff) { | |
1175 | ali_sound_dma_hack(pdev, | |
1176 | (dma_addr_mask & 0x80000000) != 0); | |
1177 | return 1; | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | if (device_mask >= (1UL << 32UL)) | |
1182 | return 0; | |
1183 | ||
1184 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
1185 | } | |
1186 | ||
bcea1db1 DM |
1187 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
1188 | const struct resource *rp, resource_size_t *start, | |
1189 | resource_size_t *end) | |
1190 | { | |
1191 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | |
1192 | unsigned long offset; | |
1193 | ||
1194 | if (rp->flags & IORESOURCE_IO) | |
1195 | offset = pbm->io_space.start; | |
1196 | else | |
1197 | offset = pbm->mem_space.start; | |
1198 | ||
1199 | *start = rp->start - offset; | |
1200 | *end = rp->end - offset; | |
1201 | } |