[deliverable/linux.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define X86_PMC_MAX_GENERIC				       32
#define X86_PMC_MAX_FIXED					3

#define X86_PMC_IDX_GENERIC				        0
#define X86_PMC_IDX_FIXED				       32
#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		      0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX			 0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED			 6

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:4;
		unsigned int reserved:28;
	} split;
	unsigned int full;
};


/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

/* IbsFetchCtl bits/masks */
#define IBS_FETCH_RAND_EN		(1ULL<<57)
#define IBS_FETCH_VAL			(1ULL<<49)
#define IBS_FETCH_ENABLE		(1ULL<<48)
#define IBS_FETCH_CNT			0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT		0x0000FFFFULL

/* IbsOpCtl bits */
#define IBS_OP_CNT_CTL			(1ULL<<19)
#define IBS_OP_VAL			(1ULL<<18)
#define IBS_OP_ENABLE			(1ULL<<17)
#define IBS_OP_MAX_CNT			0x0000FFFFULL

#ifdef CONFIG_PERF_EVENTS
extern void init_hw_perf_events(void);
extern void perf_events_lapic_init(void);

#define PERF_EVENT_INDEX_OFFSET			0

/*
 * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 * This flag is otherwise unused and ABI specified to be 0, so nobody should
 * care what we do with it.
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#else
static inline void init_hw_perf_events(void)		{ }
static inline void perf_events_lapic_init(void)	{ }
#endif

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
a072738e	8	#define X86_PMC_MAX_GENERIC 32
eb2b8618 IM	9	#define X86_PMC_MAX_FIXED 3
eb2b8618 IM	10
862a1a5f IM	11	#define X86_PMC_IDX_GENERIC 0
	12	#define X86_PMC_IDX_FIXED 32
	13	#define X86_PMC_IDX_MAX 64
	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
a098f448 RR	21	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	22	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	23	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	25	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
	26	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	27	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	28	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	29	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	30	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	31
	32	#define AMD64_EVENTSEL_EVENT \
	33	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	34	#define INTEL_ARCH_EVENT_MASK \
	35	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	36
	37	#define X86_RAW_EVENT_MASK \
	38	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	39	ARCH_PERFMON_EVENTSEL_UMASK \| \
	40	ARCH_PERFMON_EVENTSEL_EDGE \| \
	41	ARCH_PERFMON_EVENTSEL_INV \| \
	42	ARCH_PERFMON_EVENTSEL_CMASK)
	43	#define AMD64_RAW_EVENT_MASK \
	44	(X86_RAW_EVENT_MASK \| \
	45	AMD64_EVENTSEL_EVENT)
04a705df	46
241771ef IM	47	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef IM	48	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
04a705df	49	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	50	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	51	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
	52
	53	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
003a46cf	54
eb2b8618 IM	55	/*
	56	* Intel "Architectural Performance Monitoring" CPUID
	57	* detection/enumeration details:
	58	*/
003a46cf TG	59	union cpuid10_eax {
	60	struct {
	61	unsigned int version_id:8;
948b1bb8	62	unsigned int num_counters:8;
003a46cf TG	63	unsigned int bit_width:8;
	64	unsigned int mask_length:8;
	65	} split;
	66	unsigned int full;
	67	};
	68
703e937c IM	69	union cpuid10_edx {
703e937c IM	70	struct {
948b1bb8	71	unsigned int num_counters_fixed:4;
703e937c IM	72	unsigned int reserved:28;
	73	} split;
	74	unsigned int full;
	75	};
	76
	77
	78	/*
cdd6c482	79	* Fixed-purpose performance events:
703e937c IM	80	*/
703e937c IM	81
862a1a5f IM	82	/*
	83	* All 3 fixed-mode PMCs are configured via this single MSR:
	84	*/
	85	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
	86
	87	/*
	88	* The counts are available in three separate MSRs:
	89	*/
	90
703e937c IM	91	/* Instr_Retired.Any: */
703e937c IM	92	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
2f18d1e8	93	#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
703e937c IM	94
	95	/* CPU_CLK_Unhalted.Core: */
	96	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
2f18d1e8	97	#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
703e937c IM	98
	99	/* CPU_CLK_Unhalted.Ref: */
	100	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
2f18d1e8	101	#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
703e937c	102
30dd568c MM	103	/*
	104	* We model BTS tracing as another fixed-mode PMC.
	105	*
cdd6c482 IM	106	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	107	* values are used by actual fixed events and higher values are used
30dd568c MM	108	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
	109	*/
	110	#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
	111
1d6040f1 RR	112	/* IbsFetchCtl bits/masks */
	113	#define IBS_FETCH_RAND_EN (1ULL<<57)
	114	#define IBS_FETCH_VAL (1ULL<<49)
	115	#define IBS_FETCH_ENABLE (1ULL<<48)
a163b109 RR	116	#define IBS_FETCH_CNT 0xFFFF0000ULL
a163b109 RR	117	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1 RR	118
	119	/* IbsOpCtl bits */
	120	#define IBS_OP_CNT_CTL (1ULL<<19)
	121	#define IBS_OP_VAL (1ULL<<18)
	122	#define IBS_OP_ENABLE (1ULL<<17)
a163b109	123	#define IBS_OP_MAX_CNT 0x0000FFFFULL
30dd568c	124
cdd6c482 IM	125	#ifdef CONFIG_PERF_EVENTS
	126	extern void init_hw_perf_events(void);
	127	extern void perf_events_lapic_init(void);
194002b2	128
cdd6c482	129	#define PERF_EVENT_INDEX_OFFSET 0
194002b2	130
ef21f683 PZ	131	/*
	132	* Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
	133	* This flag is otherwise unused and ABI specified to be 0, so nobody should
	134	* care what we do with it.
	135	*/
	136	#define PERF_EFLAGS_EXACT (1UL << 3)
	137
39447b38 ZY	138	struct pt_regs;
	139	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	140	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	141	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	142
241771ef	143	#else
cdd6c482 IM	144	static inline void init_hw_perf_events(void) { }
cdd6c482 IM	145	static inline void perf_events_lapic_init(void) { }
241771ef IM	146	#endif
241771ef IM	147
cdd6c482	148	#endif /* _ASM_X86_PERF_EVENT_H */