Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
7dfb7103 | 35 | #include <linux/freezer.h> |
f26d6a2b | 36 | #include <linux/kthread.h> |
54168ed7 | 37 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 38 | #include <linux/slab.h> |
d4057bdb | 39 | #include <linux/bootmem.h> |
54d5d424 | 40 | |
d4057bdb | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
6d652ea1 | 44 | #include <asm/cpu.h> |
1da177e4 | 45 | #include <asm/desc.h> |
d4057bdb YL |
46 | #include <asm/proto.h> |
47 | #include <asm/acpi.h> | |
48 | #include <asm/dma.h> | |
1da177e4 | 49 | #include <asm/timer.h> |
306e440d | 50 | #include <asm/i8259.h> |
a4dbc34d | 51 | #include <asm/setup.h> |
8a8f422d | 52 | #include <asm/irq_remapping.h> |
2c1b284e | 53 | #include <asm/hw_irq.h> |
1da177e4 | 54 | |
7b6aa335 | 55 | #include <asm/apic.h> |
1da177e4 | 56 | |
f44d1692 JL |
57 | #define for_each_ioapic(idx) \ |
58 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
59 | #define for_each_ioapic_reverse(idx) \ | |
60 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
61 | #define for_each_pin(idx, pin) \ | |
62 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
63 | #define for_each_ioapic_pin(idx, pin) \ | |
64 | for_each_ioapic((idx)) \ | |
65 | for_each_pin((idx), (pin)) | |
2977fb3f | 66 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 67 | list_for_each_entry(entry, &head, list) |
32f71aff | 68 | |
1da177e4 | 69 | /* |
0be275e3 | 70 | * Is the SiS APIC rmw bug present ? |
54168ed7 | 71 | * -1 = don't know, 0 = no, 1 = yes |
0be275e3 JL |
72 | * When doing a read-modify-write operation on IOAPIC registers, older SiS APIC |
73 | * requires we rewrite the index register again where the read already set up | |
74 | * the index register. | |
75 | * The code to make use of sis_apic_bug has been removed, but we don't want to | |
76 | * lose this knowledge. | |
1da177e4 LT |
77 | */ |
78 | int sis_apic_bug = -1; | |
79 | ||
dade7716 | 80 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 81 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 82 | static unsigned int ioapic_dynirq_base; |
b81975ea | 83 | static int ioapic_initialized; |
efa2559f | 84 | |
4467715a JL |
85 | struct irq_pin_list { |
86 | struct list_head list; | |
87 | int apic, pin; | |
88 | }; | |
89 | ||
49c7e600 | 90 | struct mp_chip_data { |
4467715a | 91 | struct list_head irq_2_pin; |
49c7e600 JL |
92 | struct IO_APIC_route_entry entry; |
93 | int trigger; | |
94 | int polarity; | |
96ed44b2 | 95 | u32 count; |
49c7e600 JL |
96 | bool isa_irq; |
97 | }; | |
98 | ||
154d9e50 JL |
99 | struct mp_ioapic_gsi { |
100 | u32 gsi_base; | |
101 | u32 gsi_end; | |
102 | }; | |
103 | ||
b69c6c3b SS |
104 | static struct ioapic { |
105 | /* | |
106 | * # of IRQ routing registers | |
107 | */ | |
108 | int nr_registers; | |
57a6f740 SS |
109 | /* |
110 | * Saved state during suspend/resume, or while enabling intr-remap. | |
111 | */ | |
112 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
113 | /* I/O APIC config */ |
114 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
115 | /* IO APIC gsi routing info */ |
116 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
117 | struct ioapic_domain_cfg irqdomain_cfg; |
118 | struct irq_domain *irqdomain; | |
15516a3b | 119 | struct resource *iomem_res; |
b69c6c3b | 120 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 121 | |
6f50d45f | 122 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 123 | |
6f50d45f | 124 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 125 | { |
6f50d45f | 126 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
127 | } |
128 | ||
6f50d45f | 129 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 130 | { |
6f50d45f | 131 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
132 | } |
133 | ||
154d9e50 | 134 | static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 135 | { |
6f50d45f | 136 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 137 | } |
9f640ccb | 138 | |
18e48551 JL |
139 | static inline int mp_ioapic_pin_count(int ioapic) |
140 | { | |
141 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
142 | ||
143 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
144 | } | |
145 | ||
154d9e50 | 146 | static inline u32 mp_pin_to_gsi(int ioapic, int pin) |
18e48551 JL |
147 | { |
148 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
149 | } | |
150 | ||
d32932d0 JL |
151 | static inline bool mp_is_legacy_irq(int irq) |
152 | { | |
153 | return irq >= 0 && irq < nr_legacy_irqs(); | |
154 | } | |
155 | ||
95d76acc JL |
156 | /* |
157 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
158 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
159 | * may rely on non-legacy pins on the first IOAPIC. | |
160 | */ | |
18e48551 JL |
161 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
162 | { | |
95d76acc JL |
163 | if (!nr_legacy_irqs()) |
164 | return 0; | |
165 | ||
d32932d0 | 166 | return ioapic == 0 || mp_is_legacy_irq(irq); |
18e48551 JL |
167 | } |
168 | ||
d7f3d478 JL |
169 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
170 | { | |
171 | return ioapics[ioapic].irqdomain; | |
172 | } | |
173 | ||
c040aaeb | 174 | int nr_ioapics; |
2a4ab640 | 175 | |
a4384df3 EB |
176 | /* The one past the highest gsi number used */ |
177 | u32 gsi_top; | |
5777372a | 178 | |
584f734d | 179 | /* MP IRQ source entries */ |
c2c21745 | 180 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
181 | |
182 | /* # of MP IRQ source entries */ | |
183 | int mp_irq_entries; | |
184 | ||
bb8187d3 | 185 | #ifdef CONFIG_EISA |
8732fc4b AS |
186 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
187 | #endif | |
188 | ||
189 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
190 | ||
efa2559f YL |
191 | int skip_ioapic_setup; |
192 | ||
7167d08e HK |
193 | /** |
194 | * disable_ioapic_support() - disables ioapic support at runtime | |
195 | */ | |
196 | void disable_ioapic_support(void) | |
65a4e574 IM |
197 | { |
198 | #ifdef CONFIG_PCI | |
199 | noioapicquirk = 1; | |
200 | noioapicreroute = -1; | |
201 | #endif | |
202 | skip_ioapic_setup = 1; | |
203 | } | |
204 | ||
54168ed7 | 205 | static int __init parse_noapic(char *str) |
efa2559f YL |
206 | { |
207 | /* disable IO-APIC */ | |
7167d08e | 208 | disable_ioapic_support(); |
efa2559f YL |
209 | return 0; |
210 | } | |
211 | early_param("noapic", parse_noapic); | |
66759a01 | 212 | |
2d8009ba FT |
213 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
214 | void mp_save_irq(struct mpc_intsrc *m) | |
215 | { | |
216 | int i; | |
217 | ||
218 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
219 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
220 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
221 | m->srcbusirq, m->dstapic, m->dstirq); | |
222 | ||
223 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 224 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
225 | return; |
226 | } | |
227 | ||
0e3fa13f | 228 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
229 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
230 | panic("Max # of irq sources exceeded!!\n"); | |
231 | } | |
232 | ||
7e899419 YL |
233 | static void alloc_ioapic_saved_registers(int idx) |
234 | { | |
235 | size_t size; | |
236 | ||
237 | if (ioapics[idx].saved_registers) | |
238 | return; | |
239 | ||
240 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
241 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
242 | if (!ioapics[idx].saved_registers) | |
243 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
244 | } | |
245 | ||
15516a3b JL |
246 | static void free_ioapic_saved_registers(int idx) |
247 | { | |
248 | kfree(ioapics[idx].saved_registers); | |
249 | ioapics[idx].saved_registers = NULL; | |
250 | } | |
251 | ||
11d686e9 | 252 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 253 | { |
13315320 | 254 | int i; |
d6c88a50 | 255 | |
95d76acc | 256 | if (!nr_legacy_irqs()) |
1f91233c | 257 | io_apic_irqs = ~0UL; |
1f91233c | 258 | |
7e899419 YL |
259 | for_each_ioapic(i) |
260 | alloc_ioapic_saved_registers(i); | |
4c79185c | 261 | |
13a0c3c2 | 262 | return 0; |
0b8f1efa | 263 | } |
8f09cd20 | 264 | |
130fe05d LT |
265 | struct io_apic { |
266 | unsigned int index; | |
267 | unsigned int unused[3]; | |
268 | unsigned int data; | |
0280f7c4 SS |
269 | unsigned int unused2[11]; |
270 | unsigned int eoi; | |
130fe05d LT |
271 | }; |
272 | ||
273 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
274 | { | |
275 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 276 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
277 | } |
278 | ||
ad66e1ef | 279 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
280 | { |
281 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
282 | writel(vector, &io_apic->eoi); | |
283 | } | |
284 | ||
4a8e2a31 | 285 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
286 | { |
287 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
288 | writel(reg, &io_apic->index); | |
289 | return readl(&io_apic->data); | |
290 | } | |
291 | ||
9a93d473 JL |
292 | static void io_apic_write(unsigned int apic, unsigned int reg, |
293 | unsigned int value) | |
130fe05d LT |
294 | { |
295 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 296 | |
130fe05d LT |
297 | writel(reg, &io_apic->index); |
298 | writel(value, &io_apic->data); | |
299 | } | |
300 | ||
cf4c6a2f AK |
301 | union entry_union { |
302 | struct { u32 w1, w2; }; | |
303 | struct IO_APIC_route_entry entry; | |
304 | }; | |
305 | ||
e57253a8 SS |
306 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
307 | { | |
308 | union entry_union eu; | |
309 | ||
310 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
311 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 312 | |
e57253a8 SS |
313 | return eu.entry; |
314 | } | |
315 | ||
cf4c6a2f AK |
316 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
317 | { | |
318 | union entry_union eu; | |
319 | unsigned long flags; | |
136d249e | 320 | |
dade7716 | 321 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 322 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 323 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 324 | |
cf4c6a2f AK |
325 | return eu.entry; |
326 | } | |
327 | ||
f9dadfa7 LT |
328 | /* |
329 | * When we write a new IO APIC routing entry, we need to write the high | |
330 | * word first! If the mask bit in the low word is clear, we will enable | |
331 | * the interrupt, and we need to make sure the entry is fully populated | |
332 | * before that happens. | |
333 | */ | |
136d249e | 334 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 335 | { |
50a8d4d2 F |
336 | union entry_union eu = {{0, 0}}; |
337 | ||
cf4c6a2f | 338 | eu.entry = e; |
f9dadfa7 LT |
339 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
340 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
341 | } |
342 | ||
1a8ce7ff | 343 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
344 | { |
345 | unsigned long flags; | |
136d249e | 346 | |
dade7716 | 347 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 348 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 349 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
350 | } |
351 | ||
352 | /* | |
353 | * When we mask an IO APIC routing entry, we need to write the low | |
354 | * word first, in order to set the mask bit before we change the | |
355 | * high bits! | |
356 | */ | |
357 | static void ioapic_mask_entry(int apic, int pin) | |
358 | { | |
359 | unsigned long flags; | |
360 | union entry_union eu = { .entry.mask = 1 }; | |
361 | ||
dade7716 | 362 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
363 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
364 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 365 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
366 | } |
367 | ||
1da177e4 LT |
368 | /* |
369 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
370 | * shared ISA-space IRQs, so we have to support them. We are super | |
371 | * fast in the common case, and fast for shared ISA-space IRQs. | |
372 | */ | |
4467715a JL |
373 | static int __add_pin_to_irq_node(struct mp_chip_data *data, |
374 | int node, int apic, int pin) | |
1da177e4 | 375 | { |
a178b87b | 376 | struct irq_pin_list *entry; |
0f978f45 | 377 | |
2977fb3f | 378 | /* don't allow duplicates */ |
4467715a | 379 | for_each_irq_pin(entry, data->irq_2_pin) |
0f978f45 | 380 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 381 | return 0; |
0f978f45 | 382 | |
4467715a | 383 | entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
a7428cd2 | 384 | if (!entry) { |
c767a54b JP |
385 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
386 | node, apic, pin); | |
f3d1915a | 387 | return -ENOMEM; |
a7428cd2 | 388 | } |
1da177e4 LT |
389 | entry->apic = apic; |
390 | entry->pin = pin; | |
4467715a | 391 | list_add_tail(&entry->list, &data->irq_2_pin); |
875e68ec | 392 | |
f3d1915a CG |
393 | return 0; |
394 | } | |
395 | ||
4467715a | 396 | static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) |
df334bea | 397 | { |
a178b87b | 398 | struct irq_pin_list *tmp, *entry; |
df334bea | 399 | |
4467715a | 400 | list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) |
df334bea | 401 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 402 | list_del(&entry->list); |
df334bea JL |
403 | kfree(entry); |
404 | return; | |
df334bea JL |
405 | } |
406 | } | |
407 | ||
4467715a JL |
408 | static void add_pin_to_irq_node(struct mp_chip_data *data, |
409 | int node, int apic, int pin) | |
f3d1915a | 410 | { |
4467715a | 411 | if (__add_pin_to_irq_node(data, node, apic, pin)) |
f3d1915a | 412 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
413 | } |
414 | ||
415 | /* | |
416 | * Reroute an IRQ to a different pin. | |
417 | */ | |
4467715a | 418 | static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, |
4eea6fff JF |
419 | int oldapic, int oldpin, |
420 | int newapic, int newpin) | |
1da177e4 | 421 | { |
535b6429 | 422 | struct irq_pin_list *entry; |
1da177e4 | 423 | |
4467715a | 424 | for_each_irq_pin(entry, data->irq_2_pin) { |
1da177e4 LT |
425 | if (entry->apic == oldapic && entry->pin == oldpin) { |
426 | entry->apic = newapic; | |
427 | entry->pin = newpin; | |
0f978f45 | 428 | /* every one is different, right? */ |
4eea6fff | 429 | return; |
0f978f45 | 430 | } |
1da177e4 | 431 | } |
0f978f45 | 432 | |
4eea6fff | 433 | /* old apic/pin didn't exist, so just add new ones */ |
4467715a | 434 | add_pin_to_irq_node(data, node, newapic, newpin); |
1da177e4 LT |
435 | } |
436 | ||
4467715a | 437 | static void io_apic_modify_irq(struct mp_chip_data *data, |
2f210deb JF |
438 | int mask_and, int mask_or, |
439 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 440 | { |
0be275e3 | 441 | union entry_union eu; |
87783be4 | 442 | struct irq_pin_list *entry; |
047c8fdb | 443 | |
0be275e3 JL |
444 | eu.entry = data->entry; |
445 | eu.w1 &= mask_and; | |
446 | eu.w1 |= mask_or; | |
447 | data->entry = eu.entry; | |
448 | ||
449 | for_each_irq_pin(entry, data->irq_2_pin) { | |
450 | io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); | |
451 | if (final) | |
452 | final(entry); | |
453 | } | |
c29d9db3 SS |
454 | } |
455 | ||
7f3e632f | 456 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 457 | { |
87783be4 CG |
458 | /* |
459 | * Synchronize the IO-APIC and the CPU by doing | |
460 | * a dummy read from the IO-APIC | |
461 | */ | |
462 | struct io_apic __iomem *io_apic; | |
136d249e | 463 | |
87783be4 | 464 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 465 | readl(&io_apic->data); |
1da177e4 LT |
466 | } |
467 | ||
4467715a | 468 | static void mask_ioapic_irq(struct irq_data *irq_data) |
87783be4 | 469 | { |
4467715a | 470 | struct mp_chip_data *data = irq_data->chip_data; |
dd5f15e5 TG |
471 | unsigned long flags; |
472 | ||
473 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 474 | io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 475 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 476 | } |
1da177e4 | 477 | |
4467715a | 478 | static void __unmask_ioapic(struct mp_chip_data *data) |
dd5f15e5 | 479 | { |
4467715a | 480 | io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL); |
1da177e4 LT |
481 | } |
482 | ||
4467715a | 483 | static void unmask_ioapic_irq(struct irq_data *irq_data) |
1da177e4 | 484 | { |
4467715a | 485 | struct mp_chip_data *data = irq_data->chip_data; |
1da177e4 LT |
486 | unsigned long flags; |
487 | ||
dade7716 | 488 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
4467715a | 489 | __unmask_ioapic(data); |
dade7716 | 490 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
491 | } |
492 | ||
c0205701 SS |
493 | /* |
494 | * IO-APIC versions below 0x20 don't support EOI register. | |
495 | * For the record, here is the information about various versions: | |
496 | * 0Xh 82489DX | |
497 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
498 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
499 | * 30h-FFh Reserved | |
500 | * | |
501 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
502 | * version as 0x2. This is an error with documentation and these ICH chips | |
503 | * use io-apic's of version 0x20. | |
504 | * | |
505 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
506 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
507 | * mode to edge and then back to level, with RTE being masked during this. | |
508 | */ | |
ad66e1ef | 509 | static void __eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
510 | { |
511 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 512 | io_apic_eoi(apic, vector); |
c0205701 SS |
513 | } else { |
514 | struct IO_APIC_route_entry entry, entry1; | |
515 | ||
516 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
517 | ||
518 | /* | |
519 | * Mask the entry and change the trigger mode to edge. | |
520 | */ | |
521 | entry1.mask = 1; | |
522 | entry1.trigger = IOAPIC_EDGE; | |
523 | ||
524 | __ioapic_write_entry(apic, pin, entry1); | |
525 | ||
526 | /* | |
527 | * Restore the previous level triggered entry. | |
528 | */ | |
529 | __ioapic_write_entry(apic, pin, entry); | |
530 | } | |
531 | } | |
532 | ||
4467715a | 533 | void eoi_ioapic_pin(int vector, struct mp_chip_data *data) |
d32932d0 JL |
534 | { |
535 | unsigned long flags; | |
536 | struct irq_pin_list *entry; | |
537 | ||
538 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 539 | for_each_irq_pin(entry, data->irq_2_pin) |
ad66e1ef | 540 | __eoi_ioapic_pin(entry->apic, entry->pin, vector); |
c0205701 SS |
541 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
542 | } | |
543 | ||
1da177e4 LT |
544 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
545 | { | |
546 | struct IO_APIC_route_entry entry; | |
36062448 | 547 | |
1da177e4 | 548 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 549 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
550 | if (entry.delivery_mode == dest_SMI) |
551 | return; | |
1e75b31d | 552 | |
1da177e4 | 553 | /* |
1e75b31d SS |
554 | * Make sure the entry is masked and re-read the contents to check |
555 | * if it is a level triggered pin and if the remote-IRR is set. | |
556 | */ | |
557 | if (!entry.mask) { | |
558 | entry.mask = 1; | |
559 | ioapic_write_entry(apic, pin, entry); | |
560 | entry = ioapic_read_entry(apic, pin); | |
561 | } | |
562 | ||
563 | if (entry.irr) { | |
c0205701 SS |
564 | unsigned long flags; |
565 | ||
1e75b31d SS |
566 | /* |
567 | * Make sure the trigger mode is set to level. Explicit EOI | |
568 | * doesn't clear the remote-IRR if the trigger mode is not | |
569 | * set to level. | |
570 | */ | |
571 | if (!entry.trigger) { | |
572 | entry.trigger = IOAPIC_LEVEL; | |
573 | ioapic_write_entry(apic, pin, entry); | |
574 | } | |
c0205701 | 575 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
ad66e1ef | 576 | __eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 577 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
578 | } |
579 | ||
580 | /* | |
581 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
582 | * bit. | |
1da177e4 | 583 | */ |
f9dadfa7 | 584 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
585 | entry = ioapic_read_entry(apic, pin); |
586 | if (entry.irr) | |
c767a54b | 587 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 588 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
589 | } |
590 | ||
54168ed7 | 591 | static void clear_IO_APIC (void) |
1da177e4 LT |
592 | { |
593 | int apic, pin; | |
594 | ||
f44d1692 JL |
595 | for_each_ioapic_pin(apic, pin) |
596 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
597 | } |
598 | ||
54168ed7 | 599 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
600 | /* |
601 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
602 | * specific CPU-side IRQs. | |
603 | */ | |
604 | ||
605 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
606 | static int pirq_entries[MAX_PIRQS] = { |
607 | [0 ... MAX_PIRQS - 1] = -1 | |
608 | }; | |
1da177e4 | 609 | |
1da177e4 LT |
610 | static int __init ioapic_pirq_setup(char *str) |
611 | { | |
612 | int i, max; | |
613 | int ints[MAX_PIRQS+1]; | |
614 | ||
615 | get_options(str, ARRAY_SIZE(ints), ints); | |
616 | ||
1da177e4 LT |
617 | apic_printk(APIC_VERBOSE, KERN_INFO |
618 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
619 | max = MAX_PIRQS; | |
620 | if (ints[0] < MAX_PIRQS) | |
621 | max = ints[0]; | |
622 | ||
623 | for (i = 0; i < max; i++) { | |
624 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
625 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
626 | /* | |
627 | * PIRQs are mapped upside down, usually. | |
628 | */ | |
629 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
630 | } | |
631 | return 1; | |
632 | } | |
633 | ||
634 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
635 | #endif /* CONFIG_X86_32 */ |
636 | ||
54168ed7 | 637 | /* |
05c3dc2c | 638 | * Saves all the IO-APIC RTE's |
54168ed7 | 639 | */ |
31dce14a | 640 | int save_ioapic_entries(void) |
54168ed7 | 641 | { |
54168ed7 | 642 | int apic, pin; |
31dce14a | 643 | int err = 0; |
54168ed7 | 644 | |
f44d1692 | 645 | for_each_ioapic(apic) { |
57a6f740 | 646 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
647 | err = -ENOMEM; |
648 | continue; | |
649 | } | |
54168ed7 | 650 | |
f44d1692 | 651 | for_each_pin(apic, pin) |
57a6f740 | 652 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 653 | ioapic_read_entry(apic, pin); |
b24696bc | 654 | } |
5ffa4eb2 | 655 | |
31dce14a | 656 | return err; |
54168ed7 IM |
657 | } |
658 | ||
b24696bc FY |
659 | /* |
660 | * Mask all IO APIC entries. | |
661 | */ | |
31dce14a | 662 | void mask_ioapic_entries(void) |
05c3dc2c SS |
663 | { |
664 | int apic, pin; | |
665 | ||
f44d1692 | 666 | for_each_ioapic(apic) { |
2f344d2e | 667 | if (!ioapics[apic].saved_registers) |
31dce14a | 668 | continue; |
b24696bc | 669 | |
f44d1692 | 670 | for_each_pin(apic, pin) { |
05c3dc2c SS |
671 | struct IO_APIC_route_entry entry; |
672 | ||
57a6f740 | 673 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
674 | if (!entry.mask) { |
675 | entry.mask = 1; | |
676 | ioapic_write_entry(apic, pin, entry); | |
677 | } | |
678 | } | |
679 | } | |
680 | } | |
681 | ||
b24696bc | 682 | /* |
57a6f740 | 683 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 684 | */ |
31dce14a | 685 | int restore_ioapic_entries(void) |
54168ed7 IM |
686 | { |
687 | int apic, pin; | |
688 | ||
f44d1692 | 689 | for_each_ioapic(apic) { |
2f344d2e | 690 | if (!ioapics[apic].saved_registers) |
31dce14a | 691 | continue; |
b24696bc | 692 | |
f44d1692 | 693 | for_each_pin(apic, pin) |
54168ed7 | 694 | ioapic_write_entry(apic, pin, |
57a6f740 | 695 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 696 | } |
b24696bc | 697 | return 0; |
54168ed7 IM |
698 | } |
699 | ||
1da177e4 LT |
700 | /* |
701 | * Find the IRQ entry number of a certain pin. | |
702 | */ | |
6f50d45f | 703 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
704 | { |
705 | int i; | |
706 | ||
707 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 708 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 709 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
710 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
711 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
712 | return i; |
713 | ||
714 | return -1; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Find the pin to which IRQ[irq] (ISA) is connected | |
719 | */ | |
fcfd636a | 720 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
721 | { |
722 | int i; | |
723 | ||
724 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 725 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 726 | |
d27e2b8e | 727 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
728 | (mp_irqs[i].irqtype == type) && |
729 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 730 | |
c2c21745 | 731 | return mp_irqs[i].dstirq; |
1da177e4 LT |
732 | } |
733 | return -1; | |
734 | } | |
735 | ||
fcfd636a EB |
736 | static int __init find_isa_irq_apic(int irq, int type) |
737 | { | |
738 | int i; | |
739 | ||
740 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 741 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 742 | |
73b2961b | 743 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
744 | (mp_irqs[i].irqtype == type) && |
745 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
746 | break; |
747 | } | |
6f50d45f | 748 | |
fcfd636a | 749 | if (i < mp_irq_entries) { |
6f50d45f YL |
750 | int ioapic_idx; |
751 | ||
f44d1692 | 752 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
753 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
754 | return ioapic_idx; | |
fcfd636a EB |
755 | } |
756 | ||
757 | return -1; | |
758 | } | |
759 | ||
bb8187d3 | 760 | #ifdef CONFIG_EISA |
1da177e4 LT |
761 | /* |
762 | * EISA Edge/Level control register, ELCR | |
763 | */ | |
764 | static int EISA_ELCR(unsigned int irq) | |
765 | { | |
95d76acc | 766 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
767 | unsigned int port = 0x4d0 + (irq >> 3); |
768 | return (inb(port) >> (irq & 7)) & 1; | |
769 | } | |
770 | apic_printk(APIC_VERBOSE, KERN_INFO | |
771 | "Broken MPtable reports ISA irq %d\n", irq); | |
772 | return 0; | |
773 | } | |
54168ed7 | 774 | |
c0a282c2 | 775 | #endif |
1da177e4 | 776 | |
6728801d AS |
777 | /* ISA interrupts are always polarity zero edge triggered, |
778 | * when listed as conforming in the MP table. */ | |
779 | ||
780 | #define default_ISA_trigger(idx) (0) | |
781 | #define default_ISA_polarity(idx) (0) | |
782 | ||
1da177e4 LT |
783 | /* EISA interrupts are always polarity zero and can be edge or level |
784 | * trigger depending on the ELCR value. If an interrupt is listed as | |
785 | * EISA conforming in the MP table, that means its trigger type must | |
786 | * be read in from the ELCR */ | |
787 | ||
c2c21745 | 788 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 789 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
790 | |
791 | /* PCI interrupts are always polarity one level triggered, | |
792 | * when listed as conforming in the MP table. */ | |
793 | ||
794 | #define default_PCI_trigger(idx) (1) | |
795 | #define default_PCI_polarity(idx) (1) | |
796 | ||
b77cf6a8 | 797 | static int irq_polarity(int idx) |
1da177e4 | 798 | { |
c2c21745 | 799 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
800 | int polarity; |
801 | ||
802 | /* | |
803 | * Determine IRQ line polarity (high active or low active): | |
804 | */ | |
c2c21745 | 805 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 806 | { |
54168ed7 IM |
807 | case 0: /* conforms, ie. bus-type dependent polarity */ |
808 | if (test_bit(bus, mp_bus_not_pci)) | |
809 | polarity = default_ISA_polarity(idx); | |
810 | else | |
811 | polarity = default_PCI_polarity(idx); | |
812 | break; | |
813 | case 1: /* high active */ | |
814 | { | |
815 | polarity = 0; | |
816 | break; | |
817 | } | |
818 | case 2: /* reserved */ | |
819 | { | |
c767a54b | 820 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
821 | polarity = 1; |
822 | break; | |
823 | } | |
824 | case 3: /* low active */ | |
825 | { | |
826 | polarity = 1; | |
827 | break; | |
828 | } | |
829 | default: /* invalid */ | |
830 | { | |
c767a54b | 831 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
832 | polarity = 1; |
833 | break; | |
834 | } | |
1da177e4 LT |
835 | } |
836 | return polarity; | |
837 | } | |
838 | ||
b77cf6a8 | 839 | static int irq_trigger(int idx) |
1da177e4 | 840 | { |
c2c21745 | 841 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
842 | int trigger; |
843 | ||
844 | /* | |
845 | * Determine IRQ trigger mode (edge or level sensitive): | |
846 | */ | |
c2c21745 | 847 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 848 | { |
54168ed7 IM |
849 | case 0: /* conforms, ie. bus-type dependent */ |
850 | if (test_bit(bus, mp_bus_not_pci)) | |
851 | trigger = default_ISA_trigger(idx); | |
852 | else | |
853 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 854 | #ifdef CONFIG_EISA |
54168ed7 IM |
855 | switch (mp_bus_id_to_type[bus]) { |
856 | case MP_BUS_ISA: /* ISA pin */ | |
857 | { | |
858 | /* set before the switch */ | |
859 | break; | |
860 | } | |
861 | case MP_BUS_EISA: /* EISA pin */ | |
862 | { | |
863 | trigger = default_EISA_trigger(idx); | |
864 | break; | |
865 | } | |
866 | case MP_BUS_PCI: /* PCI pin */ | |
867 | { | |
868 | /* set before the switch */ | |
869 | break; | |
870 | } | |
54168ed7 IM |
871 | default: |
872 | { | |
c767a54b | 873 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
874 | trigger = 1; |
875 | break; | |
876 | } | |
877 | } | |
878 | #endif | |
1da177e4 | 879 | break; |
54168ed7 | 880 | case 1: /* edge */ |
1da177e4 | 881 | { |
54168ed7 | 882 | trigger = 0; |
1da177e4 LT |
883 | break; |
884 | } | |
54168ed7 | 885 | case 2: /* reserved */ |
1da177e4 | 886 | { |
c767a54b | 887 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 888 | trigger = 1; |
1da177e4 LT |
889 | break; |
890 | } | |
54168ed7 | 891 | case 3: /* level */ |
1da177e4 | 892 | { |
54168ed7 | 893 | trigger = 1; |
1da177e4 LT |
894 | break; |
895 | } | |
54168ed7 | 896 | default: /* invalid */ |
1da177e4 | 897 | { |
c767a54b | 898 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 899 | trigger = 0; |
1da177e4 LT |
900 | break; |
901 | } | |
902 | } | |
903 | return trigger; | |
904 | } | |
905 | ||
c4d05a2c JL |
906 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
907 | int trigger, int polarity) | |
908 | { | |
909 | init_irq_alloc_info(info, NULL); | |
910 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
911 | info->ioapic_node = node; | |
912 | info->ioapic_trigger = trigger; | |
913 | info->ioapic_polarity = polarity; | |
914 | info->ioapic_valid = 1; | |
915 | } | |
916 | ||
96ed44b2 JL |
917 | #ifndef CONFIG_ACPI |
918 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); | |
919 | #endif | |
920 | ||
921 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, | |
922 | struct irq_alloc_info *src, | |
923 | u32 gsi, int ioapic_idx, int pin) | |
924 | { | |
925 | int trigger, polarity; | |
926 | ||
927 | copy_irq_alloc_info(dst, src); | |
928 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
929 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); | |
930 | dst->ioapic_pin = pin; | |
931 | dst->ioapic_valid = 1; | |
932 | if (src && src->ioapic_valid) { | |
933 | dst->ioapic_node = src->ioapic_node; | |
934 | dst->ioapic_trigger = src->ioapic_trigger; | |
935 | dst->ioapic_polarity = src->ioapic_polarity; | |
936 | } else { | |
937 | dst->ioapic_node = NUMA_NO_NODE; | |
938 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { | |
939 | dst->ioapic_trigger = trigger; | |
940 | dst->ioapic_polarity = polarity; | |
941 | } else { | |
942 | /* | |
943 | * PCI interrupts are always polarity one level | |
944 | * triggered. | |
945 | */ | |
946 | dst->ioapic_trigger = 1; | |
947 | dst->ioapic_polarity = 1; | |
948 | } | |
949 | } | |
950 | } | |
951 | ||
952 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) | |
953 | { | |
954 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; | |
955 | } | |
956 | ||
49c7e600 JL |
957 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
958 | { | |
959 | irq_flow_handler_t hdl; | |
960 | bool fasteoi; | |
961 | ||
962 | if (trigger) { | |
963 | irq_set_status_flags(irq, IRQ_LEVEL); | |
964 | fasteoi = true; | |
965 | } else { | |
966 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
967 | fasteoi = false; | |
968 | } | |
969 | ||
970 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
971 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
972 | } | |
973 | ||
96ed44b2 JL |
974 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
975 | { | |
976 | struct mp_chip_data *data = irq_get_chip_data(irq); | |
977 | ||
978 | /* | |
979 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger | |
980 | * and polarity attirbutes. So allow the first user to reprogram the | |
981 | * pin with real trigger and polarity attributes. | |
982 | */ | |
983 | if (irq < nr_legacy_irqs() && data->count == 1) { | |
984 | if (info->ioapic_trigger != data->trigger) | |
985 | mp_register_handler(irq, data->trigger); | |
986 | data->entry.trigger = data->trigger = info->ioapic_trigger; | |
987 | data->entry.polarity = data->polarity = info->ioapic_polarity; | |
988 | } | |
989 | ||
990 | return data->trigger == info->ioapic_trigger && | |
991 | data->polarity == info->ioapic_polarity; | |
992 | } | |
993 | ||
d32932d0 | 994 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
c4d05a2c | 995 | struct irq_alloc_info *info) |
6b9fb708 | 996 | { |
d32932d0 | 997 | bool legacy = false; |
d7f3d478 | 998 | int irq = -1; |
d7f3d478 JL |
999 | int type = ioapics[ioapic].irqdomain_cfg.type; |
1000 | ||
1001 | switch (type) { | |
1002 | case IOAPIC_DOMAIN_LEGACY: | |
1003 | /* | |
d32932d0 JL |
1004 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
1005 | * 16 GSIs on some weird platforms. | |
d7f3d478 | 1006 | */ |
d32932d0 | 1007 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
d7f3d478 | 1008 | irq = gsi; |
d32932d0 | 1009 | legacy = mp_is_legacy_irq(irq); |
d7f3d478 JL |
1010 | break; |
1011 | case IOAPIC_DOMAIN_STRICT: | |
d32932d0 | 1012 | irq = gsi; |
d7f3d478 JL |
1013 | break; |
1014 | case IOAPIC_DOMAIN_DYNAMIC: | |
d7f3d478 JL |
1015 | break; |
1016 | default: | |
1017 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
d32932d0 JL |
1018 | return -1; |
1019 | } | |
1020 | ||
1021 | return __irq_domain_alloc_irqs(domain, irq, 1, | |
1022 | ioapic_alloc_attr_node(info), | |
1023 | info, legacy); | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins | |
1028 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping | |
1029 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are | |
1030 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1031 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and | |
1032 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for | |
1033 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be | |
1034 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. | |
1035 | */ | |
1036 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, | |
1037 | int irq, int ioapic, int pin, | |
1038 | struct irq_alloc_info *info) | |
1039 | { | |
1040 | struct mp_chip_data *data; | |
1041 | struct irq_data *irq_data = irq_get_irq_data(irq); | |
1042 | int node = ioapic_alloc_attr_node(info); | |
1043 | ||
1044 | /* | |
1045 | * Legacy ISA IRQ has already been allocated, just add pin to | |
1046 | * the pin list assoicated with this IRQ and program the IOAPIC | |
1047 | * entry. The IOAPIC entry | |
1048 | */ | |
1049 | if (irq_data && irq_data->parent_data) { | |
d32932d0 JL |
1050 | if (!mp_check_pin_attr(irq, info)) |
1051 | return -EBUSY; | |
4467715a JL |
1052 | if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, |
1053 | info->ioapic_pin)) | |
d32932d0 JL |
1054 | return -ENOMEM; |
1055 | } else { | |
1056 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true); | |
1057 | if (irq >= 0) { | |
1058 | irq_data = irq_domain_get_irq_data(domain, irq); | |
1059 | data = irq_data->chip_data; | |
1060 | data->isa_irq = true; | |
1061 | } | |
d7f3d478 JL |
1062 | } |
1063 | ||
d32932d0 | 1064 | return irq; |
d7f3d478 JL |
1065 | } |
1066 | ||
1067 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 1068 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1069 | { |
1070 | int irq; | |
d32932d0 JL |
1071 | bool legacy = false; |
1072 | struct irq_alloc_info tmp; | |
1073 | struct mp_chip_data *data; | |
d7f3d478 JL |
1074 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
1075 | ||
b81975ea | 1076 | if (!domain) |
d32932d0 | 1077 | return -ENOSYS; |
16ee7b3d | 1078 | |
16ee7b3d JL |
1079 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1080 | irq = mp_irqs[idx].srcbusirq; | |
d32932d0 JL |
1081 | legacy = mp_is_legacy_irq(irq); |
1082 | } | |
16ee7b3d | 1083 | |
d32932d0 JL |
1084 | mutex_lock(&ioapic_mutex); |
1085 | if (!(flags & IOAPIC_MAP_ALLOC)) { | |
1086 | if (!legacy) { | |
1087 | irq = irq_find_mapping(domain, pin); | |
16ee7b3d | 1088 | if (irq == 0) |
d32932d0 | 1089 | irq = -ENOENT; |
16ee7b3d JL |
1090 | } |
1091 | } else { | |
d32932d0 JL |
1092 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
1093 | if (legacy) | |
1094 | irq = alloc_isa_irq_from_domain(domain, irq, | |
1095 | ioapic, pin, &tmp); | |
1096 | else if ((irq = irq_find_mapping(domain, pin)) == 0) | |
1097 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); | |
1098 | else if (!mp_check_pin_attr(irq, &tmp)) | |
1099 | irq = -EBUSY; | |
1100 | if (irq >= 0) { | |
1101 | data = irq_get_chip_data(irq); | |
1102 | data->count++; | |
1103 | } | |
15a3c7cc | 1104 | } |
d7f3d478 JL |
1105 | mutex_unlock(&ioapic_mutex); |
1106 | ||
d32932d0 | 1107 | return irq; |
6b9fb708 JL |
1108 | } |
1109 | ||
d7f3d478 | 1110 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1111 | { |
d7f3d478 | 1112 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1113 | |
1114 | /* | |
1115 | * Debugging check, we are in big trouble if this message pops up! | |
1116 | */ | |
c2c21745 | 1117 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1118 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1119 | |
54168ed7 | 1120 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1121 | /* |
1122 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1123 | */ | |
1124 | if ((pin >= 16) && (pin <= 23)) { | |
1125 | if (pirq_entries[pin-16] != -1) { | |
1126 | if (!pirq_entries[pin-16]) { | |
1127 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1128 | "disabling PIRQ%d\n", pin-16); | |
1129 | } else { | |
d7f3d478 | 1130 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1131 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1132 | "using PIRQ%d -> IRQ %d\n", | |
1133 | pin-16, irq); | |
6b9fb708 | 1134 | return irq; |
1da177e4 LT |
1135 | } |
1136 | } | |
1137 | } | |
54168ed7 IM |
1138 | #endif |
1139 | ||
c4d05a2c | 1140 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1141 | } |
6b9fb708 | 1142 | |
154d9e50 | 1143 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1144 | { |
1145 | int ioapic, pin, idx; | |
1146 | ||
1147 | ioapic = mp_find_ioapic(gsi); | |
1148 | if (ioapic < 0) | |
1149 | return -1; | |
1150 | ||
1151 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1152 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1153 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1154 | return -1; | |
1155 | ||
c4d05a2c | 1156 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1157 | } |
1158 | ||
df334bea JL |
1159 | void mp_unmap_irq(int irq) |
1160 | { | |
d32932d0 JL |
1161 | struct irq_data *irq_data = irq_get_irq_data(irq); |
1162 | struct mp_chip_data *data; | |
df334bea | 1163 | |
d32932d0 | 1164 | if (!irq_data || !irq_data->domain) |
df334bea JL |
1165 | return; |
1166 | ||
d32932d0 JL |
1167 | data = irq_data->chip_data; |
1168 | if (!data || data->isa_irq) | |
1169 | return; | |
df334bea JL |
1170 | |
1171 | mutex_lock(&ioapic_mutex); | |
d32932d0 JL |
1172 | if (--data->count == 0) |
1173 | irq_domain_free_irqs(irq, 1); | |
df334bea JL |
1174 | mutex_unlock(&ioapic_mutex); |
1175 | } | |
1176 | ||
e20c06fd YL |
1177 | /* |
1178 | * Find a specific PCI IRQ entry. | |
1179 | * Not an __init, possibly needed by modules | |
1180 | */ | |
25d0d35e | 1181 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1182 | { |
d7f3d478 | 1183 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1184 | |
1185 | apic_printk(APIC_DEBUG, | |
1186 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1187 | bus, slot, pin); | |
1188 | if (test_bit(bus, mp_bus_not_pci)) { | |
1189 | apic_printk(APIC_VERBOSE, | |
1190 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1191 | return -1; | |
1192 | } | |
79598505 | 1193 | |
e20c06fd YL |
1194 | for (i = 0; i < mp_irq_entries; i++) { |
1195 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1196 | int ioapic_idx, found = 0; |
1197 | ||
1198 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1199 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1200 | continue; | |
e20c06fd | 1201 | |
f44d1692 | 1202 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1203 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1204 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1205 | found = 1; | |
e20c06fd | 1206 | break; |
e20c06fd | 1207 | } |
79598505 JL |
1208 | if (!found) |
1209 | continue; | |
1210 | ||
1211 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1212 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1213 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1214 | continue; |
1215 | ||
1216 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1217 | best_idx = i; |
1218 | best_ioapic = ioapic_idx; | |
1219 | goto out; | |
79598505 | 1220 | } |
d7f3d478 | 1221 | |
79598505 JL |
1222 | /* |
1223 | * Use the first all-but-pin matching entry as a | |
1224 | * best-guess fuzzy result for broken mptables. | |
1225 | */ | |
d7f3d478 JL |
1226 | if (best_idx < 0) { |
1227 | best_idx = i; | |
1228 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1229 | } |
1230 | } | |
d7f3d478 JL |
1231 | if (best_idx < 0) |
1232 | return -1; | |
1233 | ||
1234 | out: | |
25d0d35e JL |
1235 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1236 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1237 | } |
1238 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1239 | ||
d32932d0 | 1240 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
1da177e4 | 1241 | |
047c8fdb | 1242 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1243 | static inline int IO_APIC_irq_trigger(int irq) |
1244 | { | |
d6c88a50 | 1245 | int apic, idx, pin; |
1d025192 | 1246 | |
f44d1692 JL |
1247 | for_each_ioapic_pin(apic, pin) { |
1248 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1249 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1250 | return irq_trigger(idx); |
d6c88a50 TG |
1251 | } |
1252 | /* | |
54168ed7 IM |
1253 | * nonexistent IRQs are edge default |
1254 | */ | |
d6c88a50 | 1255 | return 0; |
1d025192 | 1256 | } |
047c8fdb YL |
1257 | #else |
1258 | static inline int IO_APIC_irq_trigger(int irq) | |
1259 | { | |
54168ed7 | 1260 | return 1; |
047c8fdb YL |
1261 | } |
1262 | #endif | |
1d025192 | 1263 | |
ed972ccf TG |
1264 | static void __init setup_IO_APIC_irqs(void) |
1265 | { | |
16ee7b3d JL |
1266 | unsigned int ioapic, pin; |
1267 | int idx; | |
ed972ccf TG |
1268 | |
1269 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1270 | ||
16ee7b3d JL |
1271 | for_each_ioapic_pin(ioapic, pin) { |
1272 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1273 | if (idx < 0) | |
1274 | apic_printk(APIC_VERBOSE, | |
1275 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1276 | mpc_ioapic_id(ioapic), pin); | |
1277 | else | |
1278 | pin_2_irq(idx, ioapic, pin, | |
1279 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1280 | } | |
ed972ccf TG |
1281 | } |
1282 | ||
17405453 YY |
1283 | void ioapic_zap_locks(void) |
1284 | { | |
1285 | raw_spin_lock_init(&ioapic_lock); | |
1286 | } | |
1287 | ||
a44174ee JL |
1288 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1289 | { | |
1290 | int i; | |
1291 | char buf[256]; | |
1292 | struct IO_APIC_route_entry entry; | |
1293 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; | |
1294 | ||
1295 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); | |
1296 | for (i = 0; i <= nr_entries; i++) { | |
1297 | entry = ioapic_read_entry(apic, i); | |
1298 | snprintf(buf, sizeof(buf), | |
1299 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", | |
1300 | i, entry.mask ? "disabled" : "enabled ", | |
1301 | entry.trigger ? "level" : "edge ", | |
1302 | entry.polarity ? "low " : "high", | |
1303 | entry.vector, entry.irr, entry.delivery_status); | |
1304 | if (ir_entry->format) | |
1305 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", | |
1306 | buf, (ir_entry->index << 15) | ir_entry->index, | |
1307 | ir_entry->zero); | |
1308 | else | |
1309 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", | |
1310 | buf, entry.dest_mode ? "logical " : "physical", | |
1311 | entry.dest, entry.delivery_mode); | |
1312 | } | |
1313 | } | |
1314 | ||
74afab7a | 1315 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1316 | { |
1da177e4 LT |
1317 | union IO_APIC_reg_00 reg_00; |
1318 | union IO_APIC_reg_01 reg_01; | |
1319 | union IO_APIC_reg_02 reg_02; | |
1320 | union IO_APIC_reg_03 reg_03; | |
1321 | unsigned long flags; | |
1da177e4 | 1322 | |
dade7716 | 1323 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1324 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1325 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1326 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1327 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1328 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1329 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1330 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1331 | |
6f50d45f | 1332 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1333 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1334 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1335 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1336 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1337 | |
54168ed7 | 1338 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1339 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1340 | reg_01.bits.entries); | |
1da177e4 LT |
1341 | |
1342 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1343 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1344 | reg_01.bits.version); | |
1da177e4 LT |
1345 | |
1346 | /* | |
1347 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1348 | * but the value of reg_02 is read as the previous read register | |
1349 | * value, so ignore it if reg_02 == reg_01. | |
1350 | */ | |
1351 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1352 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1353 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1354 | } |
1355 | ||
1356 | /* | |
1357 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1358 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1359 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1360 | */ | |
1361 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1362 | reg_03.raw != reg_01.raw) { | |
1363 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1364 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1365 | } |
1366 | ||
1367 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
a44174ee | 1368 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1369 | } |
1370 | ||
74afab7a | 1371 | void __init print_IO_APICs(void) |
cda417dd | 1372 | { |
6f50d45f | 1373 | int ioapic_idx; |
cda417dd YL |
1374 | unsigned int irq; |
1375 | ||
1376 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1377 | for_each_ioapic(ioapic_idx) |
cda417dd | 1378 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1379 | mpc_ioapic_id(ioapic_idx), |
1380 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1381 | |
1382 | /* | |
1383 | * We are a bit conservative about what we expect. We have to | |
1384 | * know about every hardware change ASAP. | |
1385 | */ | |
1386 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1387 | ||
f44d1692 | 1388 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1389 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1390 | |
1da177e4 | 1391 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1392 | for_each_active_irq(irq) { |
0b8f1efa | 1393 | struct irq_pin_list *entry; |
4467715a JL |
1394 | struct irq_chip *chip; |
1395 | struct mp_chip_data *data; | |
0b8f1efa | 1396 | |
6fd36ba0 | 1397 | chip = irq_get_chip(irq); |
d32932d0 | 1398 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
6fd36ba0 | 1399 | continue; |
4467715a JL |
1400 | data = irq_get_chip_data(irq); |
1401 | if (!data) | |
05e40760 | 1402 | continue; |
4467715a | 1403 | if (list_empty(&data->irq_2_pin)) |
1da177e4 | 1404 | continue; |
4467715a | 1405 | |
8f09cd20 | 1406 | printk(KERN_DEBUG "IRQ%d ", irq); |
4467715a | 1407 | for_each_irq_pin(entry, data->irq_2_pin) |
c767a54b JP |
1408 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1409 | pr_cont("\n"); | |
1da177e4 LT |
1410 | } |
1411 | ||
1412 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1413 | } |
1414 | ||
efa2559f YL |
1415 | /* Where if anywhere is the i8259 connect in external int mode */ |
1416 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1417 | ||
54168ed7 | 1418 | void __init enable_IO_APIC(void) |
1da177e4 | 1419 | { |
fcfd636a | 1420 | int i8259_apic, i8259_pin; |
f44d1692 | 1421 | int apic, pin; |
bc07844a | 1422 | |
a46f5c89 TG |
1423 | if (skip_ioapic_setup) |
1424 | nr_ioapics = 0; | |
1425 | ||
1426 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1427 | return; |
1428 | ||
f44d1692 | 1429 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1430 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1431 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1432 | |
f44d1692 JL |
1433 | /* If the interrupt line is enabled and in ExtInt mode |
1434 | * I have found the pin where the i8259 is connected. | |
1435 | */ | |
1436 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1437 | ioapic_i8259.apic = apic; | |
1438 | ioapic_i8259.pin = pin; | |
1439 | goto found_i8259; | |
fcfd636a EB |
1440 | } |
1441 | } | |
1442 | found_i8259: | |
1443 | /* Look to see what if the MP table has reported the ExtINT */ | |
1444 | /* If we could not find the appropriate pin by looking at the ioapic | |
1445 | * the i8259 probably is not connected the ioapic but give the | |
1446 | * mptable a chance anyway. | |
1447 | */ | |
1448 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1449 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1450 | /* Trust the MP table if nothing is setup in the hardware */ | |
1451 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1452 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1453 | ioapic_i8259.pin = i8259_pin; | |
1454 | ioapic_i8259.apic = i8259_apic; | |
1455 | } | |
1456 | /* Complain if the MP table and the hardware disagree */ | |
1457 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1458 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1459 | { | |
1460 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1461 | } |
1462 | ||
1463 | /* | |
1464 | * Do not trust the IO-APIC being empty at bootup | |
1465 | */ | |
1466 | clear_IO_APIC(); | |
1467 | } | |
1468 | ||
1c4248ca | 1469 | void native_disable_io_apic(void) |
1da177e4 | 1470 | { |
650927ef | 1471 | /* |
0b968d23 | 1472 | * If the i8259 is routed through an IOAPIC |
650927ef | 1473 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1474 | * so legacy interrupts can be delivered. |
650927ef | 1475 | */ |
1c4248ca | 1476 | if (ioapic_i8259.pin != -1) { |
650927ef | 1477 | struct IO_APIC_route_entry entry; |
650927ef EB |
1478 | |
1479 | memset(&entry, 0, sizeof(entry)); | |
1480 | entry.mask = 0; /* Enabled */ | |
1481 | entry.trigger = 0; /* Edge */ | |
1482 | entry.irr = 0; | |
1483 | entry.polarity = 0; /* High */ | |
1484 | entry.delivery_status = 0; | |
1485 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1486 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1487 | entry.vector = 0; |
54168ed7 | 1488 | entry.dest = read_apic_id(); |
650927ef EB |
1489 | |
1490 | /* | |
1491 | * Add it to the IO-APIC irq-routing table: | |
1492 | */ | |
cf4c6a2f | 1493 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1494 | } |
54168ed7 | 1495 | |
1c4248ca JR |
1496 | if (cpu_has_apic || apic_from_smp_config()) |
1497 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1498 | ||
1499 | } | |
1500 | ||
1501 | /* | |
1502 | * Not an __init, needed by the reboot code | |
1503 | */ | |
1504 | void disable_IO_APIC(void) | |
1505 | { | |
7c6d9f97 | 1506 | /* |
1c4248ca | 1507 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1508 | */ |
1c4248ca JR |
1509 | clear_IO_APIC(); |
1510 | ||
95d76acc | 1511 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1512 | return; |
1513 | ||
1514 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1515 | } |
1516 | ||
54168ed7 | 1517 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1518 | /* |
1519 | * function to set the IO-APIC physical IDs based on the | |
1520 | * values stored in the MPC table. | |
1521 | * | |
1522 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1523 | */ | |
a38c5380 | 1524 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1525 | { |
1526 | union IO_APIC_reg_00 reg_00; | |
1527 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1528 | int ioapic_idx; |
1da177e4 LT |
1529 | int i; |
1530 | unsigned char old_id; | |
1531 | unsigned long flags; | |
1532 | ||
1533 | /* | |
1534 | * This is broken; anything with a real cpu count has to | |
1535 | * circumvent this idiocy regardless. | |
1536 | */ | |
7abc0753 | 1537 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1538 | |
1539 | /* | |
1540 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1541 | */ | |
f44d1692 | 1542 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1543 | /* Read the register 0 value */ |
dade7716 | 1544 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1545 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1546 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1547 | |
6f50d45f | 1548 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1549 | |
6f50d45f | 1550 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1551 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1552 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1553 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1554 | reg_00.bits.ID); | |
6f50d45f | 1555 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1556 | } |
1557 | ||
1da177e4 LT |
1558 | /* |
1559 | * Sanity check, is the ID really free? Every APIC in a | |
1560 | * system must have a unique ID or we get lots of nice | |
1561 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1562 | */ | |
7abc0753 | 1563 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1564 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1565 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1566 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1567 | for (i = 0; i < get_physical_broadcast(); i++) |
1568 | if (!physid_isset(i, phys_id_present_map)) | |
1569 | break; | |
1570 | if (i >= get_physical_broadcast()) | |
1571 | panic("Max APIC ID exceeded!\n"); | |
1572 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1573 | i); | |
1574 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1575 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1576 | } else { |
1577 | physid_mask_t tmp; | |
6f50d45f | 1578 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1579 | &tmp); |
1da177e4 LT |
1580 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1581 | "phys_id_present_map\n", | |
6f50d45f | 1582 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1583 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1584 | } | |
1585 | ||
1da177e4 LT |
1586 | /* |
1587 | * We need to adjust the IRQ routing table | |
1588 | * if the ID changed. | |
1589 | */ | |
6f50d45f | 1590 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1591 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1592 | if (mp_irqs[i].dstapic == old_id) |
1593 | mp_irqs[i].dstapic | |
6f50d45f | 1594 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1595 | |
1596 | /* | |
60d79fd9 YL |
1597 | * Update the ID register according to the right value |
1598 | * from the MPC table if they are different. | |
36062448 | 1599 | */ |
6f50d45f | 1600 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1601 | continue; |
1602 | ||
1da177e4 LT |
1603 | apic_printk(APIC_VERBOSE, KERN_INFO |
1604 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1605 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1606 | |
6f50d45f | 1607 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1608 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1609 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1610 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1611 | |
1612 | /* | |
1613 | * Sanity check | |
1614 | */ | |
dade7716 | 1615 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1616 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1617 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1618 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1619 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1620 | else |
1621 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1622 | } | |
1623 | } | |
a38c5380 SAS |
1624 | |
1625 | void __init setup_ioapic_ids_from_mpc(void) | |
1626 | { | |
1627 | ||
1628 | if (acpi_ioapic) | |
1629 | return; | |
1630 | /* | |
1631 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1632 | * no meaning without the serial APIC bus. | |
1633 | */ | |
1634 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1635 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
1636 | return; | |
1637 | setup_ioapic_ids_from_mpc_nocheck(); | |
1638 | } | |
54168ed7 | 1639 | #endif |
1da177e4 | 1640 | |
7ce0bcfd | 1641 | int no_timer_check __initdata; |
8542b200 ZA |
1642 | |
1643 | static int __init notimercheck(char *s) | |
1644 | { | |
1645 | no_timer_check = 1; | |
1646 | return 1; | |
1647 | } | |
1648 | __setup("no_timer_check", notimercheck); | |
1649 | ||
1da177e4 LT |
1650 | /* |
1651 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1652 | * about the timer IRQ. We do the following to work around the situation: | |
1653 | * | |
1654 | * - timer IRQ defaults to IO-APIC IRQ | |
1655 | * - if this function detects that timer IRQs are defunct, then we fall | |
1656 | * back to ISA timer IRQs | |
1657 | */ | |
f0a7a5c9 | 1658 | static int __init timer_irq_works(void) |
1da177e4 LT |
1659 | { |
1660 | unsigned long t1 = jiffies; | |
4aae0702 | 1661 | unsigned long flags; |
1da177e4 | 1662 | |
8542b200 ZA |
1663 | if (no_timer_check) |
1664 | return 1; | |
1665 | ||
4aae0702 | 1666 | local_save_flags(flags); |
1da177e4 LT |
1667 | local_irq_enable(); |
1668 | /* Let ten ticks pass... */ | |
1669 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1670 | local_irq_restore(flags); |
1da177e4 LT |
1671 | |
1672 | /* | |
1673 | * Expect a few ticks at least, to be sure some possible | |
1674 | * glue logic does not lock up after one or two first | |
1675 | * ticks in a non-ExtINT mode. Also the local APIC | |
1676 | * might have cached one ExtINT interrupt. Finally, at | |
1677 | * least one tick may be lost due to delays. | |
1678 | */ | |
54168ed7 IM |
1679 | |
1680 | /* jiffies wrap? */ | |
1d16b53e | 1681 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1682 | return 1; |
1da177e4 LT |
1683 | return 0; |
1684 | } | |
1685 | ||
1686 | /* | |
1687 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1688 | * number of pending IRQ events unhandled. These cases are very rare, | |
1689 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1690 | * better to do it this way as thus we do not have to be aware of | |
1691 | * 'pending' interrupts in the IRQ path, except at this point. | |
1692 | */ | |
1693 | /* | |
1694 | * Edge triggered needs to resend any interrupt | |
1695 | * that was delayed but this is now handled in the device | |
1696 | * independent code. | |
1697 | */ | |
1698 | ||
1699 | /* | |
1700 | * Starting up a edge-triggered IO-APIC interrupt is | |
1701 | * nasty - we need to make sure that we get the edge. | |
1702 | * If it is already asserted for some reason, we need | |
1703 | * return 1 to indicate that is was pending. | |
1704 | * | |
1705 | * This is not complete - we should be able to fake | |
1706 | * an edge even if it isn't on the 8259A... | |
1707 | */ | |
61a38ce3 | 1708 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1709 | { |
61a38ce3 | 1710 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1711 | unsigned long flags; |
1712 | ||
dade7716 | 1713 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1714 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1715 | legacy_pic->mask(irq); |
b81bb373 | 1716 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1717 | was_pending = 1; |
1718 | } | |
4467715a | 1719 | __unmask_ioapic(data->chip_data); |
dade7716 | 1720 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1721 | |
1722 | return was_pending; | |
1723 | } | |
1724 | ||
3eb2cce8 | 1725 | atomic_t irq_mis_count; |
3eb2cce8 | 1726 | |
047c8fdb | 1727 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
4467715a | 1728 | static bool io_apic_level_ack_pending(struct mp_chip_data *data) |
d1ecad6e MN |
1729 | { |
1730 | struct irq_pin_list *entry; | |
1731 | unsigned long flags; | |
1732 | ||
1733 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 1734 | for_each_irq_pin(entry, data->irq_2_pin) { |
d1ecad6e MN |
1735 | unsigned int reg; |
1736 | int pin; | |
1737 | ||
1738 | pin = entry->pin; | |
1739 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
1740 | /* Is the remote IRR bit set? */ | |
1741 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
1742 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1743 | return true; | |
1744 | } | |
1745 | } | |
1746 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1747 | ||
1748 | return false; | |
1749 | } | |
1750 | ||
4467715a | 1751 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a | 1752 | { |
54168ed7 | 1753 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 1754 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
4467715a | 1755 | mask_ioapic_irq(data); |
4da7072a | 1756 | return true; |
54168ed7 | 1757 | } |
4da7072a AG |
1758 | return false; |
1759 | } | |
1760 | ||
4467715a | 1761 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1762 | { |
1763 | if (unlikely(masked)) { | |
1764 | /* Only migrate the irq if the ack has been received. | |
1765 | * | |
1766 | * On rare occasions the broadcast level triggered ack gets | |
1767 | * delayed going to ioapics, and if we reprogram the | |
1768 | * vector while Remote IRR is still set the irq will never | |
1769 | * fire again. | |
1770 | * | |
1771 | * To prevent this scenario we read the Remote IRR bit | |
1772 | * of the ioapic. This has two effects. | |
1773 | * - On any sane system the read of the ioapic will | |
1774 | * flush writes (and acks) going to the ioapic from | |
1775 | * this cpu. | |
1776 | * - We get to see if the ACK has actually been delivered. | |
1777 | * | |
1778 | * Based on failed experiments of reprogramming the | |
1779 | * ioapic entry from outside of irq context starting | |
1780 | * with masking the ioapic entry and then polling until | |
1781 | * Remote IRR was clear before reprogramming the | |
1782 | * ioapic I don't trust the Remote IRR bit to be | |
1783 | * completey accurate. | |
1784 | * | |
1785 | * However there appears to be no other way to plug | |
1786 | * this race, so if the Remote IRR bit is not | |
1787 | * accurate and is causing problems then it is a hardware bug | |
1788 | * and you can go talk to the chipset vendor about it. | |
1789 | */ | |
4467715a | 1790 | if (!io_apic_level_ack_pending(data->chip_data)) |
4da7072a | 1791 | irq_move_masked_irq(data); |
4467715a | 1792 | unmask_ioapic_irq(data); |
4da7072a AG |
1793 | } |
1794 | } | |
1795 | #else | |
4467715a | 1796 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a AG |
1797 | { |
1798 | return false; | |
1799 | } | |
4467715a | 1800 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1801 | { |
1802 | } | |
047c8fdb YL |
1803 | #endif |
1804 | ||
4467715a | 1805 | static void ioapic_ack_level(struct irq_data *irq_data) |
4da7072a | 1806 | { |
4467715a | 1807 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
4da7072a AG |
1808 | unsigned long v; |
1809 | bool masked; | |
d32932d0 | 1810 | int i; |
4da7072a AG |
1811 | |
1812 | irq_complete_move(cfg); | |
4467715a | 1813 | masked = ioapic_irqd_mask(irq_data); |
4da7072a | 1814 | |
3eb2cce8 | 1815 | /* |
916a0fe7 JF |
1816 | * It appears there is an erratum which affects at least version 0x11 |
1817 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1818 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1819 | * erroneously delivered as edge-triggered one but the respective IRR | |
1820 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1821 | * message but it will never arrive and further interrupts are blocked | |
1822 | * from the source. The exact reason is so far unknown, but the | |
1823 | * phenomenon was observed when two consecutive interrupt requests | |
1824 | * from a given source get delivered to the same CPU and the source is | |
1825 | * temporarily disabled in between. | |
1826 | * | |
1827 | * A workaround is to simulate an EOI message manually. We achieve it | |
1828 | * by setting the trigger mode to edge and then to level when the edge | |
1829 | * trigger mode gets detected in the TMR of a local APIC for a | |
1830 | * level-triggered interrupt. We mask the source for the time of the | |
1831 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1832 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
1833 | * |
1834 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
1835 | * any unhandled interrupt on the offlined cpu to the new cpu | |
1836 | * destination that is handling the corresponding interrupt. This | |
1837 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
1838 | * level-triggered io-apic interrupt will be seen as an edge | |
1839 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
1840 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
1841 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
1842 | * supporting EOI register, we do an explicit EOI to clear the | |
1843 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
1844 | * we use the above logic (mask+edge followed by unmask+level) from | |
1845 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 1846 | */ |
3145e941 | 1847 | i = cfg->vector; |
3eb2cce8 | 1848 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 1849 | |
54168ed7 IM |
1850 | /* |
1851 | * We must acknowledge the irq before we move it or the acknowledge will | |
1852 | * not propagate properly. | |
1853 | */ | |
1854 | ack_APIC_irq(); | |
1855 | ||
1c83995b SS |
1856 | /* |
1857 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
1858 | * message via io-apic EOI register write or simulating it using | |
1859 | * mask+edge followed by unnask+level logic) manually when the | |
1860 | * level triggered interrupt is seen as the edge triggered interrupt | |
1861 | * at the cpu. | |
1862 | */ | |
ca64c47c MR |
1863 | if (!(v & (1 << (i & 0x1f)))) { |
1864 | atomic_inc(&irq_mis_count); | |
4467715a | 1865 | eoi_ioapic_pin(cfg->vector, irq_data->chip_data); |
ca64c47c MR |
1866 | } |
1867 | ||
4467715a | 1868 | ioapic_irqd_unmask(irq_data, masked); |
3eb2cce8 | 1869 | } |
1d025192 | 1870 | |
d32932d0 JL |
1871 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
1872 | { | |
1873 | struct mp_chip_data *data = irq_data->chip_data; | |
1874 | ||
1875 | /* | |
1876 | * Intr-remapping uses pin number as the virtual vector | |
1877 | * in the RTE. Actual vector is programmed in | |
1878 | * intr-remapping table entry. Hence for the io-apic | |
1879 | * EOI we use the pin number. | |
1880 | */ | |
1881 | ack_APIC_irq(); | |
4467715a | 1882 | eoi_ioapic_pin(data->entry.vector, data); |
d32932d0 JL |
1883 | } |
1884 | ||
1885 | static int ioapic_set_affinity(struct irq_data *irq_data, | |
1886 | const struct cpumask *mask, bool force) | |
1887 | { | |
1888 | struct irq_data *parent = irq_data->parent_data; | |
1889 | struct mp_chip_data *data = irq_data->chip_data; | |
0be275e3 | 1890 | struct irq_pin_list *entry; |
d32932d0 JL |
1891 | struct irq_cfg *cfg; |
1892 | unsigned long flags; | |
1893 | int ret; | |
1894 | ||
1895 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1896 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1897 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { | |
1898 | cfg = irqd_cfg(irq_data); | |
1899 | data->entry.dest = cfg->dest_apicid; | |
1900 | data->entry.vector = cfg->vector; | |
0be275e3 JL |
1901 | for_each_irq_pin(entry, data->irq_2_pin) |
1902 | __ioapic_write_entry(entry->apic, entry->pin, | |
1903 | data->entry); | |
d32932d0 JL |
1904 | } |
1905 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1906 | ||
1907 | return ret; | |
1908 | } | |
1909 | ||
f5b9ed7a | 1910 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
1911 | .name = "IO-APIC", |
1912 | .irq_startup = startup_ioapic_irq, | |
1913 | .irq_mask = mask_ioapic_irq, | |
1914 | .irq_unmask = unmask_ioapic_irq, | |
d32932d0 JL |
1915 | .irq_ack = irq_chip_ack_parent, |
1916 | .irq_eoi = ioapic_ack_level, | |
1917 | .irq_set_affinity = ioapic_set_affinity, | |
1918 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
1919 | }; | |
1920 | ||
1921 | static struct irq_chip ioapic_ir_chip __read_mostly = { | |
1922 | .name = "IR-IO-APIC", | |
1923 | .irq_startup = startup_ioapic_irq, | |
1924 | .irq_mask = mask_ioapic_irq, | |
1925 | .irq_unmask = unmask_ioapic_irq, | |
1926 | .irq_ack = irq_chip_ack_parent, | |
1927 | .irq_eoi = ioapic_ir_ack_level, | |
1928 | .irq_set_affinity = ioapic_set_affinity, | |
5613570b | 1929 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
1930 | }; |
1931 | ||
1da177e4 LT |
1932 | static inline void init_IO_APIC_traps(void) |
1933 | { | |
da51a821 | 1934 | struct irq_cfg *cfg; |
ad9f4334 | 1935 | unsigned int irq; |
1da177e4 | 1936 | |
ad9f4334 | 1937 | for_each_active_irq(irq) { |
32f5ef5d | 1938 | cfg = irq_cfg(irq); |
0b8f1efa | 1939 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
1940 | /* |
1941 | * Hmm.. We don't have an entry for this, | |
1942 | * so default to an old-fashioned 8259 | |
1943 | * interrupt if we can.. | |
1944 | */ | |
95d76acc | 1945 | if (irq < nr_legacy_irqs()) |
b81bb373 | 1946 | legacy_pic->make_irq(irq); |
0b8f1efa | 1947 | else |
1da177e4 | 1948 | /* Strange. Oh, well.. */ |
2c778651 | 1949 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
1950 | } |
1951 | } | |
1952 | } | |
1953 | ||
f5b9ed7a IM |
1954 | /* |
1955 | * The local APIC irq-chip implementation: | |
1956 | */ | |
1da177e4 | 1957 | |
90297c5f | 1958 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
1959 | { |
1960 | unsigned long v; | |
1961 | ||
1962 | v = apic_read(APIC_LVT0); | |
593f4a78 | 1963 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1964 | } |
1965 | ||
90297c5f | 1966 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 1967 | { |
f5b9ed7a | 1968 | unsigned long v; |
1da177e4 | 1969 | |
f5b9ed7a | 1970 | v = apic_read(APIC_LVT0); |
593f4a78 | 1971 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 1972 | } |
1da177e4 | 1973 | |
90297c5f | 1974 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
1975 | { |
1976 | ack_APIC_irq(); | |
1977 | } | |
1978 | ||
f5b9ed7a | 1979 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 1980 | .name = "local-APIC", |
90297c5f TG |
1981 | .irq_mask = mask_lapic_irq, |
1982 | .irq_unmask = unmask_lapic_irq, | |
1983 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
1984 | }; |
1985 | ||
60c69948 | 1986 | static void lapic_register_intr(int irq) |
c88ac1df | 1987 | { |
60c69948 | 1988 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 1989 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 1990 | "edge"); |
c88ac1df MR |
1991 | } |
1992 | ||
1da177e4 LT |
1993 | /* |
1994 | * This looks a bit hackish but it's about the only one way of sending | |
1995 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1996 | * not support the ExtINT mode, unfortunately. We need to send these | |
1997 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1998 | * 8259A interrupt line asserted until INTA. --macro | |
1999 | */ | |
28acf285 | 2000 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2001 | { |
fcfd636a | 2002 | int apic, pin, i; |
1da177e4 LT |
2003 | struct IO_APIC_route_entry entry0, entry1; |
2004 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2005 | |
fcfd636a | 2006 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2007 | if (pin == -1) { |
2008 | WARN_ON_ONCE(1); | |
2009 | return; | |
2010 | } | |
fcfd636a | 2011 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2012 | if (apic == -1) { |
2013 | WARN_ON_ONCE(1); | |
1da177e4 | 2014 | return; |
956fb531 | 2015 | } |
1da177e4 | 2016 | |
cf4c6a2f | 2017 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2018 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2019 | |
2020 | memset(&entry1, 0, sizeof(entry1)); | |
2021 | ||
2022 | entry1.dest_mode = 0; /* physical delivery */ | |
2023 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2024 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2025 | entry1.delivery_mode = dest_ExtINT; |
2026 | entry1.polarity = entry0.polarity; | |
2027 | entry1.trigger = 0; | |
2028 | entry1.vector = 0; | |
2029 | ||
cf4c6a2f | 2030 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2031 | |
2032 | save_control = CMOS_READ(RTC_CONTROL); | |
2033 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2034 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2035 | RTC_FREQ_SELECT); | |
2036 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2037 | ||
2038 | i = 100; | |
2039 | while (i-- > 0) { | |
2040 | mdelay(10); | |
2041 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2042 | i -= 10; | |
2043 | } | |
2044 | ||
2045 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2046 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2047 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2048 | |
cf4c6a2f | 2049 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2050 | } |
2051 | ||
efa2559f | 2052 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2053 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2054 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2055 | { |
2056 | disable_timer_pin_1 = 1; | |
2057 | return 0; | |
2058 | } | |
54168ed7 | 2059 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2060 | |
d32932d0 JL |
2061 | static int mp_alloc_timer_irq(int ioapic, int pin) |
2062 | { | |
2063 | int irq = -1; | |
d32932d0 JL |
2064 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
2065 | ||
2066 | if (domain) { | |
4467715a JL |
2067 | struct irq_alloc_info info; |
2068 | ||
d32932d0 JL |
2069 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); |
2070 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2071 | info.ioapic_pin = pin; | |
2072 | mutex_lock(&ioapic_mutex); | |
2073 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); | |
2074 | mutex_unlock(&ioapic_mutex); | |
2075 | } | |
2076 | ||
2077 | return irq; | |
2078 | } | |
2079 | ||
1da177e4 LT |
2080 | /* |
2081 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2082 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2083 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2084 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2085 | * |
2086 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2087 | */ |
8542b200 | 2088 | static inline void __init check_timer(void) |
1da177e4 | 2089 | { |
4467715a JL |
2090 | struct irq_data *irq_data = irq_get_irq_data(0); |
2091 | struct mp_chip_data *data = irq_data->chip_data; | |
2092 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
f6e9456c | 2093 | int node = cpu_to_node(0); |
fcfd636a | 2094 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2095 | unsigned long flags; |
047c8fdb | 2096 | int no_pin1 = 0; |
4aae0702 IM |
2097 | |
2098 | local_irq_save(flags); | |
d4d25dec | 2099 | |
1da177e4 LT |
2100 | /* |
2101 | * get/set the timer IRQ vector: | |
2102 | */ | |
4305df94 | 2103 | legacy_pic->mask(0); |
1da177e4 LT |
2104 | |
2105 | /* | |
d11d5794 MR |
2106 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2107 | * wire has to be disabled in the local APIC. Also | |
2108 | * timer interrupts need to be acknowledged manually in | |
2109 | * the 8259A for the i82489DX when using the NMI | |
2110 | * watchdog as that APIC treats NMIs as level-triggered. | |
2111 | * The AEOI mode will finish them in the 8259A | |
2112 | * automatically. | |
1da177e4 | 2113 | */ |
593f4a78 | 2114 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2115 | legacy_pic->init(1); |
1da177e4 | 2116 | |
fcfd636a EB |
2117 | pin1 = find_isa_irq_pin(0, mp_INT); |
2118 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2119 | pin2 = ioapic_i8259.pin; | |
2120 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2121 | |
49a66a0b MR |
2122 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2123 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2124 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2125 | |
691874fa MR |
2126 | /* |
2127 | * Some BIOS writers are clueless and report the ExtINTA | |
2128 | * I/O APIC input from the cascaded 8259A as the timer | |
2129 | * interrupt input. So just in case, if only one pin | |
2130 | * was found above, try it both directly and through the | |
2131 | * 8259A. | |
2132 | */ | |
2133 | if (pin1 == -1) { | |
6a9f5de2 | 2134 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2135 | pin1 = pin2; |
2136 | apic1 = apic2; | |
2137 | no_pin1 = 1; | |
2138 | } else if (pin2 == -1) { | |
2139 | pin2 = pin1; | |
2140 | apic2 = apic1; | |
2141 | } | |
2142 | ||
1da177e4 | 2143 | if (pin1 != -1) { |
d32932d0 | 2144 | /* Ok, does IRQ0 through the IOAPIC work? */ |
691874fa | 2145 | if (no_pin1) { |
d32932d0 | 2146 | mp_alloc_timer_irq(apic1, pin1); |
f72dccac | 2147 | } else { |
d32932d0 JL |
2148 | /* |
2149 | * for edge trigger, it's already unmasked, | |
f72dccac YL |
2150 | * so only need to unmask if it is level-trigger |
2151 | * do we really have level trigger timer? | |
2152 | */ | |
2153 | int idx; | |
2154 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2155 | if (idx != -1 && irq_trigger(idx)) | |
4467715a | 2156 | unmask_ioapic_irq(irq_get_chip_data(0)); |
691874fa | 2157 | } |
4467715a | 2158 | irq_domain_activate_irq(irq_data); |
1da177e4 | 2159 | if (timer_irq_works()) { |
66759a01 CE |
2160 | if (disable_timer_pin_1 > 0) |
2161 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2162 | goto out; |
1da177e4 | 2163 | } |
6a9f5de2 | 2164 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2165 | local_irq_disable(); |
fcfd636a | 2166 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2167 | if (!no_pin1) |
49a66a0b MR |
2168 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2169 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2170 | |
49a66a0b MR |
2171 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2172 | "(IRQ0) through the 8259A ...\n"); | |
2173 | apic_printk(APIC_QUIET, KERN_INFO | |
2174 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2175 | /* |
2176 | * legacy devices should be connected to IO APIC #0 | |
2177 | */ | |
4467715a JL |
2178 | replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2); |
2179 | irq_domain_activate_irq(irq_data); | |
4305df94 | 2180 | legacy_pic->unmask(0); |
1da177e4 | 2181 | if (timer_irq_works()) { |
49a66a0b | 2182 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2183 | goto out; |
1da177e4 LT |
2184 | } |
2185 | /* | |
2186 | * Cleanup, just in case ... | |
2187 | */ | |
f72dccac | 2188 | local_irq_disable(); |
4305df94 | 2189 | legacy_pic->mask(0); |
fcfd636a | 2190 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2191 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2192 | } |
1da177e4 | 2193 | |
49a66a0b MR |
2194 | apic_printk(APIC_QUIET, KERN_INFO |
2195 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2196 | |
60c69948 | 2197 | lapic_register_intr(0); |
497c9a19 | 2198 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2199 | legacy_pic->unmask(0); |
1da177e4 LT |
2200 | |
2201 | if (timer_irq_works()) { | |
49a66a0b | 2202 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2203 | goto out; |
1da177e4 | 2204 | } |
f72dccac | 2205 | local_irq_disable(); |
4305df94 | 2206 | legacy_pic->mask(0); |
497c9a19 | 2207 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2208 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2209 | |
49a66a0b MR |
2210 | apic_printk(APIC_QUIET, KERN_INFO |
2211 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2212 | |
b81bb373 JP |
2213 | legacy_pic->init(0); |
2214 | legacy_pic->make_irq(0); | |
593f4a78 | 2215 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2216 | |
2217 | unlock_ExtINT_logic(); | |
2218 | ||
2219 | if (timer_irq_works()) { | |
49a66a0b | 2220 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2221 | goto out; |
1da177e4 | 2222 | } |
f72dccac | 2223 | local_irq_disable(); |
49a66a0b | 2224 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2225 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2226 | apic_printk(APIC_QUIET, KERN_INFO |
2227 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2228 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2229 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2230 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2231 | out: |
2232 | local_irq_restore(flags); | |
1da177e4 LT |
2233 | } |
2234 | ||
2235 | /* | |
af174783 MR |
2236 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2237 | * to devices. However there may be an I/O APIC pin available for | |
2238 | * this interrupt regardless. The pin may be left unconnected, but | |
2239 | * typically it will be reused as an ExtINT cascade interrupt for | |
2240 | * the master 8259A. In the MPS case such a pin will normally be | |
2241 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2242 | * there is no provision for ExtINT interrupts, and in the absence | |
2243 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2244 | * interrupt, that is edge-triggered and unmasked by default. We | |
2245 | * used to do this, but it caused problems on some systems because | |
2246 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2247 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2248 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2249 | * the I/O APIC in all cases now. No actual device should request | |
2250 | * it anyway. --macro | |
1da177e4 | 2251 | */ |
bc07844a | 2252 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2253 | |
44767bfa JL |
2254 | static int mp_irqdomain_create(int ioapic) |
2255 | { | |
d32932d0 JL |
2256 | struct irq_alloc_info info; |
2257 | struct irq_domain *parent; | |
44767bfa JL |
2258 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2259 | struct ioapic *ip = &ioapics[ioapic]; | |
2260 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2261 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2262 | ||
2263 | if (cfg->type == IOAPIC_DOMAIN_INVALID) | |
2264 | return 0; | |
2265 | ||
d32932d0 JL |
2266 | init_irq_alloc_info(&info, NULL); |
2267 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
2268 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2269 | parent = irq_remapping_get_ir_irq_domain(&info); | |
2270 | if (!parent) | |
2271 | parent = x86_vector_domain; | |
2272 | ||
44767bfa JL |
2273 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, |
2274 | (void *)(long)ioapic); | |
b75e818f | 2275 | if (!ip->irqdomain) |
44767bfa | 2276 | return -ENOMEM; |
b75e818f JL |
2277 | |
2278 | ip->irqdomain->parent = parent; | |
44767bfa JL |
2279 | |
2280 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2281 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2282 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2283 | gsi_cfg->gsi_end + 1); | |
2284 | ||
44767bfa JL |
2285 | return 0; |
2286 | } | |
2287 | ||
15516a3b JL |
2288 | static void ioapic_destroy_irqdomain(int idx) |
2289 | { | |
2290 | if (ioapics[idx].irqdomain) { | |
2291 | irq_domain_remove(ioapics[idx].irqdomain); | |
2292 | ioapics[idx].irqdomain = NULL; | |
2293 | } | |
15516a3b JL |
2294 | } |
2295 | ||
1da177e4 LT |
2296 | void __init setup_IO_APIC(void) |
2297 | { | |
44767bfa | 2298 | int ioapic; |
54168ed7 | 2299 | |
a46f5c89 TG |
2300 | if (skip_ioapic_setup || !nr_ioapics) |
2301 | return; | |
2302 | ||
95d76acc | 2303 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2304 | |
54168ed7 | 2305 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2306 | for_each_ioapic(ioapic) |
2307 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2308 | ||
d6c88a50 | 2309 | /* |
54168ed7 IM |
2310 | * Set up IO-APIC IRQ routing. |
2311 | */ | |
de934103 TG |
2312 | x86_init.mpparse.setup_ioapic_ids(); |
2313 | ||
1da177e4 LT |
2314 | sync_Arb_IDs(); |
2315 | setup_IO_APIC_irqs(); | |
2316 | init_IO_APIC_traps(); | |
95d76acc | 2317 | if (nr_legacy_irqs()) |
bc07844a | 2318 | check_timer(); |
b81975ea JL |
2319 | |
2320 | ioapic_initialized = 1; | |
1da177e4 LT |
2321 | } |
2322 | ||
2323 | /* | |
0d2eb44f | 2324 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2325 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2326 | */ |
36062448 | 2327 | |
1da177e4 LT |
2328 | static int __init io_apic_bug_finalize(void) |
2329 | { | |
d6c88a50 TG |
2330 | if (sis_apic_bug == -1) |
2331 | sis_apic_bug = 0; | |
2332 | return 0; | |
1da177e4 LT |
2333 | } |
2334 | ||
2335 | late_initcall(io_apic_bug_finalize); | |
2336 | ||
6f50d45f | 2337 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2338 | { |
1da177e4 LT |
2339 | unsigned long flags; |
2340 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2341 | |
dade7716 | 2342 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2343 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2344 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2345 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2346 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2347 | } |
dade7716 | 2348 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2349 | } |
1da177e4 | 2350 | |
f3c6ea1b RW |
2351 | static void ioapic_resume(void) |
2352 | { | |
6f50d45f | 2353 | int ioapic_idx; |
f3c6ea1b | 2354 | |
f44d1692 | 2355 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2356 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2357 | |
2358 | restore_ioapic_entries(); | |
1da177e4 LT |
2359 | } |
2360 | ||
f3c6ea1b | 2361 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2362 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2363 | .resume = ioapic_resume, |
2364 | }; | |
2365 | ||
f3c6ea1b | 2366 | static int __init ioapic_init_ops(void) |
1da177e4 | 2367 | { |
f3c6ea1b RW |
2368 | register_syscore_ops(&ioapic_syscore_ops); |
2369 | ||
1da177e4 LT |
2370 | return 0; |
2371 | } | |
2372 | ||
f3c6ea1b | 2373 | device_initcall(ioapic_init_ops); |
1da177e4 | 2374 | |
67dc5e70 | 2375 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2376 | { |
2377 | union IO_APIC_reg_01 reg_01; | |
2378 | unsigned long flags; | |
2379 | ||
dade7716 | 2380 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2381 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2382 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2383 | |
4b6b19a1 EB |
2384 | /* The register returns the maximum index redir index |
2385 | * supported, which is one less than the total number of redir | |
2386 | * entries. | |
2387 | */ | |
2388 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2389 | } |
2390 | ||
62a08ae2 TG |
2391 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2392 | { | |
b81975ea JL |
2393 | /* |
2394 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2395 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2396 | */ | |
2397 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2398 | } |
2399 | ||
54168ed7 | 2400 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2401 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2402 | { |
2403 | union IO_APIC_reg_00 reg_00; | |
2404 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2405 | physid_mask_t tmp; | |
2406 | unsigned long flags; | |
2407 | int i = 0; | |
2408 | ||
2409 | /* | |
36062448 PC |
2410 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2411 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2412 | * supports up to 16 on one shared APIC bus. |
36062448 | 2413 | * |
1da177e4 LT |
2414 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2415 | * advantage of new APIC bus architecture. | |
2416 | */ | |
2417 | ||
2418 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2419 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2420 | |
dade7716 | 2421 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2422 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2423 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2424 | |
2425 | if (apic_id >= get_physical_broadcast()) { | |
2426 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2427 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2428 | apic_id = reg_00.bits.ID; | |
2429 | } | |
2430 | ||
2431 | /* | |
36062448 | 2432 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2433 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2434 | */ | |
7abc0753 | 2435 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2436 | |
2437 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2438 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2439 | break; |
2440 | } | |
2441 | ||
2442 | if (i == get_physical_broadcast()) | |
2443 | panic("Max apic_id exceeded!\n"); | |
2444 | ||
2445 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2446 | "trying %d\n", ioapic, apic_id, i); | |
2447 | ||
2448 | apic_id = i; | |
36062448 | 2449 | } |
1da177e4 | 2450 | |
7abc0753 | 2451 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2452 | physids_or(apic_id_map, apic_id_map, tmp); |
2453 | ||
2454 | if (reg_00.bits.ID != apic_id) { | |
2455 | reg_00.bits.ID = apic_id; | |
2456 | ||
dade7716 | 2457 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2458 | io_apic_write(ioapic, 0, reg_00.raw); |
2459 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2460 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2461 | |
2462 | /* Sanity check */ | |
6070f9ec | 2463 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2464 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2465 | ioapic); | |
6070f9ec AD |
2466 | return -1; |
2467 | } | |
1da177e4 LT |
2468 | } |
2469 | ||
2470 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2471 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2472 | ||
2473 | return apic_id; | |
2474 | } | |
41098ffe | 2475 | |
67dc5e70 | 2476 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2477 | { |
2478 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
2479 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
5411dc4c | 2480 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2481 | else |
2482 | return id; | |
2483 | } | |
2484 | #else | |
67dc5e70 | 2485 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2486 | { |
5411dc4c | 2487 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2488 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2489 | unsigned long flags; |
2490 | u8 new_id; | |
2491 | int i; | |
41098ffe TG |
2492 | |
2493 | bitmap_zero(used, 256); | |
f44d1692 | 2494 | for_each_ioapic(i) |
d5371430 | 2495 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2496 | |
2497 | /* Hand out the requested id if available */ | |
41098ffe TG |
2498 | if (!test_bit(id, used)) |
2499 | return id; | |
5411dc4c YL |
2500 | |
2501 | /* | |
2502 | * Read the current id from the ioapic and keep it if | |
2503 | * available. | |
2504 | */ | |
2505 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2506 | reg_00.raw = io_apic_read(idx, 0); | |
2507 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2508 | new_id = reg_00.bits.ID; | |
2509 | if (!test_bit(new_id, used)) { | |
2510 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2511 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2512 | idx, new_id, id); | |
2513 | return new_id; | |
2514 | } | |
2515 | ||
2516 | /* | |
2517 | * Get the next free id and write it to the ioapic. | |
2518 | */ | |
2519 | new_id = find_first_zero_bit(used, 256); | |
2520 | reg_00.bits.ID = new_id; | |
2521 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2522 | io_apic_write(idx, 0, reg_00.raw); | |
2523 | reg_00.raw = io_apic_read(idx, 0); | |
2524 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2525 | /* Sanity check */ | |
2526 | BUG_ON(reg_00.bits.ID != new_id); | |
2527 | ||
2528 | return new_id; | |
41098ffe | 2529 | } |
58f892e0 | 2530 | #endif |
1da177e4 | 2531 | |
67dc5e70 | 2532 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2533 | { |
2534 | union IO_APIC_reg_01 reg_01; | |
2535 | unsigned long flags; | |
2536 | ||
dade7716 | 2537 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2538 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2539 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2540 | |
2541 | return reg_01.bits.version; | |
2542 | } | |
2543 | ||
9a0a91bb | 2544 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2545 | { |
9a0a91bb | 2546 | int ioapic, pin, idx; |
61fd47e0 SL |
2547 | |
2548 | if (skip_ioapic_setup) | |
2549 | return -1; | |
2550 | ||
9a0a91bb EB |
2551 | ioapic = mp_find_ioapic(gsi); |
2552 | if (ioapic < 0) | |
61fd47e0 SL |
2553 | return -1; |
2554 | ||
9a0a91bb EB |
2555 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2556 | if (pin < 0) | |
2557 | return -1; | |
2558 | ||
2559 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2560 | if (idx < 0) | |
61fd47e0 SL |
2561 | return -1; |
2562 | ||
9a0a91bb EB |
2563 | *trigger = irq_trigger(idx); |
2564 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2565 | return 0; |
2566 | } | |
2567 | ||
497c9a19 YL |
2568 | /* |
2569 | * This function currently is only a helper for the i386 smp boot process where | |
2570 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2571 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2572 | */ |
2573 | #ifdef CONFIG_SMP | |
2574 | void __init setup_ioapic_dest(void) | |
2575 | { | |
fad53995 | 2576 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2577 | const struct cpumask *mask; |
5451ddc5 | 2578 | struct irq_data *idata; |
497c9a19 YL |
2579 | |
2580 | if (skip_ioapic_setup == 1) | |
2581 | return; | |
2582 | ||
f44d1692 | 2583 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2584 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2585 | if (irq_entry == -1) | |
2586 | continue; | |
6c2e9403 | 2587 | |
d7f3d478 JL |
2588 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2589 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2590 | continue; |
2591 | ||
5451ddc5 | 2592 | idata = irq_get_irq_data(irq); |
6c2e9403 | 2593 | |
b9c61b70 YL |
2594 | /* |
2595 | * Honour affinities which have been set in early boot | |
2596 | */ | |
5451ddc5 TG |
2597 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
2598 | mask = idata->affinity; | |
b9c61b70 YL |
2599 | else |
2600 | mask = apic->target_cpus(); | |
497c9a19 | 2601 | |
aa5cb97f | 2602 | irq_set_affinity(irq, mask); |
497c9a19 | 2603 | } |
b9c61b70 | 2604 | |
497c9a19 YL |
2605 | } |
2606 | #endif | |
2607 | ||
54168ed7 IM |
2608 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2609 | ||
2610 | static struct resource *ioapic_resources; | |
2611 | ||
f44d1692 | 2612 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2613 | { |
2614 | unsigned long n; | |
2615 | struct resource *res; | |
2616 | char *mem; | |
f44d1692 | 2617 | int i, num = 0; |
54168ed7 | 2618 | |
f44d1692 JL |
2619 | for_each_ioapic(i) |
2620 | num++; | |
2621 | if (num == 0) | |
54168ed7 IM |
2622 | return NULL; |
2623 | ||
2624 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 2625 | n *= num; |
54168ed7 IM |
2626 | |
2627 | mem = alloc_bootmem(n); | |
2628 | res = (void *)mem; | |
2629 | ||
f44d1692 | 2630 | mem += sizeof(struct resource) * num; |
54168ed7 | 2631 | |
f44d1692 JL |
2632 | num = 0; |
2633 | for_each_ioapic(i) { | |
2634 | res[num].name = mem; | |
2635 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2636 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2637 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 2638 | num++; |
15516a3b | 2639 | ioapics[i].iomem_res = res; |
54168ed7 IM |
2640 | } |
2641 | ||
2642 | ioapic_resources = res; | |
2643 | ||
2644 | return res; | |
2645 | } | |
54168ed7 | 2646 | |
ca1b8862 | 2647 | void __init io_apic_init_mappings(void) |
f3294a33 YL |
2648 | { |
2649 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2650 | struct resource *ioapic_res; |
d6c88a50 | 2651 | int i; |
f3294a33 | 2652 | |
f44d1692 JL |
2653 | ioapic_res = ioapic_setup_resources(); |
2654 | for_each_ioapic(i) { | |
f3294a33 | 2655 | if (smp_found_config) { |
d5371430 | 2656 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2657 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2658 | if (!ioapic_phys) { |
2659 | printk(KERN_ERR | |
2660 | "WARNING: bogus zero IO-APIC " | |
2661 | "address found in MPTABLE, " | |
2662 | "disabling IO/APIC support!\n"); | |
2663 | smp_found_config = 0; | |
2664 | skip_ioapic_setup = 1; | |
2665 | goto fake_ioapic_page; | |
2666 | } | |
54168ed7 | 2667 | #endif |
f3294a33 | 2668 | } else { |
54168ed7 | 2669 | #ifdef CONFIG_X86_32 |
f3294a33 | 2670 | fake_ioapic_page: |
54168ed7 | 2671 | #endif |
e79c65a9 | 2672 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2673 | ioapic_phys = __pa(ioapic_phys); |
2674 | } | |
2675 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2676 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2677 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2678 | ioapic_phys); | |
f3294a33 | 2679 | idx++; |
54168ed7 | 2680 | |
ffc43836 | 2681 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2682 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2683 | ioapic_res++; |
f3294a33 YL |
2684 | } |
2685 | } | |
2686 | ||
857fdc53 | 2687 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2688 | { |
2689 | int i; | |
2690 | struct resource *r = ioapic_resources; | |
2691 | ||
2692 | if (!r) { | |
857fdc53 | 2693 | if (nr_ioapics > 0) |
04c93ce4 BZ |
2694 | printk(KERN_ERR |
2695 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 2696 | return; |
54168ed7 IM |
2697 | } |
2698 | ||
f44d1692 | 2699 | for_each_ioapic(i) { |
54168ed7 IM |
2700 | insert_resource(&iomem_resource, r); |
2701 | r++; | |
2702 | } | |
54168ed7 | 2703 | } |
2a4ab640 | 2704 | |
eddb0c55 | 2705 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 2706 | { |
f44d1692 | 2707 | int i; |
2a4ab640 | 2708 | |
678301ec PB |
2709 | if (nr_ioapics == 0) |
2710 | return -1; | |
2711 | ||
2a4ab640 | 2712 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 2713 | for_each_ioapic(i) { |
c040aaeb | 2714 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 2715 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
2716 | return i; |
2717 | } | |
54168ed7 | 2718 | |
2a4ab640 FT |
2719 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
2720 | return -1; | |
2721 | } | |
2722 | ||
eddb0c55 | 2723 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 2724 | { |
c040aaeb SS |
2725 | struct mp_ioapic_gsi *gsi_cfg; |
2726 | ||
f44d1692 | 2727 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 2728 | return -1; |
c040aaeb SS |
2729 | |
2730 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2731 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
2732 | return -1; |
2733 | ||
c040aaeb | 2734 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
2735 | } |
2736 | ||
67dc5e70 | 2737 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
2738 | { |
2739 | union IO_APIC_reg_00 reg_00; | |
2740 | union IO_APIC_reg_01 reg_01; | |
2741 | union IO_APIC_reg_02 reg_02; | |
2742 | ||
2743 | reg_00.raw = io_apic_read(idx, 0); | |
2744 | reg_01.raw = io_apic_read(idx, 1); | |
2745 | reg_02.raw = io_apic_read(idx, 2); | |
2746 | ||
2747 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
2748 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
2749 | mpc_ioapic_addr(idx)); | |
2750 | return 1; | |
2751 | } | |
2752 | ||
2753 | return 0; | |
2754 | } | |
2755 | ||
35ef9c94 JL |
2756 | static int find_free_ioapic_entry(void) |
2757 | { | |
7db298cb JL |
2758 | int idx; |
2759 | ||
2760 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
2761 | if (ioapics[idx].nr_registers == 0) | |
2762 | return idx; | |
2763 | ||
2764 | return MAX_IO_APICS; | |
35ef9c94 JL |
2765 | } |
2766 | ||
2767 | /** | |
2768 | * mp_register_ioapic - Register an IOAPIC device | |
2769 | * @id: hardware IOAPIC ID | |
2770 | * @address: physical address of IOAPIC register area | |
2771 | * @gsi_base: base of GSI associated with the IOAPIC | |
2772 | * @cfg: configuration information for the IOAPIC | |
2773 | */ | |
2774 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
2775 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 2776 | { |
7db298cb | 2777 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 2778 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
2779 | int idx, ioapic, entries; |
2780 | u32 gsi_end; | |
2a4ab640 | 2781 | |
35ef9c94 JL |
2782 | if (!address) { |
2783 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
2784 | return -EINVAL; | |
2785 | } | |
2786 | for_each_ioapic(ioapic) | |
2787 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
2788 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
2789 | address, ioapic); | |
2790 | return -EEXIST; | |
2791 | } | |
2a4ab640 | 2792 | |
35ef9c94 JL |
2793 | idx = find_free_ioapic_entry(); |
2794 | if (idx >= MAX_IO_APICS) { | |
2795 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
2796 | MAX_IO_APICS, idx); | |
2797 | return -ENOSPC; | |
2798 | } | |
2a4ab640 | 2799 | |
d5371430 SS |
2800 | ioapics[idx].mp_config.type = MP_IOAPIC; |
2801 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
2802 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
2803 | |
2804 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
2805 | if (bad_ioapic_register(idx)) { |
2806 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 2807 | return -ENODEV; |
73d63d03 SS |
2808 | } |
2809 | ||
5411dc4c | 2810 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 2811 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
2812 | |
2813 | /* | |
2814 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
2815 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
2816 | */ | |
7716a5c4 | 2817 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
2818 | gsi_end = gsi_base + entries - 1; |
2819 | for_each_ioapic(ioapic) { | |
2820 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2821 | if ((gsi_base >= gsi_cfg->gsi_base && | |
2822 | gsi_base <= gsi_cfg->gsi_end) || | |
2823 | (gsi_end >= gsi_cfg->gsi_base && | |
2824 | gsi_end <= gsi_cfg->gsi_end)) { | |
2825 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
2826 | gsi_base, gsi_end, | |
2827 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2828 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2829 | return -ENOSPC; | |
2830 | } | |
2831 | } | |
c040aaeb SS |
2832 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
2833 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 2834 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 2835 | |
35ef9c94 JL |
2836 | ioapics[idx].irqdomain = NULL; |
2837 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 2838 | |
7db298cb JL |
2839 | /* |
2840 | * If mp_register_ioapic() is called during early boot stage when | |
2841 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
2842 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
2843 | */ | |
2844 | if (hotplug) { | |
2845 | if (mp_irqdomain_create(idx)) { | |
2846 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2847 | return -ENOMEM; | |
2848 | } | |
2849 | alloc_ioapic_saved_registers(idx); | |
2850 | } | |
2851 | ||
c040aaeb SS |
2852 | if (gsi_cfg->gsi_end >= gsi_top) |
2853 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
2854 | if (nr_ioapics <= idx) |
2855 | nr_ioapics = idx + 1; | |
2856 | ||
2857 | /* Set nr_registers to mark entry present */ | |
2858 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 2859 | |
73d63d03 SS |
2860 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
2861 | idx, mpc_ioapic_id(idx), | |
2862 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
2863 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 2864 | |
35ef9c94 | 2865 | return 0; |
2a4ab640 | 2866 | } |
05ddafb1 | 2867 | |
15516a3b JL |
2868 | int mp_unregister_ioapic(u32 gsi_base) |
2869 | { | |
2870 | int ioapic, pin; | |
2871 | int found = 0; | |
15516a3b JL |
2872 | |
2873 | for_each_ioapic(ioapic) | |
2874 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
2875 | found = 1; | |
2876 | break; | |
2877 | } | |
2878 | if (!found) { | |
2879 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
2880 | return -ENODEV; | |
2881 | } | |
2882 | ||
2883 | for_each_pin(ioapic, pin) { | |
d32932d0 JL |
2884 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
2885 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); | |
2886 | struct mp_chip_data *data; | |
2887 | ||
2888 | if (irq >= 0) { | |
2889 | data = irq_get_chip_data(irq); | |
2890 | if (data && data->count) { | |
2891 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
2892 | pin, ioapic); | |
2893 | return -EBUSY; | |
2894 | } | |
15516a3b JL |
2895 | } |
2896 | } | |
2897 | ||
2898 | /* Mark entry not present */ | |
2899 | ioapics[ioapic].nr_registers = 0; | |
2900 | ioapic_destroy_irqdomain(ioapic); | |
2901 | free_ioapic_saved_registers(ioapic); | |
2902 | if (ioapics[ioapic].iomem_res) | |
2903 | release_resource(ioapics[ioapic].iomem_res); | |
2904 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
2905 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
2906 | ||
2907 | return 0; | |
2908 | } | |
2909 | ||
e89900c9 JL |
2910 | int mp_ioapic_registered(u32 gsi_base) |
2911 | { | |
2912 | int ioapic; | |
2913 | ||
2914 | for_each_ioapic(ioapic) | |
2915 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
2916 | return 1; | |
2917 | ||
2918 | return 0; | |
2919 | } | |
2920 | ||
49c7e600 | 2921 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
5ad274d4 | 2922 | struct irq_alloc_info *info) |
49c7e600 JL |
2923 | { |
2924 | if (info && info->ioapic_valid) { | |
2925 | data->trigger = info->ioapic_trigger; | |
2926 | data->polarity = info->ioapic_polarity; | |
2927 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
2928 | &data->polarity) < 0) { | |
2929 | /* PCI interrupts are always polarity one level triggered. */ | |
2930 | data->trigger = 1; | |
2931 | data->polarity = 1; | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
2936 | struct IO_APIC_route_entry *entry) | |
2937 | { | |
2938 | memset(entry, 0, sizeof(*entry)); | |
2939 | entry->delivery_mode = apic->irq_delivery_mode; | |
2940 | entry->dest_mode = apic->irq_dest_mode; | |
2941 | entry->dest = cfg->dest_apicid; | |
2942 | entry->vector = cfg->vector; | |
2943 | entry->mask = 0; /* enable IRQ */ | |
2944 | entry->trigger = data->trigger; | |
2945 | entry->polarity = data->polarity; | |
2946 | /* | |
2947 | * Mask level triggered irqs. | |
2948 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
2949 | */ | |
2950 | if (data->trigger) | |
2951 | entry->mask = 1; | |
2952 | } | |
2953 | ||
2954 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
2955 | unsigned int nr_irqs, void *arg) | |
2956 | { | |
2957 | int ret, ioapic, pin; | |
2958 | struct irq_cfg *cfg; | |
2959 | struct irq_data *irq_data; | |
2960 | struct mp_chip_data *data; | |
2961 | struct irq_alloc_info *info = arg; | |
2962 | ||
2963 | if (!info || nr_irqs > 1) | |
2964 | return -EINVAL; | |
2965 | irq_data = irq_domain_get_irq_data(domain, virq); | |
2966 | if (!irq_data) | |
2967 | return -EINVAL; | |
2968 | ||
2969 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
2970 | pin = info->ioapic_pin; | |
2971 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
2972 | return -EEXIST; | |
2973 | ||
2974 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
2975 | if (!data) | |
2976 | return -ENOMEM; | |
2977 | ||
2978 | info->ioapic_entry = &data->entry; | |
2979 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
2980 | if (ret < 0) { | |
2981 | kfree(data); | |
2982 | return ret; | |
2983 | } | |
2984 | ||
4467715a | 2985 | INIT_LIST_HEAD(&data->irq_2_pin); |
49c7e600 | 2986 | irq_data->hwirq = info->ioapic_pin; |
d32932d0 JL |
2987 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
2988 | &ioapic_chip : &ioapic_ir_chip; | |
49c7e600 JL |
2989 | irq_data->chip_data = data; |
2990 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
2991 | ||
2992 | cfg = irqd_cfg(irq_data); | |
4467715a | 2993 | add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); |
49c7e600 JL |
2994 | if (info->ioapic_entry) |
2995 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
2996 | mp_register_handler(virq, data->trigger); | |
2997 | if (virq < nr_legacy_irqs()) | |
2998 | legacy_pic->mask(virq); | |
2999 | ||
3000 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
3001 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
3002 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
3003 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
3008 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
3009 | unsigned int nr_irqs) | |
3010 | { | |
49c7e600 | 3011 | struct irq_data *irq_data; |
4467715a | 3012 | struct mp_chip_data *data; |
49c7e600 JL |
3013 | |
3014 | BUG_ON(nr_irqs != 1); | |
3015 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3016 | if (irq_data && irq_data->chip_data) { | |
4467715a JL |
3017 | data = irq_data->chip_data; |
3018 | __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), | |
49c7e600 | 3019 | (int)irq_data->hwirq); |
4467715a | 3020 | WARN_ON(!list_empty(&data->irq_2_pin)); |
49c7e600 JL |
3021 | kfree(irq_data->chip_data); |
3022 | } | |
3023 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
3024 | } | |
3025 | ||
3026 | void mp_irqdomain_activate(struct irq_domain *domain, | |
3027 | struct irq_data *irq_data) | |
3028 | { | |
3029 | unsigned long flags; | |
3030 | struct irq_pin_list *entry; | |
3031 | struct mp_chip_data *data = irq_data->chip_data; | |
49c7e600 JL |
3032 | |
3033 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 3034 | for_each_irq_pin(entry, data->irq_2_pin) |
49c7e600 JL |
3035 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); |
3036 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
3037 | } | |
3038 | ||
3039 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
3040 | struct irq_data *irq_data) | |
3041 | { | |
3042 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
3043 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
3044 | (int)irq_data->hwirq); | |
3045 | } | |
3046 | ||
49c7e600 JL |
3047 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) |
3048 | { | |
3049 | return (int)(long)domain->host_data; | |
3050 | } |