Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
d7f3d478 | 34 | #include <linux/irqdomain.h> |
7dfb7103 | 35 | #include <linux/freezer.h> |
f26d6a2b | 36 | #include <linux/kthread.h> |
54168ed7 | 37 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 38 | #include <linux/slab.h> |
d4057bdb | 39 | #include <linux/bootmem.h> |
54d5d424 | 40 | |
d4057bdb | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
6d652ea1 | 44 | #include <asm/cpu.h> |
1da177e4 | 45 | #include <asm/desc.h> |
d4057bdb YL |
46 | #include <asm/proto.h> |
47 | #include <asm/acpi.h> | |
48 | #include <asm/dma.h> | |
1da177e4 | 49 | #include <asm/timer.h> |
306e440d | 50 | #include <asm/i8259.h> |
a4dbc34d | 51 | #include <asm/setup.h> |
8a8f422d | 52 | #include <asm/irq_remapping.h> |
2c1b284e | 53 | #include <asm/hw_irq.h> |
1da177e4 | 54 | |
7b6aa335 | 55 | #include <asm/apic.h> |
1da177e4 | 56 | |
f44d1692 JL |
57 | #define for_each_ioapic(idx) \ |
58 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
59 | #define for_each_ioapic_reverse(idx) \ | |
60 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
61 | #define for_each_pin(idx, pin) \ | |
62 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
63 | #define for_each_ioapic_pin(idx, pin) \ | |
64 | for_each_ioapic((idx)) \ | |
65 | for_each_pin((idx), (pin)) | |
66 | ||
2977fb3f | 67 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 68 | list_for_each_entry(entry, &head, list) |
32f71aff | 69 | |
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
dade7716 | 76 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 77 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 78 | static unsigned int ioapic_dynirq_base; |
b81975ea | 79 | static int ioapic_initialized; |
efa2559f | 80 | |
4467715a JL |
81 | struct irq_pin_list { |
82 | struct list_head list; | |
83 | int apic, pin; | |
84 | }; | |
85 | ||
49c7e600 | 86 | struct mp_chip_data { |
4467715a | 87 | struct list_head irq_2_pin; |
49c7e600 JL |
88 | struct IO_APIC_route_entry entry; |
89 | int trigger; | |
90 | int polarity; | |
96ed44b2 | 91 | u32 count; |
49c7e600 JL |
92 | bool isa_irq; |
93 | }; | |
94 | ||
b69c6c3b SS |
95 | static struct ioapic { |
96 | /* | |
97 | * # of IRQ routing registers | |
98 | */ | |
99 | int nr_registers; | |
57a6f740 SS |
100 | /* |
101 | * Saved state during suspend/resume, or while enabling intr-remap. | |
102 | */ | |
103 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
104 | /* I/O APIC config */ |
105 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
106 | /* IO APIC gsi routing info */ |
107 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
108 | struct ioapic_domain_cfg irqdomain_cfg; |
109 | struct irq_domain *irqdomain; | |
15516a3b | 110 | struct resource *iomem_res; |
b69c6c3b | 111 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 112 | |
6f50d45f | 113 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 114 | |
6f50d45f | 115 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 116 | { |
6f50d45f | 117 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
118 | } |
119 | ||
6f50d45f | 120 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 121 | { |
6f50d45f | 122 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
123 | } |
124 | ||
6f50d45f | 125 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 126 | { |
6f50d45f | 127 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 128 | } |
9f640ccb | 129 | |
18e48551 JL |
130 | static inline int mp_ioapic_pin_count(int ioapic) |
131 | { | |
132 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
133 | ||
134 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
135 | } | |
136 | ||
137 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
138 | { | |
139 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
140 | } | |
141 | ||
d32932d0 JL |
142 | static inline bool mp_is_legacy_irq(int irq) |
143 | { | |
144 | return irq >= 0 && irq < nr_legacy_irqs(); | |
145 | } | |
146 | ||
95d76acc JL |
147 | /* |
148 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
149 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
150 | * may rely on non-legacy pins on the first IOAPIC. | |
151 | */ | |
18e48551 JL |
152 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
153 | { | |
95d76acc JL |
154 | if (!nr_legacy_irqs()) |
155 | return 0; | |
156 | ||
d32932d0 | 157 | return ioapic == 0 || mp_is_legacy_irq(irq); |
18e48551 JL |
158 | } |
159 | ||
d7f3d478 JL |
160 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
161 | { | |
162 | return ioapics[ioapic].irqdomain; | |
163 | } | |
164 | ||
c040aaeb | 165 | int nr_ioapics; |
2a4ab640 | 166 | |
a4384df3 EB |
167 | /* The one past the highest gsi number used */ |
168 | u32 gsi_top; | |
5777372a | 169 | |
584f734d | 170 | /* MP IRQ source entries */ |
c2c21745 | 171 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
172 | |
173 | /* # of MP IRQ source entries */ | |
174 | int mp_irq_entries; | |
175 | ||
bb8187d3 | 176 | #ifdef CONFIG_EISA |
8732fc4b AS |
177 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
178 | #endif | |
179 | ||
180 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
181 | ||
efa2559f YL |
182 | int skip_ioapic_setup; |
183 | ||
7167d08e HK |
184 | /** |
185 | * disable_ioapic_support() - disables ioapic support at runtime | |
186 | */ | |
187 | void disable_ioapic_support(void) | |
65a4e574 IM |
188 | { |
189 | #ifdef CONFIG_PCI | |
190 | noioapicquirk = 1; | |
191 | noioapicreroute = -1; | |
192 | #endif | |
193 | skip_ioapic_setup = 1; | |
194 | } | |
195 | ||
54168ed7 | 196 | static int __init parse_noapic(char *str) |
efa2559f YL |
197 | { |
198 | /* disable IO-APIC */ | |
7167d08e | 199 | disable_ioapic_support(); |
efa2559f YL |
200 | return 0; |
201 | } | |
202 | early_param("noapic", parse_noapic); | |
66759a01 | 203 | |
2d8009ba FT |
204 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
205 | void mp_save_irq(struct mpc_intsrc *m) | |
206 | { | |
207 | int i; | |
208 | ||
209 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
210 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
211 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
212 | m->srcbusirq, m->dstapic, m->dstirq); | |
213 | ||
214 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 215 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
216 | return; |
217 | } | |
218 | ||
0e3fa13f | 219 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
220 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
221 | panic("Max # of irq sources exceeded!!\n"); | |
222 | } | |
223 | ||
7e899419 YL |
224 | static void alloc_ioapic_saved_registers(int idx) |
225 | { | |
226 | size_t size; | |
227 | ||
228 | if (ioapics[idx].saved_registers) | |
229 | return; | |
230 | ||
231 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
232 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
233 | if (!ioapics[idx].saved_registers) | |
234 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
235 | } | |
236 | ||
15516a3b JL |
237 | static void free_ioapic_saved_registers(int idx) |
238 | { | |
239 | kfree(ioapics[idx].saved_registers); | |
240 | ioapics[idx].saved_registers = NULL; | |
241 | } | |
242 | ||
11d686e9 | 243 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 244 | { |
13315320 | 245 | int i; |
d6c88a50 | 246 | |
95d76acc | 247 | if (!nr_legacy_irqs()) |
1f91233c | 248 | io_apic_irqs = ~0UL; |
1f91233c | 249 | |
7e899419 YL |
250 | for_each_ioapic(i) |
251 | alloc_ioapic_saved_registers(i); | |
4c79185c | 252 | |
13a0c3c2 | 253 | return 0; |
0b8f1efa | 254 | } |
8f09cd20 | 255 | |
130fe05d LT |
256 | struct io_apic { |
257 | unsigned int index; | |
258 | unsigned int unused[3]; | |
259 | unsigned int data; | |
0280f7c4 SS |
260 | unsigned int unused2[11]; |
261 | unsigned int eoi; | |
130fe05d LT |
262 | }; |
263 | ||
264 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
265 | { | |
266 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 267 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
268 | } |
269 | ||
ad66e1ef | 270 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
271 | { |
272 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
273 | writel(vector, &io_apic->eoi); | |
274 | } | |
275 | ||
4a8e2a31 | 276 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
277 | { |
278 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
279 | writel(reg, &io_apic->index); | |
280 | return readl(&io_apic->data); | |
281 | } | |
282 | ||
4a8e2a31 | 283 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
284 | { |
285 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 286 | |
130fe05d LT |
287 | writel(reg, &io_apic->index); |
288 | writel(value, &io_apic->data); | |
289 | } | |
290 | ||
291 | /* | |
292 | * Re-write a value: to be used for read-modify-write | |
293 | * cycles where the read already set up the index register. | |
294 | * | |
295 | * Older SiS APIC requires we rewrite the index register | |
296 | */ | |
4a8e2a31 | 297 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 298 | { |
54168ed7 | 299 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
300 | |
301 | if (sis_apic_bug) | |
302 | writel(reg, &io_apic->index); | |
130fe05d LT |
303 | writel(value, &io_apic->data); |
304 | } | |
305 | ||
cf4c6a2f AK |
306 | union entry_union { |
307 | struct { u32 w1, w2; }; | |
308 | struct IO_APIC_route_entry entry; | |
309 | }; | |
310 | ||
e57253a8 SS |
311 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
312 | { | |
313 | union entry_union eu; | |
314 | ||
315 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
316 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 317 | |
e57253a8 SS |
318 | return eu.entry; |
319 | } | |
320 | ||
cf4c6a2f AK |
321 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
322 | { | |
323 | union entry_union eu; | |
324 | unsigned long flags; | |
136d249e | 325 | |
dade7716 | 326 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 327 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 328 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 329 | |
cf4c6a2f AK |
330 | return eu.entry; |
331 | } | |
332 | ||
f9dadfa7 LT |
333 | /* |
334 | * When we write a new IO APIC routing entry, we need to write the high | |
335 | * word first! If the mask bit in the low word is clear, we will enable | |
336 | * the interrupt, and we need to make sure the entry is fully populated | |
337 | * before that happens. | |
338 | */ | |
136d249e | 339 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 340 | { |
50a8d4d2 F |
341 | union entry_union eu = {{0, 0}}; |
342 | ||
cf4c6a2f | 343 | eu.entry = e; |
f9dadfa7 LT |
344 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
345 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
346 | } |
347 | ||
1a8ce7ff | 348 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
349 | { |
350 | unsigned long flags; | |
136d249e | 351 | |
dade7716 | 352 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 353 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 354 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
355 | } |
356 | ||
357 | /* | |
358 | * When we mask an IO APIC routing entry, we need to write the low | |
359 | * word first, in order to set the mask bit before we change the | |
360 | * high bits! | |
361 | */ | |
362 | static void ioapic_mask_entry(int apic, int pin) | |
363 | { | |
364 | unsigned long flags; | |
365 | union entry_union eu = { .entry.mask = 1 }; | |
366 | ||
dade7716 | 367 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
368 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
369 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 370 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
371 | } |
372 | ||
1da177e4 LT |
373 | /* |
374 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
375 | * shared ISA-space IRQs, so we have to support them. We are super | |
376 | * fast in the common case, and fast for shared ISA-space IRQs. | |
377 | */ | |
4467715a JL |
378 | static int __add_pin_to_irq_node(struct mp_chip_data *data, |
379 | int node, int apic, int pin) | |
1da177e4 | 380 | { |
a178b87b | 381 | struct irq_pin_list *entry; |
0f978f45 | 382 | |
2977fb3f | 383 | /* don't allow duplicates */ |
4467715a | 384 | for_each_irq_pin(entry, data->irq_2_pin) |
0f978f45 | 385 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 386 | return 0; |
0f978f45 | 387 | |
4467715a | 388 | entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
a7428cd2 | 389 | if (!entry) { |
c767a54b JP |
390 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
391 | node, apic, pin); | |
f3d1915a | 392 | return -ENOMEM; |
a7428cd2 | 393 | } |
1da177e4 LT |
394 | entry->apic = apic; |
395 | entry->pin = pin; | |
4467715a | 396 | list_add_tail(&entry->list, &data->irq_2_pin); |
875e68ec | 397 | |
f3d1915a CG |
398 | return 0; |
399 | } | |
400 | ||
4467715a | 401 | static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) |
df334bea | 402 | { |
a178b87b | 403 | struct irq_pin_list *tmp, *entry; |
df334bea | 404 | |
4467715a | 405 | list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) |
df334bea | 406 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 407 | list_del(&entry->list); |
df334bea JL |
408 | kfree(entry); |
409 | return; | |
df334bea JL |
410 | } |
411 | } | |
412 | ||
4467715a JL |
413 | static void add_pin_to_irq_node(struct mp_chip_data *data, |
414 | int node, int apic, int pin) | |
f3d1915a | 415 | { |
4467715a | 416 | if (__add_pin_to_irq_node(data, node, apic, pin)) |
f3d1915a | 417 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
418 | } |
419 | ||
420 | /* | |
421 | * Reroute an IRQ to a different pin. | |
422 | */ | |
4467715a | 423 | static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, |
4eea6fff JF |
424 | int oldapic, int oldpin, |
425 | int newapic, int newpin) | |
1da177e4 | 426 | { |
535b6429 | 427 | struct irq_pin_list *entry; |
1da177e4 | 428 | |
4467715a | 429 | for_each_irq_pin(entry, data->irq_2_pin) { |
1da177e4 LT |
430 | if (entry->apic == oldapic && entry->pin == oldpin) { |
431 | entry->apic = newapic; | |
432 | entry->pin = newpin; | |
0f978f45 | 433 | /* every one is different, right? */ |
4eea6fff | 434 | return; |
0f978f45 | 435 | } |
1da177e4 | 436 | } |
0f978f45 | 437 | |
4eea6fff | 438 | /* old apic/pin didn't exist, so just add new ones */ |
4467715a | 439 | add_pin_to_irq_node(data, node, newapic, newpin); |
1da177e4 LT |
440 | } |
441 | ||
c29d9db3 SS |
442 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
443 | int mask_and, int mask_or, | |
444 | void (*final)(struct irq_pin_list *entry)) | |
445 | { | |
446 | unsigned int reg, pin; | |
447 | ||
448 | pin = entry->pin; | |
449 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
450 | reg &= mask_and; | |
451 | reg |= mask_or; | |
452 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
453 | if (final) | |
454 | final(entry); | |
455 | } | |
456 | ||
4467715a | 457 | static void io_apic_modify_irq(struct mp_chip_data *data, |
2f210deb JF |
458 | int mask_and, int mask_or, |
459 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 460 | { |
87783be4 | 461 | struct irq_pin_list *entry; |
047c8fdb | 462 | |
4467715a | 463 | for_each_irq_pin(entry, data->irq_2_pin) |
c29d9db3 SS |
464 | __io_apic_modify_irq(entry, mask_and, mask_or, final); |
465 | } | |
466 | ||
7f3e632f | 467 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 468 | { |
87783be4 CG |
469 | /* |
470 | * Synchronize the IO-APIC and the CPU by doing | |
471 | * a dummy read from the IO-APIC | |
472 | */ | |
473 | struct io_apic __iomem *io_apic; | |
136d249e | 474 | |
87783be4 | 475 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 476 | readl(&io_apic->data); |
1da177e4 LT |
477 | } |
478 | ||
4467715a | 479 | static void mask_ioapic_irq(struct irq_data *irq_data) |
87783be4 | 480 | { |
4467715a | 481 | struct mp_chip_data *data = irq_data->chip_data; |
dd5f15e5 TG |
482 | unsigned long flags; |
483 | ||
484 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 485 | io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 486 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 487 | } |
1da177e4 | 488 | |
4467715a | 489 | static void __unmask_ioapic(struct mp_chip_data *data) |
dd5f15e5 | 490 | { |
4467715a | 491 | io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL); |
1da177e4 LT |
492 | } |
493 | ||
4467715a | 494 | static void unmask_ioapic_irq(struct irq_data *irq_data) |
1da177e4 | 495 | { |
4467715a | 496 | struct mp_chip_data *data = irq_data->chip_data; |
1da177e4 LT |
497 | unsigned long flags; |
498 | ||
dade7716 | 499 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
4467715a | 500 | __unmask_ioapic(data); |
dade7716 | 501 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
502 | } |
503 | ||
c0205701 SS |
504 | /* |
505 | * IO-APIC versions below 0x20 don't support EOI register. | |
506 | * For the record, here is the information about various versions: | |
507 | * 0Xh 82489DX | |
508 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
509 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
510 | * 30h-FFh Reserved | |
511 | * | |
512 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
513 | * version as 0x2. This is an error with documentation and these ICH chips | |
514 | * use io-apic's of version 0x20. | |
515 | * | |
516 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
517 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
518 | * mode to edge and then back to level, with RTE being masked during this. | |
519 | */ | |
ad66e1ef | 520 | static void __eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
521 | { |
522 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 523 | io_apic_eoi(apic, vector); |
c0205701 SS |
524 | } else { |
525 | struct IO_APIC_route_entry entry, entry1; | |
526 | ||
527 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
528 | ||
529 | /* | |
530 | * Mask the entry and change the trigger mode to edge. | |
531 | */ | |
532 | entry1.mask = 1; | |
533 | entry1.trigger = IOAPIC_EDGE; | |
534 | ||
535 | __ioapic_write_entry(apic, pin, entry1); | |
536 | ||
537 | /* | |
538 | * Restore the previous level triggered entry. | |
539 | */ | |
540 | __ioapic_write_entry(apic, pin, entry); | |
541 | } | |
542 | } | |
543 | ||
4467715a | 544 | void eoi_ioapic_pin(int vector, struct mp_chip_data *data) |
d32932d0 JL |
545 | { |
546 | unsigned long flags; | |
547 | struct irq_pin_list *entry; | |
548 | ||
549 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 550 | for_each_irq_pin(entry, data->irq_2_pin) |
ad66e1ef | 551 | __eoi_ioapic_pin(entry->apic, entry->pin, vector); |
c0205701 SS |
552 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
553 | } | |
554 | ||
1da177e4 LT |
555 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
556 | { | |
557 | struct IO_APIC_route_entry entry; | |
36062448 | 558 | |
1da177e4 | 559 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 560 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
561 | if (entry.delivery_mode == dest_SMI) |
562 | return; | |
1e75b31d | 563 | |
1da177e4 | 564 | /* |
1e75b31d SS |
565 | * Make sure the entry is masked and re-read the contents to check |
566 | * if it is a level triggered pin and if the remote-IRR is set. | |
567 | */ | |
568 | if (!entry.mask) { | |
569 | entry.mask = 1; | |
570 | ioapic_write_entry(apic, pin, entry); | |
571 | entry = ioapic_read_entry(apic, pin); | |
572 | } | |
573 | ||
574 | if (entry.irr) { | |
c0205701 SS |
575 | unsigned long flags; |
576 | ||
1e75b31d SS |
577 | /* |
578 | * Make sure the trigger mode is set to level. Explicit EOI | |
579 | * doesn't clear the remote-IRR if the trigger mode is not | |
580 | * set to level. | |
581 | */ | |
582 | if (!entry.trigger) { | |
583 | entry.trigger = IOAPIC_LEVEL; | |
584 | ioapic_write_entry(apic, pin, entry); | |
585 | } | |
c0205701 | 586 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
ad66e1ef | 587 | __eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 588 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
589 | } |
590 | ||
591 | /* | |
592 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
593 | * bit. | |
1da177e4 | 594 | */ |
f9dadfa7 | 595 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
596 | entry = ioapic_read_entry(apic, pin); |
597 | if (entry.irr) | |
c767a54b | 598 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 599 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
600 | } |
601 | ||
54168ed7 | 602 | static void clear_IO_APIC (void) |
1da177e4 LT |
603 | { |
604 | int apic, pin; | |
605 | ||
f44d1692 JL |
606 | for_each_ioapic_pin(apic, pin) |
607 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
608 | } |
609 | ||
54168ed7 | 610 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
611 | /* |
612 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
613 | * specific CPU-side IRQs. | |
614 | */ | |
615 | ||
616 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
617 | static int pirq_entries[MAX_PIRQS] = { |
618 | [0 ... MAX_PIRQS - 1] = -1 | |
619 | }; | |
1da177e4 | 620 | |
1da177e4 LT |
621 | static int __init ioapic_pirq_setup(char *str) |
622 | { | |
623 | int i, max; | |
624 | int ints[MAX_PIRQS+1]; | |
625 | ||
626 | get_options(str, ARRAY_SIZE(ints), ints); | |
627 | ||
1da177e4 LT |
628 | apic_printk(APIC_VERBOSE, KERN_INFO |
629 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
630 | max = MAX_PIRQS; | |
631 | if (ints[0] < MAX_PIRQS) | |
632 | max = ints[0]; | |
633 | ||
634 | for (i = 0; i < max; i++) { | |
635 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
636 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
637 | /* | |
638 | * PIRQs are mapped upside down, usually. | |
639 | */ | |
640 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
641 | } | |
642 | return 1; | |
643 | } | |
644 | ||
645 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
646 | #endif /* CONFIG_X86_32 */ |
647 | ||
54168ed7 | 648 | /* |
05c3dc2c | 649 | * Saves all the IO-APIC RTE's |
54168ed7 | 650 | */ |
31dce14a | 651 | int save_ioapic_entries(void) |
54168ed7 | 652 | { |
54168ed7 | 653 | int apic, pin; |
31dce14a | 654 | int err = 0; |
54168ed7 | 655 | |
f44d1692 | 656 | for_each_ioapic(apic) { |
57a6f740 | 657 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
658 | err = -ENOMEM; |
659 | continue; | |
660 | } | |
54168ed7 | 661 | |
f44d1692 | 662 | for_each_pin(apic, pin) |
57a6f740 | 663 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 664 | ioapic_read_entry(apic, pin); |
b24696bc | 665 | } |
5ffa4eb2 | 666 | |
31dce14a | 667 | return err; |
54168ed7 IM |
668 | } |
669 | ||
b24696bc FY |
670 | /* |
671 | * Mask all IO APIC entries. | |
672 | */ | |
31dce14a | 673 | void mask_ioapic_entries(void) |
05c3dc2c SS |
674 | { |
675 | int apic, pin; | |
676 | ||
f44d1692 | 677 | for_each_ioapic(apic) { |
2f344d2e | 678 | if (!ioapics[apic].saved_registers) |
31dce14a | 679 | continue; |
b24696bc | 680 | |
f44d1692 | 681 | for_each_pin(apic, pin) { |
05c3dc2c SS |
682 | struct IO_APIC_route_entry entry; |
683 | ||
57a6f740 | 684 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
685 | if (!entry.mask) { |
686 | entry.mask = 1; | |
687 | ioapic_write_entry(apic, pin, entry); | |
688 | } | |
689 | } | |
690 | } | |
691 | } | |
692 | ||
b24696bc | 693 | /* |
57a6f740 | 694 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 695 | */ |
31dce14a | 696 | int restore_ioapic_entries(void) |
54168ed7 IM |
697 | { |
698 | int apic, pin; | |
699 | ||
f44d1692 | 700 | for_each_ioapic(apic) { |
2f344d2e | 701 | if (!ioapics[apic].saved_registers) |
31dce14a | 702 | continue; |
b24696bc | 703 | |
f44d1692 | 704 | for_each_pin(apic, pin) |
54168ed7 | 705 | ioapic_write_entry(apic, pin, |
57a6f740 | 706 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 707 | } |
b24696bc | 708 | return 0; |
54168ed7 IM |
709 | } |
710 | ||
1da177e4 LT |
711 | /* |
712 | * Find the IRQ entry number of a certain pin. | |
713 | */ | |
6f50d45f | 714 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
715 | { |
716 | int i; | |
717 | ||
718 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 719 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 720 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
721 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
722 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
723 | return i; |
724 | ||
725 | return -1; | |
726 | } | |
727 | ||
728 | /* | |
729 | * Find the pin to which IRQ[irq] (ISA) is connected | |
730 | */ | |
fcfd636a | 731 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
732 | { |
733 | int i; | |
734 | ||
735 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 736 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 737 | |
d27e2b8e | 738 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
739 | (mp_irqs[i].irqtype == type) && |
740 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 741 | |
c2c21745 | 742 | return mp_irqs[i].dstirq; |
1da177e4 LT |
743 | } |
744 | return -1; | |
745 | } | |
746 | ||
fcfd636a EB |
747 | static int __init find_isa_irq_apic(int irq, int type) |
748 | { | |
749 | int i; | |
750 | ||
751 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 752 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 753 | |
73b2961b | 754 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
755 | (mp_irqs[i].irqtype == type) && |
756 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
757 | break; |
758 | } | |
6f50d45f | 759 | |
fcfd636a | 760 | if (i < mp_irq_entries) { |
6f50d45f YL |
761 | int ioapic_idx; |
762 | ||
f44d1692 | 763 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
764 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
765 | return ioapic_idx; | |
fcfd636a EB |
766 | } |
767 | ||
768 | return -1; | |
769 | } | |
770 | ||
bb8187d3 | 771 | #ifdef CONFIG_EISA |
1da177e4 LT |
772 | /* |
773 | * EISA Edge/Level control register, ELCR | |
774 | */ | |
775 | static int EISA_ELCR(unsigned int irq) | |
776 | { | |
95d76acc | 777 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
778 | unsigned int port = 0x4d0 + (irq >> 3); |
779 | return (inb(port) >> (irq & 7)) & 1; | |
780 | } | |
781 | apic_printk(APIC_VERBOSE, KERN_INFO | |
782 | "Broken MPtable reports ISA irq %d\n", irq); | |
783 | return 0; | |
784 | } | |
54168ed7 | 785 | |
c0a282c2 | 786 | #endif |
1da177e4 | 787 | |
6728801d AS |
788 | /* ISA interrupts are always polarity zero edge triggered, |
789 | * when listed as conforming in the MP table. */ | |
790 | ||
791 | #define default_ISA_trigger(idx) (0) | |
792 | #define default_ISA_polarity(idx) (0) | |
793 | ||
1da177e4 LT |
794 | /* EISA interrupts are always polarity zero and can be edge or level |
795 | * trigger depending on the ELCR value. If an interrupt is listed as | |
796 | * EISA conforming in the MP table, that means its trigger type must | |
797 | * be read in from the ELCR */ | |
798 | ||
c2c21745 | 799 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 800 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
801 | |
802 | /* PCI interrupts are always polarity one level triggered, | |
803 | * when listed as conforming in the MP table. */ | |
804 | ||
805 | #define default_PCI_trigger(idx) (1) | |
806 | #define default_PCI_polarity(idx) (1) | |
807 | ||
b77cf6a8 | 808 | static int irq_polarity(int idx) |
1da177e4 | 809 | { |
c2c21745 | 810 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
811 | int polarity; |
812 | ||
813 | /* | |
814 | * Determine IRQ line polarity (high active or low active): | |
815 | */ | |
c2c21745 | 816 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 817 | { |
54168ed7 IM |
818 | case 0: /* conforms, ie. bus-type dependent polarity */ |
819 | if (test_bit(bus, mp_bus_not_pci)) | |
820 | polarity = default_ISA_polarity(idx); | |
821 | else | |
822 | polarity = default_PCI_polarity(idx); | |
823 | break; | |
824 | case 1: /* high active */ | |
825 | { | |
826 | polarity = 0; | |
827 | break; | |
828 | } | |
829 | case 2: /* reserved */ | |
830 | { | |
c767a54b | 831 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
832 | polarity = 1; |
833 | break; | |
834 | } | |
835 | case 3: /* low active */ | |
836 | { | |
837 | polarity = 1; | |
838 | break; | |
839 | } | |
840 | default: /* invalid */ | |
841 | { | |
c767a54b | 842 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
843 | polarity = 1; |
844 | break; | |
845 | } | |
1da177e4 LT |
846 | } |
847 | return polarity; | |
848 | } | |
849 | ||
b77cf6a8 | 850 | static int irq_trigger(int idx) |
1da177e4 | 851 | { |
c2c21745 | 852 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
853 | int trigger; |
854 | ||
855 | /* | |
856 | * Determine IRQ trigger mode (edge or level sensitive): | |
857 | */ | |
c2c21745 | 858 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 859 | { |
54168ed7 IM |
860 | case 0: /* conforms, ie. bus-type dependent */ |
861 | if (test_bit(bus, mp_bus_not_pci)) | |
862 | trigger = default_ISA_trigger(idx); | |
863 | else | |
864 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 865 | #ifdef CONFIG_EISA |
54168ed7 IM |
866 | switch (mp_bus_id_to_type[bus]) { |
867 | case MP_BUS_ISA: /* ISA pin */ | |
868 | { | |
869 | /* set before the switch */ | |
870 | break; | |
871 | } | |
872 | case MP_BUS_EISA: /* EISA pin */ | |
873 | { | |
874 | trigger = default_EISA_trigger(idx); | |
875 | break; | |
876 | } | |
877 | case MP_BUS_PCI: /* PCI pin */ | |
878 | { | |
879 | /* set before the switch */ | |
880 | break; | |
881 | } | |
54168ed7 IM |
882 | default: |
883 | { | |
c767a54b | 884 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
885 | trigger = 1; |
886 | break; | |
887 | } | |
888 | } | |
889 | #endif | |
1da177e4 | 890 | break; |
54168ed7 | 891 | case 1: /* edge */ |
1da177e4 | 892 | { |
54168ed7 | 893 | trigger = 0; |
1da177e4 LT |
894 | break; |
895 | } | |
54168ed7 | 896 | case 2: /* reserved */ |
1da177e4 | 897 | { |
c767a54b | 898 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 899 | trigger = 1; |
1da177e4 LT |
900 | break; |
901 | } | |
54168ed7 | 902 | case 3: /* level */ |
1da177e4 | 903 | { |
54168ed7 | 904 | trigger = 1; |
1da177e4 LT |
905 | break; |
906 | } | |
54168ed7 | 907 | default: /* invalid */ |
1da177e4 | 908 | { |
c767a54b | 909 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 910 | trigger = 0; |
1da177e4 LT |
911 | break; |
912 | } | |
913 | } | |
914 | return trigger; | |
915 | } | |
916 | ||
c4d05a2c JL |
917 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
918 | int trigger, int polarity) | |
919 | { | |
920 | init_irq_alloc_info(info, NULL); | |
921 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
922 | info->ioapic_node = node; | |
923 | info->ioapic_trigger = trigger; | |
924 | info->ioapic_polarity = polarity; | |
925 | info->ioapic_valid = 1; | |
926 | } | |
927 | ||
96ed44b2 JL |
928 | #ifndef CONFIG_ACPI |
929 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); | |
930 | #endif | |
931 | ||
932 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, | |
933 | struct irq_alloc_info *src, | |
934 | u32 gsi, int ioapic_idx, int pin) | |
935 | { | |
936 | int trigger, polarity; | |
937 | ||
938 | copy_irq_alloc_info(dst, src); | |
939 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
940 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); | |
941 | dst->ioapic_pin = pin; | |
942 | dst->ioapic_valid = 1; | |
943 | if (src && src->ioapic_valid) { | |
944 | dst->ioapic_node = src->ioapic_node; | |
945 | dst->ioapic_trigger = src->ioapic_trigger; | |
946 | dst->ioapic_polarity = src->ioapic_polarity; | |
947 | } else { | |
948 | dst->ioapic_node = NUMA_NO_NODE; | |
949 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { | |
950 | dst->ioapic_trigger = trigger; | |
951 | dst->ioapic_polarity = polarity; | |
952 | } else { | |
953 | /* | |
954 | * PCI interrupts are always polarity one level | |
955 | * triggered. | |
956 | */ | |
957 | dst->ioapic_trigger = 1; | |
958 | dst->ioapic_polarity = 1; | |
959 | } | |
960 | } | |
961 | } | |
962 | ||
963 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) | |
964 | { | |
965 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; | |
966 | } | |
967 | ||
49c7e600 JL |
968 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
969 | { | |
970 | irq_flow_handler_t hdl; | |
971 | bool fasteoi; | |
972 | ||
973 | if (trigger) { | |
974 | irq_set_status_flags(irq, IRQ_LEVEL); | |
975 | fasteoi = true; | |
976 | } else { | |
977 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
978 | fasteoi = false; | |
979 | } | |
980 | ||
981 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
982 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
983 | } | |
984 | ||
96ed44b2 JL |
985 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
986 | { | |
987 | struct mp_chip_data *data = irq_get_chip_data(irq); | |
988 | ||
989 | /* | |
990 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger | |
991 | * and polarity attirbutes. So allow the first user to reprogram the | |
992 | * pin with real trigger and polarity attributes. | |
993 | */ | |
994 | if (irq < nr_legacy_irqs() && data->count == 1) { | |
995 | if (info->ioapic_trigger != data->trigger) | |
996 | mp_register_handler(irq, data->trigger); | |
997 | data->entry.trigger = data->trigger = info->ioapic_trigger; | |
998 | data->entry.polarity = data->polarity = info->ioapic_polarity; | |
999 | } | |
1000 | ||
1001 | return data->trigger == info->ioapic_trigger && | |
1002 | data->polarity == info->ioapic_polarity; | |
1003 | } | |
1004 | ||
d32932d0 | 1005 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
c4d05a2c | 1006 | struct irq_alloc_info *info) |
6b9fb708 | 1007 | { |
d32932d0 | 1008 | bool legacy = false; |
d7f3d478 | 1009 | int irq = -1; |
d7f3d478 JL |
1010 | int type = ioapics[ioapic].irqdomain_cfg.type; |
1011 | ||
1012 | switch (type) { | |
1013 | case IOAPIC_DOMAIN_LEGACY: | |
1014 | /* | |
d32932d0 JL |
1015 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
1016 | * 16 GSIs on some weird platforms. | |
d7f3d478 | 1017 | */ |
d32932d0 | 1018 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
d7f3d478 | 1019 | irq = gsi; |
d32932d0 | 1020 | legacy = mp_is_legacy_irq(irq); |
d7f3d478 JL |
1021 | break; |
1022 | case IOAPIC_DOMAIN_STRICT: | |
d32932d0 | 1023 | irq = gsi; |
d7f3d478 JL |
1024 | break; |
1025 | case IOAPIC_DOMAIN_DYNAMIC: | |
d7f3d478 JL |
1026 | break; |
1027 | default: | |
1028 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
d32932d0 JL |
1029 | return -1; |
1030 | } | |
1031 | ||
1032 | return __irq_domain_alloc_irqs(domain, irq, 1, | |
1033 | ioapic_alloc_attr_node(info), | |
1034 | info, legacy); | |
1035 | } | |
1036 | ||
1037 | /* | |
1038 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins | |
1039 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping | |
1040 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are | |
1041 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
1042 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and | |
1043 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for | |
1044 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be | |
1045 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. | |
1046 | */ | |
1047 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, | |
1048 | int irq, int ioapic, int pin, | |
1049 | struct irq_alloc_info *info) | |
1050 | { | |
1051 | struct mp_chip_data *data; | |
1052 | struct irq_data *irq_data = irq_get_irq_data(irq); | |
1053 | int node = ioapic_alloc_attr_node(info); | |
1054 | ||
1055 | /* | |
1056 | * Legacy ISA IRQ has already been allocated, just add pin to | |
1057 | * the pin list assoicated with this IRQ and program the IOAPIC | |
1058 | * entry. The IOAPIC entry | |
1059 | */ | |
1060 | if (irq_data && irq_data->parent_data) { | |
d32932d0 JL |
1061 | if (!mp_check_pin_attr(irq, info)) |
1062 | return -EBUSY; | |
4467715a JL |
1063 | if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, |
1064 | info->ioapic_pin)) | |
d32932d0 JL |
1065 | return -ENOMEM; |
1066 | } else { | |
1067 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true); | |
1068 | if (irq >= 0) { | |
1069 | irq_data = irq_domain_get_irq_data(domain, irq); | |
1070 | data = irq_data->chip_data; | |
1071 | data->isa_irq = true; | |
1072 | } | |
d7f3d478 JL |
1073 | } |
1074 | ||
d32932d0 | 1075 | return irq; |
d7f3d478 JL |
1076 | } |
1077 | ||
1078 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 1079 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1080 | { |
1081 | int irq; | |
d32932d0 JL |
1082 | bool legacy = false; |
1083 | struct irq_alloc_info tmp; | |
1084 | struct mp_chip_data *data; | |
d7f3d478 JL |
1085 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
1086 | ||
b81975ea | 1087 | if (!domain) |
d32932d0 | 1088 | return -ENOSYS; |
16ee7b3d | 1089 | |
16ee7b3d JL |
1090 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1091 | irq = mp_irqs[idx].srcbusirq; | |
d32932d0 JL |
1092 | legacy = mp_is_legacy_irq(irq); |
1093 | } | |
16ee7b3d | 1094 | |
d32932d0 JL |
1095 | mutex_lock(&ioapic_mutex); |
1096 | if (!(flags & IOAPIC_MAP_ALLOC)) { | |
1097 | if (!legacy) { | |
1098 | irq = irq_find_mapping(domain, pin); | |
16ee7b3d | 1099 | if (irq == 0) |
d32932d0 | 1100 | irq = -ENOENT; |
16ee7b3d JL |
1101 | } |
1102 | } else { | |
d32932d0 JL |
1103 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
1104 | if (legacy) | |
1105 | irq = alloc_isa_irq_from_domain(domain, irq, | |
1106 | ioapic, pin, &tmp); | |
1107 | else if ((irq = irq_find_mapping(domain, pin)) == 0) | |
1108 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); | |
1109 | else if (!mp_check_pin_attr(irq, &tmp)) | |
1110 | irq = -EBUSY; | |
1111 | if (irq >= 0) { | |
1112 | data = irq_get_chip_data(irq); | |
1113 | data->count++; | |
1114 | } | |
15a3c7cc | 1115 | } |
d7f3d478 JL |
1116 | mutex_unlock(&ioapic_mutex); |
1117 | ||
d32932d0 | 1118 | return irq; |
6b9fb708 JL |
1119 | } |
1120 | ||
d7f3d478 | 1121 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1122 | { |
d7f3d478 | 1123 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1124 | |
1125 | /* | |
1126 | * Debugging check, we are in big trouble if this message pops up! | |
1127 | */ | |
c2c21745 | 1128 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1129 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1130 | |
54168ed7 | 1131 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1132 | /* |
1133 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1134 | */ | |
1135 | if ((pin >= 16) && (pin <= 23)) { | |
1136 | if (pirq_entries[pin-16] != -1) { | |
1137 | if (!pirq_entries[pin-16]) { | |
1138 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1139 | "disabling PIRQ%d\n", pin-16); | |
1140 | } else { | |
d7f3d478 | 1141 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1142 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1143 | "using PIRQ%d -> IRQ %d\n", | |
1144 | pin-16, irq); | |
6b9fb708 | 1145 | return irq; |
1da177e4 LT |
1146 | } |
1147 | } | |
1148 | } | |
54168ed7 IM |
1149 | #endif |
1150 | ||
c4d05a2c | 1151 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1152 | } |
6b9fb708 | 1153 | |
c4d05a2c JL |
1154 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, |
1155 | struct irq_alloc_info *info) | |
d7f3d478 JL |
1156 | { |
1157 | int ioapic, pin, idx; | |
1158 | ||
1159 | ioapic = mp_find_ioapic(gsi); | |
1160 | if (ioapic < 0) | |
1161 | return -1; | |
1162 | ||
1163 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1164 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1165 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
1166 | return -1; | |
1167 | ||
c4d05a2c | 1168 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1169 | } |
1170 | ||
df334bea JL |
1171 | void mp_unmap_irq(int irq) |
1172 | { | |
d32932d0 JL |
1173 | struct irq_data *irq_data = irq_get_irq_data(irq); |
1174 | struct mp_chip_data *data; | |
df334bea | 1175 | |
d32932d0 | 1176 | if (!irq_data || !irq_data->domain) |
df334bea JL |
1177 | return; |
1178 | ||
d32932d0 JL |
1179 | data = irq_data->chip_data; |
1180 | if (!data || data->isa_irq) | |
1181 | return; | |
df334bea JL |
1182 | |
1183 | mutex_lock(&ioapic_mutex); | |
d32932d0 JL |
1184 | if (--data->count == 0) |
1185 | irq_domain_free_irqs(irq, 1); | |
df334bea JL |
1186 | mutex_unlock(&ioapic_mutex); |
1187 | } | |
1188 | ||
e20c06fd YL |
1189 | /* |
1190 | * Find a specific PCI IRQ entry. | |
1191 | * Not an __init, possibly needed by modules | |
1192 | */ | |
25d0d35e | 1193 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1194 | { |
d7f3d478 | 1195 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1196 | |
1197 | apic_printk(APIC_DEBUG, | |
1198 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1199 | bus, slot, pin); | |
1200 | if (test_bit(bus, mp_bus_not_pci)) { | |
1201 | apic_printk(APIC_VERBOSE, | |
1202 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1203 | return -1; | |
1204 | } | |
79598505 | 1205 | |
e20c06fd YL |
1206 | for (i = 0; i < mp_irq_entries; i++) { |
1207 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1208 | int ioapic_idx, found = 0; |
1209 | ||
1210 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1211 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1212 | continue; | |
e20c06fd | 1213 | |
f44d1692 | 1214 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1215 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1216 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1217 | found = 1; | |
e20c06fd | 1218 | break; |
e20c06fd | 1219 | } |
79598505 JL |
1220 | if (!found) |
1221 | continue; | |
1222 | ||
1223 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1224 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1225 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1226 | continue; |
1227 | ||
1228 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1229 | best_idx = i; |
1230 | best_ioapic = ioapic_idx; | |
1231 | goto out; | |
79598505 | 1232 | } |
d7f3d478 | 1233 | |
79598505 JL |
1234 | /* |
1235 | * Use the first all-but-pin matching entry as a | |
1236 | * best-guess fuzzy result for broken mptables. | |
1237 | */ | |
d7f3d478 JL |
1238 | if (best_idx < 0) { |
1239 | best_idx = i; | |
1240 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1241 | } |
1242 | } | |
d7f3d478 JL |
1243 | if (best_idx < 0) |
1244 | return -1; | |
1245 | ||
1246 | out: | |
25d0d35e JL |
1247 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1248 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1249 | } |
1250 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1251 | ||
d32932d0 | 1252 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
1da177e4 | 1253 | |
047c8fdb | 1254 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1255 | static inline int IO_APIC_irq_trigger(int irq) |
1256 | { | |
d6c88a50 | 1257 | int apic, idx, pin; |
1d025192 | 1258 | |
f44d1692 JL |
1259 | for_each_ioapic_pin(apic, pin) { |
1260 | idx = find_irq_entry(apic, pin, mp_INT); | |
d7f3d478 | 1261 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0))) |
f44d1692 | 1262 | return irq_trigger(idx); |
d6c88a50 TG |
1263 | } |
1264 | /* | |
54168ed7 IM |
1265 | * nonexistent IRQs are edge default |
1266 | */ | |
d6c88a50 | 1267 | return 0; |
1d025192 | 1268 | } |
047c8fdb YL |
1269 | #else |
1270 | static inline int IO_APIC_irq_trigger(int irq) | |
1271 | { | |
54168ed7 | 1272 | return 1; |
047c8fdb YL |
1273 | } |
1274 | #endif | |
1d025192 | 1275 | |
ed972ccf TG |
1276 | static void __init setup_IO_APIC_irqs(void) |
1277 | { | |
16ee7b3d JL |
1278 | unsigned int ioapic, pin; |
1279 | int idx; | |
ed972ccf TG |
1280 | |
1281 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1282 | ||
16ee7b3d JL |
1283 | for_each_ioapic_pin(ioapic, pin) { |
1284 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1285 | if (idx < 0) | |
1286 | apic_printk(APIC_VERBOSE, | |
1287 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1288 | mpc_ioapic_id(ioapic), pin); | |
1289 | else | |
1290 | pin_2_irq(idx, ioapic, pin, | |
1291 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1292 | } | |
ed972ccf TG |
1293 | } |
1294 | ||
17405453 YY |
1295 | void ioapic_zap_locks(void) |
1296 | { | |
1297 | raw_spin_lock_init(&ioapic_lock); | |
1298 | } | |
1299 | ||
a44174ee JL |
1300 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1301 | { | |
1302 | int i; | |
1303 | char buf[256]; | |
1304 | struct IO_APIC_route_entry entry; | |
1305 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; | |
1306 | ||
1307 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); | |
1308 | for (i = 0; i <= nr_entries; i++) { | |
1309 | entry = ioapic_read_entry(apic, i); | |
1310 | snprintf(buf, sizeof(buf), | |
1311 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", | |
1312 | i, entry.mask ? "disabled" : "enabled ", | |
1313 | entry.trigger ? "level" : "edge ", | |
1314 | entry.polarity ? "low " : "high", | |
1315 | entry.vector, entry.irr, entry.delivery_status); | |
1316 | if (ir_entry->format) | |
1317 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", | |
1318 | buf, (ir_entry->index << 15) | ir_entry->index, | |
1319 | ir_entry->zero); | |
1320 | else | |
1321 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", | |
1322 | buf, entry.dest_mode ? "logical " : "physical", | |
1323 | entry.dest, entry.delivery_mode); | |
1324 | } | |
1325 | } | |
1326 | ||
74afab7a | 1327 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1328 | { |
1da177e4 LT |
1329 | union IO_APIC_reg_00 reg_00; |
1330 | union IO_APIC_reg_01 reg_01; | |
1331 | union IO_APIC_reg_02 reg_02; | |
1332 | union IO_APIC_reg_03 reg_03; | |
1333 | unsigned long flags; | |
1da177e4 | 1334 | |
dade7716 | 1335 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1336 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1337 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1338 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1339 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1340 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1341 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1342 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1343 | |
6f50d45f | 1344 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1345 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1346 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1347 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1348 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1349 | |
54168ed7 | 1350 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1351 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1352 | reg_01.bits.entries); | |
1da177e4 LT |
1353 | |
1354 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1355 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1356 | reg_01.bits.version); | |
1da177e4 LT |
1357 | |
1358 | /* | |
1359 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1360 | * but the value of reg_02 is read as the previous read register | |
1361 | * value, so ignore it if reg_02 == reg_01. | |
1362 | */ | |
1363 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1364 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1365 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1366 | } |
1367 | ||
1368 | /* | |
1369 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1370 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1371 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1372 | */ | |
1373 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1374 | reg_03.raw != reg_01.raw) { | |
1375 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1376 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1377 | } |
1378 | ||
1379 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
a44174ee | 1380 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1381 | } |
1382 | ||
74afab7a | 1383 | void __init print_IO_APICs(void) |
cda417dd | 1384 | { |
6f50d45f | 1385 | int ioapic_idx; |
cda417dd YL |
1386 | unsigned int irq; |
1387 | ||
1388 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1389 | for_each_ioapic(ioapic_idx) |
cda417dd | 1390 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1391 | mpc_ioapic_id(ioapic_idx), |
1392 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1393 | |
1394 | /* | |
1395 | * We are a bit conservative about what we expect. We have to | |
1396 | * know about every hardware change ASAP. | |
1397 | */ | |
1398 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1399 | ||
f44d1692 | 1400 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1401 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1402 | |
1da177e4 | 1403 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1404 | for_each_active_irq(irq) { |
0b8f1efa | 1405 | struct irq_pin_list *entry; |
4467715a JL |
1406 | struct irq_chip *chip; |
1407 | struct mp_chip_data *data; | |
0b8f1efa | 1408 | |
6fd36ba0 | 1409 | chip = irq_get_chip(irq); |
d32932d0 | 1410 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
6fd36ba0 | 1411 | continue; |
4467715a JL |
1412 | data = irq_get_chip_data(irq); |
1413 | if (!data) | |
05e40760 | 1414 | continue; |
4467715a | 1415 | if (list_empty(&data->irq_2_pin)) |
1da177e4 | 1416 | continue; |
4467715a | 1417 | |
8f09cd20 | 1418 | printk(KERN_DEBUG "IRQ%d ", irq); |
4467715a | 1419 | for_each_irq_pin(entry, data->irq_2_pin) |
c767a54b JP |
1420 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1421 | pr_cont("\n"); | |
1da177e4 LT |
1422 | } |
1423 | ||
1424 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1425 | } |
1426 | ||
efa2559f YL |
1427 | /* Where if anywhere is the i8259 connect in external int mode */ |
1428 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1429 | ||
54168ed7 | 1430 | void __init enable_IO_APIC(void) |
1da177e4 | 1431 | { |
fcfd636a | 1432 | int i8259_apic, i8259_pin; |
f44d1692 | 1433 | int apic, pin; |
bc07844a | 1434 | |
a46f5c89 TG |
1435 | if (skip_ioapic_setup) |
1436 | nr_ioapics = 0; | |
1437 | ||
1438 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1439 | return; |
1440 | ||
f44d1692 | 1441 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1442 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1443 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1444 | |
f44d1692 JL |
1445 | /* If the interrupt line is enabled and in ExtInt mode |
1446 | * I have found the pin where the i8259 is connected. | |
1447 | */ | |
1448 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1449 | ioapic_i8259.apic = apic; | |
1450 | ioapic_i8259.pin = pin; | |
1451 | goto found_i8259; | |
fcfd636a EB |
1452 | } |
1453 | } | |
1454 | found_i8259: | |
1455 | /* Look to see what if the MP table has reported the ExtINT */ | |
1456 | /* If we could not find the appropriate pin by looking at the ioapic | |
1457 | * the i8259 probably is not connected the ioapic but give the | |
1458 | * mptable a chance anyway. | |
1459 | */ | |
1460 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1461 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1462 | /* Trust the MP table if nothing is setup in the hardware */ | |
1463 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1464 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1465 | ioapic_i8259.pin = i8259_pin; | |
1466 | ioapic_i8259.apic = i8259_apic; | |
1467 | } | |
1468 | /* Complain if the MP table and the hardware disagree */ | |
1469 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1470 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1471 | { | |
1472 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1473 | } |
1474 | ||
1475 | /* | |
1476 | * Do not trust the IO-APIC being empty at bootup | |
1477 | */ | |
1478 | clear_IO_APIC(); | |
1479 | } | |
1480 | ||
1c4248ca | 1481 | void native_disable_io_apic(void) |
1da177e4 | 1482 | { |
650927ef | 1483 | /* |
0b968d23 | 1484 | * If the i8259 is routed through an IOAPIC |
650927ef | 1485 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1486 | * so legacy interrupts can be delivered. |
650927ef | 1487 | */ |
1c4248ca | 1488 | if (ioapic_i8259.pin != -1) { |
650927ef | 1489 | struct IO_APIC_route_entry entry; |
650927ef EB |
1490 | |
1491 | memset(&entry, 0, sizeof(entry)); | |
1492 | entry.mask = 0; /* Enabled */ | |
1493 | entry.trigger = 0; /* Edge */ | |
1494 | entry.irr = 0; | |
1495 | entry.polarity = 0; /* High */ | |
1496 | entry.delivery_status = 0; | |
1497 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1498 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1499 | entry.vector = 0; |
54168ed7 | 1500 | entry.dest = read_apic_id(); |
650927ef EB |
1501 | |
1502 | /* | |
1503 | * Add it to the IO-APIC irq-routing table: | |
1504 | */ | |
cf4c6a2f | 1505 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1506 | } |
54168ed7 | 1507 | |
1c4248ca JR |
1508 | if (cpu_has_apic || apic_from_smp_config()) |
1509 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1510 | ||
1511 | } | |
1512 | ||
1513 | /* | |
1514 | * Not an __init, needed by the reboot code | |
1515 | */ | |
1516 | void disable_IO_APIC(void) | |
1517 | { | |
7c6d9f97 | 1518 | /* |
1c4248ca | 1519 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1520 | */ |
1c4248ca JR |
1521 | clear_IO_APIC(); |
1522 | ||
95d76acc | 1523 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1524 | return; |
1525 | ||
1526 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1527 | } |
1528 | ||
54168ed7 | 1529 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1530 | /* |
1531 | * function to set the IO-APIC physical IDs based on the | |
1532 | * values stored in the MPC table. | |
1533 | * | |
1534 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1535 | */ | |
a38c5380 | 1536 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1537 | { |
1538 | union IO_APIC_reg_00 reg_00; | |
1539 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1540 | int ioapic_idx; |
1da177e4 LT |
1541 | int i; |
1542 | unsigned char old_id; | |
1543 | unsigned long flags; | |
1544 | ||
1545 | /* | |
1546 | * This is broken; anything with a real cpu count has to | |
1547 | * circumvent this idiocy regardless. | |
1548 | */ | |
7abc0753 | 1549 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1550 | |
1551 | /* | |
1552 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1553 | */ | |
f44d1692 | 1554 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1555 | /* Read the register 0 value */ |
dade7716 | 1556 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1557 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1558 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1559 | |
6f50d45f | 1560 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1561 | |
6f50d45f | 1562 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1563 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1564 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1565 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1566 | reg_00.bits.ID); | |
6f50d45f | 1567 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1568 | } |
1569 | ||
1da177e4 LT |
1570 | /* |
1571 | * Sanity check, is the ID really free? Every APIC in a | |
1572 | * system must have a unique ID or we get lots of nice | |
1573 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1574 | */ | |
7abc0753 | 1575 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1576 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1577 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1578 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1579 | for (i = 0; i < get_physical_broadcast(); i++) |
1580 | if (!physid_isset(i, phys_id_present_map)) | |
1581 | break; | |
1582 | if (i >= get_physical_broadcast()) | |
1583 | panic("Max APIC ID exceeded!\n"); | |
1584 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1585 | i); | |
1586 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1587 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1588 | } else { |
1589 | physid_mask_t tmp; | |
6f50d45f | 1590 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1591 | &tmp); |
1da177e4 LT |
1592 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1593 | "phys_id_present_map\n", | |
6f50d45f | 1594 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1595 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1596 | } | |
1597 | ||
1da177e4 LT |
1598 | /* |
1599 | * We need to adjust the IRQ routing table | |
1600 | * if the ID changed. | |
1601 | */ | |
6f50d45f | 1602 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1603 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1604 | if (mp_irqs[i].dstapic == old_id) |
1605 | mp_irqs[i].dstapic | |
6f50d45f | 1606 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1607 | |
1608 | /* | |
60d79fd9 YL |
1609 | * Update the ID register according to the right value |
1610 | * from the MPC table if they are different. | |
36062448 | 1611 | */ |
6f50d45f | 1612 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1613 | continue; |
1614 | ||
1da177e4 LT |
1615 | apic_printk(APIC_VERBOSE, KERN_INFO |
1616 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1617 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1618 | |
6f50d45f | 1619 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1620 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1621 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1622 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1623 | |
1624 | /* | |
1625 | * Sanity check | |
1626 | */ | |
dade7716 | 1627 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1628 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1629 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1630 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1631 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1632 | else |
1633 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1634 | } | |
1635 | } | |
a38c5380 SAS |
1636 | |
1637 | void __init setup_ioapic_ids_from_mpc(void) | |
1638 | { | |
1639 | ||
1640 | if (acpi_ioapic) | |
1641 | return; | |
1642 | /* | |
1643 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1644 | * no meaning without the serial APIC bus. | |
1645 | */ | |
1646 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
1647 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
1648 | return; | |
1649 | setup_ioapic_ids_from_mpc_nocheck(); | |
1650 | } | |
54168ed7 | 1651 | #endif |
1da177e4 | 1652 | |
7ce0bcfd | 1653 | int no_timer_check __initdata; |
8542b200 ZA |
1654 | |
1655 | static int __init notimercheck(char *s) | |
1656 | { | |
1657 | no_timer_check = 1; | |
1658 | return 1; | |
1659 | } | |
1660 | __setup("no_timer_check", notimercheck); | |
1661 | ||
1da177e4 LT |
1662 | /* |
1663 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1664 | * about the timer IRQ. We do the following to work around the situation: | |
1665 | * | |
1666 | * - timer IRQ defaults to IO-APIC IRQ | |
1667 | * - if this function detects that timer IRQs are defunct, then we fall | |
1668 | * back to ISA timer IRQs | |
1669 | */ | |
f0a7a5c9 | 1670 | static int __init timer_irq_works(void) |
1da177e4 LT |
1671 | { |
1672 | unsigned long t1 = jiffies; | |
4aae0702 | 1673 | unsigned long flags; |
1da177e4 | 1674 | |
8542b200 ZA |
1675 | if (no_timer_check) |
1676 | return 1; | |
1677 | ||
4aae0702 | 1678 | local_save_flags(flags); |
1da177e4 LT |
1679 | local_irq_enable(); |
1680 | /* Let ten ticks pass... */ | |
1681 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1682 | local_irq_restore(flags); |
1da177e4 LT |
1683 | |
1684 | /* | |
1685 | * Expect a few ticks at least, to be sure some possible | |
1686 | * glue logic does not lock up after one or two first | |
1687 | * ticks in a non-ExtINT mode. Also the local APIC | |
1688 | * might have cached one ExtINT interrupt. Finally, at | |
1689 | * least one tick may be lost due to delays. | |
1690 | */ | |
54168ed7 IM |
1691 | |
1692 | /* jiffies wrap? */ | |
1d16b53e | 1693 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1694 | return 1; |
1da177e4 LT |
1695 | return 0; |
1696 | } | |
1697 | ||
1698 | /* | |
1699 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1700 | * number of pending IRQ events unhandled. These cases are very rare, | |
1701 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1702 | * better to do it this way as thus we do not have to be aware of | |
1703 | * 'pending' interrupts in the IRQ path, except at this point. | |
1704 | */ | |
1705 | /* | |
1706 | * Edge triggered needs to resend any interrupt | |
1707 | * that was delayed but this is now handled in the device | |
1708 | * independent code. | |
1709 | */ | |
1710 | ||
1711 | /* | |
1712 | * Starting up a edge-triggered IO-APIC interrupt is | |
1713 | * nasty - we need to make sure that we get the edge. | |
1714 | * If it is already asserted for some reason, we need | |
1715 | * return 1 to indicate that is was pending. | |
1716 | * | |
1717 | * This is not complete - we should be able to fake | |
1718 | * an edge even if it isn't on the 8259A... | |
1719 | */ | |
54168ed7 | 1720 | |
61a38ce3 | 1721 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1722 | { |
61a38ce3 | 1723 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1724 | unsigned long flags; |
1725 | ||
dade7716 | 1726 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1727 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1728 | legacy_pic->mask(irq); |
b81bb373 | 1729 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1730 | was_pending = 1; |
1731 | } | |
4467715a | 1732 | __unmask_ioapic(data->chip_data); |
dade7716 | 1733 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1734 | |
1735 | return was_pending; | |
1736 | } | |
1737 | ||
54168ed7 IM |
1738 | /* |
1739 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1740 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1741 | * handled with the level-triggered descriptor, but that one has slightly | |
1742 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1743 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1744 | * races. | |
1745 | */ | |
497c9a19 | 1746 | |
4467715a JL |
1747 | static void __target_IO_APIC_irq(unsigned int irq, struct irq_cfg *cfg, |
1748 | struct mp_chip_data *data) | |
7eb9ae07 SS |
1749 | { |
1750 | int apic, pin; | |
1751 | struct irq_pin_list *entry; | |
1752 | u8 vector = cfg->vector; | |
4467715a | 1753 | unsigned int dest = SET_APIC_LOGICAL_ID(cfg->dest_apicid); |
7eb9ae07 | 1754 | |
4467715a | 1755 | for_each_irq_pin(entry, data->irq_2_pin) { |
7eb9ae07 SS |
1756 | unsigned int reg; |
1757 | ||
1758 | apic = entry->apic; | |
1759 | pin = entry->pin; | |
9f9d39e4 JR |
1760 | |
1761 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
1762 | reg = io_apic_read(apic, 0x10 + pin*2); |
1763 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
1764 | reg |= vector; | |
1765 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
1766 | } | |
1767 | } | |
1768 | ||
3eb2cce8 | 1769 | atomic_t irq_mis_count; |
3eb2cce8 | 1770 | |
047c8fdb | 1771 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
4467715a | 1772 | static bool io_apic_level_ack_pending(struct mp_chip_data *data) |
d1ecad6e MN |
1773 | { |
1774 | struct irq_pin_list *entry; | |
1775 | unsigned long flags; | |
1776 | ||
1777 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 1778 | for_each_irq_pin(entry, data->irq_2_pin) { |
d1ecad6e MN |
1779 | unsigned int reg; |
1780 | int pin; | |
1781 | ||
1782 | pin = entry->pin; | |
1783 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
1784 | /* Is the remote IRR bit set? */ | |
1785 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
1786 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1787 | return true; | |
1788 | } | |
1789 | } | |
1790 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1791 | ||
1792 | return false; | |
1793 | } | |
1794 | ||
4467715a | 1795 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a | 1796 | { |
54168ed7 | 1797 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 1798 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
4467715a | 1799 | mask_ioapic_irq(data); |
4da7072a | 1800 | return true; |
54168ed7 | 1801 | } |
4da7072a AG |
1802 | return false; |
1803 | } | |
1804 | ||
4467715a | 1805 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1806 | { |
1807 | if (unlikely(masked)) { | |
1808 | /* Only migrate the irq if the ack has been received. | |
1809 | * | |
1810 | * On rare occasions the broadcast level triggered ack gets | |
1811 | * delayed going to ioapics, and if we reprogram the | |
1812 | * vector while Remote IRR is still set the irq will never | |
1813 | * fire again. | |
1814 | * | |
1815 | * To prevent this scenario we read the Remote IRR bit | |
1816 | * of the ioapic. This has two effects. | |
1817 | * - On any sane system the read of the ioapic will | |
1818 | * flush writes (and acks) going to the ioapic from | |
1819 | * this cpu. | |
1820 | * - We get to see if the ACK has actually been delivered. | |
1821 | * | |
1822 | * Based on failed experiments of reprogramming the | |
1823 | * ioapic entry from outside of irq context starting | |
1824 | * with masking the ioapic entry and then polling until | |
1825 | * Remote IRR was clear before reprogramming the | |
1826 | * ioapic I don't trust the Remote IRR bit to be | |
1827 | * completey accurate. | |
1828 | * | |
1829 | * However there appears to be no other way to plug | |
1830 | * this race, so if the Remote IRR bit is not | |
1831 | * accurate and is causing problems then it is a hardware bug | |
1832 | * and you can go talk to the chipset vendor about it. | |
1833 | */ | |
4467715a | 1834 | if (!io_apic_level_ack_pending(data->chip_data)) |
4da7072a | 1835 | irq_move_masked_irq(data); |
4467715a | 1836 | unmask_ioapic_irq(data); |
4da7072a AG |
1837 | } |
1838 | } | |
1839 | #else | |
4467715a | 1840 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a AG |
1841 | { |
1842 | return false; | |
1843 | } | |
4467715a | 1844 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1845 | { |
1846 | } | |
047c8fdb YL |
1847 | #endif |
1848 | ||
4467715a | 1849 | static void ioapic_ack_level(struct irq_data *irq_data) |
4da7072a | 1850 | { |
4467715a | 1851 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
4da7072a AG |
1852 | unsigned long v; |
1853 | bool masked; | |
d32932d0 | 1854 | int i; |
4da7072a AG |
1855 | |
1856 | irq_complete_move(cfg); | |
4467715a | 1857 | masked = ioapic_irqd_mask(irq_data); |
4da7072a | 1858 | |
3eb2cce8 | 1859 | /* |
916a0fe7 JF |
1860 | * It appears there is an erratum which affects at least version 0x11 |
1861 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1862 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1863 | * erroneously delivered as edge-triggered one but the respective IRR | |
1864 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1865 | * message but it will never arrive and further interrupts are blocked | |
1866 | * from the source. The exact reason is so far unknown, but the | |
1867 | * phenomenon was observed when two consecutive interrupt requests | |
1868 | * from a given source get delivered to the same CPU and the source is | |
1869 | * temporarily disabled in between. | |
1870 | * | |
1871 | * A workaround is to simulate an EOI message manually. We achieve it | |
1872 | * by setting the trigger mode to edge and then to level when the edge | |
1873 | * trigger mode gets detected in the TMR of a local APIC for a | |
1874 | * level-triggered interrupt. We mask the source for the time of the | |
1875 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1876 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
1877 | * |
1878 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
1879 | * any unhandled interrupt on the offlined cpu to the new cpu | |
1880 | * destination that is handling the corresponding interrupt. This | |
1881 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
1882 | * level-triggered io-apic interrupt will be seen as an edge | |
1883 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
1884 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
1885 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
1886 | * supporting EOI register, we do an explicit EOI to clear the | |
1887 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
1888 | * we use the above logic (mask+edge followed by unmask+level) from | |
1889 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 1890 | */ |
3145e941 | 1891 | i = cfg->vector; |
3eb2cce8 | 1892 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 1893 | |
54168ed7 IM |
1894 | /* |
1895 | * We must acknowledge the irq before we move it or the acknowledge will | |
1896 | * not propagate properly. | |
1897 | */ | |
1898 | ack_APIC_irq(); | |
1899 | ||
1c83995b SS |
1900 | /* |
1901 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
1902 | * message via io-apic EOI register write or simulating it using | |
1903 | * mask+edge followed by unnask+level logic) manually when the | |
1904 | * level triggered interrupt is seen as the edge triggered interrupt | |
1905 | * at the cpu. | |
1906 | */ | |
ca64c47c MR |
1907 | if (!(v & (1 << (i & 0x1f)))) { |
1908 | atomic_inc(&irq_mis_count); | |
4467715a | 1909 | eoi_ioapic_pin(cfg->vector, irq_data->chip_data); |
ca64c47c MR |
1910 | } |
1911 | ||
4467715a | 1912 | ioapic_irqd_unmask(irq_data, masked); |
3eb2cce8 | 1913 | } |
1d025192 | 1914 | |
d32932d0 JL |
1915 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
1916 | { | |
1917 | struct mp_chip_data *data = irq_data->chip_data; | |
1918 | ||
1919 | /* | |
1920 | * Intr-remapping uses pin number as the virtual vector | |
1921 | * in the RTE. Actual vector is programmed in | |
1922 | * intr-remapping table entry. Hence for the io-apic | |
1923 | * EOI we use the pin number. | |
1924 | */ | |
1925 | ack_APIC_irq(); | |
4467715a | 1926 | eoi_ioapic_pin(data->entry.vector, data); |
d32932d0 JL |
1927 | } |
1928 | ||
1929 | static int ioapic_set_affinity(struct irq_data *irq_data, | |
1930 | const struct cpumask *mask, bool force) | |
1931 | { | |
1932 | struct irq_data *parent = irq_data->parent_data; | |
1933 | struct mp_chip_data *data = irq_data->chip_data; | |
d32932d0 JL |
1934 | struct irq_cfg *cfg; |
1935 | unsigned long flags; | |
1936 | int ret; | |
1937 | ||
1938 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1939 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1940 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { | |
1941 | cfg = irqd_cfg(irq_data); | |
1942 | data->entry.dest = cfg->dest_apicid; | |
1943 | data->entry.vector = cfg->vector; | |
4467715a | 1944 | __target_IO_APIC_irq(irq_data->irq, cfg, irq_data->chip_data); |
d32932d0 JL |
1945 | } |
1946 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1947 | ||
1948 | return ret; | |
1949 | } | |
1950 | ||
f5b9ed7a | 1951 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
1952 | .name = "IO-APIC", |
1953 | .irq_startup = startup_ioapic_irq, | |
1954 | .irq_mask = mask_ioapic_irq, | |
1955 | .irq_unmask = unmask_ioapic_irq, | |
d32932d0 JL |
1956 | .irq_ack = irq_chip_ack_parent, |
1957 | .irq_eoi = ioapic_ack_level, | |
1958 | .irq_set_affinity = ioapic_set_affinity, | |
1959 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
1960 | }; | |
1961 | ||
1962 | static struct irq_chip ioapic_ir_chip __read_mostly = { | |
1963 | .name = "IR-IO-APIC", | |
1964 | .irq_startup = startup_ioapic_irq, | |
1965 | .irq_mask = mask_ioapic_irq, | |
1966 | .irq_unmask = unmask_ioapic_irq, | |
1967 | .irq_ack = irq_chip_ack_parent, | |
1968 | .irq_eoi = ioapic_ir_ack_level, | |
1969 | .irq_set_affinity = ioapic_set_affinity, | |
5613570b | 1970 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
1971 | }; |
1972 | ||
1da177e4 LT |
1973 | static inline void init_IO_APIC_traps(void) |
1974 | { | |
da51a821 | 1975 | struct irq_cfg *cfg; |
ad9f4334 | 1976 | unsigned int irq; |
1da177e4 | 1977 | |
ad9f4334 | 1978 | for_each_active_irq(irq) { |
32f5ef5d | 1979 | cfg = irq_cfg(irq); |
0b8f1efa | 1980 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
1981 | /* |
1982 | * Hmm.. We don't have an entry for this, | |
1983 | * so default to an old-fashioned 8259 | |
1984 | * interrupt if we can.. | |
1985 | */ | |
95d76acc | 1986 | if (irq < nr_legacy_irqs()) |
b81bb373 | 1987 | legacy_pic->make_irq(irq); |
0b8f1efa | 1988 | else |
1da177e4 | 1989 | /* Strange. Oh, well.. */ |
2c778651 | 1990 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
1991 | } |
1992 | } | |
1993 | } | |
1994 | ||
f5b9ed7a IM |
1995 | /* |
1996 | * The local APIC irq-chip implementation: | |
1997 | */ | |
1da177e4 | 1998 | |
90297c5f | 1999 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2000 | { |
2001 | unsigned long v; | |
2002 | ||
2003 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2004 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2005 | } |
2006 | ||
90297c5f | 2007 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2008 | { |
f5b9ed7a | 2009 | unsigned long v; |
1da177e4 | 2010 | |
f5b9ed7a | 2011 | v = apic_read(APIC_LVT0); |
593f4a78 | 2012 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2013 | } |
1da177e4 | 2014 | |
90297c5f | 2015 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2016 | { |
2017 | ack_APIC_irq(); | |
2018 | } | |
2019 | ||
f5b9ed7a | 2020 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2021 | .name = "local-APIC", |
90297c5f TG |
2022 | .irq_mask = mask_lapic_irq, |
2023 | .irq_unmask = unmask_lapic_irq, | |
2024 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2025 | }; |
2026 | ||
60c69948 | 2027 | static void lapic_register_intr(int irq) |
c88ac1df | 2028 | { |
60c69948 | 2029 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2030 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2031 | "edge"); |
c88ac1df MR |
2032 | } |
2033 | ||
1da177e4 LT |
2034 | /* |
2035 | * This looks a bit hackish but it's about the only one way of sending | |
2036 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2037 | * not support the ExtINT mode, unfortunately. We need to send these | |
2038 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2039 | * 8259A interrupt line asserted until INTA. --macro | |
2040 | */ | |
28acf285 | 2041 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2042 | { |
fcfd636a | 2043 | int apic, pin, i; |
1da177e4 LT |
2044 | struct IO_APIC_route_entry entry0, entry1; |
2045 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2046 | |
fcfd636a | 2047 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2048 | if (pin == -1) { |
2049 | WARN_ON_ONCE(1); | |
2050 | return; | |
2051 | } | |
fcfd636a | 2052 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2053 | if (apic == -1) { |
2054 | WARN_ON_ONCE(1); | |
1da177e4 | 2055 | return; |
956fb531 | 2056 | } |
1da177e4 | 2057 | |
cf4c6a2f | 2058 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2059 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2060 | |
2061 | memset(&entry1, 0, sizeof(entry1)); | |
2062 | ||
2063 | entry1.dest_mode = 0; /* physical delivery */ | |
2064 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2065 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2066 | entry1.delivery_mode = dest_ExtINT; |
2067 | entry1.polarity = entry0.polarity; | |
2068 | entry1.trigger = 0; | |
2069 | entry1.vector = 0; | |
2070 | ||
cf4c6a2f | 2071 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2072 | |
2073 | save_control = CMOS_READ(RTC_CONTROL); | |
2074 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2075 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2076 | RTC_FREQ_SELECT); | |
2077 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2078 | ||
2079 | i = 100; | |
2080 | while (i-- > 0) { | |
2081 | mdelay(10); | |
2082 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2083 | i -= 10; | |
2084 | } | |
2085 | ||
2086 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2087 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2088 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2089 | |
cf4c6a2f | 2090 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2091 | } |
2092 | ||
efa2559f | 2093 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2094 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2095 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2096 | { |
2097 | disable_timer_pin_1 = 1; | |
2098 | return 0; | |
2099 | } | |
54168ed7 | 2100 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2101 | |
d32932d0 JL |
2102 | static int mp_alloc_timer_irq(int ioapic, int pin) |
2103 | { | |
2104 | int irq = -1; | |
d32932d0 JL |
2105 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
2106 | ||
2107 | if (domain) { | |
4467715a JL |
2108 | struct irq_alloc_info info; |
2109 | ||
d32932d0 JL |
2110 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); |
2111 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2112 | info.ioapic_pin = pin; | |
2113 | mutex_lock(&ioapic_mutex); | |
2114 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); | |
2115 | mutex_unlock(&ioapic_mutex); | |
2116 | } | |
2117 | ||
2118 | return irq; | |
2119 | } | |
2120 | ||
1da177e4 LT |
2121 | /* |
2122 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2123 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2124 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2125 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2126 | * |
2127 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2128 | */ |
8542b200 | 2129 | static inline void __init check_timer(void) |
1da177e4 | 2130 | { |
4467715a JL |
2131 | struct irq_data *irq_data = irq_get_irq_data(0); |
2132 | struct mp_chip_data *data = irq_data->chip_data; | |
2133 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
f6e9456c | 2134 | int node = cpu_to_node(0); |
fcfd636a | 2135 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2136 | unsigned long flags; |
047c8fdb | 2137 | int no_pin1 = 0; |
4aae0702 IM |
2138 | |
2139 | local_irq_save(flags); | |
d4d25dec | 2140 | |
1da177e4 LT |
2141 | /* |
2142 | * get/set the timer IRQ vector: | |
2143 | */ | |
4305df94 | 2144 | legacy_pic->mask(0); |
1da177e4 LT |
2145 | |
2146 | /* | |
d11d5794 MR |
2147 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2148 | * wire has to be disabled in the local APIC. Also | |
2149 | * timer interrupts need to be acknowledged manually in | |
2150 | * the 8259A for the i82489DX when using the NMI | |
2151 | * watchdog as that APIC treats NMIs as level-triggered. | |
2152 | * The AEOI mode will finish them in the 8259A | |
2153 | * automatically. | |
1da177e4 | 2154 | */ |
593f4a78 | 2155 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2156 | legacy_pic->init(1); |
1da177e4 | 2157 | |
fcfd636a EB |
2158 | pin1 = find_isa_irq_pin(0, mp_INT); |
2159 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2160 | pin2 = ioapic_i8259.pin; | |
2161 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2162 | |
49a66a0b MR |
2163 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2164 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2165 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2166 | |
691874fa MR |
2167 | /* |
2168 | * Some BIOS writers are clueless and report the ExtINTA | |
2169 | * I/O APIC input from the cascaded 8259A as the timer | |
2170 | * interrupt input. So just in case, if only one pin | |
2171 | * was found above, try it both directly and through the | |
2172 | * 8259A. | |
2173 | */ | |
2174 | if (pin1 == -1) { | |
6a9f5de2 | 2175 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2176 | pin1 = pin2; |
2177 | apic1 = apic2; | |
2178 | no_pin1 = 1; | |
2179 | } else if (pin2 == -1) { | |
2180 | pin2 = pin1; | |
2181 | apic2 = apic1; | |
2182 | } | |
2183 | ||
1da177e4 | 2184 | if (pin1 != -1) { |
d32932d0 | 2185 | /* Ok, does IRQ0 through the IOAPIC work? */ |
691874fa | 2186 | if (no_pin1) { |
d32932d0 | 2187 | mp_alloc_timer_irq(apic1, pin1); |
f72dccac | 2188 | } else { |
d32932d0 JL |
2189 | /* |
2190 | * for edge trigger, it's already unmasked, | |
f72dccac YL |
2191 | * so only need to unmask if it is level-trigger |
2192 | * do we really have level trigger timer? | |
2193 | */ | |
2194 | int idx; | |
2195 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2196 | if (idx != -1 && irq_trigger(idx)) | |
4467715a | 2197 | unmask_ioapic_irq(irq_get_chip_data(0)); |
691874fa | 2198 | } |
4467715a | 2199 | irq_domain_activate_irq(irq_data); |
1da177e4 | 2200 | if (timer_irq_works()) { |
66759a01 CE |
2201 | if (disable_timer_pin_1 > 0) |
2202 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2203 | goto out; |
1da177e4 | 2204 | } |
6a9f5de2 | 2205 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2206 | local_irq_disable(); |
fcfd636a | 2207 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2208 | if (!no_pin1) |
49a66a0b MR |
2209 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2210 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2211 | |
49a66a0b MR |
2212 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2213 | "(IRQ0) through the 8259A ...\n"); | |
2214 | apic_printk(APIC_QUIET, KERN_INFO | |
2215 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2216 | /* |
2217 | * legacy devices should be connected to IO APIC #0 | |
2218 | */ | |
4467715a JL |
2219 | replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2); |
2220 | irq_domain_activate_irq(irq_data); | |
4305df94 | 2221 | legacy_pic->unmask(0); |
1da177e4 | 2222 | if (timer_irq_works()) { |
49a66a0b | 2223 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2224 | goto out; |
1da177e4 LT |
2225 | } |
2226 | /* | |
2227 | * Cleanup, just in case ... | |
2228 | */ | |
f72dccac | 2229 | local_irq_disable(); |
4305df94 | 2230 | legacy_pic->mask(0); |
fcfd636a | 2231 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2232 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2233 | } |
1da177e4 | 2234 | |
49a66a0b MR |
2235 | apic_printk(APIC_QUIET, KERN_INFO |
2236 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2237 | |
60c69948 | 2238 | lapic_register_intr(0); |
497c9a19 | 2239 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2240 | legacy_pic->unmask(0); |
1da177e4 LT |
2241 | |
2242 | if (timer_irq_works()) { | |
49a66a0b | 2243 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2244 | goto out; |
1da177e4 | 2245 | } |
f72dccac | 2246 | local_irq_disable(); |
4305df94 | 2247 | legacy_pic->mask(0); |
497c9a19 | 2248 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2249 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2250 | |
49a66a0b MR |
2251 | apic_printk(APIC_QUIET, KERN_INFO |
2252 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2253 | |
b81bb373 JP |
2254 | legacy_pic->init(0); |
2255 | legacy_pic->make_irq(0); | |
593f4a78 | 2256 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2257 | |
2258 | unlock_ExtINT_logic(); | |
2259 | ||
2260 | if (timer_irq_works()) { | |
49a66a0b | 2261 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2262 | goto out; |
1da177e4 | 2263 | } |
f72dccac | 2264 | local_irq_disable(); |
49a66a0b | 2265 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2266 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2267 | apic_printk(APIC_QUIET, KERN_INFO |
2268 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2269 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2270 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2271 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2272 | out: |
2273 | local_irq_restore(flags); | |
1da177e4 LT |
2274 | } |
2275 | ||
2276 | /* | |
af174783 MR |
2277 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2278 | * to devices. However there may be an I/O APIC pin available for | |
2279 | * this interrupt regardless. The pin may be left unconnected, but | |
2280 | * typically it will be reused as an ExtINT cascade interrupt for | |
2281 | * the master 8259A. In the MPS case such a pin will normally be | |
2282 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2283 | * there is no provision for ExtINT interrupts, and in the absence | |
2284 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2285 | * interrupt, that is edge-triggered and unmasked by default. We | |
2286 | * used to do this, but it caused problems on some systems because | |
2287 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2288 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2289 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2290 | * the I/O APIC in all cases now. No actual device should request | |
2291 | * it anyway. --macro | |
1da177e4 | 2292 | */ |
bc07844a | 2293 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2294 | |
44767bfa JL |
2295 | static int mp_irqdomain_create(int ioapic) |
2296 | { | |
d32932d0 JL |
2297 | struct irq_alloc_info info; |
2298 | struct irq_domain *parent; | |
44767bfa JL |
2299 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2300 | struct ioapic *ip = &ioapics[ioapic]; | |
2301 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2302 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2303 | ||
2304 | if (cfg->type == IOAPIC_DOMAIN_INVALID) | |
2305 | return 0; | |
2306 | ||
d32932d0 JL |
2307 | init_irq_alloc_info(&info, NULL); |
2308 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
2309 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2310 | parent = irq_remapping_get_ir_irq_domain(&info); | |
2311 | if (!parent) | |
2312 | parent = x86_vector_domain; | |
2313 | ||
44767bfa JL |
2314 | ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops, |
2315 | (void *)(long)ioapic); | |
b75e818f | 2316 | if (!ip->irqdomain) |
44767bfa | 2317 | return -ENOMEM; |
b75e818f JL |
2318 | |
2319 | ip->irqdomain->parent = parent; | |
44767bfa JL |
2320 | |
2321 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2322 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2323 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2324 | gsi_cfg->gsi_end + 1); | |
2325 | ||
44767bfa JL |
2326 | return 0; |
2327 | } | |
2328 | ||
15516a3b JL |
2329 | static void ioapic_destroy_irqdomain(int idx) |
2330 | { | |
2331 | if (ioapics[idx].irqdomain) { | |
2332 | irq_domain_remove(ioapics[idx].irqdomain); | |
2333 | ioapics[idx].irqdomain = NULL; | |
2334 | } | |
15516a3b JL |
2335 | } |
2336 | ||
1da177e4 LT |
2337 | void __init setup_IO_APIC(void) |
2338 | { | |
44767bfa | 2339 | int ioapic; |
54168ed7 | 2340 | |
a46f5c89 TG |
2341 | if (skip_ioapic_setup || !nr_ioapics) |
2342 | return; | |
2343 | ||
95d76acc | 2344 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2345 | |
54168ed7 | 2346 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2347 | for_each_ioapic(ioapic) |
2348 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2349 | ||
d6c88a50 | 2350 | /* |
54168ed7 IM |
2351 | * Set up IO-APIC IRQ routing. |
2352 | */ | |
de934103 TG |
2353 | x86_init.mpparse.setup_ioapic_ids(); |
2354 | ||
1da177e4 LT |
2355 | sync_Arb_IDs(); |
2356 | setup_IO_APIC_irqs(); | |
2357 | init_IO_APIC_traps(); | |
95d76acc | 2358 | if (nr_legacy_irqs()) |
bc07844a | 2359 | check_timer(); |
b81975ea JL |
2360 | |
2361 | ioapic_initialized = 1; | |
1da177e4 LT |
2362 | } |
2363 | ||
2364 | /* | |
0d2eb44f | 2365 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2366 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2367 | */ |
36062448 | 2368 | |
1da177e4 LT |
2369 | static int __init io_apic_bug_finalize(void) |
2370 | { | |
d6c88a50 TG |
2371 | if (sis_apic_bug == -1) |
2372 | sis_apic_bug = 0; | |
2373 | return 0; | |
1da177e4 LT |
2374 | } |
2375 | ||
2376 | late_initcall(io_apic_bug_finalize); | |
2377 | ||
6f50d45f | 2378 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2379 | { |
1da177e4 LT |
2380 | unsigned long flags; |
2381 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2382 | |
dade7716 | 2383 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2384 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2385 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2386 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2387 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2388 | } |
dade7716 | 2389 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2390 | } |
1da177e4 | 2391 | |
f3c6ea1b RW |
2392 | static void ioapic_resume(void) |
2393 | { | |
6f50d45f | 2394 | int ioapic_idx; |
f3c6ea1b | 2395 | |
f44d1692 | 2396 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2397 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2398 | |
2399 | restore_ioapic_entries(); | |
1da177e4 LT |
2400 | } |
2401 | ||
f3c6ea1b | 2402 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2403 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2404 | .resume = ioapic_resume, |
2405 | }; | |
2406 | ||
f3c6ea1b | 2407 | static int __init ioapic_init_ops(void) |
1da177e4 | 2408 | { |
f3c6ea1b RW |
2409 | register_syscore_ops(&ioapic_syscore_ops); |
2410 | ||
1da177e4 LT |
2411 | return 0; |
2412 | } | |
2413 | ||
f3c6ea1b | 2414 | device_initcall(ioapic_init_ops); |
1da177e4 | 2415 | |
67dc5e70 | 2416 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2417 | { |
2418 | union IO_APIC_reg_01 reg_01; | |
2419 | unsigned long flags; | |
2420 | ||
dade7716 | 2421 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2422 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2423 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2424 | |
4b6b19a1 EB |
2425 | /* The register returns the maximum index redir index |
2426 | * supported, which is one less than the total number of redir | |
2427 | * entries. | |
2428 | */ | |
2429 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2430 | } |
2431 | ||
62a08ae2 TG |
2432 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2433 | { | |
b81975ea JL |
2434 | /* |
2435 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2436 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2437 | */ | |
2438 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2439 | } |
2440 | ||
54168ed7 | 2441 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2442 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2443 | { |
2444 | union IO_APIC_reg_00 reg_00; | |
2445 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2446 | physid_mask_t tmp; | |
2447 | unsigned long flags; | |
2448 | int i = 0; | |
2449 | ||
2450 | /* | |
36062448 PC |
2451 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2452 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2453 | * supports up to 16 on one shared APIC bus. |
36062448 | 2454 | * |
1da177e4 LT |
2455 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2456 | * advantage of new APIC bus architecture. | |
2457 | */ | |
2458 | ||
2459 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2460 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2461 | |
dade7716 | 2462 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2463 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2464 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2465 | |
2466 | if (apic_id >= get_physical_broadcast()) { | |
2467 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2468 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2469 | apic_id = reg_00.bits.ID; | |
2470 | } | |
2471 | ||
2472 | /* | |
36062448 | 2473 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2474 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2475 | */ | |
7abc0753 | 2476 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2477 | |
2478 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2479 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2480 | break; |
2481 | } | |
2482 | ||
2483 | if (i == get_physical_broadcast()) | |
2484 | panic("Max apic_id exceeded!\n"); | |
2485 | ||
2486 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2487 | "trying %d\n", ioapic, apic_id, i); | |
2488 | ||
2489 | apic_id = i; | |
36062448 | 2490 | } |
1da177e4 | 2491 | |
7abc0753 | 2492 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2493 | physids_or(apic_id_map, apic_id_map, tmp); |
2494 | ||
2495 | if (reg_00.bits.ID != apic_id) { | |
2496 | reg_00.bits.ID = apic_id; | |
2497 | ||
dade7716 | 2498 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2499 | io_apic_write(ioapic, 0, reg_00.raw); |
2500 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2501 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2502 | |
2503 | /* Sanity check */ | |
6070f9ec | 2504 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2505 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2506 | ioapic); | |
6070f9ec AD |
2507 | return -1; |
2508 | } | |
1da177e4 LT |
2509 | } |
2510 | ||
2511 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2512 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2513 | ||
2514 | return apic_id; | |
2515 | } | |
41098ffe | 2516 | |
67dc5e70 | 2517 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2518 | { |
2519 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
2520 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
5411dc4c | 2521 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2522 | else |
2523 | return id; | |
2524 | } | |
2525 | #else | |
67dc5e70 | 2526 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2527 | { |
5411dc4c | 2528 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2529 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2530 | unsigned long flags; |
2531 | u8 new_id; | |
2532 | int i; | |
41098ffe TG |
2533 | |
2534 | bitmap_zero(used, 256); | |
f44d1692 | 2535 | for_each_ioapic(i) |
d5371430 | 2536 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2537 | |
2538 | /* Hand out the requested id if available */ | |
41098ffe TG |
2539 | if (!test_bit(id, used)) |
2540 | return id; | |
5411dc4c YL |
2541 | |
2542 | /* | |
2543 | * Read the current id from the ioapic and keep it if | |
2544 | * available. | |
2545 | */ | |
2546 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2547 | reg_00.raw = io_apic_read(idx, 0); | |
2548 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2549 | new_id = reg_00.bits.ID; | |
2550 | if (!test_bit(new_id, used)) { | |
2551 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2552 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2553 | idx, new_id, id); | |
2554 | return new_id; | |
2555 | } | |
2556 | ||
2557 | /* | |
2558 | * Get the next free id and write it to the ioapic. | |
2559 | */ | |
2560 | new_id = find_first_zero_bit(used, 256); | |
2561 | reg_00.bits.ID = new_id; | |
2562 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2563 | io_apic_write(idx, 0, reg_00.raw); | |
2564 | reg_00.raw = io_apic_read(idx, 0); | |
2565 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2566 | /* Sanity check */ | |
2567 | BUG_ON(reg_00.bits.ID != new_id); | |
2568 | ||
2569 | return new_id; | |
41098ffe | 2570 | } |
58f892e0 | 2571 | #endif |
1da177e4 | 2572 | |
67dc5e70 | 2573 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2574 | { |
2575 | union IO_APIC_reg_01 reg_01; | |
2576 | unsigned long flags; | |
2577 | ||
dade7716 | 2578 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2579 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2580 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2581 | |
2582 | return reg_01.bits.version; | |
2583 | } | |
2584 | ||
9a0a91bb | 2585 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2586 | { |
9a0a91bb | 2587 | int ioapic, pin, idx; |
61fd47e0 SL |
2588 | |
2589 | if (skip_ioapic_setup) | |
2590 | return -1; | |
2591 | ||
9a0a91bb EB |
2592 | ioapic = mp_find_ioapic(gsi); |
2593 | if (ioapic < 0) | |
61fd47e0 SL |
2594 | return -1; |
2595 | ||
9a0a91bb EB |
2596 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2597 | if (pin < 0) | |
2598 | return -1; | |
2599 | ||
2600 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2601 | if (idx < 0) | |
61fd47e0 SL |
2602 | return -1; |
2603 | ||
9a0a91bb EB |
2604 | *trigger = irq_trigger(idx); |
2605 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2606 | return 0; |
2607 | } | |
2608 | ||
497c9a19 YL |
2609 | /* |
2610 | * This function currently is only a helper for the i386 smp boot process where | |
2611 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2612 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2613 | */ |
2614 | #ifdef CONFIG_SMP | |
2615 | void __init setup_ioapic_dest(void) | |
2616 | { | |
fad53995 | 2617 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2618 | const struct cpumask *mask; |
5451ddc5 | 2619 | struct irq_data *idata; |
497c9a19 YL |
2620 | |
2621 | if (skip_ioapic_setup == 1) | |
2622 | return; | |
2623 | ||
f44d1692 | 2624 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2625 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2626 | if (irq_entry == -1) | |
2627 | continue; | |
6c2e9403 | 2628 | |
d7f3d478 JL |
2629 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2630 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2631 | continue; |
2632 | ||
5451ddc5 | 2633 | idata = irq_get_irq_data(irq); |
6c2e9403 | 2634 | |
b9c61b70 YL |
2635 | /* |
2636 | * Honour affinities which have been set in early boot | |
2637 | */ | |
5451ddc5 TG |
2638 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
2639 | mask = idata->affinity; | |
b9c61b70 YL |
2640 | else |
2641 | mask = apic->target_cpus(); | |
497c9a19 | 2642 | |
aa5cb97f | 2643 | irq_set_affinity(irq, mask); |
497c9a19 | 2644 | } |
b9c61b70 | 2645 | |
497c9a19 YL |
2646 | } |
2647 | #endif | |
2648 | ||
54168ed7 IM |
2649 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2650 | ||
2651 | static struct resource *ioapic_resources; | |
2652 | ||
f44d1692 | 2653 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2654 | { |
2655 | unsigned long n; | |
2656 | struct resource *res; | |
2657 | char *mem; | |
f44d1692 | 2658 | int i, num = 0; |
54168ed7 | 2659 | |
f44d1692 JL |
2660 | for_each_ioapic(i) |
2661 | num++; | |
2662 | if (num == 0) | |
54168ed7 IM |
2663 | return NULL; |
2664 | ||
2665 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 2666 | n *= num; |
54168ed7 IM |
2667 | |
2668 | mem = alloc_bootmem(n); | |
2669 | res = (void *)mem; | |
2670 | ||
f44d1692 | 2671 | mem += sizeof(struct resource) * num; |
54168ed7 | 2672 | |
f44d1692 JL |
2673 | num = 0; |
2674 | for_each_ioapic(i) { | |
2675 | res[num].name = mem; | |
2676 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2677 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2678 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 2679 | num++; |
15516a3b | 2680 | ioapics[i].iomem_res = res; |
54168ed7 IM |
2681 | } |
2682 | ||
2683 | ioapic_resources = res; | |
2684 | ||
2685 | return res; | |
2686 | } | |
54168ed7 | 2687 | |
4a8e2a31 | 2688 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
2689 | { |
2690 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2691 | struct resource *ioapic_res; |
d6c88a50 | 2692 | int i; |
f3294a33 | 2693 | |
f44d1692 JL |
2694 | ioapic_res = ioapic_setup_resources(); |
2695 | for_each_ioapic(i) { | |
f3294a33 | 2696 | if (smp_found_config) { |
d5371430 | 2697 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2698 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2699 | if (!ioapic_phys) { |
2700 | printk(KERN_ERR | |
2701 | "WARNING: bogus zero IO-APIC " | |
2702 | "address found in MPTABLE, " | |
2703 | "disabling IO/APIC support!\n"); | |
2704 | smp_found_config = 0; | |
2705 | skip_ioapic_setup = 1; | |
2706 | goto fake_ioapic_page; | |
2707 | } | |
54168ed7 | 2708 | #endif |
f3294a33 | 2709 | } else { |
54168ed7 | 2710 | #ifdef CONFIG_X86_32 |
f3294a33 | 2711 | fake_ioapic_page: |
54168ed7 | 2712 | #endif |
e79c65a9 | 2713 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2714 | ioapic_phys = __pa(ioapic_phys); |
2715 | } | |
2716 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2717 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2718 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2719 | ioapic_phys); | |
f3294a33 | 2720 | idx++; |
54168ed7 | 2721 | |
ffc43836 | 2722 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2723 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2724 | ioapic_res++; |
f3294a33 YL |
2725 | } |
2726 | } | |
2727 | ||
857fdc53 | 2728 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2729 | { |
2730 | int i; | |
2731 | struct resource *r = ioapic_resources; | |
2732 | ||
2733 | if (!r) { | |
857fdc53 | 2734 | if (nr_ioapics > 0) |
04c93ce4 BZ |
2735 | printk(KERN_ERR |
2736 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 2737 | return; |
54168ed7 IM |
2738 | } |
2739 | ||
f44d1692 | 2740 | for_each_ioapic(i) { |
54168ed7 IM |
2741 | insert_resource(&iomem_resource, r); |
2742 | r++; | |
2743 | } | |
54168ed7 | 2744 | } |
2a4ab640 | 2745 | |
eddb0c55 | 2746 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 2747 | { |
f44d1692 | 2748 | int i; |
2a4ab640 | 2749 | |
678301ec PB |
2750 | if (nr_ioapics == 0) |
2751 | return -1; | |
2752 | ||
2a4ab640 | 2753 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 2754 | for_each_ioapic(i) { |
c040aaeb | 2755 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 2756 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
2757 | return i; |
2758 | } | |
54168ed7 | 2759 | |
2a4ab640 FT |
2760 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
2761 | return -1; | |
2762 | } | |
2763 | ||
eddb0c55 | 2764 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 2765 | { |
c040aaeb SS |
2766 | struct mp_ioapic_gsi *gsi_cfg; |
2767 | ||
f44d1692 | 2768 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 2769 | return -1; |
c040aaeb SS |
2770 | |
2771 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2772 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
2773 | return -1; |
2774 | ||
c040aaeb | 2775 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
2776 | } |
2777 | ||
67dc5e70 | 2778 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
2779 | { |
2780 | union IO_APIC_reg_00 reg_00; | |
2781 | union IO_APIC_reg_01 reg_01; | |
2782 | union IO_APIC_reg_02 reg_02; | |
2783 | ||
2784 | reg_00.raw = io_apic_read(idx, 0); | |
2785 | reg_01.raw = io_apic_read(idx, 1); | |
2786 | reg_02.raw = io_apic_read(idx, 2); | |
2787 | ||
2788 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
2789 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
2790 | mpc_ioapic_addr(idx)); | |
2791 | return 1; | |
2792 | } | |
2793 | ||
2794 | return 0; | |
2795 | } | |
2796 | ||
35ef9c94 JL |
2797 | static int find_free_ioapic_entry(void) |
2798 | { | |
7db298cb JL |
2799 | int idx; |
2800 | ||
2801 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
2802 | if (ioapics[idx].nr_registers == 0) | |
2803 | return idx; | |
2804 | ||
2805 | return MAX_IO_APICS; | |
35ef9c94 JL |
2806 | } |
2807 | ||
2808 | /** | |
2809 | * mp_register_ioapic - Register an IOAPIC device | |
2810 | * @id: hardware IOAPIC ID | |
2811 | * @address: physical address of IOAPIC register area | |
2812 | * @gsi_base: base of GSI associated with the IOAPIC | |
2813 | * @cfg: configuration information for the IOAPIC | |
2814 | */ | |
2815 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
2816 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 2817 | { |
7db298cb | 2818 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 2819 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
2820 | int idx, ioapic, entries; |
2821 | u32 gsi_end; | |
2a4ab640 | 2822 | |
35ef9c94 JL |
2823 | if (!address) { |
2824 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
2825 | return -EINVAL; | |
2826 | } | |
2827 | for_each_ioapic(ioapic) | |
2828 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
2829 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
2830 | address, ioapic); | |
2831 | return -EEXIST; | |
2832 | } | |
2a4ab640 | 2833 | |
35ef9c94 JL |
2834 | idx = find_free_ioapic_entry(); |
2835 | if (idx >= MAX_IO_APICS) { | |
2836 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
2837 | MAX_IO_APICS, idx); | |
2838 | return -ENOSPC; | |
2839 | } | |
2a4ab640 | 2840 | |
d5371430 SS |
2841 | ioapics[idx].mp_config.type = MP_IOAPIC; |
2842 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
2843 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
2844 | |
2845 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
2846 | if (bad_ioapic_register(idx)) { |
2847 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 2848 | return -ENODEV; |
73d63d03 SS |
2849 | } |
2850 | ||
5411dc4c | 2851 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 2852 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
2853 | |
2854 | /* | |
2855 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
2856 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
2857 | */ | |
7716a5c4 | 2858 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
2859 | gsi_end = gsi_base + entries - 1; |
2860 | for_each_ioapic(ioapic) { | |
2861 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2862 | if ((gsi_base >= gsi_cfg->gsi_base && | |
2863 | gsi_base <= gsi_cfg->gsi_end) || | |
2864 | (gsi_end >= gsi_cfg->gsi_base && | |
2865 | gsi_end <= gsi_cfg->gsi_end)) { | |
2866 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
2867 | gsi_base, gsi_end, | |
2868 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2869 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2870 | return -ENOSPC; | |
2871 | } | |
2872 | } | |
c040aaeb SS |
2873 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
2874 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 2875 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 2876 | |
35ef9c94 JL |
2877 | ioapics[idx].irqdomain = NULL; |
2878 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 2879 | |
7db298cb JL |
2880 | /* |
2881 | * If mp_register_ioapic() is called during early boot stage when | |
2882 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
2883 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
2884 | */ | |
2885 | if (hotplug) { | |
2886 | if (mp_irqdomain_create(idx)) { | |
2887 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2888 | return -ENOMEM; | |
2889 | } | |
2890 | alloc_ioapic_saved_registers(idx); | |
2891 | } | |
2892 | ||
c040aaeb SS |
2893 | if (gsi_cfg->gsi_end >= gsi_top) |
2894 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
2895 | if (nr_ioapics <= idx) |
2896 | nr_ioapics = idx + 1; | |
2897 | ||
2898 | /* Set nr_registers to mark entry present */ | |
2899 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 2900 | |
73d63d03 SS |
2901 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
2902 | idx, mpc_ioapic_id(idx), | |
2903 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
2904 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 2905 | |
35ef9c94 | 2906 | return 0; |
2a4ab640 | 2907 | } |
05ddafb1 | 2908 | |
15516a3b JL |
2909 | int mp_unregister_ioapic(u32 gsi_base) |
2910 | { | |
2911 | int ioapic, pin; | |
2912 | int found = 0; | |
15516a3b JL |
2913 | |
2914 | for_each_ioapic(ioapic) | |
2915 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
2916 | found = 1; | |
2917 | break; | |
2918 | } | |
2919 | if (!found) { | |
2920 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
2921 | return -ENODEV; | |
2922 | } | |
2923 | ||
2924 | for_each_pin(ioapic, pin) { | |
d32932d0 JL |
2925 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
2926 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); | |
2927 | struct mp_chip_data *data; | |
2928 | ||
2929 | if (irq >= 0) { | |
2930 | data = irq_get_chip_data(irq); | |
2931 | if (data && data->count) { | |
2932 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
2933 | pin, ioapic); | |
2934 | return -EBUSY; | |
2935 | } | |
15516a3b JL |
2936 | } |
2937 | } | |
2938 | ||
2939 | /* Mark entry not present */ | |
2940 | ioapics[ioapic].nr_registers = 0; | |
2941 | ioapic_destroy_irqdomain(ioapic); | |
2942 | free_ioapic_saved_registers(ioapic); | |
2943 | if (ioapics[ioapic].iomem_res) | |
2944 | release_resource(ioapics[ioapic].iomem_res); | |
2945 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
2946 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
2947 | ||
2948 | return 0; | |
2949 | } | |
2950 | ||
e89900c9 JL |
2951 | int mp_ioapic_registered(u32 gsi_base) |
2952 | { | |
2953 | int ioapic; | |
2954 | ||
2955 | for_each_ioapic(ioapic) | |
2956 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
2957 | return 1; | |
2958 | ||
2959 | return 0; | |
2960 | } | |
2961 | ||
49c7e600 | 2962 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
5ad274d4 | 2963 | struct irq_alloc_info *info) |
49c7e600 JL |
2964 | { |
2965 | if (info && info->ioapic_valid) { | |
2966 | data->trigger = info->ioapic_trigger; | |
2967 | data->polarity = info->ioapic_polarity; | |
2968 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
2969 | &data->polarity) < 0) { | |
2970 | /* PCI interrupts are always polarity one level triggered. */ | |
2971 | data->trigger = 1; | |
2972 | data->polarity = 1; | |
2973 | } | |
2974 | } | |
2975 | ||
2976 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
2977 | struct IO_APIC_route_entry *entry) | |
2978 | { | |
2979 | memset(entry, 0, sizeof(*entry)); | |
2980 | entry->delivery_mode = apic->irq_delivery_mode; | |
2981 | entry->dest_mode = apic->irq_dest_mode; | |
2982 | entry->dest = cfg->dest_apicid; | |
2983 | entry->vector = cfg->vector; | |
2984 | entry->mask = 0; /* enable IRQ */ | |
2985 | entry->trigger = data->trigger; | |
2986 | entry->polarity = data->polarity; | |
2987 | /* | |
2988 | * Mask level triggered irqs. | |
2989 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
2990 | */ | |
2991 | if (data->trigger) | |
2992 | entry->mask = 1; | |
2993 | } | |
2994 | ||
2995 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
2996 | unsigned int nr_irqs, void *arg) | |
2997 | { | |
2998 | int ret, ioapic, pin; | |
2999 | struct irq_cfg *cfg; | |
3000 | struct irq_data *irq_data; | |
3001 | struct mp_chip_data *data; | |
3002 | struct irq_alloc_info *info = arg; | |
3003 | ||
3004 | if (!info || nr_irqs > 1) | |
3005 | return -EINVAL; | |
3006 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3007 | if (!irq_data) | |
3008 | return -EINVAL; | |
3009 | ||
3010 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
3011 | pin = info->ioapic_pin; | |
3012 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
3013 | return -EEXIST; | |
3014 | ||
3015 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3016 | if (!data) | |
3017 | return -ENOMEM; | |
3018 | ||
3019 | info->ioapic_entry = &data->entry; | |
3020 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
3021 | if (ret < 0) { | |
3022 | kfree(data); | |
3023 | return ret; | |
3024 | } | |
3025 | ||
4467715a | 3026 | INIT_LIST_HEAD(&data->irq_2_pin); |
49c7e600 | 3027 | irq_data->hwirq = info->ioapic_pin; |
d32932d0 JL |
3028 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
3029 | &ioapic_chip : &ioapic_ir_chip; | |
49c7e600 JL |
3030 | irq_data->chip_data = data; |
3031 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
3032 | ||
3033 | cfg = irqd_cfg(irq_data); | |
4467715a | 3034 | add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); |
49c7e600 JL |
3035 | if (info->ioapic_entry) |
3036 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
3037 | mp_register_handler(virq, data->trigger); | |
3038 | if (virq < nr_legacy_irqs()) | |
3039 | legacy_pic->mask(virq); | |
3040 | ||
3041 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
3042 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
3043 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
3044 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
3045 | ||
3046 | return 0; | |
3047 | } | |
3048 | ||
3049 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
3050 | unsigned int nr_irqs) | |
3051 | { | |
49c7e600 | 3052 | struct irq_data *irq_data; |
4467715a | 3053 | struct mp_chip_data *data; |
49c7e600 JL |
3054 | |
3055 | BUG_ON(nr_irqs != 1); | |
3056 | irq_data = irq_domain_get_irq_data(domain, virq); | |
3057 | if (irq_data && irq_data->chip_data) { | |
4467715a JL |
3058 | data = irq_data->chip_data; |
3059 | __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), | |
49c7e600 | 3060 | (int)irq_data->hwirq); |
4467715a | 3061 | WARN_ON(!list_empty(&data->irq_2_pin)); |
49c7e600 JL |
3062 | kfree(irq_data->chip_data); |
3063 | } | |
3064 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
3065 | } | |
3066 | ||
3067 | void mp_irqdomain_activate(struct irq_domain *domain, | |
3068 | struct irq_data *irq_data) | |
3069 | { | |
3070 | unsigned long flags; | |
3071 | struct irq_pin_list *entry; | |
3072 | struct mp_chip_data *data = irq_data->chip_data; | |
49c7e600 JL |
3073 | |
3074 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 3075 | for_each_irq_pin(entry, data->irq_2_pin) |
49c7e600 JL |
3076 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); |
3077 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
3078 | } | |
3079 | ||
3080 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
3081 | struct irq_data *irq_data) | |
3082 | { | |
3083 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
3084 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
3085 | (int)irq_data->hwirq); | |
3086 | } | |
3087 | ||
49c7e600 JL |
3088 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) |
3089 | { | |
3090 | return (int)(long)domain->host_data; | |
3091 | } |