Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
7b6aa335 | 65 | #include <asm/apic.h> |
1da177e4 | 66 | |
32f71aff MR |
67 | #define __apicdebuginit(type) static type __init |
68 | ||
1da177e4 | 69 | /* |
54168ed7 IM |
70 | * Is the SiS APIC rmw bug present ? |
71 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
72 | */ |
73 | int sis_apic_bug = -1; | |
74 | ||
efa2559f YL |
75 | static DEFINE_SPINLOCK(ioapic_lock); |
76 | static DEFINE_SPINLOCK(vector_lock); | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * # of IRQ routing registers | |
80 | */ | |
81 | int nr_ioapic_registers[MAX_IO_APICS]; | |
82 | ||
9f640ccb | 83 | /* I/O APIC entries */ |
b5ba7e6d | 84 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
85 | int nr_ioapics; |
86 | ||
584f734d | 87 | /* MP IRQ source entries */ |
c2c21745 | 88 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
89 | |
90 | /* # of MP IRQ source entries */ | |
91 | int mp_irq_entries; | |
92 | ||
8732fc4b AS |
93 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
94 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
95 | #endif | |
96 | ||
97 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
98 | ||
efa2559f YL |
99 | int skip_ioapic_setup; |
100 | ||
65a4e574 IM |
101 | void arch_disable_smp_support(void) |
102 | { | |
103 | #ifdef CONFIG_PCI | |
104 | noioapicquirk = 1; | |
105 | noioapicreroute = -1; | |
106 | #endif | |
107 | skip_ioapic_setup = 1; | |
108 | } | |
109 | ||
54168ed7 | 110 | static int __init parse_noapic(char *str) |
efa2559f YL |
111 | { |
112 | /* disable IO-APIC */ | |
65a4e574 | 113 | arch_disable_smp_support(); |
efa2559f YL |
114 | return 0; |
115 | } | |
116 | early_param("noapic", parse_noapic); | |
66759a01 | 117 | |
0f978f45 | 118 | struct irq_pin_list; |
0b8f1efa YL |
119 | |
120 | /* | |
121 | * This is performance-critical, we want to do it O(1) | |
122 | * | |
123 | * the indexing order of this array favors 1:1 mappings | |
124 | * between pins and IRQs. | |
125 | */ | |
126 | ||
127 | struct irq_pin_list { | |
128 | int apic, pin; | |
129 | struct irq_pin_list *next; | |
130 | }; | |
131 | ||
85ac16d0 | 132 | static struct irq_pin_list *get_one_free_irq_2_pin(int node) |
0b8f1efa YL |
133 | { |
134 | struct irq_pin_list *pin; | |
0b8f1efa YL |
135 | |
136 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
137 | |
138 | return pin; | |
139 | } | |
140 | ||
a1420f39 | 141 | struct irq_cfg { |
0f978f45 | 142 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
143 | cpumask_var_t domain; |
144 | cpumask_var_t old_domain; | |
497c9a19 | 145 | unsigned move_cleanup_count; |
a1420f39 | 146 | u8 vector; |
497c9a19 | 147 | u8 move_in_progress : 1; |
a1420f39 YL |
148 | }; |
149 | ||
a1420f39 | 150 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
151 | #ifdef CONFIG_SPARSE_IRQ |
152 | static struct irq_cfg irq_cfgx[] = { | |
153 | #else | |
d6c88a50 | 154 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 155 | #endif |
22f65d31 MT |
156 | [0] = { .vector = IRQ0_VECTOR, }, |
157 | [1] = { .vector = IRQ1_VECTOR, }, | |
158 | [2] = { .vector = IRQ2_VECTOR, }, | |
159 | [3] = { .vector = IRQ3_VECTOR, }, | |
160 | [4] = { .vector = IRQ4_VECTOR, }, | |
161 | [5] = { .vector = IRQ5_VECTOR, }, | |
162 | [6] = { .vector = IRQ6_VECTOR, }, | |
163 | [7] = { .vector = IRQ7_VECTOR, }, | |
164 | [8] = { .vector = IRQ8_VECTOR, }, | |
165 | [9] = { .vector = IRQ9_VECTOR, }, | |
166 | [10] = { .vector = IRQ10_VECTOR, }, | |
167 | [11] = { .vector = IRQ11_VECTOR, }, | |
168 | [12] = { .vector = IRQ12_VECTOR, }, | |
169 | [13] = { .vector = IRQ13_VECTOR, }, | |
170 | [14] = { .vector = IRQ14_VECTOR, }, | |
171 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
172 | }; |
173 | ||
13a0c3c2 | 174 | int __init arch_early_irq_init(void) |
8f09cd20 | 175 | { |
0b8f1efa YL |
176 | struct irq_cfg *cfg; |
177 | struct irq_desc *desc; | |
178 | int count; | |
179 | int i; | |
d6c88a50 | 180 | |
0b8f1efa YL |
181 | cfg = irq_cfgx; |
182 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 183 | |
0b8f1efa YL |
184 | for (i = 0; i < count; i++) { |
185 | desc = irq_to_desc(i); | |
186 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
187 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
188 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
189 | if (i < NR_IRQS_LEGACY) | |
190 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 191 | } |
13a0c3c2 YL |
192 | |
193 | return 0; | |
0b8f1efa | 194 | } |
8f09cd20 | 195 | |
0b8f1efa | 196 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 197 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 198 | { |
0b8f1efa YL |
199 | struct irq_cfg *cfg = NULL; |
200 | struct irq_desc *desc; | |
1da177e4 | 201 | |
0b8f1efa YL |
202 | desc = irq_to_desc(irq); |
203 | if (desc) | |
204 | cfg = desc->chip_data; | |
0f978f45 | 205 | |
0b8f1efa | 206 | return cfg; |
8f09cd20 | 207 | } |
d6c88a50 | 208 | |
85ac16d0 | 209 | static struct irq_cfg *get_one_free_irq_cfg(int node) |
8f09cd20 | 210 | { |
0b8f1efa | 211 | struct irq_cfg *cfg; |
0f978f45 | 212 | |
0b8f1efa | 213 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 214 | if (cfg) { |
80855f73 | 215 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
216 | kfree(cfg); |
217 | cfg = NULL; | |
80855f73 MT |
218 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
219 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
220 | free_cpumask_var(cfg->domain); |
221 | kfree(cfg); | |
222 | cfg = NULL; | |
223 | } else { | |
224 | cpumask_clear(cfg->domain); | |
225 | cpumask_clear(cfg->old_domain); | |
226 | } | |
227 | } | |
0f978f45 | 228 | |
0b8f1efa | 229 | return cfg; |
8f09cd20 YL |
230 | } |
231 | ||
85ac16d0 | 232 | int arch_init_chip_data(struct irq_desc *desc, int node) |
0f978f45 | 233 | { |
0b8f1efa | 234 | struct irq_cfg *cfg; |
d6c88a50 | 235 | |
0b8f1efa YL |
236 | cfg = desc->chip_data; |
237 | if (!cfg) { | |
85ac16d0 | 238 | desc->chip_data = get_one_free_irq_cfg(node); |
0b8f1efa YL |
239 | if (!desc->chip_data) { |
240 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
241 | BUG_ON(1); | |
242 | } | |
243 | } | |
1da177e4 | 244 | |
13a0c3c2 | 245 | return 0; |
0b8f1efa | 246 | } |
0f978f45 | 247 | |
fcef5911 | 248 | /* for move_irq_desc */ |
48a1b10a | 249 | static void |
85ac16d0 | 250 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node) |
0f978f45 | 251 | { |
48a1b10a YL |
252 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
253 | ||
254 | cfg->irq_2_pin = NULL; | |
255 | old_entry = old_cfg->irq_2_pin; | |
256 | if (!old_entry) | |
257 | return; | |
0f978f45 | 258 | |
85ac16d0 | 259 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
260 | if (!entry) |
261 | return; | |
0f978f45 | 262 | |
48a1b10a YL |
263 | entry->apic = old_entry->apic; |
264 | entry->pin = old_entry->pin; | |
265 | head = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | while (old_entry) { | |
85ac16d0 | 269 | entry = get_one_free_irq_2_pin(node); |
48a1b10a YL |
270 | if (!entry) { |
271 | entry = head; | |
272 | while (entry) { | |
273 | head = entry->next; | |
274 | kfree(entry); | |
275 | entry = head; | |
276 | } | |
277 | /* still use the old one */ | |
278 | return; | |
279 | } | |
280 | entry->apic = old_entry->apic; | |
281 | entry->pin = old_entry->pin; | |
282 | tail->next = entry; | |
283 | tail = entry; | |
284 | old_entry = old_entry->next; | |
285 | } | |
0f978f45 | 286 | |
48a1b10a YL |
287 | tail->next = NULL; |
288 | cfg->irq_2_pin = head; | |
0f978f45 | 289 | } |
0f978f45 | 290 | |
48a1b10a | 291 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 292 | { |
48a1b10a | 293 | struct irq_pin_list *entry, *next; |
0f978f45 | 294 | |
48a1b10a YL |
295 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
296 | return; | |
301e6190 | 297 | |
48a1b10a | 298 | entry = old_cfg->irq_2_pin; |
0f978f45 | 299 | |
48a1b10a YL |
300 | while (entry) { |
301 | next = entry->next; | |
302 | kfree(entry); | |
303 | entry = next; | |
304 | } | |
305 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 306 | } |
0f978f45 | 307 | |
48a1b10a | 308 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
85ac16d0 | 309 | struct irq_desc *desc, int node) |
0f978f45 | 310 | { |
48a1b10a YL |
311 | struct irq_cfg *cfg; |
312 | struct irq_cfg *old_cfg; | |
0f978f45 | 313 | |
85ac16d0 | 314 | cfg = get_one_free_irq_cfg(node); |
301e6190 | 315 | |
48a1b10a YL |
316 | if (!cfg) |
317 | return; | |
318 | ||
319 | desc->chip_data = cfg; | |
320 | ||
321 | old_cfg = old_desc->chip_data; | |
322 | ||
323 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
324 | ||
85ac16d0 | 325 | init_copy_irq_2_pin(old_cfg, cfg, node); |
0f978f45 | 326 | } |
1da177e4 | 327 | |
48a1b10a YL |
328 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
329 | { | |
330 | kfree(old_cfg); | |
331 | } | |
332 | ||
333 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
334 | { | |
335 | struct irq_cfg *old_cfg, *cfg; | |
336 | ||
337 | old_cfg = old_desc->chip_data; | |
338 | cfg = desc->chip_data; | |
339 | ||
340 | if (old_cfg == cfg) | |
341 | return; | |
342 | ||
343 | if (old_cfg) { | |
344 | free_irq_2_pin(old_cfg, cfg); | |
345 | free_irq_cfg(old_cfg); | |
346 | old_desc->chip_data = NULL; | |
347 | } | |
348 | } | |
fcef5911 | 349 | /* end for move_irq_desc */ |
48a1b10a | 350 | |
0b8f1efa YL |
351 | #else |
352 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
353 | { | |
354 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 355 | } |
1da177e4 | 356 | |
0b8f1efa YL |
357 | #endif |
358 | ||
130fe05d LT |
359 | struct io_apic { |
360 | unsigned int index; | |
361 | unsigned int unused[3]; | |
362 | unsigned int data; | |
0280f7c4 SS |
363 | unsigned int unused2[11]; |
364 | unsigned int eoi; | |
130fe05d LT |
365 | }; |
366 | ||
367 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
368 | { | |
369 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 370 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
371 | } |
372 | ||
0280f7c4 SS |
373 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
374 | { | |
375 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
376 | writel(vector, &io_apic->eoi); | |
377 | } | |
378 | ||
130fe05d LT |
379 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) |
380 | { | |
381 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
382 | writel(reg, &io_apic->index); | |
383 | return readl(&io_apic->data); | |
384 | } | |
385 | ||
386 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
387 | { | |
388 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
389 | writel(reg, &io_apic->index); | |
390 | writel(value, &io_apic->data); | |
391 | } | |
392 | ||
393 | /* | |
394 | * Re-write a value: to be used for read-modify-write | |
395 | * cycles where the read already set up the index register. | |
396 | * | |
397 | * Older SiS APIC requires we rewrite the index register | |
398 | */ | |
399 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
400 | { | |
54168ed7 | 401 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
402 | |
403 | if (sis_apic_bug) | |
404 | writel(reg, &io_apic->index); | |
130fe05d LT |
405 | writel(value, &io_apic->data); |
406 | } | |
407 | ||
3145e941 | 408 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
409 | { |
410 | struct irq_pin_list *entry; | |
411 | unsigned long flags; | |
047c8fdb YL |
412 | |
413 | spin_lock_irqsave(&ioapic_lock, flags); | |
414 | entry = cfg->irq_2_pin; | |
415 | for (;;) { | |
416 | unsigned int reg; | |
417 | int pin; | |
418 | ||
419 | if (!entry) | |
420 | break; | |
421 | pin = entry->pin; | |
422 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
423 | /* Is the remote IRR bit set? */ | |
424 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
425 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
426 | return true; | |
427 | } | |
428 | if (!entry->next) | |
429 | break; | |
430 | entry = entry->next; | |
431 | } | |
432 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
433 | ||
434 | return false; | |
435 | } | |
047c8fdb | 436 | |
cf4c6a2f AK |
437 | union entry_union { |
438 | struct { u32 w1, w2; }; | |
439 | struct IO_APIC_route_entry entry; | |
440 | }; | |
441 | ||
442 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
443 | { | |
444 | union entry_union eu; | |
445 | unsigned long flags; | |
446 | spin_lock_irqsave(&ioapic_lock, flags); | |
447 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
448 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
449 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
450 | return eu.entry; | |
451 | } | |
452 | ||
f9dadfa7 LT |
453 | /* |
454 | * When we write a new IO APIC routing entry, we need to write the high | |
455 | * word first! If the mask bit in the low word is clear, we will enable | |
456 | * the interrupt, and we need to make sure the entry is fully populated | |
457 | * before that happens. | |
458 | */ | |
d15512f4 AK |
459 | static void |
460 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 461 | { |
cf4c6a2f AK |
462 | union entry_union eu; |
463 | eu.entry = e; | |
f9dadfa7 LT |
464 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
465 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
466 | } |
467 | ||
ca97ab90 | 468 | void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
469 | { |
470 | unsigned long flags; | |
471 | spin_lock_irqsave(&ioapic_lock, flags); | |
472 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
473 | spin_unlock_irqrestore(&ioapic_lock, flags); |
474 | } | |
475 | ||
476 | /* | |
477 | * When we mask an IO APIC routing entry, we need to write the low | |
478 | * word first, in order to set the mask bit before we change the | |
479 | * high bits! | |
480 | */ | |
481 | static void ioapic_mask_entry(int apic, int pin) | |
482 | { | |
483 | unsigned long flags; | |
484 | union entry_union eu = { .entry.mask = 1 }; | |
485 | ||
cf4c6a2f AK |
486 | spin_lock_irqsave(&ioapic_lock, flags); |
487 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
488 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
489 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
490 | } | |
491 | ||
1da177e4 LT |
492 | /* |
493 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
494 | * shared ISA-space IRQs, so we have to support them. We are super | |
495 | * fast in the common case, and fast for shared ISA-space IRQs. | |
496 | */ | |
85ac16d0 | 497 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 498 | { |
0f978f45 YL |
499 | struct irq_pin_list *entry; |
500 | ||
0f978f45 YL |
501 | entry = cfg->irq_2_pin; |
502 | if (!entry) { | |
85ac16d0 | 503 | entry = get_one_free_irq_2_pin(node); |
0b8f1efa YL |
504 | if (!entry) { |
505 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
506 | apic, pin); | |
507 | return; | |
508 | } | |
0f978f45 YL |
509 | cfg->irq_2_pin = entry; |
510 | entry->apic = apic; | |
511 | entry->pin = pin; | |
0f978f45 YL |
512 | return; |
513 | } | |
1da177e4 | 514 | |
0f978f45 YL |
515 | while (entry->next) { |
516 | /* not again, please */ | |
517 | if (entry->apic == apic && entry->pin == pin) | |
518 | return; | |
1da177e4 | 519 | |
0f978f45 | 520 | entry = entry->next; |
1da177e4 | 521 | } |
0f978f45 | 522 | |
85ac16d0 | 523 | entry->next = get_one_free_irq_2_pin(node); |
0f978f45 | 524 | entry = entry->next; |
1da177e4 LT |
525 | entry->apic = apic; |
526 | entry->pin = pin; | |
527 | } | |
528 | ||
529 | /* | |
530 | * Reroute an IRQ to a different pin. | |
531 | */ | |
85ac16d0 | 532 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
1da177e4 LT |
533 | int oldapic, int oldpin, |
534 | int newapic, int newpin) | |
535 | { | |
0f978f45 YL |
536 | struct irq_pin_list *entry = cfg->irq_2_pin; |
537 | int replaced = 0; | |
1da177e4 | 538 | |
0f978f45 | 539 | while (entry) { |
1da177e4 LT |
540 | if (entry->apic == oldapic && entry->pin == oldpin) { |
541 | entry->apic = newapic; | |
542 | entry->pin = newpin; | |
0f978f45 YL |
543 | replaced = 1; |
544 | /* every one is different, right? */ | |
1da177e4 | 545 | break; |
0f978f45 YL |
546 | } |
547 | entry = entry->next; | |
1da177e4 | 548 | } |
0f978f45 YL |
549 | |
550 | /* why? call replace before add? */ | |
551 | if (!replaced) | |
85ac16d0 | 552 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
1da177e4 LT |
553 | } |
554 | ||
3145e941 | 555 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
556 | int mask_and, int mask_or, |
557 | void (*final)(struct irq_pin_list *entry)) | |
558 | { | |
559 | int pin; | |
87783be4 | 560 | struct irq_pin_list *entry; |
047c8fdb | 561 | |
87783be4 CG |
562 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
563 | unsigned int reg; | |
564 | pin = entry->pin; | |
565 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
566 | reg &= mask_and; | |
567 | reg |= mask_or; | |
568 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
569 | if (final) | |
570 | final(entry); | |
571 | } | |
572 | } | |
047c8fdb | 573 | |
3145e941 | 574 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 575 | { |
3145e941 | 576 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 577 | } |
047c8fdb | 578 | |
4e738e2f | 579 | #ifdef CONFIG_X86_64 |
7f3e632f | 580 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 581 | { |
87783be4 CG |
582 | /* |
583 | * Synchronize the IO-APIC and the CPU by doing | |
584 | * a dummy read from the IO-APIC | |
585 | */ | |
586 | struct io_apic __iomem *io_apic; | |
587 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 588 | readl(&io_apic->data); |
1da177e4 LT |
589 | } |
590 | ||
3145e941 | 591 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 592 | { |
3145e941 | 593 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
594 | } |
595 | #else /* CONFIG_X86_32 */ | |
3145e941 | 596 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 597 | { |
3145e941 | 598 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 599 | } |
1da177e4 | 600 | |
3145e941 | 601 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 602 | { |
3145e941 | 603 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
604 | IO_APIC_REDIR_MASKED, NULL); |
605 | } | |
1da177e4 | 606 | |
3145e941 | 607 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 608 | { |
3145e941 | 609 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
610 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
611 | } | |
612 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 613 | |
3145e941 | 614 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 615 | { |
3145e941 | 616 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
617 | unsigned long flags; |
618 | ||
3145e941 YL |
619 | BUG_ON(!cfg); |
620 | ||
1da177e4 | 621 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 622 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
623 | spin_unlock_irqrestore(&ioapic_lock, flags); |
624 | } | |
625 | ||
3145e941 | 626 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 627 | { |
3145e941 | 628 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
629 | unsigned long flags; |
630 | ||
631 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 632 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
633 | spin_unlock_irqrestore(&ioapic_lock, flags); |
634 | } | |
635 | ||
3145e941 YL |
636 | static void mask_IO_APIC_irq(unsigned int irq) |
637 | { | |
638 | struct irq_desc *desc = irq_to_desc(irq); | |
639 | ||
640 | mask_IO_APIC_irq_desc(desc); | |
641 | } | |
642 | static void unmask_IO_APIC_irq(unsigned int irq) | |
643 | { | |
644 | struct irq_desc *desc = irq_to_desc(irq); | |
645 | ||
646 | unmask_IO_APIC_irq_desc(desc); | |
647 | } | |
648 | ||
1da177e4 LT |
649 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
650 | { | |
651 | struct IO_APIC_route_entry entry; | |
36062448 | 652 | |
1da177e4 | 653 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 654 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
655 | if (entry.delivery_mode == dest_SMI) |
656 | return; | |
1da177e4 LT |
657 | /* |
658 | * Disable it in the IO-APIC irq-routing table: | |
659 | */ | |
f9dadfa7 | 660 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
661 | } |
662 | ||
54168ed7 | 663 | static void clear_IO_APIC (void) |
1da177e4 LT |
664 | { |
665 | int apic, pin; | |
666 | ||
667 | for (apic = 0; apic < nr_ioapics; apic++) | |
668 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
669 | clear_IO_APIC_pin(apic, pin); | |
670 | } | |
671 | ||
54168ed7 | 672 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
673 | /* |
674 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
675 | * specific CPU-side IRQs. | |
676 | */ | |
677 | ||
678 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
679 | static int pirq_entries[MAX_PIRQS] = { |
680 | [0 ... MAX_PIRQS - 1] = -1 | |
681 | }; | |
1da177e4 | 682 | |
1da177e4 LT |
683 | static int __init ioapic_pirq_setup(char *str) |
684 | { | |
685 | int i, max; | |
686 | int ints[MAX_PIRQS+1]; | |
687 | ||
688 | get_options(str, ARRAY_SIZE(ints), ints); | |
689 | ||
1da177e4 LT |
690 | apic_printk(APIC_VERBOSE, KERN_INFO |
691 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
692 | max = MAX_PIRQS; | |
693 | if (ints[0] < MAX_PIRQS) | |
694 | max = ints[0]; | |
695 | ||
696 | for (i = 0; i < max; i++) { | |
697 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
698 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
699 | /* | |
700 | * PIRQs are mapped upside down, usually. | |
701 | */ | |
702 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
703 | } | |
704 | return 1; | |
705 | } | |
706 | ||
707 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
708 | #endif /* CONFIG_X86_32 */ |
709 | ||
b24696bc FY |
710 | struct IO_APIC_route_entry **alloc_ioapic_entries(void) |
711 | { | |
712 | int apic; | |
713 | struct IO_APIC_route_entry **ioapic_entries; | |
714 | ||
715 | ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics, | |
716 | GFP_ATOMIC); | |
717 | if (!ioapic_entries) | |
718 | return 0; | |
719 | ||
720 | for (apic = 0; apic < nr_ioapics; apic++) { | |
721 | ioapic_entries[apic] = | |
722 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
723 | nr_ioapic_registers[apic], GFP_ATOMIC); | |
724 | if (!ioapic_entries[apic]) | |
725 | goto nomem; | |
726 | } | |
727 | ||
728 | return ioapic_entries; | |
729 | ||
730 | nomem: | |
731 | while (--apic >= 0) | |
732 | kfree(ioapic_entries[apic]); | |
733 | kfree(ioapic_entries); | |
734 | ||
735 | return 0; | |
736 | } | |
54168ed7 IM |
737 | |
738 | /* | |
05c3dc2c | 739 | * Saves all the IO-APIC RTE's |
54168ed7 | 740 | */ |
b24696bc | 741 | int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) |
54168ed7 | 742 | { |
54168ed7 IM |
743 | int apic, pin; |
744 | ||
b24696bc FY |
745 | if (!ioapic_entries) |
746 | return -ENOMEM; | |
54168ed7 IM |
747 | |
748 | for (apic = 0; apic < nr_ioapics; apic++) { | |
b24696bc FY |
749 | if (!ioapic_entries[apic]) |
750 | return -ENOMEM; | |
54168ed7 | 751 | |
05c3dc2c | 752 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
b24696bc | 753 | ioapic_entries[apic][pin] = |
54168ed7 | 754 | ioapic_read_entry(apic, pin); |
b24696bc | 755 | } |
5ffa4eb2 | 756 | |
54168ed7 IM |
757 | return 0; |
758 | } | |
759 | ||
b24696bc FY |
760 | /* |
761 | * Mask all IO APIC entries. | |
762 | */ | |
763 | void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
05c3dc2c SS |
764 | { |
765 | int apic, pin; | |
766 | ||
b24696bc FY |
767 | if (!ioapic_entries) |
768 | return; | |
769 | ||
05c3dc2c | 770 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc | 771 | if (!ioapic_entries[apic]) |
05c3dc2c | 772 | break; |
b24696bc | 773 | |
05c3dc2c SS |
774 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
775 | struct IO_APIC_route_entry entry; | |
776 | ||
b24696bc | 777 | entry = ioapic_entries[apic][pin]; |
05c3dc2c SS |
778 | if (!entry.mask) { |
779 | entry.mask = 1; | |
780 | ioapic_write_entry(apic, pin, entry); | |
781 | } | |
782 | } | |
783 | } | |
784 | } | |
785 | ||
b24696bc FY |
786 | /* |
787 | * Restore IO APIC entries which was saved in ioapic_entries. | |
788 | */ | |
789 | int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries) | |
54168ed7 IM |
790 | { |
791 | int apic, pin; | |
792 | ||
b24696bc FY |
793 | if (!ioapic_entries) |
794 | return -ENOMEM; | |
795 | ||
5ffa4eb2 | 796 | for (apic = 0; apic < nr_ioapics; apic++) { |
b24696bc FY |
797 | if (!ioapic_entries[apic]) |
798 | return -ENOMEM; | |
799 | ||
54168ed7 IM |
800 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
801 | ioapic_write_entry(apic, pin, | |
b24696bc | 802 | ioapic_entries[apic][pin]); |
5ffa4eb2 | 803 | } |
b24696bc | 804 | return 0; |
54168ed7 IM |
805 | } |
806 | ||
b24696bc FY |
807 | void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries) |
808 | { | |
809 | int apic; | |
810 | ||
811 | for (apic = 0; apic < nr_ioapics; apic++) | |
812 | kfree(ioapic_entries[apic]); | |
813 | ||
814 | kfree(ioapic_entries); | |
54168ed7 | 815 | } |
1da177e4 LT |
816 | |
817 | /* | |
818 | * Find the IRQ entry number of a certain pin. | |
819 | */ | |
820 | static int find_irq_entry(int apic, int pin, int type) | |
821 | { | |
822 | int i; | |
823 | ||
824 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
825 | if (mp_irqs[i].irqtype == type && |
826 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
827 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
828 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
829 | return i; |
830 | ||
831 | return -1; | |
832 | } | |
833 | ||
834 | /* | |
835 | * Find the pin to which IRQ[irq] (ISA) is connected | |
836 | */ | |
fcfd636a | 837 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
838 | { |
839 | int i; | |
840 | ||
841 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 842 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 843 | |
d27e2b8e | 844 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
845 | (mp_irqs[i].irqtype == type) && |
846 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 847 | |
c2c21745 | 848 | return mp_irqs[i].dstirq; |
1da177e4 LT |
849 | } |
850 | return -1; | |
851 | } | |
852 | ||
fcfd636a EB |
853 | static int __init find_isa_irq_apic(int irq, int type) |
854 | { | |
855 | int i; | |
856 | ||
857 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 858 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 859 | |
73b2961b | 860 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
861 | (mp_irqs[i].irqtype == type) && |
862 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
863 | break; |
864 | } | |
865 | if (i < mp_irq_entries) { | |
866 | int apic; | |
54168ed7 | 867 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 868 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
869 | return apic; |
870 | } | |
871 | } | |
872 | ||
873 | return -1; | |
874 | } | |
875 | ||
1da177e4 LT |
876 | /* |
877 | * Find a specific PCI IRQ entry. | |
878 | * Not an __init, possibly needed by modules | |
879 | */ | |
880 | static int pin_2_irq(int idx, int apic, int pin); | |
881 | ||
882 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
883 | { | |
884 | int apic, i, best_guess = -1; | |
885 | ||
54168ed7 IM |
886 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
887 | bus, slot, pin); | |
ce6444d3 | 888 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 889 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
890 | return -1; |
891 | } | |
892 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 893 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
894 | |
895 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
896 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
897 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
898 | break; |
899 | ||
47cab822 | 900 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 901 | !mp_irqs[i].irqtype && |
1da177e4 | 902 | (bus == lbus) && |
c2c21745 JSR |
903 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
904 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
905 | |
906 | if (!(apic || IO_APIC_IRQ(irq))) | |
907 | continue; | |
908 | ||
c2c21745 | 909 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
910 | return irq; |
911 | /* | |
912 | * Use the first all-but-pin matching entry as a | |
913 | * best-guess fuzzy result for broken mptables. | |
914 | */ | |
915 | if (best_guess < 0) | |
916 | best_guess = irq; | |
917 | } | |
918 | } | |
919 | return best_guess; | |
920 | } | |
54168ed7 | 921 | |
129f6946 | 922 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 923 | |
c0a282c2 | 924 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
925 | /* |
926 | * EISA Edge/Level control register, ELCR | |
927 | */ | |
928 | static int EISA_ELCR(unsigned int irq) | |
929 | { | |
99d093d1 | 930 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
931 | unsigned int port = 0x4d0 + (irq >> 3); |
932 | return (inb(port) >> (irq & 7)) & 1; | |
933 | } | |
934 | apic_printk(APIC_VERBOSE, KERN_INFO | |
935 | "Broken MPtable reports ISA irq %d\n", irq); | |
936 | return 0; | |
937 | } | |
54168ed7 | 938 | |
c0a282c2 | 939 | #endif |
1da177e4 | 940 | |
6728801d AS |
941 | /* ISA interrupts are always polarity zero edge triggered, |
942 | * when listed as conforming in the MP table. */ | |
943 | ||
944 | #define default_ISA_trigger(idx) (0) | |
945 | #define default_ISA_polarity(idx) (0) | |
946 | ||
1da177e4 LT |
947 | /* EISA interrupts are always polarity zero and can be edge or level |
948 | * trigger depending on the ELCR value. If an interrupt is listed as | |
949 | * EISA conforming in the MP table, that means its trigger type must | |
950 | * be read in from the ELCR */ | |
951 | ||
c2c21745 | 952 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 953 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
954 | |
955 | /* PCI interrupts are always polarity one level triggered, | |
956 | * when listed as conforming in the MP table. */ | |
957 | ||
958 | #define default_PCI_trigger(idx) (1) | |
959 | #define default_PCI_polarity(idx) (1) | |
960 | ||
961 | /* MCA interrupts are always polarity zero level triggered, | |
962 | * when listed as conforming in the MP table. */ | |
963 | ||
964 | #define default_MCA_trigger(idx) (1) | |
6728801d | 965 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 966 | |
61fd47e0 | 967 | static int MPBIOS_polarity(int idx) |
1da177e4 | 968 | { |
c2c21745 | 969 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
970 | int polarity; |
971 | ||
972 | /* | |
973 | * Determine IRQ line polarity (high active or low active): | |
974 | */ | |
c2c21745 | 975 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 976 | { |
54168ed7 IM |
977 | case 0: /* conforms, ie. bus-type dependent polarity */ |
978 | if (test_bit(bus, mp_bus_not_pci)) | |
979 | polarity = default_ISA_polarity(idx); | |
980 | else | |
981 | polarity = default_PCI_polarity(idx); | |
982 | break; | |
983 | case 1: /* high active */ | |
984 | { | |
985 | polarity = 0; | |
986 | break; | |
987 | } | |
988 | case 2: /* reserved */ | |
989 | { | |
990 | printk(KERN_WARNING "broken BIOS!!\n"); | |
991 | polarity = 1; | |
992 | break; | |
993 | } | |
994 | case 3: /* low active */ | |
995 | { | |
996 | polarity = 1; | |
997 | break; | |
998 | } | |
999 | default: /* invalid */ | |
1000 | { | |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1002 | polarity = 1; | |
1003 | break; | |
1004 | } | |
1da177e4 LT |
1005 | } |
1006 | return polarity; | |
1007 | } | |
1008 | ||
1009 | static int MPBIOS_trigger(int idx) | |
1010 | { | |
c2c21745 | 1011 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1012 | int trigger; |
1013 | ||
1014 | /* | |
1015 | * Determine IRQ trigger mode (edge or level sensitive): | |
1016 | */ | |
c2c21745 | 1017 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1018 | { |
54168ed7 IM |
1019 | case 0: /* conforms, ie. bus-type dependent */ |
1020 | if (test_bit(bus, mp_bus_not_pci)) | |
1021 | trigger = default_ISA_trigger(idx); | |
1022 | else | |
1023 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1024 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1025 | switch (mp_bus_id_to_type[bus]) { |
1026 | case MP_BUS_ISA: /* ISA pin */ | |
1027 | { | |
1028 | /* set before the switch */ | |
1029 | break; | |
1030 | } | |
1031 | case MP_BUS_EISA: /* EISA pin */ | |
1032 | { | |
1033 | trigger = default_EISA_trigger(idx); | |
1034 | break; | |
1035 | } | |
1036 | case MP_BUS_PCI: /* PCI pin */ | |
1037 | { | |
1038 | /* set before the switch */ | |
1039 | break; | |
1040 | } | |
1041 | case MP_BUS_MCA: /* MCA pin */ | |
1042 | { | |
1043 | trigger = default_MCA_trigger(idx); | |
1044 | break; | |
1045 | } | |
1046 | default: | |
1047 | { | |
1048 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1049 | trigger = 1; | |
1050 | break; | |
1051 | } | |
1052 | } | |
1053 | #endif | |
1da177e4 | 1054 | break; |
54168ed7 | 1055 | case 1: /* edge */ |
1da177e4 | 1056 | { |
54168ed7 | 1057 | trigger = 0; |
1da177e4 LT |
1058 | break; |
1059 | } | |
54168ed7 | 1060 | case 2: /* reserved */ |
1da177e4 | 1061 | { |
54168ed7 IM |
1062 | printk(KERN_WARNING "broken BIOS!!\n"); |
1063 | trigger = 1; | |
1da177e4 LT |
1064 | break; |
1065 | } | |
54168ed7 | 1066 | case 3: /* level */ |
1da177e4 | 1067 | { |
54168ed7 | 1068 | trigger = 1; |
1da177e4 LT |
1069 | break; |
1070 | } | |
54168ed7 | 1071 | default: /* invalid */ |
1da177e4 LT |
1072 | { |
1073 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1074 | trigger = 0; |
1da177e4 LT |
1075 | break; |
1076 | } | |
1077 | } | |
1078 | return trigger; | |
1079 | } | |
1080 | ||
1081 | static inline int irq_polarity(int idx) | |
1082 | { | |
1083 | return MPBIOS_polarity(idx); | |
1084 | } | |
1085 | ||
1086 | static inline int irq_trigger(int idx) | |
1087 | { | |
1088 | return MPBIOS_trigger(idx); | |
1089 | } | |
1090 | ||
efa2559f | 1091 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1092 | static int pin_2_irq(int idx, int apic, int pin) |
1093 | { | |
1094 | int irq, i; | |
c2c21745 | 1095 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1096 | |
1097 | /* | |
1098 | * Debugging check, we are in big trouble if this message pops up! | |
1099 | */ | |
c2c21745 | 1100 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1101 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1102 | ||
54168ed7 | 1103 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1104 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1105 | } else { |
643befed AS |
1106 | /* |
1107 | * PCI IRQs are mapped in order | |
1108 | */ | |
1109 | i = irq = 0; | |
1110 | while (i < apic) | |
1111 | irq += nr_ioapic_registers[i++]; | |
1112 | irq += pin; | |
d6c88a50 | 1113 | /* |
54168ed7 IM |
1114 | * For MPS mode, so far only needed by ES7000 platform |
1115 | */ | |
d6c88a50 TG |
1116 | if (ioapic_renumber_irq) |
1117 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1118 | } |
1119 | ||
54168ed7 | 1120 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1121 | /* |
1122 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1123 | */ | |
1124 | if ((pin >= 16) && (pin <= 23)) { | |
1125 | if (pirq_entries[pin-16] != -1) { | |
1126 | if (!pirq_entries[pin-16]) { | |
1127 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1128 | "disabling PIRQ%d\n", pin-16); | |
1129 | } else { | |
1130 | irq = pirq_entries[pin-16]; | |
1131 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1132 | "using PIRQ%d -> IRQ %d\n", | |
1133 | pin-16, irq); | |
1134 | } | |
1135 | } | |
1136 | } | |
54168ed7 IM |
1137 | #endif |
1138 | ||
1da177e4 LT |
1139 | return irq; |
1140 | } | |
1141 | ||
497c9a19 YL |
1142 | void lock_vector_lock(void) |
1143 | { | |
1144 | /* Used to the online set of cpus does not change | |
1145 | * during assign_irq_vector. | |
1146 | */ | |
1147 | spin_lock(&vector_lock); | |
1148 | } | |
1da177e4 | 1149 | |
497c9a19 | 1150 | void unlock_vector_lock(void) |
1da177e4 | 1151 | { |
497c9a19 YL |
1152 | spin_unlock(&vector_lock); |
1153 | } | |
1da177e4 | 1154 | |
e7986739 MT |
1155 | static int |
1156 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1157 | { |
047c8fdb YL |
1158 | /* |
1159 | * NOTE! The local APIC isn't very good at handling | |
1160 | * multiple interrupts at the same interrupt level. | |
1161 | * As the interrupt level is determined by taking the | |
1162 | * vector number and shifting that right by 4, we | |
1163 | * want to spread these out a bit so that they don't | |
1164 | * all fall in the same interrupt level. | |
1165 | * | |
1166 | * Also, we've got to be careful not to trash gate | |
1167 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1168 | */ | |
54168ed7 IM |
1169 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1170 | unsigned int old_vector; | |
22f65d31 MT |
1171 | int cpu, err; |
1172 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1173 | |
54168ed7 IM |
1174 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1175 | return -EBUSY; | |
0a1ad60d | 1176 | |
22f65d31 MT |
1177 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1178 | return -ENOMEM; | |
ace80ab7 | 1179 | |
54168ed7 IM |
1180 | old_vector = cfg->vector; |
1181 | if (old_vector) { | |
22f65d31 MT |
1182 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1183 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1184 | if (!cpumask_empty(tmp_mask)) { | |
1185 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1186 | return 0; |
22f65d31 | 1187 | } |
54168ed7 | 1188 | } |
497c9a19 | 1189 | |
e7986739 | 1190 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1191 | err = -ENOSPC; |
1192 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1193 | int new_cpu; |
1194 | int vector, offset; | |
497c9a19 | 1195 | |
e2d40b18 | 1196 | apic->vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1197 | |
54168ed7 IM |
1198 | vector = current_vector; |
1199 | offset = current_offset; | |
497c9a19 | 1200 | next: |
54168ed7 IM |
1201 | vector += 8; |
1202 | if (vector >= first_system_vector) { | |
e7986739 | 1203 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1204 | offset = (offset + 1) % 8; |
1205 | vector = FIRST_DEVICE_VECTOR + offset; | |
1206 | } | |
1207 | if (unlikely(current_vector == vector)) | |
1208 | continue; | |
b77b881f YL |
1209 | |
1210 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1211 | goto next; |
b77b881f | 1212 | |
22f65d31 | 1213 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1214 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1215 | goto next; | |
1216 | /* Found one! */ | |
1217 | current_vector = vector; | |
1218 | current_offset = offset; | |
1219 | if (old_vector) { | |
1220 | cfg->move_in_progress = 1; | |
22f65d31 | 1221 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1222 | } |
22f65d31 | 1223 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1224 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1225 | cfg->vector = vector; | |
22f65d31 MT |
1226 | cpumask_copy(cfg->domain, tmp_mask); |
1227 | err = 0; | |
1228 | break; | |
54168ed7 | 1229 | } |
22f65d31 MT |
1230 | free_cpumask_var(tmp_mask); |
1231 | return err; | |
497c9a19 YL |
1232 | } |
1233 | ||
e7986739 MT |
1234 | static int |
1235 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1236 | { |
1237 | int err; | |
ace80ab7 | 1238 | unsigned long flags; |
ace80ab7 EB |
1239 | |
1240 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1241 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1242 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1243 | return err; |
1244 | } | |
1245 | ||
3145e941 | 1246 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1247 | { |
497c9a19 YL |
1248 | int cpu, vector; |
1249 | ||
497c9a19 YL |
1250 | BUG_ON(!cfg->vector); |
1251 | ||
1252 | vector = cfg->vector; | |
22f65d31 | 1253 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1254 | per_cpu(vector_irq, cpu)[vector] = -1; |
1255 | ||
1256 | cfg->vector = 0; | |
22f65d31 | 1257 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1258 | |
1259 | if (likely(!cfg->move_in_progress)) | |
1260 | return; | |
22f65d31 | 1261 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1262 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1263 | vector++) { | |
1264 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1265 | continue; | |
1266 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1267 | break; | |
1268 | } | |
1269 | } | |
1270 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1271 | } |
1272 | ||
1273 | void __setup_vector_irq(int cpu) | |
1274 | { | |
1275 | /* Initialize vector_irq on a new cpu */ | |
1276 | /* This function must be called with vector_lock held */ | |
1277 | int irq, vector; | |
1278 | struct irq_cfg *cfg; | |
0b8f1efa | 1279 | struct irq_desc *desc; |
497c9a19 YL |
1280 | |
1281 | /* Mark the inuse vectors */ | |
0b8f1efa | 1282 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1283 | cfg = desc->chip_data; |
22f65d31 | 1284 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1285 | continue; |
1286 | vector = cfg->vector; | |
497c9a19 YL |
1287 | per_cpu(vector_irq, cpu)[vector] = irq; |
1288 | } | |
1289 | /* Mark the free vectors */ | |
1290 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1291 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1292 | if (irq < 0) | |
1293 | continue; | |
1294 | ||
1295 | cfg = irq_cfg(irq); | |
22f65d31 | 1296 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1297 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1298 | } |
1da177e4 | 1299 | } |
3fde6900 | 1300 | |
f5b9ed7a | 1301 | static struct irq_chip ioapic_chip; |
54168ed7 | 1302 | static struct irq_chip ir_ioapic_chip; |
1da177e4 | 1303 | |
54168ed7 IM |
1304 | #define IOAPIC_AUTO -1 |
1305 | #define IOAPIC_EDGE 0 | |
1306 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1307 | |
047c8fdb | 1308 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1309 | static inline int IO_APIC_irq_trigger(int irq) |
1310 | { | |
d6c88a50 | 1311 | int apic, idx, pin; |
1d025192 | 1312 | |
d6c88a50 TG |
1313 | for (apic = 0; apic < nr_ioapics; apic++) { |
1314 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1315 | idx = find_irq_entry(apic, pin, mp_INT); | |
1316 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1317 | return irq_trigger(idx); | |
1318 | } | |
1319 | } | |
1320 | /* | |
54168ed7 IM |
1321 | * nonexistent IRQs are edge default |
1322 | */ | |
d6c88a50 | 1323 | return 0; |
1d025192 | 1324 | } |
047c8fdb YL |
1325 | #else |
1326 | static inline int IO_APIC_irq_trigger(int irq) | |
1327 | { | |
54168ed7 | 1328 | return 1; |
047c8fdb YL |
1329 | } |
1330 | #endif | |
1d025192 | 1331 | |
3145e941 | 1332 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1333 | { |
199751d7 | 1334 | |
6ebcc00e | 1335 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1336 | trigger == IOAPIC_LEVEL) |
08678b08 | 1337 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1338 | else |
1339 | desc->status &= ~IRQ_LEVEL; | |
1340 | ||
54168ed7 IM |
1341 | if (irq_remapped(irq)) { |
1342 | desc->status |= IRQ_MOVE_PCNTXT; | |
1343 | if (trigger) | |
1344 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1345 | handle_fasteoi_irq, | |
1346 | "fasteoi"); | |
1347 | else | |
1348 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1349 | handle_edge_irq, "edge"); | |
1350 | return; | |
1351 | } | |
29b61be6 | 1352 | |
047c8fdb YL |
1353 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1354 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1355 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1356 | handle_fasteoi_irq, |
1357 | "fasteoi"); | |
047c8fdb | 1358 | else |
a460e745 | 1359 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1360 | handle_edge_irq, "edge"); |
1da177e4 LT |
1361 | } |
1362 | ||
ca97ab90 JF |
1363 | int setup_ioapic_entry(int apic_id, int irq, |
1364 | struct IO_APIC_route_entry *entry, | |
1365 | unsigned int destination, int trigger, | |
0280f7c4 | 1366 | int polarity, int vector, int pin) |
1da177e4 | 1367 | { |
497c9a19 YL |
1368 | /* |
1369 | * add it to the IO-APIC irq-routing table: | |
1370 | */ | |
1371 | memset(entry,0,sizeof(*entry)); | |
1372 | ||
54168ed7 | 1373 | if (intr_remapping_enabled) { |
c8d46cf0 | 1374 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1375 | struct irte irte; |
1376 | struct IR_IO_APIC_route_entry *ir_entry = | |
1377 | (struct IR_IO_APIC_route_entry *) entry; | |
1378 | int index; | |
1379 | ||
1380 | if (!iommu) | |
c8d46cf0 | 1381 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1382 | |
1383 | index = alloc_irte(iommu, irq, 1); | |
1384 | if (index < 0) | |
c8d46cf0 | 1385 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1386 | |
1387 | memset(&irte, 0, sizeof(irte)); | |
1388 | ||
1389 | irte.present = 1; | |
9b5bc8dc | 1390 | irte.dst_mode = apic->irq_dest_mode; |
0280f7c4 SS |
1391 | /* |
1392 | * Trigger mode in the IRTE will always be edge, and the | |
1393 | * actual level or edge trigger will be setup in the IO-APIC | |
1394 | * RTE. This will help simplify level triggered irq migration. | |
1395 | * For more details, see the comments above explainig IO-APIC | |
1396 | * irq migration in the presence of interrupt-remapping. | |
1397 | */ | |
1398 | irte.trigger_mode = 0; | |
9b5bc8dc | 1399 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1400 | irte.vector = vector; |
1401 | irte.dest_id = IRTE_DEST(destination); | |
1402 | ||
1403 | modify_irte(irq, &irte); | |
1404 | ||
1405 | ir_entry->index2 = (index >> 15) & 0x1; | |
1406 | ir_entry->zero = 0; | |
1407 | ir_entry->format = 1; | |
1408 | ir_entry->index = (index & 0x7fff); | |
0280f7c4 SS |
1409 | /* |
1410 | * IO-APIC RTE will be configured with virtual vector. | |
1411 | * irq handler will do the explicit EOI to the io-apic. | |
1412 | */ | |
1413 | ir_entry->vector = pin; | |
29b61be6 | 1414 | } else { |
9b5bc8dc IM |
1415 | entry->delivery_mode = apic->irq_delivery_mode; |
1416 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 | 1417 | entry->dest = destination; |
0280f7c4 | 1418 | entry->vector = vector; |
54168ed7 | 1419 | } |
497c9a19 | 1420 | |
54168ed7 | 1421 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1422 | entry->trigger = trigger; |
1423 | entry->polarity = polarity; | |
497c9a19 YL |
1424 | |
1425 | /* Mask level triggered irqs. | |
1426 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1427 | */ | |
1428 | if (trigger) | |
1429 | entry->mask = 1; | |
497c9a19 YL |
1430 | return 0; |
1431 | } | |
1432 | ||
c8d46cf0 | 1433 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1434 | int trigger, int polarity) |
497c9a19 YL |
1435 | { |
1436 | struct irq_cfg *cfg; | |
1da177e4 | 1437 | struct IO_APIC_route_entry entry; |
22f65d31 | 1438 | unsigned int dest; |
497c9a19 YL |
1439 | |
1440 | if (!IO_APIC_IRQ(irq)) | |
1441 | return; | |
1442 | ||
3145e941 | 1443 | cfg = desc->chip_data; |
497c9a19 | 1444 | |
fe402e1f | 1445 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1446 | return; |
1447 | ||
debccb3e | 1448 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 YL |
1449 | |
1450 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1451 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1452 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1453 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1454 | irq, trigger, polarity); |
1455 | ||
1456 | ||
c8d46cf0 | 1457 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
0280f7c4 | 1458 | dest, trigger, polarity, cfg->vector, pin)) { |
497c9a19 | 1459 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1460 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1461 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1462 | return; |
1463 | } | |
1464 | ||
3145e941 | 1465 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1466 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1467 | disable_8259A_irq(irq); |
1468 | ||
c8d46cf0 | 1469 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1470 | } |
1471 | ||
1472 | static void __init setup_IO_APIC_irqs(void) | |
1473 | { | |
c8d46cf0 | 1474 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1475 | int notcon = 0; |
0b8f1efa | 1476 | struct irq_desc *desc; |
3145e941 | 1477 | struct irq_cfg *cfg; |
85ac16d0 | 1478 | int node = cpu_to_node(boot_cpu_id); |
1da177e4 LT |
1479 | |
1480 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1481 | ||
c8d46cf0 IM |
1482 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1483 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1484 | |
c8d46cf0 | 1485 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1486 | if (idx == -1) { |
2a554fb1 | 1487 | if (!notcon) { |
3c2cbd24 | 1488 | notcon = 1; |
2a554fb1 CG |
1489 | apic_printk(APIC_VERBOSE, |
1490 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1491 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1492 | } else |
1493 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1494 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1495 | continue; |
1496 | } | |
56ffa1a0 CG |
1497 | if (notcon) { |
1498 | apic_printk(APIC_VERBOSE, | |
1499 | " (apicid-pin) not connected\n"); | |
1500 | notcon = 0; | |
1501 | } | |
3c2cbd24 | 1502 | |
c8d46cf0 | 1503 | irq = pin_2_irq(idx, apic_id, pin); |
33a201fa IM |
1504 | |
1505 | /* | |
1506 | * Skip the timer IRQ if there's a quirk handler | |
1507 | * installed and if it returns 1: | |
1508 | */ | |
1509 | if (apic->multi_timer_check && | |
1510 | apic->multi_timer_check(apic_id, irq)) | |
3c2cbd24 | 1511 | continue; |
33a201fa | 1512 | |
85ac16d0 | 1513 | desc = irq_to_desc_alloc_node(irq, node); |
0b8f1efa YL |
1514 | if (!desc) { |
1515 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1516 | continue; | |
1517 | } | |
3145e941 | 1518 | cfg = desc->chip_data; |
85ac16d0 | 1519 | add_pin_to_irq_node(cfg, node, apic_id, pin); |
36062448 | 1520 | |
c8d46cf0 | 1521 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1522 | irq_trigger(idx), irq_polarity(idx)); |
1523 | } | |
1da177e4 LT |
1524 | } |
1525 | ||
3c2cbd24 CG |
1526 | if (notcon) |
1527 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1528 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1529 | } |
1530 | ||
1531 | /* | |
f7633ce5 | 1532 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1533 | */ |
c8d46cf0 | 1534 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1535 | int vector) |
1da177e4 LT |
1536 | { |
1537 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1538 | |
54168ed7 IM |
1539 | if (intr_remapping_enabled) |
1540 | return; | |
54168ed7 | 1541 | |
36062448 | 1542 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1543 | |
1544 | /* | |
1545 | * We use logical delivery to get the timer IRQ | |
1546 | * to the first CPU. | |
1547 | */ | |
9b5bc8dc | 1548 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1549 | entry.mask = 0; /* don't mask IRQ for edge */ |
debccb3e | 1550 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); |
9b5bc8dc | 1551 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1552 | entry.polarity = 0; |
1553 | entry.trigger = 0; | |
1554 | entry.vector = vector; | |
1555 | ||
1556 | /* | |
1557 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1558 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1559 | */ |
54168ed7 | 1560 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1561 | |
1562 | /* | |
1563 | * Add it to the IO-APIC irq-routing table: | |
1564 | */ | |
c8d46cf0 | 1565 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1566 | } |
1567 | ||
32f71aff MR |
1568 | |
1569 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1570 | { |
1571 | int apic, i; | |
1572 | union IO_APIC_reg_00 reg_00; | |
1573 | union IO_APIC_reg_01 reg_01; | |
1574 | union IO_APIC_reg_02 reg_02; | |
1575 | union IO_APIC_reg_03 reg_03; | |
1576 | unsigned long flags; | |
0f978f45 | 1577 | struct irq_cfg *cfg; |
0b8f1efa | 1578 | struct irq_desc *desc; |
8f09cd20 | 1579 | unsigned int irq; |
1da177e4 LT |
1580 | |
1581 | if (apic_verbosity == APIC_QUIET) | |
1582 | return; | |
1583 | ||
36062448 | 1584 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1585 | for (i = 0; i < nr_ioapics; i++) |
1586 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1587 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1588 | |
1589 | /* | |
1590 | * We are a bit conservative about what we expect. We have to | |
1591 | * know about every hardware change ASAP. | |
1592 | */ | |
1593 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1594 | ||
1595 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1596 | ||
1597 | spin_lock_irqsave(&ioapic_lock, flags); | |
1598 | reg_00.raw = io_apic_read(apic, 0); | |
1599 | reg_01.raw = io_apic_read(apic, 1); | |
1600 | if (reg_01.bits.version >= 0x10) | |
1601 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1602 | if (reg_01.bits.version >= 0x20) |
1603 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1604 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1605 | ||
54168ed7 | 1606 | printk("\n"); |
b5ba7e6d | 1607 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1608 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1609 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1610 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1611 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1612 | |
54168ed7 | 1613 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1614 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1615 | |
1616 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1617 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1618 | |
1619 | /* | |
1620 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1621 | * but the value of reg_02 is read as the previous read register | |
1622 | * value, so ignore it if reg_02 == reg_01. | |
1623 | */ | |
1624 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1625 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1626 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1627 | } |
1628 | ||
1629 | /* | |
1630 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1631 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1632 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1633 | */ | |
1634 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1635 | reg_03.raw != reg_01.raw) { | |
1636 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1637 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1638 | } |
1639 | ||
1640 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1641 | ||
d83e94ac YL |
1642 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1643 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1644 | |
1645 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1646 | struct IO_APIC_route_entry entry; | |
1647 | ||
cf4c6a2f | 1648 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1649 | |
54168ed7 IM |
1650 | printk(KERN_DEBUG " %02x %03X ", |
1651 | i, | |
1652 | entry.dest | |
1653 | ); | |
1da177e4 LT |
1654 | |
1655 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1656 | entry.mask, | |
1657 | entry.trigger, | |
1658 | entry.irr, | |
1659 | entry.polarity, | |
1660 | entry.delivery_status, | |
1661 | entry.dest_mode, | |
1662 | entry.delivery_mode, | |
1663 | entry.vector | |
1664 | ); | |
1665 | } | |
1666 | } | |
1da177e4 | 1667 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1668 | for_each_irq_desc(irq, desc) { |
1669 | struct irq_pin_list *entry; | |
1670 | ||
0b8f1efa YL |
1671 | cfg = desc->chip_data; |
1672 | entry = cfg->irq_2_pin; | |
0f978f45 | 1673 | if (!entry) |
1da177e4 | 1674 | continue; |
8f09cd20 | 1675 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1676 | for (;;) { |
1677 | printk("-> %d:%d", entry->apic, entry->pin); | |
1678 | if (!entry->next) | |
1679 | break; | |
0f978f45 | 1680 | entry = entry->next; |
1da177e4 LT |
1681 | } |
1682 | printk("\n"); | |
1683 | } | |
1684 | ||
1685 | printk(KERN_INFO ".................................... done.\n"); | |
1686 | ||
1687 | return; | |
1688 | } | |
1689 | ||
32f71aff | 1690 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1691 | { |
1692 | unsigned int v; | |
1693 | int i, j; | |
1694 | ||
1695 | if (apic_verbosity == APIC_QUIET) | |
1696 | return; | |
1697 | ||
1698 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1699 | for (i = 0; i < 8; i++) { | |
1700 | v = apic_read(base + i*0x10); | |
1701 | for (j = 0; j < 32; j++) { | |
1702 | if (v & (1<<j)) | |
1703 | printk("1"); | |
1704 | else | |
1705 | printk("0"); | |
1706 | } | |
1707 | printk("\n"); | |
1708 | } | |
1709 | } | |
1710 | ||
32f71aff | 1711 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1712 | { |
1713 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1714 | u64 icr; |
1da177e4 LT |
1715 | |
1716 | if (apic_verbosity == APIC_QUIET) | |
1717 | return; | |
1718 | ||
1719 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1720 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1721 | v = apic_read(APIC_ID); |
54168ed7 | 1722 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1723 | v = apic_read(APIC_LVR); |
1724 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1725 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1726 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1727 | |
1728 | v = apic_read(APIC_TASKPRI); | |
1729 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1730 | ||
54168ed7 | 1731 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1732 | if (!APIC_XAPIC(ver)) { |
1733 | v = apic_read(APIC_ARBPRI); | |
1734 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1735 | v & APIC_ARBPRI_MASK); | |
1736 | } | |
1da177e4 LT |
1737 | v = apic_read(APIC_PROCPRI); |
1738 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1739 | } | |
1740 | ||
a11b5abe YL |
1741 | /* |
1742 | * Remote read supported only in the 82489DX and local APIC for | |
1743 | * Pentium processors. | |
1744 | */ | |
1745 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1746 | v = apic_read(APIC_RRR); | |
1747 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1748 | } | |
1749 | ||
1da177e4 LT |
1750 | v = apic_read(APIC_LDR); |
1751 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1752 | if (!x2apic_enabled()) { |
1753 | v = apic_read(APIC_DFR); | |
1754 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1755 | } | |
1da177e4 LT |
1756 | v = apic_read(APIC_SPIV); |
1757 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1758 | ||
1759 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1760 | print_APIC_bitfield(APIC_ISR); | |
1761 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1762 | print_APIC_bitfield(APIC_TMR); | |
1763 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1764 | print_APIC_bitfield(APIC_IRR); | |
1765 | ||
54168ed7 IM |
1766 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1767 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1768 | apic_write(APIC_ESR, 0); |
54168ed7 | 1769 | |
1da177e4 LT |
1770 | v = apic_read(APIC_ESR); |
1771 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1772 | } | |
1773 | ||
7ab6af7a | 1774 | icr = apic_icr_read(); |
0c425cec IM |
1775 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1776 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1777 | |
1778 | v = apic_read(APIC_LVTT); | |
1779 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1780 | ||
1781 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1782 | v = apic_read(APIC_LVTPC); | |
1783 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1784 | } | |
1785 | v = apic_read(APIC_LVT0); | |
1786 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1787 | v = apic_read(APIC_LVT1); | |
1788 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1789 | ||
1790 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1791 | v = apic_read(APIC_LVTERR); | |
1792 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1793 | } | |
1794 | ||
1795 | v = apic_read(APIC_TMICT); | |
1796 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1797 | v = apic_read(APIC_TMCCT); | |
1798 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1799 | v = apic_read(APIC_TDCR); | |
1800 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1801 | printk("\n"); | |
1802 | } | |
1803 | ||
32f71aff | 1804 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1805 | { |
ffd5aae7 YL |
1806 | int cpu; |
1807 | ||
1808 | preempt_disable(); | |
1809 | for_each_online_cpu(cpu) | |
1810 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1811 | preempt_enable(); | |
1da177e4 LT |
1812 | } |
1813 | ||
32f71aff | 1814 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1815 | { |
1da177e4 LT |
1816 | unsigned int v; |
1817 | unsigned long flags; | |
1818 | ||
1819 | if (apic_verbosity == APIC_QUIET) | |
1820 | return; | |
1821 | ||
1822 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1823 | ||
1824 | spin_lock_irqsave(&i8259A_lock, flags); | |
1825 | ||
1826 | v = inb(0xa1) << 8 | inb(0x21); | |
1827 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1828 | ||
1829 | v = inb(0xa0) << 8 | inb(0x20); | |
1830 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1831 | ||
54168ed7 IM |
1832 | outb(0x0b,0xa0); |
1833 | outb(0x0b,0x20); | |
1da177e4 | 1834 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1835 | outb(0x0a,0xa0); |
1836 | outb(0x0a,0x20); | |
1da177e4 LT |
1837 | |
1838 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1839 | ||
1840 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1841 | ||
1842 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1843 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1844 | } | |
1845 | ||
32f71aff MR |
1846 | __apicdebuginit(int) print_all_ICs(void) |
1847 | { | |
1848 | print_PIC(); | |
1849 | print_all_local_APICs(); | |
1850 | print_IO_APIC(); | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | fs_initcall(print_all_ICs); | |
1856 | ||
1da177e4 | 1857 | |
efa2559f YL |
1858 | /* Where if anywhere is the i8259 connect in external int mode */ |
1859 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1860 | ||
54168ed7 | 1861 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1862 | { |
1863 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1864 | int i8259_apic, i8259_pin; |
54168ed7 | 1865 | int apic; |
1da177e4 LT |
1866 | unsigned long flags; |
1867 | ||
1da177e4 LT |
1868 | /* |
1869 | * The number of IO-APIC IRQ registers (== #pins): | |
1870 | */ | |
fcfd636a | 1871 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1872 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1873 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1874 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1875 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1876 | } | |
54168ed7 | 1877 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1878 | int pin; |
1879 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1880 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1881 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1882 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1883 | |
fcfd636a EB |
1884 | /* If the interrupt line is enabled and in ExtInt mode |
1885 | * I have found the pin where the i8259 is connected. | |
1886 | */ | |
1887 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1888 | ioapic_i8259.apic = apic; | |
1889 | ioapic_i8259.pin = pin; | |
1890 | goto found_i8259; | |
1891 | } | |
1892 | } | |
1893 | } | |
1894 | found_i8259: | |
1895 | /* Look to see what if the MP table has reported the ExtINT */ | |
1896 | /* If we could not find the appropriate pin by looking at the ioapic | |
1897 | * the i8259 probably is not connected the ioapic but give the | |
1898 | * mptable a chance anyway. | |
1899 | */ | |
1900 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1901 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1902 | /* Trust the MP table if nothing is setup in the hardware */ | |
1903 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1904 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1905 | ioapic_i8259.pin = i8259_pin; | |
1906 | ioapic_i8259.apic = i8259_apic; | |
1907 | } | |
1908 | /* Complain if the MP table and the hardware disagree */ | |
1909 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1910 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1911 | { | |
1912 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1913 | } |
1914 | ||
1915 | /* | |
1916 | * Do not trust the IO-APIC being empty at bootup | |
1917 | */ | |
1918 | clear_IO_APIC(); | |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * Not an __init, needed by the reboot code | |
1923 | */ | |
1924 | void disable_IO_APIC(void) | |
1925 | { | |
1926 | /* | |
1927 | * Clear the IO-APIC before rebooting: | |
1928 | */ | |
1929 | clear_IO_APIC(); | |
1930 | ||
650927ef | 1931 | /* |
0b968d23 | 1932 | * If the i8259 is routed through an IOAPIC |
650927ef | 1933 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1934 | * so legacy interrupts can be delivered. |
7c6d9f97 SS |
1935 | * |
1936 | * With interrupt-remapping, for now we will use virtual wire A mode, | |
1937 | * as virtual wire B is little complex (need to configure both | |
1938 | * IOAPIC RTE aswell as interrupt-remapping table entry). | |
1939 | * As this gets called during crash dump, keep this simple for now. | |
650927ef | 1940 | */ |
7c6d9f97 | 1941 | if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { |
650927ef | 1942 | struct IO_APIC_route_entry entry; |
650927ef EB |
1943 | |
1944 | memset(&entry, 0, sizeof(entry)); | |
1945 | entry.mask = 0; /* Enabled */ | |
1946 | entry.trigger = 0; /* Edge */ | |
1947 | entry.irr = 0; | |
1948 | entry.polarity = 0; /* High */ | |
1949 | entry.delivery_status = 0; | |
1950 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1951 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1952 | entry.vector = 0; |
54168ed7 | 1953 | entry.dest = read_apic_id(); |
650927ef EB |
1954 | |
1955 | /* | |
1956 | * Add it to the IO-APIC irq-routing table: | |
1957 | */ | |
cf4c6a2f | 1958 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1959 | } |
54168ed7 | 1960 | |
7c6d9f97 SS |
1961 | /* |
1962 | * Use virtual wire A mode when interrupt remapping is enabled. | |
1963 | */ | |
1964 | disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1); | |
1da177e4 LT |
1965 | } |
1966 | ||
54168ed7 | 1967 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1968 | /* |
1969 | * function to set the IO-APIC physical IDs based on the | |
1970 | * values stored in the MPC table. | |
1971 | * | |
1972 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1973 | */ | |
1974 | ||
1da177e4 LT |
1975 | static void __init setup_ioapic_ids_from_mpc(void) |
1976 | { | |
1977 | union IO_APIC_reg_00 reg_00; | |
1978 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 1979 | int apic_id; |
1da177e4 LT |
1980 | int i; |
1981 | unsigned char old_id; | |
1982 | unsigned long flags; | |
1983 | ||
a4dbc34d | 1984 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1985 | return; |
d49c4288 | 1986 | |
ca05fea6 NP |
1987 | /* |
1988 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1989 | * no meaning without the serial APIC bus. | |
1990 | */ | |
7c5c1e42 SL |
1991 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1992 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1993 | return; |
1da177e4 LT |
1994 | /* |
1995 | * This is broken; anything with a real cpu count has to | |
1996 | * circumvent this idiocy regardless. | |
1997 | */ | |
d190cb87 | 1998 | phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
1999 | |
2000 | /* | |
2001 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2002 | */ | |
c8d46cf0 | 2003 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2004 | |
2005 | /* Read the register 0 value */ | |
2006 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2007 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2008 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2009 | |
c8d46cf0 | 2010 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2011 | |
c8d46cf0 | 2012 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2013 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2014 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2015 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2016 | reg_00.bits.ID); | |
c8d46cf0 | 2017 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2018 | } |
2019 | ||
1da177e4 LT |
2020 | /* |
2021 | * Sanity check, is the ID really free? Every APIC in a | |
2022 | * system must have a unique ID or we get lots of nice | |
2023 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2024 | */ | |
d1d7cae8 | 2025 | if (apic->check_apicid_used(phys_id_present_map, |
c8d46cf0 | 2026 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2027 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2028 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2029 | for (i = 0; i < get_physical_broadcast(); i++) |
2030 | if (!physid_isset(i, phys_id_present_map)) | |
2031 | break; | |
2032 | if (i >= get_physical_broadcast()) | |
2033 | panic("Max APIC ID exceeded!\n"); | |
2034 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2035 | i); | |
2036 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2037 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2038 | } else { |
2039 | physid_mask_t tmp; | |
8058714a | 2040 | tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2041 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2042 | "phys_id_present_map\n", | |
c8d46cf0 | 2043 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2044 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2045 | } | |
2046 | ||
2047 | ||
2048 | /* | |
2049 | * We need to adjust the IRQ routing table | |
2050 | * if the ID changed. | |
2051 | */ | |
c8d46cf0 | 2052 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2053 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2054 | if (mp_irqs[i].dstapic == old_id) |
2055 | mp_irqs[i].dstapic | |
c8d46cf0 | 2056 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2057 | |
2058 | /* | |
2059 | * Read the right value from the MPC table and | |
2060 | * write it into the ID register. | |
36062448 | 2061 | */ |
1da177e4 LT |
2062 | apic_printk(APIC_VERBOSE, KERN_INFO |
2063 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2064 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2065 | |
c8d46cf0 | 2066 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2067 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2068 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2069 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2070 | |
2071 | /* | |
2072 | * Sanity check | |
2073 | */ | |
2074 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2075 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2076 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2077 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2078 | printk("could not set ID!\n"); |
2079 | else | |
2080 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2081 | } | |
2082 | } | |
54168ed7 | 2083 | #endif |
1da177e4 | 2084 | |
7ce0bcfd | 2085 | int no_timer_check __initdata; |
8542b200 ZA |
2086 | |
2087 | static int __init notimercheck(char *s) | |
2088 | { | |
2089 | no_timer_check = 1; | |
2090 | return 1; | |
2091 | } | |
2092 | __setup("no_timer_check", notimercheck); | |
2093 | ||
1da177e4 LT |
2094 | /* |
2095 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2096 | * about the timer IRQ. We do the following to work around the situation: | |
2097 | * | |
2098 | * - timer IRQ defaults to IO-APIC IRQ | |
2099 | * - if this function detects that timer IRQs are defunct, then we fall | |
2100 | * back to ISA timer IRQs | |
2101 | */ | |
f0a7a5c9 | 2102 | static int __init timer_irq_works(void) |
1da177e4 LT |
2103 | { |
2104 | unsigned long t1 = jiffies; | |
4aae0702 | 2105 | unsigned long flags; |
1da177e4 | 2106 | |
8542b200 ZA |
2107 | if (no_timer_check) |
2108 | return 1; | |
2109 | ||
4aae0702 | 2110 | local_save_flags(flags); |
1da177e4 LT |
2111 | local_irq_enable(); |
2112 | /* Let ten ticks pass... */ | |
2113 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2114 | local_irq_restore(flags); |
1da177e4 LT |
2115 | |
2116 | /* | |
2117 | * Expect a few ticks at least, to be sure some possible | |
2118 | * glue logic does not lock up after one or two first | |
2119 | * ticks in a non-ExtINT mode. Also the local APIC | |
2120 | * might have cached one ExtINT interrupt. Finally, at | |
2121 | * least one tick may be lost due to delays. | |
2122 | */ | |
54168ed7 IM |
2123 | |
2124 | /* jiffies wrap? */ | |
1d16b53e | 2125 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2126 | return 1; |
1da177e4 LT |
2127 | return 0; |
2128 | } | |
2129 | ||
2130 | /* | |
2131 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2132 | * number of pending IRQ events unhandled. These cases are very rare, | |
2133 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2134 | * better to do it this way as thus we do not have to be aware of | |
2135 | * 'pending' interrupts in the IRQ path, except at this point. | |
2136 | */ | |
2137 | /* | |
2138 | * Edge triggered needs to resend any interrupt | |
2139 | * that was delayed but this is now handled in the device | |
2140 | * independent code. | |
2141 | */ | |
2142 | ||
2143 | /* | |
2144 | * Starting up a edge-triggered IO-APIC interrupt is | |
2145 | * nasty - we need to make sure that we get the edge. | |
2146 | * If it is already asserted for some reason, we need | |
2147 | * return 1 to indicate that is was pending. | |
2148 | * | |
2149 | * This is not complete - we should be able to fake | |
2150 | * an edge even if it isn't on the 8259A... | |
2151 | */ | |
54168ed7 | 2152 | |
f5b9ed7a | 2153 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2154 | { |
2155 | int was_pending = 0; | |
2156 | unsigned long flags; | |
0b8f1efa | 2157 | struct irq_cfg *cfg; |
1da177e4 LT |
2158 | |
2159 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2160 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2161 | disable_8259A_irq(irq); |
2162 | if (i8259A_irq_pending(irq)) | |
2163 | was_pending = 1; | |
2164 | } | |
0b8f1efa | 2165 | cfg = irq_cfg(irq); |
3145e941 | 2166 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2167 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2168 | ||
2169 | return was_pending; | |
2170 | } | |
2171 | ||
54168ed7 | 2172 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2173 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2174 | { |
54168ed7 IM |
2175 | |
2176 | struct irq_cfg *cfg = irq_cfg(irq); | |
2177 | unsigned long flags; | |
2178 | ||
2179 | spin_lock_irqsave(&vector_lock, flags); | |
dac5f412 | 2180 | apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2181 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2182 | |
2183 | return 1; | |
2184 | } | |
54168ed7 IM |
2185 | #else |
2186 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2187 | { |
dac5f412 | 2188 | apic->send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2189 | |
d6c88a50 | 2190 | return 1; |
54168ed7 IM |
2191 | } |
2192 | #endif | |
497c9a19 | 2193 | |
54168ed7 IM |
2194 | /* |
2195 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2196 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2197 | * handled with the level-triggered descriptor, but that one has slightly | |
2198 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2199 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2200 | * races. | |
2201 | */ | |
497c9a19 | 2202 | |
54168ed7 | 2203 | #ifdef CONFIG_SMP |
e85abf8f GH |
2204 | static void send_cleanup_vector(struct irq_cfg *cfg) |
2205 | { | |
2206 | cpumask_var_t cleanup_mask; | |
2207 | ||
2208 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2209 | unsigned int i; | |
2210 | cfg->move_cleanup_count = 0; | |
2211 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2212 | cfg->move_cleanup_count++; | |
2213 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
2214 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2215 | } else { | |
2216 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
2217 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
2218 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2219 | free_cpumask_var(cleanup_mask); | |
2220 | } | |
2221 | cfg->move_in_progress = 0; | |
2222 | } | |
2223 | ||
4420471f | 2224 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
e85abf8f GH |
2225 | { |
2226 | int apic, pin; | |
2227 | struct irq_pin_list *entry; | |
2228 | u8 vector = cfg->vector; | |
2229 | ||
2230 | entry = cfg->irq_2_pin; | |
2231 | for (;;) { | |
2232 | unsigned int reg; | |
2233 | ||
2234 | if (!entry) | |
2235 | break; | |
2236 | ||
2237 | apic = entry->apic; | |
2238 | pin = entry->pin; | |
2239 | /* | |
2240 | * With interrupt-remapping, destination information comes | |
2241 | * from interrupt-remapping table entry. | |
2242 | */ | |
2243 | if (!irq_remapped(irq)) | |
2244 | io_apic_write(apic, 0x11 + pin*2, dest); | |
2245 | reg = io_apic_read(apic, 0x10 + pin*2); | |
2246 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2247 | reg |= vector; | |
2248 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2249 | if (!entry->next) | |
2250 | break; | |
2251 | entry = entry->next; | |
2252 | } | |
2253 | } | |
2254 | ||
4420471f IM |
2255 | static int |
2256 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
2257 | ||
e85abf8f GH |
2258 | /* |
2259 | * Either sets desc->affinity to a valid value, and returns | |
2260 | * ->cpu_mask_to_apicid of that, or returns BAD_APICID and | |
2261 | * leaves desc->affinity untouched. | |
2262 | */ | |
2263 | static unsigned int | |
2264 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
2265 | { | |
2266 | struct irq_cfg *cfg; | |
2267 | unsigned int irq; | |
2268 | ||
2269 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2270 | return BAD_APICID; | |
2271 | ||
2272 | irq = desc->irq; | |
2273 | cfg = desc->chip_data; | |
2274 | if (assign_irq_vector(irq, cfg, mask)) | |
2275 | return BAD_APICID; | |
2276 | ||
e85abf8f GH |
2277 | cpumask_copy(desc->affinity, mask); |
2278 | ||
2279 | return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain); | |
2280 | } | |
2281 | ||
4420471f | 2282 | static int |
e85abf8f GH |
2283 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
2284 | { | |
2285 | struct irq_cfg *cfg; | |
2286 | unsigned long flags; | |
2287 | unsigned int dest; | |
2288 | unsigned int irq; | |
4420471f | 2289 | int ret = -1; |
e85abf8f GH |
2290 | |
2291 | irq = desc->irq; | |
2292 | cfg = desc->chip_data; | |
2293 | ||
2294 | spin_lock_irqsave(&ioapic_lock, flags); | |
2295 | dest = set_desc_affinity(desc, mask); | |
2296 | if (dest != BAD_APICID) { | |
2297 | /* Only the high 8 bits are valid. */ | |
2298 | dest = SET_APIC_LOGICAL_ID(dest); | |
2299 | __target_IO_APIC_irq(irq, dest, cfg); | |
4420471f | 2300 | ret = 0; |
e85abf8f GH |
2301 | } |
2302 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
4420471f IM |
2303 | |
2304 | return ret; | |
e85abf8f GH |
2305 | } |
2306 | ||
4420471f | 2307 | static int |
e85abf8f GH |
2308 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) |
2309 | { | |
2310 | struct irq_desc *desc; | |
2311 | ||
2312 | desc = irq_to_desc(irq); | |
2313 | ||
4420471f | 2314 | return set_ioapic_affinity_irq_desc(desc, mask); |
e85abf8f | 2315 | } |
497c9a19 | 2316 | |
54168ed7 | 2317 | #ifdef CONFIG_INTR_REMAP |
497c9a19 | 2318 | |
54168ed7 IM |
2319 | /* |
2320 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2321 | * | |
0280f7c4 SS |
2322 | * For both level and edge triggered, irq migration is a simple atomic |
2323 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
54168ed7 | 2324 | * |
0280f7c4 SS |
2325 | * For level triggered, we eliminate the io-apic RTE modification (with the |
2326 | * updated vector information), by using a virtual vector (io-apic pin number). | |
2327 | * Real vector that is used for interrupting cpu will be coming from | |
2328 | * the interrupt-remapping table entry. | |
54168ed7 | 2329 | */ |
d5dedd45 | 2330 | static int |
e7986739 | 2331 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) |
497c9a19 | 2332 | { |
54168ed7 | 2333 | struct irq_cfg *cfg; |
54168ed7 | 2334 | struct irte irte; |
54168ed7 | 2335 | unsigned int dest; |
3145e941 | 2336 | unsigned int irq; |
d5dedd45 | 2337 | int ret = -1; |
497c9a19 | 2338 | |
22f65d31 | 2339 | if (!cpumask_intersects(mask, cpu_online_mask)) |
d5dedd45 | 2340 | return ret; |
497c9a19 | 2341 | |
3145e941 | 2342 | irq = desc->irq; |
54168ed7 | 2343 | if (get_irte(irq, &irte)) |
d5dedd45 | 2344 | return ret; |
497c9a19 | 2345 | |
3145e941 YL |
2346 | cfg = desc->chip_data; |
2347 | if (assign_irq_vector(irq, cfg, mask)) | |
d5dedd45 | 2348 | return ret; |
54168ed7 | 2349 | |
debccb3e | 2350 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2351 | |
54168ed7 IM |
2352 | irte.vector = cfg->vector; |
2353 | irte.dest_id = IRTE_DEST(dest); | |
2354 | ||
2355 | /* | |
2356 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2357 | */ | |
2358 | modify_irte(irq, &irte); | |
2359 | ||
22f65d31 MT |
2360 | if (cfg->move_in_progress) |
2361 | send_cleanup_vector(cfg); | |
54168ed7 | 2362 | |
7f7ace0c | 2363 | cpumask_copy(desc->affinity, mask); |
d5dedd45 YL |
2364 | |
2365 | return 0; | |
54168ed7 IM |
2366 | } |
2367 | ||
54168ed7 IM |
2368 | /* |
2369 | * Migrates the IRQ destination in the process context. | |
2370 | */ | |
d5dedd45 | 2371 | static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
968ea6d8 | 2372 | const struct cpumask *mask) |
54168ed7 | 2373 | { |
d5dedd45 | 2374 | return migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2375 | } |
d5dedd45 | 2376 | static int set_ir_ioapic_affinity_irq(unsigned int irq, |
968ea6d8 | 2377 | const struct cpumask *mask) |
3145e941 YL |
2378 | { |
2379 | struct irq_desc *desc = irq_to_desc(irq); | |
2380 | ||
d5dedd45 | 2381 | return set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 2382 | } |
29b61be6 | 2383 | #else |
d5dedd45 | 2384 | static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
29b61be6 SS |
2385 | const struct cpumask *mask) |
2386 | { | |
d5dedd45 | 2387 | return 0; |
29b61be6 | 2388 | } |
54168ed7 IM |
2389 | #endif |
2390 | ||
2391 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2392 | { | |
2393 | unsigned vector, me; | |
8f2466f4 | 2394 | |
54168ed7 | 2395 | ack_APIC_irq(); |
54168ed7 | 2396 | exit_idle(); |
54168ed7 IM |
2397 | irq_enter(); |
2398 | ||
2399 | me = smp_processor_id(); | |
2400 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2401 | unsigned int irq; | |
68a8ca59 | 2402 | unsigned int irr; |
54168ed7 IM |
2403 | struct irq_desc *desc; |
2404 | struct irq_cfg *cfg; | |
2405 | irq = __get_cpu_var(vector_irq)[vector]; | |
2406 | ||
0b8f1efa YL |
2407 | if (irq == -1) |
2408 | continue; | |
2409 | ||
54168ed7 IM |
2410 | desc = irq_to_desc(irq); |
2411 | if (!desc) | |
2412 | continue; | |
2413 | ||
2414 | cfg = irq_cfg(irq); | |
2415 | spin_lock(&desc->lock); | |
2416 | if (!cfg->move_cleanup_count) | |
2417 | goto unlock; | |
2418 | ||
22f65d31 | 2419 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2420 | goto unlock; |
2421 | ||
68a8ca59 SS |
2422 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2423 | /* | |
2424 | * Check if the vector that needs to be cleanedup is | |
2425 | * registered at the cpu's IRR. If so, then this is not | |
2426 | * the best time to clean it up. Lets clean it up in the | |
2427 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2428 | * to myself. | |
2429 | */ | |
2430 | if (irr & (1 << (vector % 32))) { | |
2431 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2432 | goto unlock; | |
2433 | } | |
54168ed7 IM |
2434 | __get_cpu_var(vector_irq)[vector] = -1; |
2435 | cfg->move_cleanup_count--; | |
2436 | unlock: | |
2437 | spin_unlock(&desc->lock); | |
2438 | } | |
2439 | ||
2440 | irq_exit(); | |
2441 | } | |
2442 | ||
3145e941 | 2443 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2444 | { |
3145e941 YL |
2445 | struct irq_desc *desc = *descp; |
2446 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2447 | unsigned vector, me; |
2448 | ||
fcef5911 | 2449 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2450 | return; |
2451 | ||
2452 | vector = ~get_irq_regs()->orig_ax; | |
2453 | me = smp_processor_id(); | |
10b888d6 | 2454 | |
fcef5911 | 2455 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2456 | send_cleanup_vector(cfg); |
497c9a19 YL |
2457 | } |
2458 | #else | |
3145e941 | 2459 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2460 | #endif |
3145e941 | 2461 | |
1d025192 YL |
2462 | static void ack_apic_edge(unsigned int irq) |
2463 | { | |
3145e941 YL |
2464 | struct irq_desc *desc = irq_to_desc(irq); |
2465 | ||
2466 | irq_complete_move(&desc); | |
1d025192 YL |
2467 | move_native_irq(irq); |
2468 | ack_APIC_irq(); | |
2469 | } | |
2470 | ||
3eb2cce8 | 2471 | atomic_t irq_mis_count; |
3eb2cce8 | 2472 | |
047c8fdb YL |
2473 | static void ack_apic_level(unsigned int irq) |
2474 | { | |
3145e941 YL |
2475 | struct irq_desc *desc = irq_to_desc(irq); |
2476 | ||
3eb2cce8 YL |
2477 | #ifdef CONFIG_X86_32 |
2478 | unsigned long v; | |
2479 | int i; | |
2480 | #endif | |
3145e941 | 2481 | struct irq_cfg *cfg; |
54168ed7 | 2482 | int do_unmask_irq = 0; |
047c8fdb | 2483 | |
3145e941 | 2484 | irq_complete_move(&desc); |
047c8fdb | 2485 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2486 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2487 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2488 | do_unmask_irq = 1; |
3145e941 | 2489 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2490 | } |
047c8fdb YL |
2491 | #endif |
2492 | ||
3eb2cce8 YL |
2493 | #ifdef CONFIG_X86_32 |
2494 | /* | |
2495 | * It appears there is an erratum which affects at least version 0x11 | |
2496 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2497 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2498 | * erroneously delivered as edge-triggered one but the respective IRR | |
2499 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2500 | * message but it will never arrive and further interrupts are blocked | |
2501 | * from the source. The exact reason is so far unknown, but the | |
2502 | * phenomenon was observed when two consecutive interrupt requests | |
2503 | * from a given source get delivered to the same CPU and the source is | |
2504 | * temporarily disabled in between. | |
2505 | * | |
2506 | * A workaround is to simulate an EOI message manually. We achieve it | |
2507 | * by setting the trigger mode to edge and then to level when the edge | |
2508 | * trigger mode gets detected in the TMR of a local APIC for a | |
2509 | * level-triggered interrupt. We mask the source for the time of the | |
2510 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2511 | * The idea is from Manfred Spraul. --macro | |
2512 | */ | |
3145e941 YL |
2513 | cfg = desc->chip_data; |
2514 | i = cfg->vector; | |
3eb2cce8 YL |
2515 | |
2516 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2517 | #endif | |
2518 | ||
54168ed7 IM |
2519 | /* |
2520 | * We must acknowledge the irq before we move it or the acknowledge will | |
2521 | * not propagate properly. | |
2522 | */ | |
2523 | ack_APIC_irq(); | |
2524 | ||
2525 | /* Now we can move and renable the irq */ | |
2526 | if (unlikely(do_unmask_irq)) { | |
2527 | /* Only migrate the irq if the ack has been received. | |
2528 | * | |
2529 | * On rare occasions the broadcast level triggered ack gets | |
2530 | * delayed going to ioapics, and if we reprogram the | |
2531 | * vector while Remote IRR is still set the irq will never | |
2532 | * fire again. | |
2533 | * | |
2534 | * To prevent this scenario we read the Remote IRR bit | |
2535 | * of the ioapic. This has two effects. | |
2536 | * - On any sane system the read of the ioapic will | |
2537 | * flush writes (and acks) going to the ioapic from | |
2538 | * this cpu. | |
2539 | * - We get to see if the ACK has actually been delivered. | |
2540 | * | |
2541 | * Based on failed experiments of reprogramming the | |
2542 | * ioapic entry from outside of irq context starting | |
2543 | * with masking the ioapic entry and then polling until | |
2544 | * Remote IRR was clear before reprogramming the | |
2545 | * ioapic I don't trust the Remote IRR bit to be | |
2546 | * completey accurate. | |
2547 | * | |
2548 | * However there appears to be no other way to plug | |
2549 | * this race, so if the Remote IRR bit is not | |
2550 | * accurate and is causing problems then it is a hardware bug | |
2551 | * and you can go talk to the chipset vendor about it. | |
2552 | */ | |
3145e941 YL |
2553 | cfg = desc->chip_data; |
2554 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2555 | move_masked_irq(irq); |
3145e941 | 2556 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2557 | } |
1d025192 | 2558 | |
3eb2cce8 | 2559 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2560 | if (!(v & (1 << (i & 0x1f)))) { |
2561 | atomic_inc(&irq_mis_count); | |
2562 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2563 | __mask_and_edge_IO_APIC_irq(cfg); |
2564 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2565 | spin_unlock(&ioapic_lock); |
2566 | } | |
047c8fdb | 2567 | #endif |
3eb2cce8 | 2568 | } |
1d025192 | 2569 | |
d0b03bd1 | 2570 | #ifdef CONFIG_INTR_REMAP |
25629d81 SS |
2571 | static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
2572 | { | |
2573 | int apic, pin; | |
2574 | struct irq_pin_list *entry; | |
2575 | ||
2576 | entry = cfg->irq_2_pin; | |
2577 | for (;;) { | |
2578 | ||
2579 | if (!entry) | |
2580 | break; | |
2581 | ||
2582 | apic = entry->apic; | |
2583 | pin = entry->pin; | |
2584 | io_apic_eoi(apic, pin); | |
2585 | entry = entry->next; | |
2586 | } | |
2587 | } | |
2588 | ||
2589 | static void | |
2590 | eoi_ioapic_irq(struct irq_desc *desc) | |
2591 | { | |
2592 | struct irq_cfg *cfg; | |
2593 | unsigned long flags; | |
2594 | unsigned int irq; | |
2595 | ||
2596 | irq = desc->irq; | |
2597 | cfg = desc->chip_data; | |
2598 | ||
2599 | spin_lock_irqsave(&ioapic_lock, flags); | |
2600 | __eoi_ioapic_irq(irq, cfg); | |
2601 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2602 | } | |
2603 | ||
d0b03bd1 HW |
2604 | static void ir_ack_apic_edge(unsigned int irq) |
2605 | { | |
5d0ae2db | 2606 | ack_APIC_irq(); |
d0b03bd1 HW |
2607 | } |
2608 | ||
2609 | static void ir_ack_apic_level(unsigned int irq) | |
2610 | { | |
5d0ae2db WH |
2611 | struct irq_desc *desc = irq_to_desc(irq); |
2612 | ||
2613 | ack_APIC_irq(); | |
2614 | eoi_ioapic_irq(desc); | |
d0b03bd1 HW |
2615 | } |
2616 | #endif /* CONFIG_INTR_REMAP */ | |
2617 | ||
f5b9ed7a | 2618 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2619 | .name = "IO-APIC", |
2620 | .startup = startup_ioapic_irq, | |
2621 | .mask = mask_IO_APIC_irq, | |
2622 | .unmask = unmask_IO_APIC_irq, | |
2623 | .ack = ack_apic_edge, | |
2624 | .eoi = ack_apic_level, | |
54d5d424 | 2625 | #ifdef CONFIG_SMP |
d6c88a50 | 2626 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2627 | #endif |
ace80ab7 | 2628 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2629 | }; |
2630 | ||
54168ed7 | 2631 | static struct irq_chip ir_ioapic_chip __read_mostly = { |
d6c88a50 TG |
2632 | .name = "IR-IO-APIC", |
2633 | .startup = startup_ioapic_irq, | |
2634 | .mask = mask_IO_APIC_irq, | |
2635 | .unmask = unmask_IO_APIC_irq, | |
a1e38ca5 | 2636 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 HW |
2637 | .ack = ir_ack_apic_edge, |
2638 | .eoi = ir_ack_apic_level, | |
54168ed7 | 2639 | #ifdef CONFIG_SMP |
d6c88a50 | 2640 | .set_affinity = set_ir_ioapic_affinity_irq, |
a1e38ca5 | 2641 | #endif |
54168ed7 IM |
2642 | #endif |
2643 | .retrigger = ioapic_retrigger_irq, | |
2644 | }; | |
1da177e4 LT |
2645 | |
2646 | static inline void init_IO_APIC_traps(void) | |
2647 | { | |
2648 | int irq; | |
08678b08 | 2649 | struct irq_desc *desc; |
da51a821 | 2650 | struct irq_cfg *cfg; |
1da177e4 LT |
2651 | |
2652 | /* | |
2653 | * NOTE! The local APIC isn't very good at handling | |
2654 | * multiple interrupts at the same interrupt level. | |
2655 | * As the interrupt level is determined by taking the | |
2656 | * vector number and shifting that right by 4, we | |
2657 | * want to spread these out a bit so that they don't | |
2658 | * all fall in the same interrupt level. | |
2659 | * | |
2660 | * Also, we've got to be careful not to trash gate | |
2661 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2662 | */ | |
0b8f1efa | 2663 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2664 | cfg = desc->chip_data; |
2665 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2666 | /* |
2667 | * Hmm.. We don't have an entry for this, | |
2668 | * so default to an old-fashioned 8259 | |
2669 | * interrupt if we can.. | |
2670 | */ | |
99d093d1 | 2671 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2672 | make_8259A_irq(irq); |
0b8f1efa | 2673 | else |
1da177e4 | 2674 | /* Strange. Oh, well.. */ |
08678b08 | 2675 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2676 | } |
2677 | } | |
2678 | } | |
2679 | ||
f5b9ed7a IM |
2680 | /* |
2681 | * The local APIC irq-chip implementation: | |
2682 | */ | |
1da177e4 | 2683 | |
36062448 | 2684 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2685 | { |
2686 | unsigned long v; | |
2687 | ||
2688 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2689 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2690 | } |
2691 | ||
36062448 | 2692 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2693 | { |
f5b9ed7a | 2694 | unsigned long v; |
1da177e4 | 2695 | |
f5b9ed7a | 2696 | v = apic_read(APIC_LVT0); |
593f4a78 | 2697 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2698 | } |
1da177e4 | 2699 | |
3145e941 | 2700 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2701 | { |
2702 | ack_APIC_irq(); | |
2703 | } | |
2704 | ||
f5b9ed7a | 2705 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2706 | .name = "local-APIC", |
f5b9ed7a IM |
2707 | .mask = mask_lapic_irq, |
2708 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2709 | .ack = ack_lapic_irq, |
1da177e4 LT |
2710 | }; |
2711 | ||
3145e941 | 2712 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2713 | { |
08678b08 | 2714 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2715 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2716 | "edge"); | |
c88ac1df MR |
2717 | } |
2718 | ||
e9427101 | 2719 | static void __init setup_nmi(void) |
1da177e4 LT |
2720 | { |
2721 | /* | |
36062448 | 2722 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2723 | * We put the 8259A master into AEOI mode and |
2724 | * unmask on all local APICs LVT0 as NMI. | |
2725 | * | |
2726 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2727 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2728 | * the NMI handler or the timer interrupt. | |
36062448 | 2729 | */ |
1da177e4 LT |
2730 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2731 | ||
e9427101 | 2732 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2733 | |
2734 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2735 | } | |
2736 | ||
2737 | /* | |
2738 | * This looks a bit hackish but it's about the only one way of sending | |
2739 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2740 | * not support the ExtINT mode, unfortunately. We need to send these | |
2741 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2742 | * 8259A interrupt line asserted until INTA. --macro | |
2743 | */ | |
28acf285 | 2744 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2745 | { |
fcfd636a | 2746 | int apic, pin, i; |
1da177e4 LT |
2747 | struct IO_APIC_route_entry entry0, entry1; |
2748 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2749 | |
fcfd636a | 2750 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2751 | if (pin == -1) { |
2752 | WARN_ON_ONCE(1); | |
2753 | return; | |
2754 | } | |
fcfd636a | 2755 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2756 | if (apic == -1) { |
2757 | WARN_ON_ONCE(1); | |
1da177e4 | 2758 | return; |
956fb531 | 2759 | } |
1da177e4 | 2760 | |
cf4c6a2f | 2761 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2762 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2763 | |
2764 | memset(&entry1, 0, sizeof(entry1)); | |
2765 | ||
2766 | entry1.dest_mode = 0; /* physical delivery */ | |
2767 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2768 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2769 | entry1.delivery_mode = dest_ExtINT; |
2770 | entry1.polarity = entry0.polarity; | |
2771 | entry1.trigger = 0; | |
2772 | entry1.vector = 0; | |
2773 | ||
cf4c6a2f | 2774 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2775 | |
2776 | save_control = CMOS_READ(RTC_CONTROL); | |
2777 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2778 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2779 | RTC_FREQ_SELECT); | |
2780 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2781 | ||
2782 | i = 100; | |
2783 | while (i-- > 0) { | |
2784 | mdelay(10); | |
2785 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2786 | i -= 10; | |
2787 | } | |
2788 | ||
2789 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2790 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2791 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2792 | |
cf4c6a2f | 2793 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2794 | } |
2795 | ||
efa2559f | 2796 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2797 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2798 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2799 | { |
2800 | disable_timer_pin_1 = 1; | |
2801 | return 0; | |
2802 | } | |
54168ed7 | 2803 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2804 | |
2805 | int timer_through_8259 __initdata; | |
2806 | ||
1da177e4 LT |
2807 | /* |
2808 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2809 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2810 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2811 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2812 | * |
2813 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2814 | */ |
8542b200 | 2815 | static inline void __init check_timer(void) |
1da177e4 | 2816 | { |
3145e941 YL |
2817 | struct irq_desc *desc = irq_to_desc(0); |
2818 | struct irq_cfg *cfg = desc->chip_data; | |
85ac16d0 | 2819 | int node = cpu_to_node(boot_cpu_id); |
fcfd636a | 2820 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2821 | unsigned long flags; |
047c8fdb | 2822 | int no_pin1 = 0; |
4aae0702 IM |
2823 | |
2824 | local_irq_save(flags); | |
d4d25dec | 2825 | |
1da177e4 LT |
2826 | /* |
2827 | * get/set the timer IRQ vector: | |
2828 | */ | |
2829 | disable_8259A_irq(0); | |
fe402e1f | 2830 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2831 | |
2832 | /* | |
d11d5794 MR |
2833 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2834 | * wire has to be disabled in the local APIC. Also | |
2835 | * timer interrupts need to be acknowledged manually in | |
2836 | * the 8259A for the i82489DX when using the NMI | |
2837 | * watchdog as that APIC treats NMIs as level-triggered. | |
2838 | * The AEOI mode will finish them in the 8259A | |
2839 | * automatically. | |
1da177e4 | 2840 | */ |
593f4a78 | 2841 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2842 | init_8259A(1); |
54168ed7 | 2843 | #ifdef CONFIG_X86_32 |
f72dccac YL |
2844 | { |
2845 | unsigned int ver; | |
2846 | ||
2847 | ver = apic_read(APIC_LVR); | |
2848 | ver = GET_APIC_VERSION(ver); | |
2849 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
2850 | } | |
54168ed7 | 2851 | #endif |
1da177e4 | 2852 | |
fcfd636a EB |
2853 | pin1 = find_isa_irq_pin(0, mp_INT); |
2854 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2855 | pin2 = ioapic_i8259.pin; | |
2856 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2857 | |
49a66a0b MR |
2858 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2859 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2860 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2861 | |
691874fa MR |
2862 | /* |
2863 | * Some BIOS writers are clueless and report the ExtINTA | |
2864 | * I/O APIC input from the cascaded 8259A as the timer | |
2865 | * interrupt input. So just in case, if only one pin | |
2866 | * was found above, try it both directly and through the | |
2867 | * 8259A. | |
2868 | */ | |
2869 | if (pin1 == -1) { | |
54168ed7 IM |
2870 | if (intr_remapping_enabled) |
2871 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2872 | pin1 = pin2; |
2873 | apic1 = apic2; | |
2874 | no_pin1 = 1; | |
2875 | } else if (pin2 == -1) { | |
2876 | pin2 = pin1; | |
2877 | apic2 = apic1; | |
2878 | } | |
2879 | ||
1da177e4 LT |
2880 | if (pin1 != -1) { |
2881 | /* | |
2882 | * Ok, does IRQ0 through the IOAPIC work? | |
2883 | */ | |
691874fa | 2884 | if (no_pin1) { |
85ac16d0 | 2885 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2886 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac YL |
2887 | } else { |
2888 | /* for edge trigger, setup_IO_APIC_irq already | |
2889 | * leave it unmasked. | |
2890 | * so only need to unmask if it is level-trigger | |
2891 | * do we really have level trigger timer? | |
2892 | */ | |
2893 | int idx; | |
2894 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2895 | if (idx != -1 && irq_trigger(idx)) | |
2896 | unmask_IO_APIC_irq_desc(desc); | |
691874fa | 2897 | } |
1da177e4 LT |
2898 | if (timer_irq_works()) { |
2899 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2900 | setup_nmi(); |
2901 | enable_8259A_irq(0); | |
1da177e4 | 2902 | } |
66759a01 CE |
2903 | if (disable_timer_pin_1 > 0) |
2904 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2905 | goto out; |
1da177e4 | 2906 | } |
54168ed7 IM |
2907 | if (intr_remapping_enabled) |
2908 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
f72dccac | 2909 | local_irq_disable(); |
fcfd636a | 2910 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2911 | if (!no_pin1) |
49a66a0b MR |
2912 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2913 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2914 | |
49a66a0b MR |
2915 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2916 | "(IRQ0) through the 8259A ...\n"); | |
2917 | apic_printk(APIC_QUIET, KERN_INFO | |
2918 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2919 | /* |
2920 | * legacy devices should be connected to IO APIC #0 | |
2921 | */ | |
85ac16d0 | 2922 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2923 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
ecd29476 | 2924 | enable_8259A_irq(0); |
1da177e4 | 2925 | if (timer_irq_works()) { |
49a66a0b | 2926 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2927 | timer_through_8259 = 1; |
1da177e4 | 2928 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2929 | disable_8259A_irq(0); |
1da177e4 | 2930 | setup_nmi(); |
60134ebe | 2931 | enable_8259A_irq(0); |
1da177e4 | 2932 | } |
4aae0702 | 2933 | goto out; |
1da177e4 LT |
2934 | } |
2935 | /* | |
2936 | * Cleanup, just in case ... | |
2937 | */ | |
f72dccac | 2938 | local_irq_disable(); |
ecd29476 | 2939 | disable_8259A_irq(0); |
fcfd636a | 2940 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2941 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2942 | } |
1da177e4 LT |
2943 | |
2944 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2945 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2946 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2947 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2948 | } |
54168ed7 | 2949 | #ifdef CONFIG_X86_32 |
d11d5794 | 2950 | timer_ack = 0; |
54168ed7 | 2951 | #endif |
1da177e4 | 2952 | |
49a66a0b MR |
2953 | apic_printk(APIC_QUIET, KERN_INFO |
2954 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2955 | |
3145e941 | 2956 | lapic_register_intr(0, desc); |
497c9a19 | 2957 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2958 | enable_8259A_irq(0); |
2959 | ||
2960 | if (timer_irq_works()) { | |
49a66a0b | 2961 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2962 | goto out; |
1da177e4 | 2963 | } |
f72dccac | 2964 | local_irq_disable(); |
e67465f1 | 2965 | disable_8259A_irq(0); |
497c9a19 | 2966 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2967 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2968 | |
49a66a0b MR |
2969 | apic_printk(APIC_QUIET, KERN_INFO |
2970 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2971 | |
1da177e4 LT |
2972 | init_8259A(0); |
2973 | make_8259A_irq(0); | |
593f4a78 | 2974 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2975 | |
2976 | unlock_ExtINT_logic(); | |
2977 | ||
2978 | if (timer_irq_works()) { | |
49a66a0b | 2979 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2980 | goto out; |
1da177e4 | 2981 | } |
f72dccac | 2982 | local_irq_disable(); |
49a66a0b | 2983 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2984 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2985 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2986 | out: |
2987 | local_irq_restore(flags); | |
1da177e4 LT |
2988 | } |
2989 | ||
2990 | /* | |
af174783 MR |
2991 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2992 | * to devices. However there may be an I/O APIC pin available for | |
2993 | * this interrupt regardless. The pin may be left unconnected, but | |
2994 | * typically it will be reused as an ExtINT cascade interrupt for | |
2995 | * the master 8259A. In the MPS case such a pin will normally be | |
2996 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2997 | * there is no provision for ExtINT interrupts, and in the absence | |
2998 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2999 | * interrupt, that is edge-triggered and unmasked by default. We | |
3000 | * used to do this, but it caused problems on some systems because | |
3001 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3002 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3003 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3004 | * the I/O APIC in all cases now. No actual device should request | |
3005 | * it anyway. --macro | |
1da177e4 LT |
3006 | */ |
3007 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3008 | ||
3009 | void __init setup_IO_APIC(void) | |
3010 | { | |
54168ed7 | 3011 | |
54168ed7 IM |
3012 | /* |
3013 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3014 | */ | |
1da177e4 | 3015 | |
af174783 | 3016 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3017 | |
54168ed7 | 3018 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3019 | /* |
54168ed7 IM |
3020 | * Set up IO-APIC IRQ routing. |
3021 | */ | |
3022 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3023 | if (!acpi_ioapic) |
3024 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3025 | #endif |
1da177e4 LT |
3026 | sync_Arb_IDs(); |
3027 | setup_IO_APIC_irqs(); | |
3028 | init_IO_APIC_traps(); | |
1e4c85f9 | 3029 | check_timer(); |
1da177e4 LT |
3030 | } |
3031 | ||
3032 | /* | |
54168ed7 IM |
3033 | * Called after all the initialization is done. If we didnt find any |
3034 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3035 | */ |
36062448 | 3036 | |
1da177e4 LT |
3037 | static int __init io_apic_bug_finalize(void) |
3038 | { | |
d6c88a50 TG |
3039 | if (sis_apic_bug == -1) |
3040 | sis_apic_bug = 0; | |
3041 | return 0; | |
1da177e4 LT |
3042 | } |
3043 | ||
3044 | late_initcall(io_apic_bug_finalize); | |
3045 | ||
3046 | struct sysfs_ioapic_data { | |
3047 | struct sys_device dev; | |
3048 | struct IO_APIC_route_entry entry[0]; | |
3049 | }; | |
54168ed7 | 3050 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3051 | |
438510f6 | 3052 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3053 | { |
3054 | struct IO_APIC_route_entry *entry; | |
3055 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3056 | int i; |
36062448 | 3057 | |
1da177e4 LT |
3058 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3059 | entry = data->entry; | |
54168ed7 IM |
3060 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3061 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3062 | |
3063 | return 0; | |
3064 | } | |
3065 | ||
3066 | static int ioapic_resume(struct sys_device *dev) | |
3067 | { | |
3068 | struct IO_APIC_route_entry *entry; | |
3069 | struct sysfs_ioapic_data *data; | |
3070 | unsigned long flags; | |
3071 | union IO_APIC_reg_00 reg_00; | |
3072 | int i; | |
36062448 | 3073 | |
1da177e4 LT |
3074 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3075 | entry = data->entry; | |
3076 | ||
3077 | spin_lock_irqsave(&ioapic_lock, flags); | |
3078 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3079 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3080 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3081 | io_apic_write(dev->id, 0, reg_00.raw); |
3082 | } | |
1da177e4 | 3083 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3084 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3085 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3086 | |
3087 | return 0; | |
3088 | } | |
3089 | ||
3090 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3091 | .name = "ioapic", |
1da177e4 LT |
3092 | .suspend = ioapic_suspend, |
3093 | .resume = ioapic_resume, | |
3094 | }; | |
3095 | ||
3096 | static int __init ioapic_init_sysfs(void) | |
3097 | { | |
54168ed7 IM |
3098 | struct sys_device * dev; |
3099 | int i, size, error; | |
1da177e4 LT |
3100 | |
3101 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3102 | if (error) | |
3103 | return error; | |
3104 | ||
54168ed7 | 3105 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3106 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3107 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3108 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3109 | if (!mp_ioapic_data[i]) { |
3110 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3111 | continue; | |
3112 | } | |
1da177e4 | 3113 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3114 | dev->id = i; |
1da177e4 LT |
3115 | dev->cls = &ioapic_sysdev_class; |
3116 | error = sysdev_register(dev); | |
3117 | if (error) { | |
3118 | kfree(mp_ioapic_data[i]); | |
3119 | mp_ioapic_data[i] = NULL; | |
3120 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3121 | continue; | |
3122 | } | |
3123 | } | |
3124 | ||
3125 | return 0; | |
3126 | } | |
3127 | ||
3128 | device_initcall(ioapic_init_sysfs); | |
3129 | ||
abcaa2b8 | 3130 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
3fc471ed | 3131 | /* |
95d77884 | 3132 | * Dynamic irq allocate and deallocation |
3fc471ed | 3133 | */ |
d047f53a | 3134 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
3fc471ed | 3135 | { |
ace80ab7 | 3136 | /* Allocate an unused irq */ |
54168ed7 IM |
3137 | unsigned int irq; |
3138 | unsigned int new; | |
3fc471ed | 3139 | unsigned long flags; |
0b8f1efa | 3140 | struct irq_cfg *cfg_new = NULL; |
0b8f1efa | 3141 | struct irq_desc *desc_new = NULL; |
199751d7 YL |
3142 | |
3143 | irq = 0; | |
abcaa2b8 YL |
3144 | if (irq_want < nr_irqs_gsi) |
3145 | irq_want = nr_irqs_gsi; | |
3146 | ||
ace80ab7 | 3147 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3148 | for (new = irq_want; new < nr_irqs; new++) { |
85ac16d0 | 3149 | desc_new = irq_to_desc_alloc_node(new, node); |
0b8f1efa YL |
3150 | if (!desc_new) { |
3151 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3152 | continue; |
0b8f1efa YL |
3153 | } |
3154 | cfg_new = desc_new->chip_data; | |
3155 | ||
3156 | if (cfg_new->vector != 0) | |
ace80ab7 | 3157 | continue; |
d047f53a | 3158 | |
15e957d0 | 3159 | desc_new = move_irq_desc(desc_new, node); |
d047f53a | 3160 | |
fe402e1f | 3161 | if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0) |
ace80ab7 EB |
3162 | irq = new; |
3163 | break; | |
3164 | } | |
3165 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3166 | |
199751d7 | 3167 | if (irq > 0) { |
3fc471ed | 3168 | dynamic_irq_init(irq); |
0b8f1efa YL |
3169 | /* restore it, in case dynamic_irq_init clear it */ |
3170 | if (desc_new) | |
3171 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3172 | } |
3173 | return irq; | |
3174 | } | |
3175 | ||
199751d7 YL |
3176 | int create_irq(void) |
3177 | { | |
d047f53a | 3178 | int node = cpu_to_node(boot_cpu_id); |
be5d5350 | 3179 | unsigned int irq_want; |
54168ed7 IM |
3180 | int irq; |
3181 | ||
be5d5350 | 3182 | irq_want = nr_irqs_gsi; |
d047f53a | 3183 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3184 | |
3185 | if (irq == 0) | |
3186 | irq = -1; | |
3187 | ||
3188 | return irq; | |
199751d7 YL |
3189 | } |
3190 | ||
3fc471ed EB |
3191 | void destroy_irq(unsigned int irq) |
3192 | { | |
3193 | unsigned long flags; | |
0b8f1efa YL |
3194 | struct irq_cfg *cfg; |
3195 | struct irq_desc *desc; | |
3fc471ed | 3196 | |
0b8f1efa YL |
3197 | /* store it, in case dynamic_irq_cleanup clear it */ |
3198 | desc = irq_to_desc(irq); | |
3199 | cfg = desc->chip_data; | |
3fc471ed | 3200 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3201 | /* connect back irq_cfg */ |
3202 | if (desc) | |
3203 | desc->chip_data = cfg; | |
3fc471ed | 3204 | |
54168ed7 | 3205 | free_irte(irq); |
3fc471ed | 3206 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3207 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3208 | spin_unlock_irqrestore(&vector_lock, flags); |
3209 | } | |
3fc471ed | 3210 | |
2d3fcc1c | 3211 | /* |
27b46d76 | 3212 | * MSI message composition |
2d3fcc1c EB |
3213 | */ |
3214 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3215 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3216 | { |
497c9a19 YL |
3217 | struct irq_cfg *cfg; |
3218 | int err; | |
2d3fcc1c EB |
3219 | unsigned dest; |
3220 | ||
f1182638 JB |
3221 | if (disable_apic) |
3222 | return -ENXIO; | |
3223 | ||
3145e941 | 3224 | cfg = irq_cfg(irq); |
fe402e1f | 3225 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
497c9a19 YL |
3226 | if (err) |
3227 | return err; | |
2d3fcc1c | 3228 | |
debccb3e | 3229 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); |
497c9a19 | 3230 | |
54168ed7 IM |
3231 | if (irq_remapped(irq)) { |
3232 | struct irte irte; | |
3233 | int ir_index; | |
3234 | u16 sub_handle; | |
3235 | ||
3236 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3237 | BUG_ON(ir_index == -1); | |
3238 | ||
3239 | memset (&irte, 0, sizeof(irte)); | |
3240 | ||
3241 | irte.present = 1; | |
9b5bc8dc | 3242 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3243 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3244 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3245 | irte.vector = cfg->vector; |
3246 | irte.dest_id = IRTE_DEST(dest); | |
3247 | ||
3248 | modify_irte(irq, &irte); | |
3249 | ||
3250 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3251 | msg->data = sub_handle; | |
3252 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3253 | MSI_ADDR_IR_SHV | | |
3254 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3255 | MSI_ADDR_IR_INDEX2(ir_index); | |
29b61be6 | 3256 | } else { |
9d783ba0 SS |
3257 | if (x2apic_enabled()) |
3258 | msg->address_hi = MSI_ADDR_BASE_HI | | |
3259 | MSI_ADDR_EXT_DEST_ID(dest); | |
3260 | else | |
3261 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3262 | ||
54168ed7 IM |
3263 | msg->address_lo = |
3264 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3265 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3266 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3267 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3268 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3269 | MSI_ADDR_REDIRECTION_CPU: |
3270 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3271 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3272 | |
54168ed7 IM |
3273 | msg->data = |
3274 | MSI_DATA_TRIGGER_EDGE | | |
3275 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3276 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3277 | MSI_DATA_DELIVERY_FIXED: |
3278 | MSI_DATA_DELIVERY_LOWPRI) | | |
3279 | MSI_DATA_VECTOR(cfg->vector); | |
3280 | } | |
497c9a19 | 3281 | return err; |
2d3fcc1c EB |
3282 | } |
3283 | ||
3b7d1921 | 3284 | #ifdef CONFIG_SMP |
d5dedd45 | 3285 | static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3286 | { |
3145e941 | 3287 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3288 | struct irq_cfg *cfg; |
3b7d1921 EB |
3289 | struct msi_msg msg; |
3290 | unsigned int dest; | |
3b7d1921 | 3291 | |
22f65d31 MT |
3292 | dest = set_desc_affinity(desc, mask); |
3293 | if (dest == BAD_APICID) | |
d5dedd45 | 3294 | return -1; |
2d3fcc1c | 3295 | |
3145e941 | 3296 | cfg = desc->chip_data; |
2d3fcc1c | 3297 | |
3145e941 | 3298 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3299 | |
3300 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3301 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3302 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3303 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3304 | ||
3145e941 | 3305 | write_msi_msg_desc(desc, &msg); |
d5dedd45 YL |
3306 | |
3307 | return 0; | |
2d3fcc1c | 3308 | } |
54168ed7 IM |
3309 | #ifdef CONFIG_INTR_REMAP |
3310 | /* | |
3311 | * Migrate the MSI irq to another cpumask. This migration is | |
3312 | * done in the process context using interrupt-remapping hardware. | |
3313 | */ | |
d5dedd45 | 3314 | static int |
e7986739 | 3315 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3316 | { |
3145e941 | 3317 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3318 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3319 | unsigned int dest; |
54168ed7 | 3320 | struct irte irte; |
54168ed7 IM |
3321 | |
3322 | if (get_irte(irq, &irte)) | |
d5dedd45 | 3323 | return -1; |
54168ed7 | 3324 | |
22f65d31 MT |
3325 | dest = set_desc_affinity(desc, mask); |
3326 | if (dest == BAD_APICID) | |
d5dedd45 | 3327 | return -1; |
54168ed7 | 3328 | |
54168ed7 IM |
3329 | irte.vector = cfg->vector; |
3330 | irte.dest_id = IRTE_DEST(dest); | |
3331 | ||
3332 | /* | |
3333 | * atomically update the IRTE with the new destination and vector. | |
3334 | */ | |
3335 | modify_irte(irq, &irte); | |
3336 | ||
3337 | /* | |
3338 | * After this point, all the interrupts will start arriving | |
3339 | * at the new destination. So, time to cleanup the previous | |
3340 | * vector allocation. | |
3341 | */ | |
22f65d31 MT |
3342 | if (cfg->move_in_progress) |
3343 | send_cleanup_vector(cfg); | |
d5dedd45 YL |
3344 | |
3345 | return 0; | |
54168ed7 | 3346 | } |
3145e941 | 3347 | |
54168ed7 | 3348 | #endif |
3b7d1921 | 3349 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3350 | |
3b7d1921 EB |
3351 | /* |
3352 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3353 | * which implement the MSI or MSI-X Capability Structure. | |
3354 | */ | |
3355 | static struct irq_chip msi_chip = { | |
3356 | .name = "PCI-MSI", | |
3357 | .unmask = unmask_msi_irq, | |
3358 | .mask = mask_msi_irq, | |
1d025192 | 3359 | .ack = ack_apic_edge, |
3b7d1921 EB |
3360 | #ifdef CONFIG_SMP |
3361 | .set_affinity = set_msi_irq_affinity, | |
3362 | #endif | |
3363 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3364 | }; |
3365 | ||
54168ed7 IM |
3366 | static struct irq_chip msi_ir_chip = { |
3367 | .name = "IR-PCI-MSI", | |
3368 | .unmask = unmask_msi_irq, | |
3369 | .mask = mask_msi_irq, | |
a1e38ca5 | 3370 | #ifdef CONFIG_INTR_REMAP |
d0b03bd1 | 3371 | .ack = ir_ack_apic_edge, |
54168ed7 IM |
3372 | #ifdef CONFIG_SMP |
3373 | .set_affinity = ir_set_msi_irq_affinity, | |
a1e38ca5 | 3374 | #endif |
54168ed7 IM |
3375 | #endif |
3376 | .retrigger = ioapic_retrigger_irq, | |
3377 | }; | |
3378 | ||
3379 | /* | |
3380 | * Map the PCI dev to the corresponding remapping hardware unit | |
3381 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3382 | * in it. | |
3383 | */ | |
3384 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3385 | { | |
3386 | struct intel_iommu *iommu; | |
3387 | int index; | |
3388 | ||
3389 | iommu = map_dev_to_ir(dev); | |
3390 | if (!iommu) { | |
3391 | printk(KERN_ERR | |
3392 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3393 | return -ENOENT; | |
3394 | } | |
3395 | ||
3396 | index = alloc_irte(iommu, irq, nvec); | |
3397 | if (index < 0) { | |
3398 | printk(KERN_ERR | |
3399 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3400 | pci_name(dev)); |
54168ed7 IM |
3401 | return -ENOSPC; |
3402 | } | |
3403 | return index; | |
3404 | } | |
1d025192 | 3405 | |
3145e941 | 3406 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3407 | { |
3408 | int ret; | |
3409 | struct msi_msg msg; | |
3410 | ||
3411 | ret = msi_compose_msg(dev, irq, &msg); | |
3412 | if (ret < 0) | |
3413 | return ret; | |
3414 | ||
3145e941 | 3415 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3416 | write_msi_msg(irq, &msg); |
3417 | ||
54168ed7 IM |
3418 | if (irq_remapped(irq)) { |
3419 | struct irq_desc *desc = irq_to_desc(irq); | |
3420 | /* | |
3421 | * irq migration in process context | |
3422 | */ | |
3423 | desc->status |= IRQ_MOVE_PCNTXT; | |
3424 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3425 | } else | |
54168ed7 | 3426 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
1d025192 | 3427 | |
c81bba49 YL |
3428 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3429 | ||
1d025192 YL |
3430 | return 0; |
3431 | } | |
3432 | ||
047c8fdb YL |
3433 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3434 | { | |
54168ed7 IM |
3435 | unsigned int irq; |
3436 | int ret, sub_handle; | |
0b8f1efa | 3437 | struct msi_desc *msidesc; |
54168ed7 | 3438 | unsigned int irq_want; |
1cc18521 | 3439 | struct intel_iommu *iommu = NULL; |
54168ed7 | 3440 | int index = 0; |
d047f53a | 3441 | int node; |
54168ed7 | 3442 | |
1c8d7b0a MW |
3443 | /* x86 doesn't support multiple MSI yet */ |
3444 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3445 | return 1; | |
3446 | ||
d047f53a | 3447 | node = dev_to_node(&dev->dev); |
be5d5350 | 3448 | irq_want = nr_irqs_gsi; |
54168ed7 | 3449 | sub_handle = 0; |
0b8f1efa | 3450 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
d047f53a | 3451 | irq = create_irq_nr(irq_want, node); |
54168ed7 IM |
3452 | if (irq == 0) |
3453 | return -1; | |
f1ee5548 | 3454 | irq_want = irq + 1; |
54168ed7 IM |
3455 | if (!intr_remapping_enabled) |
3456 | goto no_ir; | |
3457 | ||
3458 | if (!sub_handle) { | |
3459 | /* | |
3460 | * allocate the consecutive block of IRTE's | |
3461 | * for 'nvec' | |
3462 | */ | |
3463 | index = msi_alloc_irte(dev, irq, nvec); | |
3464 | if (index < 0) { | |
3465 | ret = index; | |
3466 | goto error; | |
3467 | } | |
3468 | } else { | |
3469 | iommu = map_dev_to_ir(dev); | |
3470 | if (!iommu) { | |
3471 | ret = -ENOENT; | |
3472 | goto error; | |
3473 | } | |
3474 | /* | |
3475 | * setup the mapping between the irq and the IRTE | |
3476 | * base index, the sub_handle pointing to the | |
3477 | * appropriate interrupt remap table entry. | |
3478 | */ | |
3479 | set_irte_irq(irq, iommu, index, sub_handle); | |
3480 | } | |
3481 | no_ir: | |
0b8f1efa | 3482 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3483 | if (ret < 0) |
3484 | goto error; | |
3485 | sub_handle++; | |
3486 | } | |
3487 | return 0; | |
047c8fdb YL |
3488 | |
3489 | error: | |
54168ed7 IM |
3490 | destroy_irq(irq); |
3491 | return ret; | |
047c8fdb YL |
3492 | } |
3493 | ||
3b7d1921 EB |
3494 | void arch_teardown_msi_irq(unsigned int irq) |
3495 | { | |
f7feaca7 | 3496 | destroy_irq(irq); |
3b7d1921 EB |
3497 | } |
3498 | ||
9d783ba0 | 3499 | #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP) |
54168ed7 | 3500 | #ifdef CONFIG_SMP |
d5dedd45 | 3501 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3502 | { |
3145e941 | 3503 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3504 | struct irq_cfg *cfg; |
3505 | struct msi_msg msg; | |
3506 | unsigned int dest; | |
54168ed7 | 3507 | |
22f65d31 MT |
3508 | dest = set_desc_affinity(desc, mask); |
3509 | if (dest == BAD_APICID) | |
d5dedd45 | 3510 | return -1; |
54168ed7 | 3511 | |
3145e941 | 3512 | cfg = desc->chip_data; |
54168ed7 IM |
3513 | |
3514 | dmar_msi_read(irq, &msg); | |
3515 | ||
3516 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3517 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3518 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3519 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3520 | ||
3521 | dmar_msi_write(irq, &msg); | |
d5dedd45 YL |
3522 | |
3523 | return 0; | |
54168ed7 | 3524 | } |
3145e941 | 3525 | |
54168ed7 IM |
3526 | #endif /* CONFIG_SMP */ |
3527 | ||
3528 | struct irq_chip dmar_msi_type = { | |
3529 | .name = "DMAR_MSI", | |
3530 | .unmask = dmar_msi_unmask, | |
3531 | .mask = dmar_msi_mask, | |
3532 | .ack = ack_apic_edge, | |
3533 | #ifdef CONFIG_SMP | |
3534 | .set_affinity = dmar_msi_set_affinity, | |
3535 | #endif | |
3536 | .retrigger = ioapic_retrigger_irq, | |
3537 | }; | |
3538 | ||
3539 | int arch_setup_dmar_msi(unsigned int irq) | |
3540 | { | |
3541 | int ret; | |
3542 | struct msi_msg msg; | |
2d3fcc1c | 3543 | |
54168ed7 IM |
3544 | ret = msi_compose_msg(NULL, irq, &msg); |
3545 | if (ret < 0) | |
3546 | return ret; | |
3547 | dmar_msi_write(irq, &msg); | |
3548 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3549 | "edge"); | |
3550 | return 0; | |
3551 | } | |
3552 | #endif | |
3553 | ||
58ac1e76 | 3554 | #ifdef CONFIG_HPET_TIMER |
3555 | ||
3556 | #ifdef CONFIG_SMP | |
d5dedd45 | 3557 | static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3558 | { |
3145e941 | 3559 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3560 | struct irq_cfg *cfg; |
58ac1e76 | 3561 | struct msi_msg msg; |
3562 | unsigned int dest; | |
58ac1e76 | 3563 | |
22f65d31 MT |
3564 | dest = set_desc_affinity(desc, mask); |
3565 | if (dest == BAD_APICID) | |
d5dedd45 | 3566 | return -1; |
58ac1e76 | 3567 | |
3145e941 | 3568 | cfg = desc->chip_data; |
58ac1e76 | 3569 | |
3570 | hpet_msi_read(irq, &msg); | |
3571 | ||
3572 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3573 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3574 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3575 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3576 | ||
3577 | hpet_msi_write(irq, &msg); | |
d5dedd45 YL |
3578 | |
3579 | return 0; | |
58ac1e76 | 3580 | } |
3145e941 | 3581 | |
58ac1e76 | 3582 | #endif /* CONFIG_SMP */ |
3583 | ||
1cc18521 | 3584 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3585 | .name = "HPET_MSI", |
3586 | .unmask = hpet_msi_unmask, | |
3587 | .mask = hpet_msi_mask, | |
3588 | .ack = ack_apic_edge, | |
3589 | #ifdef CONFIG_SMP | |
3590 | .set_affinity = hpet_msi_set_affinity, | |
3591 | #endif | |
3592 | .retrigger = ioapic_retrigger_irq, | |
3593 | }; | |
3594 | ||
3595 | int arch_setup_hpet_msi(unsigned int irq) | |
3596 | { | |
3597 | int ret; | |
3598 | struct msi_msg msg; | |
6ec3cfec | 3599 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3600 | |
3601 | ret = msi_compose_msg(NULL, irq, &msg); | |
3602 | if (ret < 0) | |
3603 | return ret; | |
3604 | ||
3605 | hpet_msi_write(irq, &msg); | |
6ec3cfec | 3606 | desc->status |= IRQ_MOVE_PCNTXT; |
58ac1e76 | 3607 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3608 | "edge"); | |
c81bba49 | 3609 | |
58ac1e76 | 3610 | return 0; |
3611 | } | |
3612 | #endif | |
3613 | ||
54168ed7 | 3614 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3615 | /* |
3616 | * Hypertransport interrupt support | |
3617 | */ | |
3618 | #ifdef CONFIG_HT_IRQ | |
3619 | ||
3620 | #ifdef CONFIG_SMP | |
3621 | ||
497c9a19 | 3622 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3623 | { |
ec68307c EB |
3624 | struct ht_irq_msg msg; |
3625 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3626 | |
497c9a19 | 3627 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3628 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3629 | |
497c9a19 | 3630 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3631 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3632 | |
ec68307c | 3633 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3634 | } |
3635 | ||
d5dedd45 | 3636 | static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3637 | { |
3145e941 | 3638 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3639 | struct irq_cfg *cfg; |
8b955b0d | 3640 | unsigned int dest; |
8b955b0d | 3641 | |
22f65d31 MT |
3642 | dest = set_desc_affinity(desc, mask); |
3643 | if (dest == BAD_APICID) | |
d5dedd45 | 3644 | return -1; |
8b955b0d | 3645 | |
3145e941 | 3646 | cfg = desc->chip_data; |
8b955b0d | 3647 | |
497c9a19 | 3648 | target_ht_irq(irq, dest, cfg->vector); |
d5dedd45 YL |
3649 | |
3650 | return 0; | |
8b955b0d | 3651 | } |
3145e941 | 3652 | |
8b955b0d EB |
3653 | #endif |
3654 | ||
c37e108d | 3655 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3656 | .name = "PCI-HT", |
3657 | .mask = mask_ht_irq, | |
3658 | .unmask = unmask_ht_irq, | |
1d025192 | 3659 | .ack = ack_apic_edge, |
8b955b0d EB |
3660 | #ifdef CONFIG_SMP |
3661 | .set_affinity = set_ht_irq_affinity, | |
3662 | #endif | |
3663 | .retrigger = ioapic_retrigger_irq, | |
3664 | }; | |
3665 | ||
3666 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3667 | { | |
497c9a19 YL |
3668 | struct irq_cfg *cfg; |
3669 | int err; | |
8b955b0d | 3670 | |
f1182638 JB |
3671 | if (disable_apic) |
3672 | return -ENXIO; | |
3673 | ||
3145e941 | 3674 | cfg = irq_cfg(irq); |
fe402e1f | 3675 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
54168ed7 | 3676 | if (!err) { |
ec68307c | 3677 | struct ht_irq_msg msg; |
8b955b0d | 3678 | unsigned dest; |
8b955b0d | 3679 | |
debccb3e IM |
3680 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, |
3681 | apic->target_cpus()); | |
8b955b0d | 3682 | |
ec68307c | 3683 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3684 | |
ec68307c EB |
3685 | msg.address_lo = |
3686 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3687 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3688 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3689 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3690 | HT_IRQ_LOW_DM_PHYSICAL : |
3691 | HT_IRQ_LOW_DM_LOGICAL) | | |
3692 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3693 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3694 | HT_IRQ_LOW_MT_FIXED : |
3695 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3696 | HT_IRQ_LOW_IRQ_MASKED; | |
3697 | ||
ec68307c | 3698 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3699 | |
a460e745 IM |
3700 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3701 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3702 | |
3703 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3704 | } |
497c9a19 | 3705 | return err; |
8b955b0d EB |
3706 | } |
3707 | #endif /* CONFIG_HT_IRQ */ | |
3708 | ||
03b48632 | 3709 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3710 | /* |
3711 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3712 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3713 | */ | |
3714 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3715 | unsigned long mmr_offset) | |
3716 | { | |
22f65d31 | 3717 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3718 | struct irq_cfg *cfg; |
3719 | int mmr_pnode; | |
3720 | unsigned long mmr_value; | |
3721 | struct uv_IO_APIC_route_entry *entry; | |
3722 | unsigned long flags; | |
3723 | int err; | |
3724 | ||
3145e941 YL |
3725 | cfg = irq_cfg(irq); |
3726 | ||
e7986739 | 3727 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3728 | if (err != 0) |
3729 | return err; | |
3730 | ||
3731 | spin_lock_irqsave(&vector_lock, flags); | |
3732 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3733 | irq_name); | |
3734 | spin_unlock_irqrestore(&vector_lock, flags); | |
3735 | ||
4173a0e7 DN |
3736 | mmr_value = 0; |
3737 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3738 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3739 | ||
3740 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3741 | entry->delivery_mode = apic->irq_delivery_mode; |
3742 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3743 | entry->polarity = 0; |
3744 | entry->trigger = 0; | |
3745 | entry->mask = 0; | |
debccb3e | 3746 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3747 | |
3748 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3749 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3750 | ||
3751 | return irq; | |
3752 | } | |
3753 | ||
3754 | /* | |
3755 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3756 | * longer allowed to be sent. | |
3757 | */ | |
3758 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3759 | { | |
3760 | unsigned long mmr_value; | |
3761 | struct uv_IO_APIC_route_entry *entry; | |
3762 | int mmr_pnode; | |
3763 | ||
3764 | mmr_value = 0; | |
3765 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3766 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3767 | ||
3768 | entry->mask = 1; | |
3769 | ||
3770 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3771 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3772 | } | |
3773 | #endif /* CONFIG_X86_64 */ | |
3774 | ||
9d6a4d08 YL |
3775 | int __init io_apic_get_redir_entries (int ioapic) |
3776 | { | |
3777 | union IO_APIC_reg_01 reg_01; | |
3778 | unsigned long flags; | |
3779 | ||
3780 | spin_lock_irqsave(&ioapic_lock, flags); | |
3781 | reg_01.raw = io_apic_read(ioapic, 1); | |
3782 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3783 | ||
3784 | return reg_01.bits.entries; | |
3785 | } | |
3786 | ||
be5d5350 | 3787 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3788 | { |
be5d5350 YL |
3789 | int nr = 0; |
3790 | ||
cc6c5006 YL |
3791 | nr = acpi_probe_gsi(); |
3792 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3793 | nr_irqs_gsi = nr; |
cc6c5006 YL |
3794 | } else { |
3795 | /* for acpi=off or acpi is not compiled in */ | |
3796 | int idx; | |
3797 | ||
3798 | nr = 0; | |
3799 | for (idx = 0; idx < nr_ioapics; idx++) | |
3800 | nr += io_apic_get_redir_entries(idx) + 1; | |
3801 | ||
3802 | if (nr > nr_irqs_gsi) | |
3803 | nr_irqs_gsi = nr; | |
3804 | } | |
3805 | ||
3806 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3807 | } |
3808 | ||
4a046d17 YL |
3809 | #ifdef CONFIG_SPARSE_IRQ |
3810 | int __init arch_probe_nr_irqs(void) | |
3811 | { | |
3812 | int nr; | |
3813 | ||
f1ee5548 YL |
3814 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3815 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3816 | |
f1ee5548 YL |
3817 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
3818 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
3819 | /* | |
3820 | * for MSI and HT dyn irq | |
3821 | */ | |
3822 | nr += nr_irqs_gsi * 16; | |
3823 | #endif | |
3824 | if (nr < nr_irqs) | |
4a046d17 YL |
3825 | nr_irqs = nr; |
3826 | ||
3827 | return 0; | |
3828 | } | |
3829 | #endif | |
3830 | ||
1da177e4 | 3831 | /* -------------------------------------------------------------------------- |
54168ed7 | 3832 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3833 | -------------------------------------------------------------------------- */ |
3834 | ||
888ba6c6 | 3835 | #ifdef CONFIG_ACPI |
1da177e4 | 3836 | |
54168ed7 | 3837 | #ifdef CONFIG_X86_32 |
36062448 | 3838 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3839 | { |
3840 | union IO_APIC_reg_00 reg_00; | |
3841 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3842 | physid_mask_t tmp; | |
3843 | unsigned long flags; | |
3844 | int i = 0; | |
3845 | ||
3846 | /* | |
36062448 PC |
3847 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3848 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3849 | * supports up to 16 on one shared APIC bus. |
36062448 | 3850 | * |
1da177e4 LT |
3851 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3852 | * advantage of new APIC bus architecture. | |
3853 | */ | |
3854 | ||
3855 | if (physids_empty(apic_id_map)) | |
d190cb87 | 3856 | apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map); |
1da177e4 LT |
3857 | |
3858 | spin_lock_irqsave(&ioapic_lock, flags); | |
3859 | reg_00.raw = io_apic_read(ioapic, 0); | |
3860 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3861 | ||
3862 | if (apic_id >= get_physical_broadcast()) { | |
3863 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3864 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3865 | apic_id = reg_00.bits.ID; | |
3866 | } | |
3867 | ||
3868 | /* | |
36062448 | 3869 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3870 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3871 | */ | |
d1d7cae8 | 3872 | if (apic->check_apicid_used(apic_id_map, apic_id)) { |
1da177e4 LT |
3873 | |
3874 | for (i = 0; i < get_physical_broadcast(); i++) { | |
d1d7cae8 | 3875 | if (!apic->check_apicid_used(apic_id_map, i)) |
1da177e4 LT |
3876 | break; |
3877 | } | |
3878 | ||
3879 | if (i == get_physical_broadcast()) | |
3880 | panic("Max apic_id exceeded!\n"); | |
3881 | ||
3882 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3883 | "trying %d\n", ioapic, apic_id, i); | |
3884 | ||
3885 | apic_id = i; | |
36062448 | 3886 | } |
1da177e4 | 3887 | |
8058714a | 3888 | tmp = apic->apicid_to_cpu_present(apic_id); |
1da177e4 LT |
3889 | physids_or(apic_id_map, apic_id_map, tmp); |
3890 | ||
3891 | if (reg_00.bits.ID != apic_id) { | |
3892 | reg_00.bits.ID = apic_id; | |
3893 | ||
3894 | spin_lock_irqsave(&ioapic_lock, flags); | |
3895 | io_apic_write(ioapic, 0, reg_00.raw); | |
3896 | reg_00.raw = io_apic_read(ioapic, 0); | |
3897 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3898 | ||
3899 | /* Sanity check */ | |
6070f9ec AD |
3900 | if (reg_00.bits.ID != apic_id) { |
3901 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3902 | return -1; | |
3903 | } | |
1da177e4 LT |
3904 | } |
3905 | ||
3906 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3907 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3908 | ||
3909 | return apic_id; | |
3910 | } | |
3911 | ||
36062448 | 3912 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3913 | { |
3914 | union IO_APIC_reg_01 reg_01; | |
3915 | unsigned long flags; | |
3916 | ||
3917 | spin_lock_irqsave(&ioapic_lock, flags); | |
3918 | reg_01.raw = io_apic_read(ioapic, 1); | |
3919 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3920 | ||
3921 | return reg_01.bits.version; | |
3922 | } | |
54168ed7 | 3923 | #endif |
1da177e4 | 3924 | |
bdfe8ac1 | 3925 | static int __io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq, |
a2f809b0 | 3926 | int triggering, int polarity) |
1da177e4 | 3927 | { |
0b8f1efa YL |
3928 | struct irq_desc *desc; |
3929 | struct irq_cfg *cfg; | |
024154cf | 3930 | int node; |
0b8f1efa | 3931 | |
1da177e4 | 3932 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3933 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3934 | ioapic); |
3935 | return -EINVAL; | |
3936 | } | |
3937 | ||
024154cf YL |
3938 | if (dev) |
3939 | node = dev_to_node(dev); | |
3940 | else | |
3941 | node = cpu_to_node(boot_cpu_id); | |
3942 | ||
85ac16d0 | 3943 | desc = irq_to_desc_alloc_node(irq, node); |
0b8f1efa YL |
3944 | if (!desc) { |
3945 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3946 | return 0; | |
3947 | } | |
3948 | ||
1da177e4 LT |
3949 | /* |
3950 | * IRQs < 16 are already in the irq_2_pin[] map | |
3951 | */ | |
99d093d1 | 3952 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3953 | cfg = desc->chip_data; |
85ac16d0 | 3954 | add_pin_to_irq_node(cfg, node, ioapic, pin); |
0b8f1efa | 3955 | } |
1da177e4 | 3956 | |
3145e941 | 3957 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3958 | |
3959 | return 0; | |
3960 | } | |
3961 | ||
bdfe8ac1 YL |
3962 | static struct { |
3963 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); | |
3964 | } mp_ioapic_routing[MAX_IO_APICS]; | |
3965 | ||
3966 | int io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq, | |
3967 | int triggering, int polarity) | |
3968 | { | |
3969 | ||
3970 | /* | |
3971 | * Avoid pin reprogramming. PRTs typically include entries | |
3972 | * with redundant pin->gsi mappings (but unique PCI devices); | |
3973 | * we only program the IOAPIC on the first. | |
3974 | */ | |
3975 | if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) { | |
3976 | pr_debug("Pin %d-%d already programmed\n", | |
3977 | mp_ioapics[ioapic].apicid, pin); | |
3978 | return 0; | |
3979 | } | |
3980 | set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed); | |
3981 | ||
3982 | return __io_apic_set_pci_routing(dev, ioapic, pin, irq, | |
3983 | triggering, polarity); | |
3984 | } | |
54168ed7 | 3985 | |
61fd47e0 SL |
3986 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3987 | { | |
3988 | int i; | |
3989 | ||
3990 | if (skip_ioapic_setup) | |
3991 | return -1; | |
3992 | ||
3993 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
3994 | if (mp_irqs[i].irqtype == mp_INT && |
3995 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
3996 | break; |
3997 | if (i >= mp_irq_entries) | |
3998 | return -1; | |
3999 | ||
4000 | *trigger = irq_trigger(i); | |
4001 | *polarity = irq_polarity(i); | |
4002 | return 0; | |
4003 | } | |
4004 | ||
888ba6c6 | 4005 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4006 | |
497c9a19 YL |
4007 | /* |
4008 | * This function currently is only a helper for the i386 smp boot process where | |
4009 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 4010 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
4011 | */ |
4012 | #ifdef CONFIG_SMP | |
4013 | void __init setup_ioapic_dest(void) | |
4014 | { | |
4015 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4016 | struct irq_desc *desc; |
497c9a19 | 4017 | struct irq_cfg *cfg; |
22f65d31 | 4018 | const struct cpumask *mask; |
497c9a19 YL |
4019 | |
4020 | if (skip_ioapic_setup == 1) | |
4021 | return; | |
4022 | ||
4023 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4024 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4025 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4026 | if (irq_entry == -1) | |
4027 | continue; | |
4028 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4029 | ||
4030 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4031 | * when you have too many devices, because at that time only boot | |
4032 | * cpu is online. | |
4033 | */ | |
0b8f1efa YL |
4034 | desc = irq_to_desc(irq); |
4035 | cfg = desc->chip_data; | |
6c2e9403 | 4036 | if (!cfg->vector) { |
3145e941 | 4037 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4038 | irq_trigger(irq_entry), |
4039 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4040 | continue; |
4041 | ||
4042 | } | |
4043 | ||
4044 | /* | |
4045 | * Honour affinities which have been set in early boot | |
4046 | */ | |
6c2e9403 TG |
4047 | if (desc->status & |
4048 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4049 | mask = desc->affinity; |
6c2e9403 | 4050 | else |
fe402e1f | 4051 | mask = apic->target_cpus(); |
6c2e9403 | 4052 | |
6c2e9403 | 4053 | if (intr_remapping_enabled) |
3145e941 | 4054 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4055 | else |
3145e941 | 4056 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4057 | } |
4058 | ||
4059 | } | |
4060 | } | |
4061 | #endif | |
4062 | ||
54168ed7 IM |
4063 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4064 | ||
4065 | static struct resource *ioapic_resources; | |
4066 | ||
4067 | static struct resource * __init ioapic_setup_resources(void) | |
4068 | { | |
4069 | unsigned long n; | |
4070 | struct resource *res; | |
4071 | char *mem; | |
4072 | int i; | |
4073 | ||
4074 | if (nr_ioapics <= 0) | |
4075 | return NULL; | |
4076 | ||
4077 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4078 | n *= nr_ioapics; | |
4079 | ||
4080 | mem = alloc_bootmem(n); | |
4081 | res = (void *)mem; | |
4082 | ||
4083 | if (mem != NULL) { | |
4084 | mem += sizeof(struct resource) * nr_ioapics; | |
4085 | ||
4086 | for (i = 0; i < nr_ioapics; i++) { | |
4087 | res[i].name = mem; | |
4088 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4089 | sprintf(mem, "IOAPIC %u", i); | |
4090 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4091 | } | |
4092 | } | |
4093 | ||
4094 | ioapic_resources = res; | |
4095 | ||
4096 | return res; | |
4097 | } | |
54168ed7 | 4098 | |
f3294a33 YL |
4099 | void __init ioapic_init_mappings(void) |
4100 | { | |
4101 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4102 | struct resource *ioapic_res; |
d6c88a50 | 4103 | int i; |
f3294a33 | 4104 | |
54168ed7 | 4105 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4106 | for (i = 0; i < nr_ioapics; i++) { |
4107 | if (smp_found_config) { | |
b5ba7e6d | 4108 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4109 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4110 | if (!ioapic_phys) { |
4111 | printk(KERN_ERR | |
4112 | "WARNING: bogus zero IO-APIC " | |
4113 | "address found in MPTABLE, " | |
4114 | "disabling IO/APIC support!\n"); | |
4115 | smp_found_config = 0; | |
4116 | skip_ioapic_setup = 1; | |
4117 | goto fake_ioapic_page; | |
4118 | } | |
54168ed7 | 4119 | #endif |
f3294a33 | 4120 | } else { |
54168ed7 | 4121 | #ifdef CONFIG_X86_32 |
f3294a33 | 4122 | fake_ioapic_page: |
54168ed7 | 4123 | #endif |
f3294a33 | 4124 | ioapic_phys = (unsigned long) |
54168ed7 | 4125 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4126 | ioapic_phys = __pa(ioapic_phys); |
4127 | } | |
4128 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4129 | apic_printk(APIC_VERBOSE, |
4130 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4131 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4132 | idx++; |
54168ed7 | 4133 | |
54168ed7 IM |
4134 | if (ioapic_res != NULL) { |
4135 | ioapic_res->start = ioapic_phys; | |
4136 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4137 | ioapic_res++; | |
4138 | } | |
f3294a33 YL |
4139 | } |
4140 | } | |
4141 | ||
54168ed7 IM |
4142 | static int __init ioapic_insert_resources(void) |
4143 | { | |
4144 | int i; | |
4145 | struct resource *r = ioapic_resources; | |
4146 | ||
4147 | if (!r) { | |
04c93ce4 BZ |
4148 | if (nr_ioapics > 0) { |
4149 | printk(KERN_ERR | |
4150 | "IO APIC resources couldn't be allocated.\n"); | |
4151 | return -1; | |
4152 | } | |
4153 | return 0; | |
54168ed7 IM |
4154 | } |
4155 | ||
4156 | for (i = 0; i < nr_ioapics; i++) { | |
4157 | insert_resource(&iomem_resource, r); | |
4158 | r++; | |
4159 | } | |
4160 | ||
4161 | return 0; | |
4162 | } | |
4163 | ||
4164 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4165 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4166 | late_initcall(ioapic_insert_resources); |