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perf/x86: Add Intel LBR MSR definitions
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7
KW		 7
8#include <linux/stddef.h>
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/slab.h>
69c60c88 12#include <linux/export.h>
de0428a7
KW		 13
14#include <asm/hardirq.h>
15#include <asm/apic.h>
16
17#include "perf_event.h"
a7e3ed1e 18
f22f54f4 19/*
b622d644 20 * Intel PerfMon, used on Core and later.
f22f54f4 21 */
ec75a716 22static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4
PZ		 23{
24 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
25 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
26 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
27 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
28 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
29 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
30 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
9c1497ea 31 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 32};
33
5c543e3c 34static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 35{
36 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
37 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
38 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
39 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
40 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
41 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
42 EVENT_CONSTRAINT_END
43};
44
5c543e3c 45static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 46{
b622d644
PZ		 47 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
48 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 49 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 50 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
51 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
52 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
53 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
54 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
55 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
56 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
57 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 58 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 59 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
60 EVENT_CONSTRAINT_END
61};
62
5c543e3c 63static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 64{
b622d644
PZ		 65 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
66 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 67 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 68 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
69 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
70 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
71 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
72 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
73 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
74 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
75 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
76 EVENT_CONSTRAINT_END
77};
78
5c543e3c 79static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 80{
efc9f05d 81 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
a7e3ed1e
AK		 82 EVENT_EXTRA_END
83};
84
5c543e3c 85static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 86{
b622d644
PZ		 87 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
88 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 89 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 90 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
91 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
92 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 93 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 94 EVENT_CONSTRAINT_END
95};
96
5c543e3c 97static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 98{
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
b06b3d49 102 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 103 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
104 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
105 EVENT_CONSTRAINT_END
106};
107
5c543e3c 108static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 109{
efc9f05d
SE		 110 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
111 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
a7e3ed1e
AK		 112 EVENT_EXTRA_END
113};
114
0af3ac1f
AK		 115static struct event_constraint intel_v1_event_constraints[] __read_mostly =
116{
117 EVENT_CONSTRAINT_END
118};
119
5c543e3c 120static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 121{
b622d644
PZ		 122 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
123 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 124 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 125 EVENT_CONSTRAINT_END
126};
127
ee89cbc2
SE		 128static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
129 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
130 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
131 EVENT_EXTRA_END
132};
133
f22f54f4
PZ		 134static u64 intel_pmu_event_map(int hw_event)
135{
136 return intel_perfmon_event_map[hw_event];
137}
138
b06b3d49
LM		 139static __initconst const u64 snb_hw_cache_event_ids
140 [PERF_COUNT_HW_CACHE_MAX]
141 [PERF_COUNT_HW_CACHE_OP_MAX]
142 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
143{
144 [ C(L1D) ] = {
145 [ C(OP_READ) ] = {
146 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
147 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
148 },
149 [ C(OP_WRITE) ] = {
150 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
151 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
152 },
153 [ C(OP_PREFETCH) ] = {
154 [ C(RESULT_ACCESS) ] = 0x0,
155 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
156 },
157 },
158 [ C(L1I ) ] = {
159 [ C(OP_READ) ] = {
160 [ C(RESULT_ACCESS) ] = 0x0,
161 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
162 },
163 [ C(OP_WRITE) ] = {
164 [ C(RESULT_ACCESS) ] = -1,
165 [ C(RESULT_MISS) ] = -1,
166 },
167 [ C(OP_PREFETCH) ] = {
168 [ C(RESULT_ACCESS) ] = 0x0,
169 [ C(RESULT_MISS) ] = 0x0,
170 },
171 },
172 [ C(LL ) ] = {
b06b3d49 173 [ C(OP_READ) ] = {
63b6a675 174 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 175 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 176 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
177 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 178 },
179 [ C(OP_WRITE) ] = {
63b6a675 180 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 181 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 182 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
183 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 184 },
185 [ C(OP_PREFETCH) ] = {
63b6a675 186 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 187 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 188 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
189 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 190 },
191 },
192 [ C(DTLB) ] = {
193 [ C(OP_READ) ] = {
194 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
195 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
196 },
197 [ C(OP_WRITE) ] = {
198 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
199 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
200 },
201 [ C(OP_PREFETCH) ] = {
202 [ C(RESULT_ACCESS) ] = 0x0,
203 [ C(RESULT_MISS) ] = 0x0,
204 },
205 },
206 [ C(ITLB) ] = {
207 [ C(OP_READ) ] = {
208 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
209 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
210 },
211 [ C(OP_WRITE) ] = {
212 [ C(RESULT_ACCESS) ] = -1,
213 [ C(RESULT_MISS) ] = -1,
214 },
215 [ C(OP_PREFETCH) ] = {
216 [ C(RESULT_ACCESS) ] = -1,
217 [ C(RESULT_MISS) ] = -1,
218 },
219 },
220 [ C(BPU ) ] = {
221 [ C(OP_READ) ] = {
222 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
223 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
224 },
225 [ C(OP_WRITE) ] = {
226 [ C(RESULT_ACCESS) ] = -1,
227 [ C(RESULT_MISS) ] = -1,
228 },
229 [ C(OP_PREFETCH) ] = {
230 [ C(RESULT_ACCESS) ] = -1,
231 [ C(RESULT_MISS) ] = -1,
232 },
233 },
89d6c0b5
PZ		 234 [ C(NODE) ] = {
235 [ C(OP_READ) ] = {
236 [ C(RESULT_ACCESS) ] = -1,
237 [ C(RESULT_MISS) ] = -1,
238 },
239 [ C(OP_WRITE) ] = {
240 [ C(RESULT_ACCESS) ] = -1,
241 [ C(RESULT_MISS) ] = -1,
242 },
243 [ C(OP_PREFETCH) ] = {
244 [ C(RESULT_ACCESS) ] = -1,
245 [ C(RESULT_MISS) ] = -1,
246 },
247 },
248
b06b3d49
LM		 249};
250
caaa8be3 251static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 252 [PERF_COUNT_HW_CACHE_MAX]
253 [PERF_COUNT_HW_CACHE_OP_MAX]
254 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
255{
256 [ C(L1D) ] = {
257 [ C(OP_READ) ] = {
258 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
259 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
260 },
261 [ C(OP_WRITE) ] = {
262 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
263 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
264 },
265 [ C(OP_PREFETCH) ] = {
266 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
267 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
268 },
269 },
270 [ C(L1I ) ] = {
271 [ C(OP_READ) ] = {
272 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
273 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
274 },
275 [ C(OP_WRITE) ] = {
276 [ C(RESULT_ACCESS) ] = -1,
277 [ C(RESULT_MISS) ] = -1,
278 },
279 [ C(OP_PREFETCH) ] = {
280 [ C(RESULT_ACCESS) ] = 0x0,
281 [ C(RESULT_MISS) ] = 0x0,
282 },
283 },
284 [ C(LL ) ] = {
285 [ C(OP_READ) ] = {
63b6a675 286 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 287 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 288 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
289 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 290 },
e994d7d2
AK		 291 /*
292 * Use RFO, not WRITEBACK, because a write miss would typically occur
293 * on RFO.
294 */
f22f54f4 295 [ C(OP_WRITE) ] = {
63b6a675
PZ		 296 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
297 [ C(RESULT_ACCESS) ] = 0x01b7,
298 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 299 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 300 },
301 [ C(OP_PREFETCH) ] = {
63b6a675 302 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 303 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 304 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
305 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 306 },
307 },
308 [ C(DTLB) ] = {
309 [ C(OP_READ) ] = {
310 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
311 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
312 },
313 [ C(OP_WRITE) ] = {
314 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
315 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
316 },
317 [ C(OP_PREFETCH) ] = {
318 [ C(RESULT_ACCESS) ] = 0x0,
319 [ C(RESULT_MISS) ] = 0x0,
320 },
321 },
322 [ C(ITLB) ] = {
323 [ C(OP_READ) ] = {
324 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
325 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
326 },
327 [ C(OP_WRITE) ] = {
328 [ C(RESULT_ACCESS) ] = -1,
329 [ C(RESULT_MISS) ] = -1,
330 },
331 [ C(OP_PREFETCH) ] = {
332 [ C(RESULT_ACCESS) ] = -1,
333 [ C(RESULT_MISS) ] = -1,
334 },
335 },
336 [ C(BPU ) ] = {
337 [ C(OP_READ) ] = {
338 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
339 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
340 },
341 [ C(OP_WRITE) ] = {
342 [ C(RESULT_ACCESS) ] = -1,
343 [ C(RESULT_MISS) ] = -1,
344 },
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = -1,
347 [ C(RESULT_MISS) ] = -1,
348 },
349 },
89d6c0b5
PZ		 350 [ C(NODE) ] = {
351 [ C(OP_READ) ] = {
352 [ C(RESULT_ACCESS) ] = 0x01b7,
353 [ C(RESULT_MISS) ] = 0x01b7,
354 },
355 [ C(OP_WRITE) ] = {
356 [ C(RESULT_ACCESS) ] = 0x01b7,
357 [ C(RESULT_MISS) ] = 0x01b7,
358 },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = 0x01b7,
361 [ C(RESULT_MISS) ] = 0x01b7,
362 },
363 },
f22f54f4
PZ		 364};
365
e994d7d2 366/*
63b6a675
PZ		 367 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
368 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 369 */
370
63b6a675
PZ		 371#define NHM_DMND_DATA_RD (1 << 0)
372#define NHM_DMND_RFO (1 << 1)
373#define NHM_DMND_IFETCH (1 << 2)
374#define NHM_DMND_WB (1 << 3)
375#define NHM_PF_DATA_RD (1 << 4)
376#define NHM_PF_DATA_RFO (1 << 5)
377#define NHM_PF_IFETCH (1 << 6)
378#define NHM_OFFCORE_OTHER (1 << 7)
379#define NHM_UNCORE_HIT (1 << 8)
380#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
381#define NHM_OTHER_CORE_HITM (1 << 10)
382 /* reserved */
383#define NHM_REMOTE_CACHE_FWD (1 << 12)
384#define NHM_REMOTE_DRAM (1 << 13)
385#define NHM_LOCAL_DRAM (1 << 14)
386#define NHM_NON_DRAM (1 << 15)
387
388#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
389
390#define NHM_DMND_READ (NHM_DMND_DATA_RD)
391#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
392#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
393
394#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
395#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
396#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 397
398static __initconst const u64 nehalem_hw_cache_extra_regs
399 [PERF_COUNT_HW_CACHE_MAX]
400 [PERF_COUNT_HW_CACHE_OP_MAX]
401 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
402{
403 [ C(LL ) ] = {
404 [ C(OP_READ) ] = {
63b6a675
PZ		 405 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
406 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 407 },
408 [ C(OP_WRITE) ] = {
63b6a675
PZ		 409 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
410 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 411 },
412 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 413 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
414 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 415 },
89d6c0b5
PZ		 416 },
417 [ C(NODE) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_ALL_DRAM,
420 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE_DRAM,
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_ALL_DRAM,
424 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE_DRAM,
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_ALL_DRAM,
428 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE_DRAM,
429 },
430 },
e994d7d2
AK		 431};
432
caaa8be3 433static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 434 [PERF_COUNT_HW_CACHE_MAX]
435 [PERF_COUNT_HW_CACHE_OP_MAX]
436 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
437{
438 [ C(L1D) ] = {
439 [ C(OP_READ) ] = {
f4929bd3
PZ		 440 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
441 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 442 },
443 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 444 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
445 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 446 },
447 [ C(OP_PREFETCH) ] = {
448 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
449 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
450 },
451 },
452 [ C(L1I ) ] = {
453 [ C(OP_READ) ] = {
454 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
455 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
456 },
457 [ C(OP_WRITE) ] = {
458 [ C(RESULT_ACCESS) ] = -1,
459 [ C(RESULT_MISS) ] = -1,
460 },
461 [ C(OP_PREFETCH) ] = {
462 [ C(RESULT_ACCESS) ] = 0x0,
463 [ C(RESULT_MISS) ] = 0x0,
464 },
465 },
466 [ C(LL ) ] = {
467 [ C(OP_READ) ] = {
e994d7d2
AK		 468 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
469 [ C(RESULT_ACCESS) ] = 0x01b7,
470 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
471 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 472 },
e994d7d2
AK		 473 /*
474 * Use RFO, not WRITEBACK, because a write miss would typically occur
475 * on RFO.
476 */
f22f54f4 477 [ C(OP_WRITE) ] = {
e994d7d2
AK		 478 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
479 [ C(RESULT_ACCESS) ] = 0x01b7,
480 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
481 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 482 },
483 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 484 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
485 [ C(RESULT_ACCESS) ] = 0x01b7,
486 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
487 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 488 },
489 },
490 [ C(DTLB) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
493 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
497 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = 0x0,
501 [ C(RESULT_MISS) ] = 0x0,
502 },
503 },
504 [ C(ITLB) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
507 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = -1,
511 [ C(RESULT_MISS) ] = -1,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = -1,
515 [ C(RESULT_MISS) ] = -1,
516 },
517 },
518 [ C(BPU ) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
521 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = -1,
525 [ C(RESULT_MISS) ] = -1,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = -1,
529 [ C(RESULT_MISS) ] = -1,
530 },
531 },
89d6c0b5
PZ		 532 [ C(NODE) ] = {
533 [ C(OP_READ) ] = {
534 [ C(RESULT_ACCESS) ] = 0x01b7,
535 [ C(RESULT_MISS) ] = 0x01b7,
536 },
537 [ C(OP_WRITE) ] = {
538 [ C(RESULT_ACCESS) ] = 0x01b7,
539 [ C(RESULT_MISS) ] = 0x01b7,
540 },
541 [ C(OP_PREFETCH) ] = {
542 [ C(RESULT_ACCESS) ] = 0x01b7,
543 [ C(RESULT_MISS) ] = 0x01b7,
544 },
545 },
f22f54f4
PZ		 546};
547
caaa8be3 548static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 549 [PERF_COUNT_HW_CACHE_MAX]
550 [PERF_COUNT_HW_CACHE_OP_MAX]
551 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
552{
553 [ C(L1D) ] = {
554 [ C(OP_READ) ] = {
555 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
556 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
557 },
558 [ C(OP_WRITE) ] = {
559 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
560 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
561 },
562 [ C(OP_PREFETCH) ] = {
563 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
564 [ C(RESULT_MISS) ] = 0,
565 },
566 },
567 [ C(L1I ) ] = {
568 [ C(OP_READ) ] = {
569 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
570 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
571 },
572 [ C(OP_WRITE) ] = {
573 [ C(RESULT_ACCESS) ] = -1,
574 [ C(RESULT_MISS) ] = -1,
575 },
576 [ C(OP_PREFETCH) ] = {
577 [ C(RESULT_ACCESS) ] = 0,
578 [ C(RESULT_MISS) ] = 0,
579 },
580 },
581 [ C(LL ) ] = {
582 [ C(OP_READ) ] = {
583 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
584 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
585 },
586 [ C(OP_WRITE) ] = {
587 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
588 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
589 },
590 [ C(OP_PREFETCH) ] = {
591 [ C(RESULT_ACCESS) ] = 0,
592 [ C(RESULT_MISS) ] = 0,
593 },
594 },
595 [ C(DTLB) ] = {
596 [ C(OP_READ) ] = {
597 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
598 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
599 },
600 [ C(OP_WRITE) ] = {
601 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
602 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
603 },
604 [ C(OP_PREFETCH) ] = {
605 [ C(RESULT_ACCESS) ] = 0,
606 [ C(RESULT_MISS) ] = 0,
607 },
608 },
609 [ C(ITLB) ] = {
610 [ C(OP_READ) ] = {
611 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
612 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
613 },
614 [ C(OP_WRITE) ] = {
615 [ C(RESULT_ACCESS) ] = -1,
616 [ C(RESULT_MISS) ] = -1,
617 },
618 [ C(OP_PREFETCH) ] = {
619 [ C(RESULT_ACCESS) ] = -1,
620 [ C(RESULT_MISS) ] = -1,
621 },
622 },
623 [ C(BPU ) ] = {
624 [ C(OP_READ) ] = {
625 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
626 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
627 },
628 [ C(OP_WRITE) ] = {
629 [ C(RESULT_ACCESS) ] = -1,
630 [ C(RESULT_MISS) ] = -1,
631 },
632 [ C(OP_PREFETCH) ] = {
633 [ C(RESULT_ACCESS) ] = -1,
634 [ C(RESULT_MISS) ] = -1,
635 },
636 },
637};
638
caaa8be3 639static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 640 [PERF_COUNT_HW_CACHE_MAX]
641 [PERF_COUNT_HW_CACHE_OP_MAX]
642 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
643{
644 [ C(L1D) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
647 [ C(RESULT_MISS) ] = 0,
648 },
649 [ C(OP_WRITE) ] = {
650 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
651 [ C(RESULT_MISS) ] = 0,
652 },
653 [ C(OP_PREFETCH) ] = {
654 [ C(RESULT_ACCESS) ] = 0x0,
655 [ C(RESULT_MISS) ] = 0,
656 },
657 },
658 [ C(L1I ) ] = {
659 [ C(OP_READ) ] = {
660 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
661 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
662 },
663 [ C(OP_WRITE) ] = {
664 [ C(RESULT_ACCESS) ] = -1,
665 [ C(RESULT_MISS) ] = -1,
666 },
667 [ C(OP_PREFETCH) ] = {
668 [ C(RESULT_ACCESS) ] = 0,
669 [ C(RESULT_MISS) ] = 0,
670 },
671 },
672 [ C(LL ) ] = {
673 [ C(OP_READ) ] = {
674 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
675 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
676 },
677 [ C(OP_WRITE) ] = {
678 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
679 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
680 },
681 [ C(OP_PREFETCH) ] = {
682 [ C(RESULT_ACCESS) ] = 0,
683 [ C(RESULT_MISS) ] = 0,
684 },
685 },
686 [ C(DTLB) ] = {
687 [ C(OP_READ) ] = {
688 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
689 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
690 },
691 [ C(OP_WRITE) ] = {
692 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
693 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
694 },
695 [ C(OP_PREFETCH) ] = {
696 [ C(RESULT_ACCESS) ] = 0,
697 [ C(RESULT_MISS) ] = 0,
698 },
699 },
700 [ C(ITLB) ] = {
701 [ C(OP_READ) ] = {
702 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
703 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
704 },
705 [ C(OP_WRITE) ] = {
706 [ C(RESULT_ACCESS) ] = -1,
707 [ C(RESULT_MISS) ] = -1,
708 },
709 [ C(OP_PREFETCH) ] = {
710 [ C(RESULT_ACCESS) ] = -1,
711 [ C(RESULT_MISS) ] = -1,
712 },
713 },
714 [ C(BPU ) ] = {
715 [ C(OP_READ) ] = {
716 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
717 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
718 },
719 [ C(OP_WRITE) ] = {
720 [ C(RESULT_ACCESS) ] = -1,
721 [ C(RESULT_MISS) ] = -1,
722 },
723 [ C(OP_PREFETCH) ] = {
724 [ C(RESULT_ACCESS) ] = -1,
725 [ C(RESULT_MISS) ] = -1,
726 },
727 },
728};
729
f22f54f4
PZ		 730static void intel_pmu_disable_all(void)
731{
732 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
733
734 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
735
736 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
737 intel_pmu_disable_bts();
ca037701
PZ		 738
739 intel_pmu_pebs_disable_all();
caff2bef 740 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 741}
742
11164cd4 743static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 744{
745 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
746
d329527e
PZ		 747 intel_pmu_pebs_enable_all();
748 intel_pmu_lbr_enable_all();
144d31e6
GN		 749 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
750 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4
PZ		 751
752 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
753 struct perf_event *event =
754 cpuc->events[X86_PMC_IDX_FIXED_BTS];
755
756 if (WARN_ON_ONCE(!event))
757 return;
758
759 intel_pmu_enable_bts(event->hw.config);
760 }
761}
762
11164cd4
PZ		 763/*
764 * Workaround for:
765 * Intel Errata AAK100 (model 26)
766 * Intel Errata AAP53 (model 30)
40b91cd1 767 * Intel Errata BD53 (model 44)
11164cd4 768 *
351af072
ZY		 769 * The official story:
770 * These chips need to be 'reset' when adding counters by programming the
771 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
772 * in sequence on the same PMC or on different PMCs.
773 *
774 * In practise it appears some of these events do in fact count, and
775 * we need to programm all 4 events.
11164cd4 776 */
351af072 777static void intel_pmu_nhm_workaround(void)
11164cd4 778{
351af072
ZY		 779 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
780 static const unsigned long nhm_magic[4] = {
781 0x4300B5,
782 0x4300D2,
783 0x4300B1,
784 0x4300B1
785 };
786 struct perf_event *event;
787 int i;
11164cd4 788
351af072
ZY		 789 /*
790 * The Errata requires below steps:
791 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
792 * 2) Configure 4 PERFEVTSELx with the magic events and clear
793 * the corresponding PMCx;
794 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
795 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
796 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
797 */
11164cd4 798
351af072
ZY		 799 /*
800 * The real steps we choose are a little different from above.
801 * A) To reduce MSR operations, we don't run step 1) as they
802 * are already cleared before this function is called;
803 * B) Call x86_perf_event_update to save PMCx before configuring
804 * PERFEVTSELx with magic number;
805 * C) With step 5), we do clear only when the PERFEVTSELx is
806 * not used currently.
807 * D) Call x86_perf_event_set_period to restore PMCx;
808 */
11164cd4 809
351af072
ZY		 810 /* We always operate 4 pairs of PERF Counters */
811 for (i = 0; i < 4; i++) {
812 event = cpuc->events[i];
813 if (event)
814 x86_perf_event_update(event);
815 }
11164cd4 816
351af072
ZY		 817 for (i = 0; i < 4; i++) {
818 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
819 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
820 }
821
822 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
823 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 824
351af072
ZY		 825 for (i = 0; i < 4; i++) {
826 event = cpuc->events[i];
827
828 if (event) {
829 x86_perf_event_set_period(event);
31fa58af 830 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 831 ARCH_PERFMON_EVENTSEL_ENABLE);
832 } else
833 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 834 }
351af072
ZY		 835}
836
837static void intel_pmu_nhm_enable_all(int added)
838{
839 if (added)
840 intel_pmu_nhm_workaround();
11164cd4
PZ		 841 intel_pmu_enable_all(added);
842}
843
f22f54f4
PZ		 844static inline u64 intel_pmu_get_status(void)
845{
846 u64 status;
847
848 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
849
850 return status;
851}
852
853static inline void intel_pmu_ack_status(u64 ack)
854{
855 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
856}
857
ca037701 858static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 859{
aff3d91a 860 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4
PZ		 861 u64 ctrl_val, mask;
862
863 mask = 0xfULL << (idx * 4);
864
865 rdmsrl(hwc->config_base, ctrl_val);
866 ctrl_val &= ~mask;
7645a24c 867 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 868}
869
ca037701 870static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 871{
aff3d91a 872 struct hw_perf_event *hwc = &event->hw;
144d31e6 873 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a
PZ		 874
875 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 876 intel_pmu_disable_bts();
877 intel_pmu_drain_bts_buffer();
878 return;
879 }
880
144d31e6
GN		 881 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
882 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
883
f22f54f4 884 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 885 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 886 return;
887 }
888
aff3d91a 889 x86_pmu_disable_event(event);
ca037701 890
ab608344 891 if (unlikely(event->attr.precise_ip))
ef21f683 892 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 893}
894
ca037701 895static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 896{
aff3d91a 897 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4 898 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 899
900 /*
901 * Enable IRQ generation (0x8),
902 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
903 * if requested:
904 */
905 bits = 0x8ULL;
906 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
907 bits |= 0x2;
908 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
909 bits |= 0x1;
910
911 /*
912 * ANY bit is supported in v3 and up
913 */
914 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
915 bits |= 0x4;
916
917 bits <<= (idx * 4);
918 mask = 0xfULL << (idx * 4);
919
920 rdmsrl(hwc->config_base, ctrl_val);
921 ctrl_val &= ~mask;
922 ctrl_val |= bits;
7645a24c 923 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 924}
925
aff3d91a 926static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 927{
aff3d91a 928 struct hw_perf_event *hwc = &event->hw;
144d31e6 929 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a
PZ		 930
931 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
0a3aee0d 932 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 933 return;
934
935 intel_pmu_enable_bts(hwc->config);
936 return;
937 }
938
144d31e6
GN		 939 if (event->attr.exclude_host)
940 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
941 if (event->attr.exclude_guest)
942 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
943
f22f54f4 944 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 945 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 946 return;
947 }
948
ab608344 949 if (unlikely(event->attr.precise_ip))
ef21f683 950 intel_pmu_pebs_enable(event);
ca037701 951
31fa58af 952 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 953}
954
955/*
956 * Save and restart an expired event. Called by NMI contexts,
957 * so it has to be careful about preempting normal event ops:
958 */
de0428a7 959int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 960{
cc2ad4ba
PZ		 961 x86_perf_event_update(event);
962 return x86_perf_event_set_period(event);
f22f54f4
PZ		 963}
964
965static void intel_pmu_reset(void)
966{
0a3aee0d 967 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 968 unsigned long flags;
969 int idx;
970
948b1bb8 971 if (!x86_pmu.num_counters)
f22f54f4
PZ		 972 return;
973
974 local_irq_save(flags);
975
976 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
977
948b1bb8 978 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
41bf4989
RR		 979 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
980 checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
f22f54f4 981 }
948b1bb8 982 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
f22f54f4 983 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 984
f22f54f4
PZ		 985 if (ds)
986 ds->bts_index = ds->bts_buffer_base;
987
988 local_irq_restore(flags);
989}
990
991/*
992 * This handler is triggered by the local APIC, so the APIC IRQ handling
993 * rules apply:
994 */
995static int intel_pmu_handle_irq(struct pt_regs *regs)
996{
997 struct perf_sample_data data;
998 struct cpu_hw_events *cpuc;
999 int bit, loops;
2e556b5b 1000 u64 status;
b0b2072d 1001 int handled;
f22f54f4 1002
dc1d628a 1003 perf_sample_data_init(&data, 0);
f22f54f4
PZ		 1004
1005 cpuc = &__get_cpu_var(cpu_hw_events);
1006
2bce5dac
DZ		 1007 /*
1008 * Some chipsets need to unmask the LVTPC in a particular spot
1009 * inside the nmi handler. As a result, the unmasking was pushed
1010 * into all the nmi handlers.
1011 *
1012 * This handler doesn't seem to have any issues with the unmasking
1013 * so it was left at the top.
1014 */
1015 apic_write(APIC_LVTPC, APIC_DM_NMI);
1016
3fb2b8dd 1017 intel_pmu_disable_all();
b0b2072d 1018 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1019 status = intel_pmu_get_status();
1020 if (!status) {
11164cd4 1021 intel_pmu_enable_all(0);
b0b2072d 1022 return handled;
f22f54f4
PZ		 1023 }
1024
1025 loops = 0;
1026again:
2e556b5b 1027 intel_pmu_ack_status(status);
f22f54f4
PZ		 1028 if (++loops > 100) {
1029 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1030 perf_event_print_debug();
1031 intel_pmu_reset();
3fb2b8dd 1032 goto done;
f22f54f4
PZ		 1033 }
1034
1035 inc_irq_stat(apic_perf_irqs);
ca037701 1036
caff2bef
PZ		 1037 intel_pmu_lbr_read();
1038
ca037701
PZ		 1039 /*
1040 * PEBS overflow sets bit 62 in the global status register
1041 */
de725dec
PZ		 1042 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1043 handled++;
ca037701 1044 x86_pmu.drain_pebs(regs);
de725dec 1045 }
ca037701 1046
984b3f57 1047 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1048 struct perf_event *event = cpuc->events[bit];
1049
de725dec
PZ		 1050 handled++;
1051
f22f54f4
PZ		 1052 if (!test_bit(bit, cpuc->active_mask))
1053 continue;
1054
1055 if (!intel_pmu_save_and_restart(event))
1056 continue;
1057
1058 data.period = event->hw.last_period;
1059
a8b0ca17 1060 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1061 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1062 }
1063
f22f54f4
PZ		 1064 /*
1065 * Repeat if there is more work to be done:
1066 */
1067 status = intel_pmu_get_status();
1068 if (status)
1069 goto again;
1070
3fb2b8dd 1071done:
11164cd4 1072 intel_pmu_enable_all(0);
de725dec 1073 return handled;
f22f54f4
PZ		 1074}
1075
f22f54f4 1076static struct event_constraint *
ca037701 1077intel_bts_constraints(struct perf_event *event)
f22f54f4 1078{
ca037701
PZ		 1079 struct hw_perf_event *hwc = &event->hw;
1080 unsigned int hw_event, bts_event;
f22f54f4 1081
18a073a3
PZ		 1082 if (event->attr.freq)
1083 return NULL;
1084
ca037701
PZ		 1085 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1086 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1087
ca037701 1088 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1089 return &bts_constraint;
ca037701 1090
f22f54f4
PZ		 1091 return NULL;
1092}
1093
b79e8941
PZ		 1094static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
1095{
1096 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1097 return false;
1098
1099 if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
1100 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1101 event->hw.config |= 0x01bb;
1102 event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
1103 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1104 } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
1105 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1106 event->hw.config |= 0x01b7;
1107 event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
1108 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1109 }
1110
1111 if (event->hw.extra_reg.idx == orig_idx)
1112 return false;
1113
1114 return true;
1115}
1116
efc9f05d
SE		 1117/*
1118 * manage allocation of shared extra msr for certain events
1119 *
1120 * sharing can be:
1121 * per-cpu: to be shared between the various events on a single PMU
1122 * per-core: per-cpu + shared by HT threads
1123 */
a7e3ed1e 1124static struct event_constraint *
efc9f05d 1125__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b79e8941 1126 struct perf_event *event)
a7e3ed1e 1127{
efc9f05d 1128 struct event_constraint *c = &emptyconstraint;
b79e8941 1129 struct hw_perf_event_extra *reg = &event->hw.extra_reg;
a7e3ed1e 1130 struct er_account *era;
cd8a38d3 1131 unsigned long flags;
b79e8941 1132 int orig_idx = reg->idx;
a7e3ed1e 1133
efc9f05d 1134 /* already allocated shared msr */
cd8a38d3 1135 if (reg->alloc)
efc9f05d 1136 return &unconstrained;
a7e3ed1e 1137
b79e8941 1138again:
efc9f05d 1139 era = &cpuc->shared_regs->regs[reg->idx];
cd8a38d3
SE		 1140 /*
1141 * we use spin_lock_irqsave() to avoid lockdep issues when
1142 * passing a fake cpuc
1143 */
1144 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1145
1146 if (!atomic_read(&era->ref) || era->config == reg->config) {
1147
1148 /* lock in msr value */
1149 era->config = reg->config;
1150 era->reg = reg->reg;
1151
1152 /* one more user */
1153 atomic_inc(&era->ref);
1154
1155 /* no need to reallocate during incremental event scheduling */
1156 reg->alloc = 1;
a7e3ed1e
AK		 1157
1158 /*
efc9f05d
SE		 1159 * All events using extra_reg are unconstrained.
1160 * Avoids calling x86_get_event_constraints()
1161 *
1162 * Must revisit if extra_reg controlling events
1163 * ever have constraints. Worst case we go through
1164 * the regular event constraint table.
a7e3ed1e 1165 */
efc9f05d 1166 c = &unconstrained;
b79e8941 1167 } else if (intel_try_alt_er(event, orig_idx)) {
2e64694d 1168 raw_spin_unlock_irqrestore(&era->lock, flags);
b79e8941 1169 goto again;
a7e3ed1e 1170 }
cd8a38d3 1171 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1172
efc9f05d
SE		 1173 return c;
1174}
1175
1176static void
1177__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1178 struct hw_perf_event_extra *reg)
1179{
1180 struct er_account *era;
1181
1182 /*
1183 * only put constraint if extra reg was actually
1184 * allocated. Also takes care of event which do
1185 * not use an extra shared reg
1186 */
1187 if (!reg->alloc)
1188 return;
1189
1190 era = &cpuc->shared_regs->regs[reg->idx];
1191
1192 /* one fewer user */
1193 atomic_dec(&era->ref);
1194
1195 /* allocate again next time */
1196 reg->alloc = 0;
1197}
1198
1199static struct event_constraint *
1200intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1201 struct perf_event *event)
1202{
1203 struct event_constraint *c = NULL;
efc9f05d 1204
b79e8941
PZ		 1205 if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
1206 c = __intel_shared_reg_get_constraints(cpuc, event);
1207
efc9f05d 1208 return c;
a7e3ed1e
AK		 1209}
1210
de0428a7
KW		 1211struct event_constraint *
1212x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1213{
1214 struct event_constraint *c;
1215
1216 if (x86_pmu.event_constraints) {
1217 for_each_event_constraint(c, x86_pmu.event_constraints) {
1218 if ((event->hw.config & c->cmask) == c->code)
1219 return c;
1220 }
1221 }
1222
1223 return &unconstrained;
1224}
1225
f22f54f4
PZ		 1226static struct event_constraint *
1227intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1228{
1229 struct event_constraint *c;
1230
ca037701
PZ		 1231 c = intel_bts_constraints(event);
1232 if (c)
1233 return c;
1234
1235 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1236 if (c)
1237 return c;
1238
efc9f05d 1239 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1240 if (c)
1241 return c;
1242
f22f54f4
PZ		 1243 return x86_get_event_constraints(cpuc, event);
1244}
1245
efc9f05d
SE		 1246static void
1247intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1248 struct perf_event *event)
1249{
efc9f05d 1250 struct hw_perf_event_extra *reg;
a7e3ed1e 1251
efc9f05d
SE		 1252 reg = &event->hw.extra_reg;
1253 if (reg->idx != EXTRA_REG_NONE)
1254 __intel_shared_reg_put_constraints(cpuc, reg);
1255}
a7e3ed1e 1256
efc9f05d
SE		 1257static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1258 struct perf_event *event)
1259{
1260 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1261}
1262
b4cdc5c2
PZ		 1263static int intel_pmu_hw_config(struct perf_event *event)
1264{
1265 int ret = x86_pmu_hw_config(event);
1266
1267 if (ret)
1268 return ret;
1269
7639dae0
PZ		 1270 if (event->attr.precise_ip &&
1271 (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1272 /*
1273 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1274 * (0x003c) so that we can use it with PEBS.
1275 *
1276 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1277 * PEBS capable. However we can use INST_RETIRED.ANY_P
1278 * (0x00c0), which is a PEBS capable event, to get the same
1279 * count.
1280 *
1281 * INST_RETIRED.ANY_P counts the number of cycles that retires
1282 * CNTMASK instructions. By setting CNTMASK to a value (16)
1283 * larger than the maximum number of instructions that can be
1284 * retired per cycle (4) and then inverting the condition, we
1285 * count all cycles that retire 16 or less instructions, which
1286 * is every cycle.
1287 *
1288 * Thereby we gain a PEBS capable cycle counter.
1289 */
1290 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
1291
1292 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1293 event->hw.config = alt_config;
1294 }
1295
b4cdc5c2
PZ		 1296 if (event->attr.type != PERF_TYPE_RAW)
1297 return 0;
1298
1299 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1300 return 0;
1301
1302 if (x86_pmu.version < 3)
1303 return -EINVAL;
1304
1305 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1306 return -EACCES;
1307
1308 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1309
1310 return 0;
1311}
1312
144d31e6
GN		 1313struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1314{
1315 if (x86_pmu.guest_get_msrs)
1316 return x86_pmu.guest_get_msrs(nr);
1317 *nr = 0;
1318 return NULL;
1319}
1320EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1321
1322static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1323{
1324 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1325 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1326
1327 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1328 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1329 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1330
1331 *nr = 1;
1332 return arr;
1333}
1334
1335static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1336{
1337 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1338 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1339 int idx;
1340
1341 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1342 struct perf_event *event = cpuc->events[idx];
1343
1344 arr[idx].msr = x86_pmu_config_addr(idx);
1345 arr[idx].host = arr[idx].guest = 0;
1346
1347 if (!test_bit(idx, cpuc->active_mask))
1348 continue;
1349
1350 arr[idx].host = arr[idx].guest =
1351 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1352
1353 if (event->attr.exclude_host)
1354 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1355 else if (event->attr.exclude_guest)
1356 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1357 }
1358
1359 *nr = x86_pmu.num_counters;
1360 return arr;
1361}
1362
1363static void core_pmu_enable_event(struct perf_event *event)
1364{
1365 if (!event->attr.exclude_host)
1366 x86_pmu_enable_event(event);
1367}
1368
1369static void core_pmu_enable_all(int added)
1370{
1371 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1372 int idx;
1373
1374 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1375 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1376
1377 if (!test_bit(idx, cpuc->active_mask) ||
1378 cpuc->events[idx]->attr.exclude_host)
1379 continue;
1380
1381 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1382 }
1383}
1384
caaa8be3 1385static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1386 .name = "core",
1387 .handle_irq = x86_pmu_handle_irq,
1388 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1389 .enable_all = core_pmu_enable_all,
1390 .enable = core_pmu_enable_event,
f22f54f4 1391 .disable = x86_pmu_disable_event,
b4cdc5c2 1392 .hw_config = x86_pmu_hw_config,
a072738e 1393 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1394 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1395 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1396 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1397 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1398 .apic = 1,
1399 /*
1400 * Intel PMCs cannot be accessed sanely above 32 bit width,
1401 * so we install an artificial 1<<31 period regardless of
1402 * the generic event period:
1403 */
1404 .max_period = (1ULL << 31) - 1,
1405 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1406 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1407 .event_constraints = intel_core_event_constraints,
144d31e6 1408 .guest_get_msrs = core_guest_get_msrs,
f22f54f4
PZ		 1409};
1410
de0428a7 1411struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1412{
1413 struct intel_shared_regs *regs;
1414 int i;
1415
1416 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1417 GFP_KERNEL, cpu_to_node(cpu));
1418 if (regs) {
1419 /*
1420 * initialize the locks to keep lockdep happy
1421 */
1422 for (i = 0; i < EXTRA_REG_MAX; i++)
1423 raw_spin_lock_init(&regs->regs[i].lock);
1424
1425 regs->core_id = -1;
1426 }
1427 return regs;
1428}
1429
a7e3ed1e
AK		 1430static int intel_pmu_cpu_prepare(int cpu)
1431{
1432 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1433
efc9f05d 1434 if (!x86_pmu.extra_regs)
69092624
LM		 1435 return NOTIFY_OK;
1436
efc9f05d
SE		 1437 cpuc->shared_regs = allocate_shared_regs(cpu);
1438 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1439 return NOTIFY_BAD;
1440
a7e3ed1e
AK		 1441 return NOTIFY_OK;
1442}
1443
74846d35
PZ		 1444static void intel_pmu_cpu_starting(int cpu)
1445{
a7e3ed1e
AK		 1446 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1447 int core_id = topology_core_id(cpu);
1448 int i;
1449
69092624
LM		 1450 init_debug_store_on_cpu(cpu);
1451 /*
1452 * Deal with CPUs that don't clear their LBRs on power-up.
1453 */
1454 intel_pmu_lbr_reset();
1455
b79e8941 1456 if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
69092624
LM		 1457 return;
1458
a7e3ed1e 1459 for_each_cpu(i, topology_thread_cpumask(cpu)) {
efc9f05d 1460 struct intel_shared_regs *pc;
a7e3ed1e 1461
efc9f05d 1462 pc = per_cpu(cpu_hw_events, i).shared_regs;
a7e3ed1e 1463 if (pc && pc->core_id == core_id) {
7fdba1ca 1464 cpuc->kfree_on_online = cpuc->shared_regs;
efc9f05d 1465 cpuc->shared_regs = pc;
a7e3ed1e
AK		 1466 break;
1467 }
1468 }
1469
efc9f05d
SE		 1470 cpuc->shared_regs->core_id = core_id;
1471 cpuc->shared_regs->refcnt++;
74846d35
PZ		 1472}
1473
1474static void intel_pmu_cpu_dying(int cpu)
1475{
a7e3ed1e 1476 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1477 struct intel_shared_regs *pc;
a7e3ed1e 1478
efc9f05d 1479 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1480 if (pc) {
1481 if (pc->core_id == -1 || --pc->refcnt == 0)
1482 kfree(pc);
efc9f05d 1483 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1484 }
1485
74846d35
PZ		 1486 fini_debug_store_on_cpu(cpu);
1487}
1488
caaa8be3 1489static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1490 .name = "Intel",
1491 .handle_irq = intel_pmu_handle_irq,
1492 .disable_all = intel_pmu_disable_all,
1493 .enable_all = intel_pmu_enable_all,
1494 .enable = intel_pmu_enable_event,
1495 .disable = intel_pmu_disable_event,
b4cdc5c2 1496 .hw_config = intel_pmu_hw_config,
a072738e 1497 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1498 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1499 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1500 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1501 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1502 .apic = 1,
1503 /*
1504 * Intel PMCs cannot be accessed sanely above 32 bit width,
1505 * so we install an artificial 1<<31 period regardless of
1506 * the generic event period:
1507 */
1508 .max_period = (1ULL << 31) - 1,
3f6da390 1509 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1510 .put_event_constraints = intel_put_event_constraints,
3f6da390 1511
a7e3ed1e 1512 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1513 .cpu_starting = intel_pmu_cpu_starting,
1514 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1515 .guest_get_msrs = intel_guest_get_msrs,
f22f54f4
PZ		 1516};
1517
c1d6f42f 1518static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1519{
1520 /*
1521 * PEBS is unreliable due to:
1522 *
1523 * AJ67 - PEBS may experience CPL leaks
1524 * AJ68 - PEBS PMI may be delayed by one event
1525 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1526 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1527 *
1528 * AJ67 could be worked around by restricting the OS/USR flags.
1529 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1530 *
1531 * AJ106 could possibly be worked around by not allowing LBR
1532 * usage from PEBS, including the fixup.
1533 * AJ68 could possibly be worked around by always programming
ec75a716 1534 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1535 *
1536 * But taken together it might just make sense to not enable PEBS on
1537 * these chips.
1538 */
1539 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1540 x86_pmu.pebs = 0;
1541 x86_pmu.pebs_constraints = NULL;
1542}
1543
c1d6f42f 1544static __init void intel_sandybridge_quirk(void)
6a600a8b
PZ		 1545{
1546 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1547 x86_pmu.pebs = 0;
1548 x86_pmu.pebs_constraints = NULL;
1549}
1550
c1d6f42f
PZ		 1551static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1552 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1553 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1554 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1555 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1556 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1557 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1558 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 1559};
1560
c1d6f42f
PZ		 1561static __init void intel_arch_events_quirk(void)
1562{
1563 int bit;
1564
1565 /* disable event that reported as not presend by cpuid */
1566 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1567 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
1568 printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n",
1569 intel_arch_events_map[bit].name);
1570 }
1571}
1572
1573static __init void intel_nehalem_quirk(void)
1574{
1575 union cpuid10_ebx ebx;
1576
1577 ebx.full = x86_pmu.events_maskl;
1578 if (ebx.split.no_branch_misses_retired) {
1579 /*
1580 * Erratum AAJ80 detected, we work it around by using
1581 * the BR_MISP_EXEC.ANY event. This will over-count
1582 * branch-misses, but it's still much better than the
1583 * architectural event which is often completely bogus:
1584 */
1585 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1586 ebx.split.no_branch_misses_retired = 0;
1587 x86_pmu.events_maskl = ebx.full;
1588 printk(KERN_INFO "CPU erratum AAJ80 worked around\n");
1589 }
1590}
1591
de0428a7 1592__init int intel_pmu_init(void)
f22f54f4
PZ		 1593{
1594 union cpuid10_edx edx;
1595 union cpuid10_eax eax;
ffb871bc 1596 union cpuid10_ebx ebx;
f22f54f4 1597 unsigned int unused;
f22f54f4
PZ		 1598 int version;
1599
1600 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 1601 switch (boot_cpu_data.x86) {
1602 case 0x6:
1603 return p6_pmu_init();
1604 case 0xf:
1605 return p4_pmu_init();
1606 }
f22f54f4 1607 return -ENODEV;
f22f54f4
PZ		 1608 }
1609
1610 /*
1611 * Check whether the Architectural PerfMon supports
1612 * Branch Misses Retired hw_event or not.
1613 */
ffb871bc
GN		 1614 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1615 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 1616 return -ENODEV;
1617
1618 version = eax.split.version_id;
1619 if (version < 2)
1620 x86_pmu = core_pmu;
1621 else
1622 x86_pmu = intel_pmu;
1623
1624 x86_pmu.version = version;
948b1bb8
RR		 1625 x86_pmu.num_counters = eax.split.num_counters;
1626 x86_pmu.cntval_bits = eax.split.bit_width;
1627 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 1628
c1d6f42f
PZ		 1629 x86_pmu.events_maskl = ebx.full;
1630 x86_pmu.events_mask_len = eax.split.mask_length;
1631
f22f54f4
PZ		 1632 /*
1633 * Quirk: v2 perfmon does not report fixed-purpose events, so
1634 * assume at least 3 events:
1635 */
1636 if (version > 1)
948b1bb8 1637 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 1638
8db909a7
PZ		 1639 /*
1640 * v2 and above have a perf capabilities MSR
1641 */
1642 if (version > 1) {
1643 u64 capabilities;
1644
1645 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1646 x86_pmu.intel_cap.capabilities = capabilities;
1647 }
1648
ca037701
PZ		 1649 intel_ds_init();
1650
c1d6f42f
PZ		 1651 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
1652
f22f54f4
PZ		 1653 /*
1654 * Install the hw-cache-events table:
1655 */
1656 switch (boot_cpu_data.x86_model) {
1657 case 14: /* 65 nm core solo/duo, "Yonah" */
1658 pr_cont("Core events, ");
1659 break;
1660
1661 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 1662 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 1663 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1664 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1665 case 29: /* six-core 45 nm xeon "Dunnington" */
1666 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1667 sizeof(hw_cache_event_ids));
1668
caff2bef
PZ		 1669 intel_pmu_lbr_init_core();
1670
f22f54f4 1671 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 1672 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 1673 pr_cont("Core2 events, ");
1674 break;
1675
1676 case 26: /* 45 nm nehalem, "Bloomfield" */
1677 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 1678 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 1679 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1680 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1681 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1682 sizeof(hw_cache_extra_regs));
f22f54f4 1683
caff2bef
PZ		 1684 intel_pmu_lbr_init_nhm();
1685
f22f54f4 1686 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 1687 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 1688 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 1689 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 1690
91fc4cc0
IM		 1691 /* UOPS_ISSUED.STALLED_CYCLES */
1692 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1693 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8f622422 1694 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
94403f88 1695
c1d6f42f 1696 x86_add_quirk(intel_nehalem_quirk);
ec75a716 1697
11164cd4 1698 pr_cont("Nehalem events, ");
f22f54f4 1699 break;
caff2bef 1700
b622d644 1701 case 28: /* Atom */
f22f54f4
PZ		 1702 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1703 sizeof(hw_cache_event_ids));
1704
caff2bef
PZ		 1705 intel_pmu_lbr_init_atom();
1706
f22f54f4 1707 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 1708 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 1709 pr_cont("Atom events, ");
1710 break;
1711
1712 case 37: /* 32 nm nehalem, "Clarkdale" */
1713 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 1714 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 1715 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1716 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1717 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1718 sizeof(hw_cache_extra_regs));
f22f54f4 1719
caff2bef
PZ		 1720 intel_pmu_lbr_init_nhm();
1721
f22f54f4 1722 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 1723 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 1724 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 1725 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 1726 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039
IM		 1727
1728 /* UOPS_ISSUED.STALLED_CYCLES */
1729 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1730 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1731 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1732
f22f54f4
PZ		 1733 pr_cont("Westmere events, ");
1734 break;
b622d644 1735
b06b3d49 1736 case 42: /* SandyBridge */
c1d6f42f 1737 x86_add_quirk(intel_sandybridge_quirk);
a34668f6 1738 case 45: /* SandyBridge, "Romely-EP" */
b06b3d49
LM		 1739 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1740 sizeof(hw_cache_event_ids));
1741
1742 intel_pmu_lbr_init_nhm();
1743
1744 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 1745 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
ee89cbc2
SE		 1746 x86_pmu.extra_regs = intel_snb_extra_regs;
1747 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 1748 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1749 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23
LM		 1750
1751 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1752 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1753 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1754 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
1755
b06b3d49
LM		 1756 pr_cont("SandyBridge events, ");
1757 break;
1758
f22f54f4 1759 default:
0af3ac1f
AK		 1760 switch (x86_pmu.version) {
1761 case 1:
1762 x86_pmu.event_constraints = intel_v1_event_constraints;
1763 pr_cont("generic architected perfmon v1, ");
1764 break;
1765 default:
1766 /*
1767 * default constraints for v2 and up
1768 */
1769 x86_pmu.event_constraints = intel_gen_event_constraints;
1770 pr_cont("generic architected perfmon, ");
1771 break;
1772 }
f22f54f4 1773 }
ffb871bc 1774
f22f54f4
PZ		 1775 return 0;
1776}
Linux kernel - Deliverables
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