Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
9f5314fb | 8 | * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee JS |
9 | */ |
10 | ||
83f5d894 | 11 | #include <linux/kernel.h> |
ac23d4ee JS |
12 | #include <linux/threads.h> |
13 | #include <linux/cpumask.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ctype.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/bootmem.h> | |
20 | #include <linux/module.h> | |
0c81c746 | 21 | #include <linux/hardirq.h> |
ac23d4ee JS |
22 | #include <asm/smp.h> |
23 | #include <asm/ipi.h> | |
24 | #include <asm/genapic.h> | |
83f5d894 | 25 | #include <asm/pgtable.h> |
ac23d4ee JS |
26 | #include <asm/uv/uv_mmrs.h> |
27 | #include <asm/uv/uv_hub.h> | |
7019cc2d | 28 | #include <asm/uv/bios.h> |
ac23d4ee | 29 | |
1b9b89e7 YL |
30 | static enum uv_system_type uv_system_type; |
31 | ||
32 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |
33 | { | |
34 | if (!strcmp(oem_id, "SGI")) { | |
35 | if (!strcmp(oem_table_id, "UVL")) | |
36 | uv_system_type = UV_LEGACY_APIC; | |
37 | else if (!strcmp(oem_table_id, "UVX")) | |
38 | uv_system_type = UV_X2APIC; | |
39 | else if (!strcmp(oem_table_id, "UVH")) { | |
40 | uv_system_type = UV_NON_UNIQUE_APIC; | |
41 | return 1; | |
42 | } | |
43 | } | |
44 | return 0; | |
45 | } | |
46 | ||
47 | enum uv_system_type get_uv_system_type(void) | |
48 | { | |
49 | return uv_system_type; | |
50 | } | |
51 | ||
52 | int is_uv_system(void) | |
53 | { | |
54 | return uv_system_type != UV_NONE; | |
55 | } | |
56 | ||
ac23d4ee JS |
57 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
58 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
59 | ||
60 | struct uv_blade_info *uv_blade_info; | |
61 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
62 | ||
63 | short *uv_node_to_blade; | |
64 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
65 | ||
66 | short *uv_cpu_to_blade; | |
67 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
68 | ||
69 | short uv_possible_blades; | |
70 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
71 | ||
7019cc2d RA |
72 | unsigned long sn_rtc_cycles_per_second; |
73 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
74 | ||
ac23d4ee JS |
75 | /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ |
76 | ||
77 | static cpumask_t uv_target_cpus(void) | |
78 | { | |
79 | return cpumask_of_cpu(0); | |
80 | } | |
81 | ||
82 | static cpumask_t uv_vector_allocation_domain(int cpu) | |
83 | { | |
84 | cpumask_t domain = CPU_MASK_NONE; | |
85 | cpu_set(cpu, domain); | |
86 | return domain; | |
87 | } | |
88 | ||
89 | int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip) | |
90 | { | |
91 | unsigned long val; | |
9f5314fb | 92 | int pnode; |
ac23d4ee | 93 | |
9f5314fb | 94 | pnode = uv_apicid_to_pnode(phys_apicid); |
ac23d4ee JS |
95 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
96 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
97 | (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | | |
34d05591 | 98 | APIC_DM_INIT; |
9f5314fb | 99 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
100 | mdelay(10); |
101 | ||
102 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
103 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
104 | (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | | |
105 | APIC_DM_STARTUP; | |
9f5314fb | 106 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
ac23d4ee JS |
107 | return 0; |
108 | } | |
109 | ||
110 | static void uv_send_IPI_one(int cpu, int vector) | |
111 | { | |
34d05591 | 112 | unsigned long val, apicid, lapicid; |
9f5314fb | 113 | int pnode; |
ac23d4ee JS |
114 | |
115 | apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */ | |
34d05591 | 116 | lapicid = apicid & 0x3f; /* ZZZ macro needed */ |
9f5314fb | 117 | pnode = uv_apicid_to_pnode(apicid); |
ac23d4ee | 118 | val = |
34d05591 | 119 | (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid << |
ac23d4ee JS |
120 | UVH_IPI_INT_APIC_ID_SHFT) | |
121 | (vector << UVH_IPI_INT_VECTOR_SHFT); | |
9f5314fb | 122 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
ac23d4ee JS |
123 | } |
124 | ||
125 | static void uv_send_IPI_mask(cpumask_t mask, int vector) | |
126 | { | |
127 | unsigned int cpu; | |
128 | ||
129 | for (cpu = 0; cpu < NR_CPUS; ++cpu) | |
130 | if (cpu_isset(cpu, mask)) | |
131 | uv_send_IPI_one(cpu, vector); | |
132 | } | |
133 | ||
134 | static void uv_send_IPI_allbutself(int vector) | |
135 | { | |
136 | cpumask_t mask = cpu_online_map; | |
137 | ||
138 | cpu_clear(smp_processor_id(), mask); | |
139 | ||
140 | if (!cpus_empty(mask)) | |
141 | uv_send_IPI_mask(mask, vector); | |
142 | } | |
143 | ||
144 | static void uv_send_IPI_all(int vector) | |
145 | { | |
146 | uv_send_IPI_mask(cpu_online_map, vector); | |
147 | } | |
148 | ||
149 | static int uv_apic_id_registered(void) | |
150 | { | |
151 | return 1; | |
152 | } | |
153 | ||
277d1f58 | 154 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
155 | { |
156 | } | |
157 | ||
ac23d4ee JS |
158 | static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask) |
159 | { | |
160 | int cpu; | |
161 | ||
162 | /* | |
163 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
164 | * May as well be the first. | |
165 | */ | |
166 | cpu = first_cpu(cpumask); | |
167 | if ((unsigned)cpu < NR_CPUS) | |
168 | return per_cpu(x86_cpu_to_apicid, cpu); | |
169 | else | |
170 | return BAD_APICID; | |
171 | } | |
172 | ||
f910a9dc | 173 | static unsigned int get_apic_id(unsigned long x) |
0c81c746 SS |
174 | { |
175 | unsigned int id; | |
176 | ||
177 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
f910a9dc | 178 | id = x | __get_cpu_var(x2apic_extra_bits); |
0c81c746 SS |
179 | |
180 | return id; | |
181 | } | |
182 | ||
1b9b89e7 | 183 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
184 | { |
185 | unsigned long x; | |
186 | ||
187 | /* maskout x2apic_extra_bits ? */ | |
188 | x = id; | |
189 | return x; | |
190 | } | |
191 | ||
192 | static unsigned int uv_read_apic_id(void) | |
193 | { | |
194 | ||
195 | return get_apic_id(apic_read(APIC_ID)); | |
196 | } | |
197 | ||
ac23d4ee JS |
198 | static unsigned int phys_pkg_id(int index_msb) |
199 | { | |
0c81c746 | 200 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
201 | } |
202 | ||
203 | #ifdef ZZZ /* Needs x2apic patch */ | |
204 | static void uv_send_IPI_self(int vector) | |
205 | { | |
206 | apic_write(APIC_SELF_IPI, vector); | |
207 | } | |
208 | #endif | |
209 | ||
210 | struct genapic apic_x2apic_uv_x = { | |
211 | .name = "UV large system", | |
1b9b89e7 | 212 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
ac23d4ee JS |
213 | .int_delivery_mode = dest_Fixed, |
214 | .int_dest_mode = (APIC_DEST_PHYSICAL != 0), | |
215 | .target_cpus = uv_target_cpus, | |
216 | .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */ | |
217 | .apic_id_registered = uv_apic_id_registered, | |
5c520a67 | 218 | .init_apic_ldr = uv_init_apic_ldr, |
ac23d4ee JS |
219 | .send_IPI_all = uv_send_IPI_all, |
220 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
221 | .send_IPI_mask = uv_send_IPI_mask, | |
222 | /* ZZZ.send_IPI_self = uv_send_IPI_self, */ | |
223 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
224 | .phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */ | |
f910a9dc YL |
225 | .get_apic_id = get_apic_id, |
226 | .set_apic_id = set_apic_id, | |
227 | .apic_id_mask = (0xFFFFFFFFu), | |
ac23d4ee JS |
228 | }; |
229 | ||
9f5314fb | 230 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 231 | { |
9f5314fb | 232 | __get_cpu_var(x2apic_extra_bits) = (pnode << 6); |
ac23d4ee JS |
233 | } |
234 | ||
235 | /* | |
236 | * Called on boot cpu. | |
237 | */ | |
9f5314fb JS |
238 | static __init int boot_pnode_to_blade(int pnode) |
239 | { | |
240 | int blade; | |
241 | ||
242 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
243 | if (pnode == uv_blade_info[blade].pnode) | |
244 | return blade; | |
245 | BUG(); | |
246 | } | |
247 | ||
248 | struct redir_addr { | |
249 | unsigned long redirect; | |
250 | unsigned long alias; | |
251 | }; | |
252 | ||
253 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
254 | ||
255 | static __initdata struct redir_addr redir_addrs[] = { | |
256 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG}, | |
257 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG}, | |
258 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG}, | |
259 | }; | |
260 | ||
261 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
262 | { | |
263 | union uvh_si_alias0_overlay_config_u alias; | |
264 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; | |
265 | int i; | |
266 | ||
267 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
268 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
269 | if (alias.s.base == 0) { | |
270 | *size = (1UL << alias.s.m_alias); | |
271 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
272 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
273 | return; | |
274 | } | |
275 | } | |
276 | BUG(); | |
277 | } | |
278 | ||
83f5d894 JS |
279 | static __init void map_low_mmrs(void) |
280 | { | |
281 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
282 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
283 | } | |
284 | ||
285 | enum map_type {map_wb, map_uc}; | |
286 | ||
287 | static void map_high(char *id, unsigned long base, int shift, enum map_type map_type) | |
288 | { | |
289 | unsigned long bytes, paddr; | |
290 | ||
291 | paddr = base << shift; | |
292 | bytes = (1UL << shift); | |
293 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, | |
294 | paddr + bytes); | |
295 | if (map_type == map_uc) | |
296 | init_extra_mapping_uc(paddr, bytes); | |
297 | else | |
298 | init_extra_mapping_wb(paddr, bytes); | |
299 | ||
300 | } | |
301 | static __init void map_gru_high(int max_pnode) | |
302 | { | |
303 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
304 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
305 | ||
306 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
307 | if (gru.s.enable) | |
308 | map_high("GRU", gru.s.base, shift, map_wb); | |
309 | } | |
310 | ||
311 | static __init void map_config_high(int max_pnode) | |
312 | { | |
313 | union uvh_rh_gam_cfg_overlay_config_mmr_u cfg; | |
314 | int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
315 | ||
316 | cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR); | |
317 | if (cfg.s.enable) | |
318 | map_high("CONFIG", cfg.s.base, shift, map_uc); | |
319 | } | |
320 | ||
321 | static __init void map_mmr_high(int max_pnode) | |
322 | { | |
323 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
324 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
325 | ||
326 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
327 | if (mmr.s.enable) | |
328 | map_high("MMR", mmr.s.base, shift, map_uc); | |
329 | } | |
330 | ||
331 | static __init void map_mmioh_high(int max_pnode) | |
332 | { | |
333 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
334 | int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
335 | ||
336 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
337 | if (mmioh.s.enable) | |
338 | map_high("MMIOH", mmioh.s.base, shift, map_uc); | |
339 | } | |
340 | ||
7019cc2d RA |
341 | static __init void uv_rtc_init(void) |
342 | { | |
343 | long status, ticks_per_sec, drift; | |
344 | ||
345 | status = | |
346 | x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, | |
347 | &drift); | |
348 | if (status != 0 || ticks_per_sec < 100000) { | |
349 | printk(KERN_WARNING | |
350 | "unable to determine platform RTC clock frequency, " | |
351 | "guessing.\n"); | |
352 | /* BIOS gives wrong value for clock freq. so guess */ | |
353 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
354 | } else | |
355 | sn_rtc_cycles_per_second = ticks_per_sec; | |
356 | } | |
357 | ||
ac23d4ee JS |
358 | static __init void uv_system_init(void) |
359 | { | |
360 | union uvh_si_addr_map_config_u m_n_config; | |
9f5314fb JS |
361 | union uvh_node_id_u node_id; |
362 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
363 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; | |
83f5d894 | 364 | int max_pnode = 0; |
9f5314fb | 365 | unsigned long mmr_base, present; |
ac23d4ee | 366 | |
83f5d894 JS |
367 | map_low_mmrs(); |
368 | ||
ac23d4ee | 369 | m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG); |
9f5314fb JS |
370 | m_val = m_n_config.s.m_skt; |
371 | n_val = m_n_config.s.n_skt; | |
ac23d4ee JS |
372 | mmr_base = |
373 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
374 | ~UV_MMR_ENABLE; | |
375 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); | |
376 | ||
9f5314fb JS |
377 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
378 | uv_possible_blades += | |
379 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
ac23d4ee JS |
380 | printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); |
381 | ||
382 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
383 | uv_blade_info = alloc_bootmem_pages(bytes); | |
384 | ||
9f5314fb JS |
385 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
386 | ||
ac23d4ee JS |
387 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
388 | uv_node_to_blade = alloc_bootmem_pages(bytes); | |
389 | memset(uv_node_to_blade, 255, bytes); | |
390 | ||
391 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
392 | uv_cpu_to_blade = alloc_bootmem_pages(bytes); | |
393 | memset(uv_cpu_to_blade, 255, bytes); | |
394 | ||
9f5314fb JS |
395 | blade = 0; |
396 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
397 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
398 | for (j = 0; j < 64; j++) { | |
399 | if (!test_bit(j, &present)) | |
400 | continue; | |
401 | uv_blade_info[blade].pnode = (i * 64 + j); | |
402 | uv_blade_info[blade].nr_possible_cpus = 0; | |
ac23d4ee | 403 | uv_blade_info[blade].nr_online_cpus = 0; |
9f5314fb | 404 | blade++; |
ac23d4ee | 405 | } |
9f5314fb | 406 | } |
ac23d4ee | 407 | |
9f5314fb JS |
408 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
409 | gnode_upper = (((unsigned long)node_id.s.node_id) & | |
410 | ~((1 << n_val) - 1)) << m_val; | |
411 | ||
7019cc2d RA |
412 | uv_rtc_init(); |
413 | ||
9f5314fb JS |
414 | for_each_present_cpu(cpu) { |
415 | nid = cpu_to_node(cpu); | |
416 | pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu)); | |
417 | blade = boot_pnode_to_blade(pnode); | |
418 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
419 | uv_blade_info[blade].nr_possible_cpus++; | |
420 | ||
421 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; | |
422 | uv_cpu_hub_info(cpu)->lowmem_remap_top = | |
423 | lowmem_redir_base + lowmem_redir_size; | |
424 | uv_cpu_hub_info(cpu)->m_val = m_val; | |
425 | uv_cpu_hub_info(cpu)->n_val = m_val; | |
ac23d4ee JS |
426 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
427 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb JS |
428 | uv_cpu_hub_info(cpu)->pnode = pnode; |
429 | uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1; | |
430 | uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1; | |
431 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; | |
ac23d4ee JS |
432 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
433 | uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */ | |
ac23d4ee JS |
434 | uv_node_to_blade[nid] = blade; |
435 | uv_cpu_to_blade[cpu] = blade; | |
83f5d894 | 436 | max_pnode = max(pnode, max_pnode); |
ac23d4ee | 437 | |
83f5d894 | 438 | printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, " |
9f5314fb JS |
439 | "lcpu %d, blade %d\n", |
440 | cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid, | |
441 | lcpu, blade); | |
ac23d4ee | 442 | } |
83f5d894 JS |
443 | |
444 | map_gru_high(max_pnode); | |
445 | map_mmr_high(max_pnode); | |
446 | map_config_high(max_pnode); | |
447 | map_mmioh_high(max_pnode); | |
ac23d4ee JS |
448 | } |
449 | ||
450 | /* | |
451 | * Called on each cpu to initialize the per_cpu UV data area. | |
9f5314fb | 452 | * ZZZ hotplug not supported yet |
ac23d4ee JS |
453 | */ |
454 | void __cpuinit uv_cpu_init(void) | |
455 | { | |
456 | if (!uv_node_to_blade) | |
457 | uv_system_init(); | |
458 | ||
459 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
460 | ||
461 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
9f5314fb | 462 | set_x2apic_extra_bits(uv_hub_info->pnode); |
ac23d4ee | 463 | } |
1b9b89e7 YL |
464 | |
465 |