[deliverable/linux.git] / arch / x86 / kernel / genx2apic_uv_x.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV APIC functions (note: not an Intel compatible APIC)
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <asm/smp.h>
#include <asm/ipi.h>
#include <asm/genapic.h>
#include <asm/pgtable.h>
#include <asm/uv/uv_mmrs.h>
#include <asm/uv/uv_hub.h>

DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);

struct uv_blade_info *uv_blade_info;
EXPORT_SYMBOL_GPL(uv_blade_info);

short *uv_node_to_blade;
EXPORT_SYMBOL_GPL(uv_node_to_blade);

short *uv_cpu_to_blade;
EXPORT_SYMBOL_GPL(uv_cpu_to_blade);

short uv_possible_blades;
EXPORT_SYMBOL_GPL(uv_possible_blades);

/* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */

static cpumask_t uv_target_cpus(void)
{
	return cpumask_of_cpu(0);
}

static cpumask_t uv_vector_allocation_domain(int cpu)
{
	cpumask_t domain = CPU_MASK_NONE;
	cpu_set(cpu, domain);
	return domain;
}

int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
{
	unsigned long val;
	int pnode;

	pnode = uv_apicid_to_pnode(phys_apicid);
	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_INIT;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	mdelay(10);

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
	    (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
	    (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
	    APIC_DM_STARTUP;
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	return 0;
}

static void uv_send_IPI_one(int cpu, int vector)
{
	unsigned long val, apicid, lapicid;
	int pnode;

	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
	lapicid = apicid & 0x3f;		/* ZZZ macro needed */
	pnode = uv_apicid_to_pnode(apicid);
	val =
	    (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
					      UVH_IPI_INT_APIC_ID_SHFT) |
	    (vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

static void uv_send_IPI_mask(cpumask_t mask, int vector)
{
	unsigned int cpu;

	for (cpu = 0; cpu < NR_CPUS; ++cpu)
		if (cpu_isset(cpu, mask))
			uv_send_IPI_one(cpu, vector);
}

static void uv_send_IPI_allbutself(int vector)
{
	cpumask_t mask = cpu_online_map;

	cpu_clear(smp_processor_id(), mask);

	if (!cpus_empty(mask))
		uv_send_IPI_mask(mask, vector);
}

static void uv_send_IPI_all(int vector)
{
	uv_send_IPI_mask(cpu_online_map, vector);
}

static int uv_apic_id_registered(void)
{
	return 1;
}

static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;

	/*
	 * We're using fixed IRQ delivery, can only return one phys APIC ID.
	 * May as well be the first.
	 */
	cpu = first_cpu(cpumask);
	if ((unsigned)cpu < NR_CPUS)
		return per_cpu(x86_cpu_to_apicid, cpu);
	else
		return BAD_APICID;
}

static unsigned int phys_pkg_id(int index_msb)
{
	return GET_APIC_ID(read_apic_id()) >> index_msb;
}

#ifdef ZZZ		/* Needs x2apic patch */
static void uv_send_IPI_self(int vector)
{
	apic_write(APIC_SELF_IPI, vector);
}
#endif

struct genapic apic_x2apic_uv_x = {
	.name = "UV large system",
	.int_delivery_mode = dest_Fixed,
	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	.target_cpus = uv_target_cpus,
	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
	.apic_id_registered = uv_apic_id_registered,
	.send_IPI_all = uv_send_IPI_all,
	.send_IPI_allbutself = uv_send_IPI_allbutself,
	.send_IPI_mask = uv_send_IPI_mask,
	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
	.phys_pkg_id = phys_pkg_id,	/* Fixme ZZZ */
};

static __cpuinit void set_x2apic_extra_bits(int pnode)
{
	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
}

/*
 * Called on boot cpu.
 */
static __init int boot_pnode_to_blade(int pnode)
{
	int blade;

	for (blade = 0; blade < uv_num_possible_blades(); blade++)
		if (pnode == uv_blade_info[blade].pnode)
			return blade;
	BUG();
}

struct redir_addr {
	unsigned long redirect;
	unsigned long alias;
};

#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT

static __initdata struct redir_addr redir_addrs[] = {
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
};

static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
{
	union uvh_si_alias0_overlay_config_u alias;
	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	int i;

	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
		alias.v = uv_read_local_mmr(redir_addrs[i].alias);
		if (alias.s.base == 0) {
			*size = (1UL << alias.s.m_alias);
			redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
			*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
			return;
		}
	}
	BUG();
}

static __init void map_low_mmrs(void)
{
	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
}

enum map_type {map_wb, map_uc};

static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
{
	unsigned long bytes, paddr;

	paddr = base << shift;
	bytes = (1UL << shift);
	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	       					paddr + bytes);
	if (map_type == map_uc)
		init_extra_mapping_uc(paddr, bytes);
	else
		init_extra_mapping_wb(paddr, bytes);

}
static __init void map_gru_high(int max_pnode)
{
	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;

	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	if (gru.s.enable)
		map_high("GRU", gru.s.base, shift, map_wb);
}

static __init void map_config_high(int max_pnode)
{
	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;

	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	if (cfg.s.enable)
		map_high("CONFIG", cfg.s.base, shift, map_uc);
}

static __init void map_mmr_high(int max_pnode)
{
	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	if (mmr.s.enable)
		map_high("MMR", mmr.s.base, shift, map_uc);
}

static __init void map_mmioh_high(int max_pnode)
{
	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;

	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	if (mmioh.s.enable)
		map_high("MMIOH", mmioh.s.base, shift, map_uc);
}

static __init void uv_system_init(void)
{
	union uvh_si_addr_map_config_u m_n_config;
	union uvh_node_id_u node_id;
	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
	int max_pnode = 0;
	unsigned long mmr_base, present;

	map_low_mmrs();

	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
	m_val = m_n_config.s.m_skt;
	n_val = m_n_config.s.n_skt;
	mmr_base =
	    uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	    ~UV_MMR_ENABLE;
	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);

	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
		uv_possible_blades +=
		  hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());

	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	uv_blade_info = alloc_bootmem_pages(bytes);

	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);

	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	uv_node_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_node_to_blade, 255, bytes);

	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	memset(uv_cpu_to_blade, 255, bytes);

	blade = 0;
	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
		present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
		for (j = 0; j < 64; j++) {
			if (!test_bit(j, &present))
				continue;
			uv_blade_info[blade].pnode = (i * 64 + j);
			uv_blade_info[blade].nr_possible_cpus = 0;
			uv_blade_info[blade].nr_online_cpus = 0;
			blade++;
		}
	}

	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	gnode_upper = (((unsigned long)node_id.s.node_id) &
		       ~((1 << n_val) - 1)) << m_val;

	for_each_present_cpu(cpu) {
		nid = cpu_to_node(cpu);
		pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
		blade = boot_pnode_to_blade(pnode);
		lcpu = uv_blade_info[blade].nr_possible_cpus;
		uv_blade_info[blade].nr_possible_cpus++;

		uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
		uv_cpu_hub_info(cpu)->lowmem_remap_top =
					lowmem_redir_base + lowmem_redir_size;
		uv_cpu_hub_info(cpu)->m_val = m_val;
		uv_cpu_hub_info(cpu)->n_val = m_val;
		uv_cpu_hub_info(cpu)->numa_blade_id = blade;
		uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
		uv_cpu_hub_info(cpu)->pnode = pnode;
		uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
		uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
		uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
		uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
		uv_node_to_blade[nid] = blade;
		uv_cpu_to_blade[cpu] = blade;
		max_pnode = max(pnode, max_pnode);

		printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
			"lcpu %d, blade %d\n",
			cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
			lcpu, blade);
	}

	map_gru_high(max_pnode);
	map_mmr_high(max_pnode);
	map_config_high(max_pnode);
	map_mmioh_high(max_pnode);
}

/*
 * Called on each cpu to initialize the per_cpu UV data area.
 * 	ZZZ hotplug not supported yet
 */
void __cpuinit uv_cpu_init(void)
{
	if (!uv_node_to_blade)
		uv_system_init();

	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;

	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
		set_x2apic_extra_bits(uv_hub_info->pnode);
}
Commit	Line	Data
ac23d4ee JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV APIC functions (note: not an Intel compatible APIC)
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
ac23d4ee JS	9	*/
ac23d4ee JS	10
83f5d894	11	#include <linux/kernel.h>
ac23d4ee JS	12	#include <linux/threads.h>
	13	#include <linux/cpumask.h>
	14	#include <linux/string.h>
	15	#include <linux/kernel.h>
	16	#include <linux/ctype.h>
	17	#include <linux/init.h>
	18	#include <linux/sched.h>
	19	#include <linux/bootmem.h>
	20	#include <linux/module.h>
	21	#include <asm/smp.h>
	22	#include <asm/ipi.h>
	23	#include <asm/genapic.h>
83f5d894	24	#include <asm/pgtable.h>
ac23d4ee JS	25	#include <asm/uv/uv_mmrs.h>
	26	#include <asm/uv/uv_hub.h>
	27
	28	DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	29	EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
	30
	31	struct uv_blade_info *uv_blade_info;
	32	EXPORT_SYMBOL_GPL(uv_blade_info);
	33
	34	short *uv_node_to_blade;
	35	EXPORT_SYMBOL_GPL(uv_node_to_blade);
	36
	37	short *uv_cpu_to_blade;
	38	EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
	39
	40	short uv_possible_blades;
	41	EXPORT_SYMBOL_GPL(uv_possible_blades);
	42
	43	/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
	44
	45	static cpumask_t uv_target_cpus(void)
	46	{
	47	return cpumask_of_cpu(0);
	48	}
	49
	50	static cpumask_t uv_vector_allocation_domain(int cpu)
	51	{
	52	cpumask_t domain = CPU_MASK_NONE;
	53	cpu_set(cpu, domain);
	54	return domain;
	55	}
	56
	57	int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
	58	{
	59	unsigned long val;
9f5314fb	60	int pnode;
ac23d4ee	61
9f5314fb	62	pnode = uv_apicid_to_pnode(phys_apicid);
ac23d4ee JS	63	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	64	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	65	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
34d05591	66	APIC_DM_INIT;
9f5314fb	67	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591 JS	68	mdelay(10);
	69
	70	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	71	(phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) \|
	72	(((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) \|
	73	APIC_DM_STARTUP;
9f5314fb	74	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	75	return 0;
	76	}
	77
	78	static void uv_send_IPI_one(int cpu, int vector)
	79	{
34d05591	80	unsigned long val, apicid, lapicid;
9f5314fb	81	int pnode;
ac23d4ee JS	82
ac23d4ee JS	83	apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
34d05591	84	lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb	85	pnode = uv_apicid_to_pnode(apicid);
ac23d4ee	86	val =
34d05591	87	(1UL << UVH_IPI_INT_SEND_SHFT) \| (lapicid <<
ac23d4ee JS	88	UVH_IPI_INT_APIC_ID_SHFT) \|
ac23d4ee JS	89	(vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb	90	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
ac23d4ee JS	91	}
	92
	93	static void uv_send_IPI_mask(cpumask_t mask, int vector)
	94	{
	95	unsigned int cpu;
	96
	97	for (cpu = 0; cpu < NR_CPUS; ++cpu)
	98	if (cpu_isset(cpu, mask))
	99	uv_send_IPI_one(cpu, vector);
	100	}
	101
	102	static void uv_send_IPI_allbutself(int vector)
	103	{
	104	cpumask_t mask = cpu_online_map;
	105
	106	cpu_clear(smp_processor_id(), mask);
	107
	108	if (!cpus_empty(mask))
	109	uv_send_IPI_mask(mask, vector);
	110	}
	111
	112	static void uv_send_IPI_all(int vector)
	113	{
	114	uv_send_IPI_mask(cpu_online_map, vector);
	115	}
	116
	117	static int uv_apic_id_registered(void)
	118	{
	119	return 1;
	120	}
	121
	122	static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
	123	{
	124	int cpu;
	125
	126	/*
	127	* We're using fixed IRQ delivery, can only return one phys APIC ID.
	128	* May as well be the first.
	129	*/
	130	cpu = first_cpu(cpumask);
	131	if ((unsigned)cpu < NR_CPUS)
	132	return per_cpu(x86_cpu_to_apicid, cpu);
	133	else
	134	return BAD_APICID;
	135	}
	136
	137	static unsigned int phys_pkg_id(int index_msb)
	138	{
	139	return GET_APIC_ID(read_apic_id()) >> index_msb;
	140	}
	141
	142	#ifdef ZZZ /* Needs x2apic patch */
	143	static void uv_send_IPI_self(int vector)
	144	{
	145	apic_write(APIC_SELF_IPI, vector);
	146	}
	147	#endif
	148
	149	struct genapic apic_x2apic_uv_x = {
	150	.name = "UV large system",
	151	.int_delivery_mode = dest_Fixed,
	152	.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
	153	.target_cpus = uv_target_cpus,
	154	.vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
155	.apic_id_registered = uv_apic_id_registered,
156	.send_IPI_all = uv_send_IPI_all,
157	.send_IPI_allbutself = uv_send_IPI_allbutself,
158	.send_IPI_mask = uv_send_IPI_mask,
159	/* ZZZ.send_IPI_self = uv_send_IPI_self, */
160	.cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
161	.phys_pkg_id = phys_pkg_id, /* Fixme ZZZ */
162	};
163
9f5314fb	164	static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee	165	{
9f5314fb	166	__get_cpu_var(x2apic_extra_bits) = (pnode << 6);
ac23d4ee JS	167	}
	168
	169	/*
	170	* Called on boot cpu.
	171	*/
9f5314fb JS	172	static __init int boot_pnode_to_blade(int pnode)
	173	{
	174	int blade;
	175
	176	for (blade = 0; blade < uv_num_possible_blades(); blade++)
	177	if (pnode == uv_blade_info[blade].pnode)
	178	return blade;
	179	BUG();
	180	}
	181
	182	struct redir_addr {
	183	unsigned long redirect;
	184	unsigned long alias;
	185	};
	186
	187	#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
	188
	189	static __initdata struct redir_addr redir_addrs[] = {
	190	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
	191	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
	192	{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
	193	};
	194
	195	static __init void get_lowmem_redirect(unsigned long base, unsigned long size)
	196	{
	197	union uvh_si_alias0_overlay_config_u alias;
	198	union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
	199	int i;
	200
	201	for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
	202	alias.v = uv_read_local_mmr(redir_addrs[i].alias);
	203	if (alias.s.base == 0) {
	204	*size = (1UL << alias.s.m_alias);
	205	redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
	206	*base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
	207	return;
	208	}
	209	}
	210	BUG();
	211	}
	212
83f5d894 JS	213	static __init void map_low_mmrs(void)
	214	{
	215	init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
	216	init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
	217	}
	218
	219	enum map_type {map_wb, map_uc};
	220
	221	static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
	222	{
	223	unsigned long bytes, paddr;
	224
	225	paddr = base << shift;
	226	bytes = (1UL << shift);
	227	printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
	228	paddr + bytes);
	229	if (map_type == map_uc)
	230	init_extra_mapping_uc(paddr, bytes);
	231	else
	232	init_extra_mapping_wb(paddr, bytes);
	233
	234	}
	235	static __init void map_gru_high(int max_pnode)
	236	{
	237	union uvh_rh_gam_gru_overlay_config_mmr_u gru;
	238	int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
	239
	240	gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
	241	if (gru.s.enable)
	242	map_high("GRU", gru.s.base, shift, map_wb);
	243	}
	244
	245	static __init void map_config_high(int max_pnode)
	246	{
	247	union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
	248	int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
	249
	250	cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
	251	if (cfg.s.enable)
	252	map_high("CONFIG", cfg.s.base, shift, map_uc);
	253	}
	254
	255	static __init void map_mmr_high(int max_pnode)
	256	{
	257	union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
	258	int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
	259
	260	mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
	261	if (mmr.s.enable)
	262	map_high("MMR", mmr.s.base, shift, map_uc);
	263	}
	264
	265	static __init void map_mmioh_high(int max_pnode)
	266	{
	267	union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
	268	int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
	269
	270	mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
	271	if (mmioh.s.enable)
	272	map_high("MMIOH", mmioh.s.base, shift, map_uc);
	273	}
	274
ac23d4ee JS	275	static __init void uv_system_init(void)
	276	{
	277	union uvh_si_addr_map_config_u m_n_config;
9f5314fb JS	278	union uvh_node_id_u node_id;
	279	unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
	280	int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894	281	int max_pnode = 0;
9f5314fb	282	unsigned long mmr_base, present;
ac23d4ee	283
83f5d894 JS	284	map_low_mmrs();
83f5d894 JS	285
ac23d4ee	286	m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
9f5314fb JS	287	m_val = m_n_config.s.m_skt;
9f5314fb JS	288	n_val = m_n_config.s.n_skt;
ac23d4ee JS	289	mmr_base =
	290	uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
	291	~UV_MMR_ENABLE;
	292	printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
	293
9f5314fb JS	294	for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
	295	uv_possible_blades +=
	296	hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
ac23d4ee JS	297	printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
	298
	299	bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
	300	uv_blade_info = alloc_bootmem_pages(bytes);
	301
9f5314fb JS	302	get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
9f5314fb JS	303
ac23d4ee JS	304	bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
	305	uv_node_to_blade = alloc_bootmem_pages(bytes);
	306	memset(uv_node_to_blade, 255, bytes);
	307
	308	bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
	309	uv_cpu_to_blade = alloc_bootmem_pages(bytes);
	310	memset(uv_cpu_to_blade, 255, bytes);
	311
9f5314fb JS	312	blade = 0;
	313	for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
	314	present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
	315	for (j = 0; j < 64; j++) {
	316	if (!test_bit(j, &present))
	317	continue;
	318	uv_blade_info[blade].pnode = (i * 64 + j);
	319	uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee	320	uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb	321	blade++;
ac23d4ee	322	}
9f5314fb	323	}
ac23d4ee	324
9f5314fb JS	325	node_id.v = uv_read_local_mmr(UVH_NODE_ID);
	326	gnode_upper = (((unsigned long)node_id.s.node_id) &
	327	~((1 << n_val) - 1)) << m_val;
	328
	329	for_each_present_cpu(cpu) {
	330	nid = cpu_to_node(cpu);
	331	pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
	332	blade = boot_pnode_to_blade(pnode);
	333	lcpu = uv_blade_info[blade].nr_possible_cpus;
	334	uv_blade_info[blade].nr_possible_cpus++;
	335
	336	uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
	337	uv_cpu_hub_info(cpu)->lowmem_remap_top =
	338	lowmem_redir_base + lowmem_redir_size;
	339	uv_cpu_hub_info(cpu)->m_val = m_val;
	340	uv_cpu_hub_info(cpu)->n_val = m_val;
ac23d4ee JS	341	uv_cpu_hub_info(cpu)->numa_blade_id = blade;
ac23d4ee JS	342	uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
9f5314fb JS	343	uv_cpu_hub_info(cpu)->pnode = pnode;
	344	uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
	345	uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
	346	uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee JS	347	uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
ac23d4ee JS	348	uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
ac23d4ee JS	349	uv_node_to_blade[nid] = blade;
ac23d4ee JS	350	uv_cpu_to_blade[cpu] = blade;
83f5d894	351	max_pnode = max(pnode, max_pnode);
ac23d4ee	352
83f5d894	353	printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
9f5314fb JS	354	"lcpu %d, blade %d\n",
	355	cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
	356	lcpu, blade);
ac23d4ee	357	}
83f5d894 JS	358
	359	map_gru_high(max_pnode);
	360	map_mmr_high(max_pnode);
	361	map_config_high(max_pnode);
	362	map_mmioh_high(max_pnode);
ac23d4ee JS	363	}
	364
	365	/*
	366	* Called on each cpu to initialize the per_cpu UV data area.
9f5314fb	367	* ZZZ hotplug not supported yet
ac23d4ee JS	368	*/
	369	void __cpuinit uv_cpu_init(void)
	370	{
	371	if (!uv_node_to_blade)
	372	uv_system_init();
	373
	374	uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
	375
	376	if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
9f5314fb	377	set_x2apic_extra_bits(uv_hub_info->pnode);
ac23d4ee	378	}