Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1991, 1992 Linus Torvalds | |
4 | * | |
5 | * Enhanced CPU detection and feature setting code by Mike Jagdis | |
6 | * and Martin Mares, November 1997. | |
7 | */ | |
8 | ||
9 | .text | |
1da177e4 | 10 | #include <linux/threads.h> |
8b2f7fff | 11 | #include <linux/init.h> |
1da177e4 LT |
12 | #include <linux/linkage.h> |
13 | #include <asm/segment.h> | |
0341c14d JF |
14 | #include <asm/page_types.h> |
15 | #include <asm/pgtable_types.h> | |
1da177e4 LT |
16 | #include <asm/cache.h> |
17 | #include <asm/thread_info.h> | |
86feeaa8 | 18 | #include <asm/asm-offsets.h> |
1da177e4 | 19 | #include <asm/setup.h> |
551889a6 | 20 | #include <asm/processor-flags.h> |
8a50e513 | 21 | #include <asm/msr-index.h> |
cd4d09ec | 22 | #include <asm/cpufeatures.h> |
60a5317f | 23 | #include <asm/percpu.h> |
4c5023a3 | 24 | #include <asm/nops.h> |
fb148d83 | 25 | #include <asm/bootparam.h> |
784d5699 | 26 | #include <asm/export.h> |
551889a6 IC |
27 | |
28 | /* Physical address */ | |
29 | #define pa(X) ((X) - __PAGE_OFFSET) | |
1da177e4 LT |
30 | |
31 | /* | |
32 | * References to members of the new_cpu_data structure. | |
33 | */ | |
34 | ||
35 | #define X86 new_cpu_data+CPUINFO_x86 | |
36 | #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor | |
37 | #define X86_MODEL new_cpu_data+CPUINFO_x86_model | |
38 | #define X86_MASK new_cpu_data+CPUINFO_x86_mask | |
39 | #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math | |
40 | #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level | |
41 | #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability | |
42 | #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id | |
43 | ||
44 | /* | |
c090f532 JF |
45 | * This is how much memory in addition to the memory covered up to |
46 | * and including _end we need mapped initially. | |
9ce8c2ed | 47 | * We need: |
2bd2753f YL |
48 | * (KERNEL_IMAGE_SIZE/4096) / 1024 pages (worst case, non PAE) |
49 | * (KERNEL_IMAGE_SIZE/4096) / 512 + 4 pages (worst case for PAE) | |
1da177e4 LT |
50 | * |
51 | * Modulo rounding, each megabyte assigned here requires a kilobyte of | |
52 | * memory, which is currently unreclaimed. | |
53 | * | |
54 | * This should be a multiple of a page. | |
2bd2753f YL |
55 | * |
56 | * KERNEL_IMAGE_SIZE should be greater than pa(_end) | |
57 | * and small than max_low_pfn, otherwise will waste some page table entries | |
1da177e4 | 58 | */ |
1da177e4 | 59 | |
9ce8c2ed | 60 | #if PTRS_PER_PMD > 1 |
c090f532 | 61 | #define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD) |
9ce8c2ed | 62 | #else |
c090f532 | 63 | #define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD) |
9ce8c2ed | 64 | #endif |
9ce8c2ed | 65 | |
04c17341 BP |
66 | /* |
67 | * Number of possible pages in the lowmem region. | |
68 | * | |
69 | * We shift 2 by 31 instead of 1 by 32 to the left in order to avoid a | |
70 | * gas warning about overflowing shift count when gas has been compiled | |
71 | * with only a host target support using a 32-bit type for internal | |
72 | * representation. | |
73 | */ | |
74 | LOWMEM_PAGES = (((2<<31) - __PAGE_OFFSET) >> PAGE_SHIFT) | |
75 | ||
c090f532 | 76 | /* Enough space to fit pagetables for the low memory linear map */ |
147dd561 | 77 | MAPPING_BEYOND_END = PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT |
c090f532 JF |
78 | |
79 | /* | |
80 | * Worst-case size of the kernel mapping we need to make: | |
147dd561 PA |
81 | * a relocatable kernel can live anywhere in lowmem, so we need to be able |
82 | * to map all of lowmem. | |
c090f532 | 83 | */ |
147dd561 | 84 | KERNEL_PAGES = LOWMEM_PAGES |
c090f532 | 85 | |
7bf04be8 | 86 | INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE |
2bd2753f | 87 | RESERVE_BRK(pagetables, INIT_MAP_SIZE) |
796216a5 | 88 | |
1da177e4 LT |
89 | /* |
90 | * 32-bit kernel entrypoint; only used by the boot CPU. On entry, | |
91 | * %esi points to the real-mode code as a 32-bit pointer. | |
92 | * CS and DS must be 4 GB flat segments, but we don't depend on | |
93 | * any particular GDT layout, because we load our own as soon as we | |
94 | * can. | |
95 | */ | |
4ae59b91 | 96 | __HEAD |
1da177e4 | 97 | ENTRY(startup_32) |
11d4c3f9 PA |
98 | movl pa(stack_start),%ecx |
99 | ||
a24e7851 RR |
100 | /* test KEEP_SEGMENTS flag to see if the bootloader is asking |
101 | us to not reload segments */ | |
fb148d83 | 102 | testb $KEEP_SEGMENTS, BP_loadflags(%esi) |
a24e7851 | 103 | jnz 2f |
1da177e4 LT |
104 | |
105 | /* | |
106 | * Set segments to known values. | |
107 | */ | |
551889a6 | 108 | lgdt pa(boot_gdt_descr) |
1da177e4 LT |
109 | movl $(__BOOT_DS),%eax |
110 | movl %eax,%ds | |
111 | movl %eax,%es | |
112 | movl %eax,%fs | |
113 | movl %eax,%gs | |
11d4c3f9 | 114 | movl %eax,%ss |
a24e7851 | 115 | 2: |
11d4c3f9 | 116 | leal -__PAGE_OFFSET(%ecx),%esp |
1da177e4 LT |
117 | |
118 | /* | |
119 | * Clear BSS first so that there are no surprises... | |
1da177e4 | 120 | */ |
a24e7851 | 121 | cld |
1da177e4 | 122 | xorl %eax,%eax |
551889a6 IC |
123 | movl $pa(__bss_start),%edi |
124 | movl $pa(__bss_stop),%ecx | |
1da177e4 LT |
125 | subl %edi,%ecx |
126 | shrl $2,%ecx | |
127 | rep ; stosl | |
484b90c4 VG |
128 | /* |
129 | * Copy bootup parameters out of the way. | |
130 | * Note: %esi still has the pointer to the real-mode data. | |
131 | * With the kexec as boot loader, parameter segment might be loaded beyond | |
132 | * kernel image and might not even be addressable by early boot page tables. | |
133 | * (kexec on panic case). Hence copy out the parameters before initializing | |
134 | * page tables. | |
135 | */ | |
551889a6 | 136 | movl $pa(boot_params),%edi |
484b90c4 VG |
137 | movl $(PARAM_SIZE/4),%ecx |
138 | cld | |
139 | rep | |
140 | movsl | |
551889a6 | 141 | movl pa(boot_params) + NEW_CL_POINTER,%esi |
484b90c4 | 142 | andl %esi,%esi |
b595076a | 143 | jz 1f # No command line |
551889a6 | 144 | movl $pa(boot_command_line),%edi |
484b90c4 VG |
145 | movl $(COMMAND_LINE_SIZE/4),%ecx |
146 | rep | |
147 | movsl | |
148 | 1: | |
1da177e4 | 149 | |
dc3119e7 | 150 | #ifdef CONFIG_OLPC |
fd699c76 AS |
151 | /* save OFW's pgdir table for later use when calling into OFW */ |
152 | movl %cr3, %eax | |
153 | movl %eax, pa(olpc_ofw_pgd) | |
154 | #endif | |
155 | ||
fe055896 | 156 | #ifdef CONFIG_MICROCODE |
63b553c6 FY |
157 | /* Early load ucode on BSP. */ |
158 | call load_ucode_bsp | |
159 | #endif | |
160 | ||
1da177e4 LT |
161 | /* |
162 | * Initialize page tables. This creates a PDE and a set of page | |
2bd2753f | 163 | * tables, which are located immediately beyond __brk_base. The variable |
ccf3fe02 | 164 | * _brk_end is set up to point to the first "safe" location. |
1da177e4 | 165 | * Mappings are created both at virtual address 0 (identity mapping) |
2bd2753f | 166 | * and PAGE_OFFSET for up to _end. |
1da177e4 | 167 | */ |
551889a6 IC |
168 | #ifdef CONFIG_X86_PAE |
169 | ||
170 | /* | |
b40827fa BP |
171 | * In PAE mode initial_page_table is statically defined to contain |
172 | * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3 | |
173 | * entries). The identity mapping is handled by pointing two PGD entries | |
174 | * to the first kernel PMD. | |
551889a6 | 175 | * |
b40827fa | 176 | * Note the upper half of each PMD or PTE are always zero at this stage. |
551889a6 IC |
177 | */ |
178 | ||
86b2b70e | 179 | #define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */ |
551889a6 IC |
180 | |
181 | xorl %ebx,%ebx /* %ebx is kept at zero */ | |
182 | ||
ccf3fe02 | 183 | movl $pa(__brk_base), %edi |
b40827fa | 184 | movl $pa(initial_pg_pmd), %edx |
b2bc2731 | 185 | movl $PTE_IDENT_ATTR, %eax |
551889a6 | 186 | 10: |
b2bc2731 | 187 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */ |
551889a6 IC |
188 | movl %ecx,(%edx) /* Store PMD entry */ |
189 | /* Upper half already zero */ | |
190 | addl $8,%edx | |
191 | movl $512,%ecx | |
192 | 11: | |
193 | stosl | |
194 | xchgl %eax,%ebx | |
195 | stosl | |
196 | xchgl %eax,%ebx | |
197 | addl $0x1000,%eax | |
198 | loop 11b | |
199 | ||
200 | /* | |
c090f532 | 201 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 202 | */ |
c090f532 | 203 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
551889a6 IC |
204 | cmpl %ebp,%eax |
205 | jb 10b | |
206 | 1: | |
ccf3fe02 JF |
207 | addl $__PAGE_OFFSET, %edi |
208 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
209 | shrl $12, %eax |
210 | movl %eax, pa(max_pfn_mapped) | |
551889a6 IC |
211 | |
212 | /* Do early initialization of the fixmap area */ | |
b40827fa BP |
213 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
214 | movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8) | |
551889a6 IC |
215 | #else /* Not PAE */ |
216 | ||
217 | page_pde_offset = (__PAGE_OFFSET >> 20); | |
218 | ||
ccf3fe02 | 219 | movl $pa(__brk_base), %edi |
b40827fa | 220 | movl $pa(initial_page_table), %edx |
b2bc2731 | 221 | movl $PTE_IDENT_ATTR, %eax |
1da177e4 | 222 | 10: |
b2bc2731 | 223 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */ |
1da177e4 LT |
224 | movl %ecx,(%edx) /* Store identity PDE entry */ |
225 | movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */ | |
226 | addl $4,%edx | |
227 | movl $1024, %ecx | |
228 | 11: | |
229 | stosl | |
230 | addl $0x1000,%eax | |
231 | loop 11b | |
551889a6 | 232 | /* |
c090f532 | 233 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 234 | */ |
c090f532 | 235 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
1da177e4 LT |
236 | cmpl %ebp,%eax |
237 | jb 10b | |
ccf3fe02 JF |
238 | addl $__PAGE_OFFSET, %edi |
239 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
240 | shrl $12, %eax |
241 | movl %eax, pa(max_pfn_mapped) | |
17d57a92 | 242 | |
551889a6 | 243 | /* Do early initialization of the fixmap area */ |
b40827fa BP |
244 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
245 | movl %eax,pa(initial_page_table+0xffc) | |
551889a6 | 246 | #endif |
d50d8fe1 RR |
247 | |
248 | #ifdef CONFIG_PARAVIRT | |
249 | /* This is can only trip for a broken bootloader... */ | |
250 | cmpw $0x207, pa(boot_params + BP_version) | |
251 | jb default_entry | |
252 | ||
253 | /* Paravirt-compatible boot parameters. Look to see what architecture | |
254 | we're booting under. */ | |
255 | movl pa(boot_params + BP_hardware_subarch), %eax | |
256 | cmpl $num_subarch_entries, %eax | |
257 | jae bad_subarch | |
258 | ||
259 | movl pa(subarch_entries)(,%eax,4), %eax | |
260 | subl $__PAGE_OFFSET, %eax | |
261 | jmp *%eax | |
262 | ||
263 | bad_subarch: | |
264 | WEAK(lguest_entry) | |
265 | WEAK(xen_entry) | |
266 | /* Unknown implementation; there's really | |
267 | nothing we can do at this point. */ | |
268 | ud2a | |
269 | ||
270 | __INITDATA | |
271 | ||
272 | subarch_entries: | |
273 | .long default_entry /* normal x86/PC */ | |
274 | .long lguest_entry /* lguest hypervisor */ | |
275 | .long xen_entry /* Xen hypervisor */ | |
276 | .long default_entry /* Moorestown MID */ | |
277 | num_subarch_entries = (. - subarch_entries) / 4 | |
278 | .previous | |
279 | #else | |
280 | jmp default_entry | |
281 | #endif /* CONFIG_PARAVIRT */ | |
282 | ||
3e2a0cc3 FY |
283 | #ifdef CONFIG_HOTPLUG_CPU |
284 | /* | |
285 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
286 | * up already except stack. We just set up stack here. Then call | |
287 | * start_secondary(). | |
288 | */ | |
289 | ENTRY(start_cpu0) | |
290 | movl stack_start, %ecx | |
291 | movl %ecx, %esp | |
292 | jmp *(initial_code) | |
293 | ENDPROC(start_cpu0) | |
294 | #endif | |
295 | ||
1da177e4 LT |
296 | /* |
297 | * Non-boot CPU entry point; entered from trampoline.S | |
298 | * We can't lgdt here, because lgdt itself uses a data segment, but | |
52de74dd | 299 | * we know the trampoline has already loaded the boot_gdt for us. |
f8657e1b VG |
300 | * |
301 | * If cpu hotplug is not supported then this code can go in init section | |
302 | * which will be freed later | |
1da177e4 LT |
303 | */ |
304 | ENTRY(startup_32_smp) | |
305 | cld | |
306 | movl $(__BOOT_DS),%eax | |
307 | movl %eax,%ds | |
308 | movl %eax,%es | |
309 | movl %eax,%fs | |
310 | movl %eax,%gs | |
11d4c3f9 PA |
311 | movl pa(stack_start),%ecx |
312 | movl %eax,%ss | |
313 | leal -__PAGE_OFFSET(%ecx),%esp | |
48927bbb | 314 | |
fe055896 | 315 | #ifdef CONFIG_MICROCODE |
63b553c6 FY |
316 | /* Early load ucode on AP. */ |
317 | call load_ucode_ap | |
318 | #endif | |
319 | ||
d50d8fe1 | 320 | default_entry: |
021ef050 PA |
321 | #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ |
322 | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ | |
323 | X86_CR0_PG) | |
324 | movl $(CR0_STATE & ~X86_CR0_PG),%eax | |
325 | movl %eax,%cr0 | |
326 | ||
1da177e4 | 327 | /* |
9efb58de BP |
328 | * We want to start out with EFLAGS unambiguously cleared. Some BIOSes leave |
329 | * bits like NT set. This would confuse the debugger if this code is traced. So | |
330 | * initialize them properly now before switching to protected mode. That means | |
331 | * DF in particular (even though we have cleared it earlier after copying the | |
332 | * command line) because GCC expects it. | |
333 | */ | |
334 | pushl $0 | |
335 | popfl | |
336 | ||
337 | /* | |
338 | * New page tables may be in 4Mbyte page mode and may be using the global pages. | |
1da177e4 | 339 | * |
9efb58de BP |
340 | * NOTE! If we are on a 486 we may have no cr4 at all! Specifically, cr4 exists |
341 | * if and only if CPUID exists and has flags other than the FPU flag set. | |
1da177e4 | 342 | */ |
9efb58de | 343 | movl $-1,pa(X86_CPUID) # preset CPUID level |
5a5a51db PA |
344 | movl $X86_EFLAGS_ID,%ecx |
345 | pushl %ecx | |
9efb58de | 346 | popfl # set EFLAGS=ID |
5a5a51db | 347 | pushfl |
9efb58de BP |
348 | popl %eax # get EFLAGS |
349 | testl $X86_EFLAGS_ID,%eax # did EFLAGS.ID remained set? | |
5e2a044d | 350 | jz enable_paging # hw disallowed setting of ID bit |
9efb58de BP |
351 | # which means no CPUID and no CR4 |
352 | ||
353 | xorl %eax,%eax | |
354 | cpuid | |
355 | movl %eax,pa(X86_CPUID) # save largest std CPUID function | |
5a5a51db | 356 | |
6662c34f PA |
357 | movl $1,%eax |
358 | cpuid | |
9efb58de | 359 | andl $~1,%edx # Ignore CPUID.FPU |
5e2a044d | 360 | jz enable_paging # No flags or only CPUID.FPU = no CR4 |
6662c34f | 361 | |
5a5a51db | 362 | movl pa(mmu_cr4_features),%eax |
1da177e4 LT |
363 | movl %eax,%cr4 |
364 | ||
8a50e513 | 365 | testb $X86_CR4_PAE, %al # check if PAE is enabled |
5e2a044d | 366 | jz enable_paging |
1da177e4 LT |
367 | |
368 | /* Check if extended functions are implemented */ | |
369 | movl $0x80000000, %eax | |
370 | cpuid | |
8a50e513 PA |
371 | /* Value must be in the range 0x80000001 to 0x8000ffff */ |
372 | subl $0x80000001, %eax | |
373 | cmpl $(0x8000ffff-0x80000001), %eax | |
5e2a044d | 374 | ja enable_paging |
ebba638a KC |
375 | |
376 | /* Clear bogus XD_DISABLE bits */ | |
377 | call verify_cpu | |
378 | ||
1da177e4 LT |
379 | mov $0x80000001, %eax |
380 | cpuid | |
381 | /* Execute Disable bit supported? */ | |
8a50e513 | 382 | btl $(X86_FEATURE_NX & 31), %edx |
5e2a044d | 383 | jnc enable_paging |
1da177e4 LT |
384 | |
385 | /* Setup EFER (Extended Feature Enable Register) */ | |
8a50e513 | 386 | movl $MSR_EFER, %ecx |
1da177e4 LT |
387 | rdmsr |
388 | ||
8a50e513 | 389 | btsl $_EFER_NX, %eax |
1da177e4 LT |
390 | /* Make changes effective */ |
391 | wrmsr | |
392 | ||
5e2a044d | 393 | enable_paging: |
1da177e4 LT |
394 | |
395 | /* | |
396 | * Enable paging | |
397 | */ | |
b40827fa | 398 | movl $pa(initial_page_table), %eax |
1da177e4 | 399 | movl %eax,%cr3 /* set the page table pointer.. */ |
021ef050 | 400 | movl $CR0_STATE,%eax |
1da177e4 LT |
401 | movl %eax,%cr0 /* ..and set paging (PG) bit */ |
402 | ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ | |
403 | 1: | |
11d4c3f9 PA |
404 | /* Shift the stack pointer to a virtual address */ |
405 | addl $__PAGE_OFFSET, %esp | |
1da177e4 | 406 | |
1da177e4 LT |
407 | /* |
408 | * start system 32-bit setup. We need to re-do some of the things done | |
409 | * in 16-bit mode for the "real" operations. | |
410 | */ | |
4c5023a3 PA |
411 | movl setup_once_ref,%eax |
412 | andl %eax,%eax | |
413 | jz 1f # Did we do this already? | |
414 | call *%eax | |
415 | 1: | |
166df91d | 416 | |
1da177e4 | 417 | /* |
166df91d | 418 | * Check if it is 486 |
1da177e4 | 419 | */ |
237d1548 | 420 | movb $4,X86 # at least 486 |
c3a22a26 | 421 | cmpl $-1,X86_CPUID |
1da177e4 LT |
422 | je is486 |
423 | ||
424 | /* get vendor info */ | |
425 | xorl %eax,%eax # call CPUID with 0 -> return vendor ID | |
426 | cpuid | |
427 | movl %eax,X86_CPUID # save CPUID level | |
428 | movl %ebx,X86_VENDOR_ID # lo 4 chars | |
429 | movl %edx,X86_VENDOR_ID+4 # next 4 chars | |
430 | movl %ecx,X86_VENDOR_ID+8 # last 4 chars | |
431 | ||
432 | orl %eax,%eax # do we have processor info as well? | |
433 | je is486 | |
434 | ||
435 | movl $1,%eax # Use the CPUID instruction to get CPU type | |
436 | cpuid | |
437 | movb %al,%cl # save reg for future use | |
438 | andb $0x0f,%ah # mask processor family | |
439 | movb %ah,X86 | |
440 | andb $0xf0,%al # mask model | |
441 | shrb $4,%al | |
442 | movb %al,X86_MODEL | |
443 | andb $0x0f,%cl # mask mask revision | |
444 | movb %cl,X86_MASK | |
445 | movl %edx,X86_CAPABILITY | |
446 | ||
c3a22a26 | 447 | is486: |
c3a22a26 | 448 | movl $0x50022,%ecx # set AM, WP, NE and MP |
166df91d | 449 | movl %cr0,%eax |
1da177e4 LT |
450 | andl $0x80000011,%eax # Save PG,PE,ET |
451 | orl %ecx,%eax | |
452 | movl %eax,%cr0 | |
453 | ||
2a57ff1a | 454 | lgdt early_gdt_descr |
1da177e4 LT |
455 | lidt idt_descr |
456 | ljmp $(__KERNEL_CS),$1f | |
457 | 1: movl $(__KERNEL_DS),%eax # reload all the segment registers | |
458 | movl %eax,%ss # after changing gdt. | |
459 | ||
460 | movl $(__USER_DS),%eax # DS/ES contains default USER segment | |
461 | movl %eax,%ds | |
462 | movl %eax,%es | |
463 | ||
0dd76d73 BG |
464 | movl $(__KERNEL_PERCPU), %eax |
465 | movl %eax,%fs # set this cpu's percpu | |
466 | ||
60a5317f | 467 | movl $(__KERNEL_STACK_CANARY),%eax |
464d1a78 | 468 | movl %eax,%gs |
60a5317f TH |
469 | |
470 | xorl %eax,%eax # Clear LDT | |
1da177e4 | 471 | lldt %ax |
f95d47ca | 472 | |
26fd5e08 | 473 | pushl $0 # fake return address for unwinder |
e3f77edf | 474 | jmp *(initial_code) |
1da177e4 | 475 | |
4c5023a3 PA |
476 | #include "verify_cpu.S" |
477 | ||
1da177e4 | 478 | /* |
4c5023a3 | 479 | * setup_once |
1da177e4 | 480 | * |
4c5023a3 | 481 | * The setup work we only want to run on the BSP. |
1da177e4 LT |
482 | * |
483 | * Warning: %esi is live across this function. | |
484 | */ | |
4c5023a3 PA |
485 | __INIT |
486 | setup_once: | |
487 | /* | |
425be567 AL |
488 | * Set up a idt with 256 interrupt gates that push zero if there |
489 | * is no error code and then jump to early_idt_handler_common. | |
490 | * It doesn't actually load the idt - that needs to be done on | |
491 | * each CPU. Interrupts are enabled elsewhere, when we can be | |
492 | * relatively sure everything is ok. | |
4c5023a3 | 493 | */ |
1da177e4 | 494 | |
4c5023a3 | 495 | movl $idt_table,%edi |
425be567 | 496 | movl $early_idt_handler_array,%eax |
4c5023a3 PA |
497 | movl $NUM_EXCEPTION_VECTORS,%ecx |
498 | 1: | |
1da177e4 | 499 | movl %eax,(%edi) |
4c5023a3 PA |
500 | movl %eax,4(%edi) |
501 | /* interrupt gate, dpl=0, present */ | |
502 | movl $(0x8E000000 + __KERNEL_CS),2(%edi) | |
425be567 | 503 | addl $EARLY_IDT_HANDLER_SIZE,%eax |
1da177e4 | 504 | addl $8,%edi |
4c5023a3 | 505 | loop 1b |
ec5c0926 | 506 | |
4c5023a3 PA |
507 | movl $256 - NUM_EXCEPTION_VECTORS,%ecx |
508 | movl $ignore_int,%edx | |
ec5c0926 | 509 | movl $(__KERNEL_CS << 16),%eax |
4c5023a3 | 510 | movw %dx,%ax /* selector = 0x0010 = cs */ |
ec5c0926 | 511 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ |
4c5023a3 PA |
512 | 2: |
513 | movl %eax,(%edi) | |
514 | movl %edx,4(%edi) | |
515 | addl $8,%edi | |
516 | loop 2b | |
ec5c0926 | 517 | |
4c5023a3 PA |
518 | #ifdef CONFIG_CC_STACKPROTECTOR |
519 | /* | |
520 | * Configure the stack canary. The linker can't handle this by | |
521 | * relocation. Manually set base address in stack canary | |
522 | * segment descriptor. | |
523 | */ | |
524 | movl $gdt_page,%eax | |
525 | movl $stack_canary,%ecx | |
526 | movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax) | |
527 | shrl $16, %ecx | |
528 | movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax) | |
529 | movb %ch, 8 * GDT_ENTRY_STACK_CANARY + 7(%eax) | |
530 | #endif | |
ec5c0926 | 531 | |
4c5023a3 | 532 | andl $0,setup_once_ref /* Once is enough, thanks */ |
1da177e4 LT |
533 | ret |
534 | ||
425be567 | 535 | ENTRY(early_idt_handler_array) |
4c5023a3 PA |
536 | # 36(%esp) %eflags |
537 | # 32(%esp) %cs | |
538 | # 28(%esp) %eip | |
539 | # 24(%rsp) error code | |
540 | i = 0 | |
541 | .rept NUM_EXCEPTION_VECTORS | |
425be567 | 542 | .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 |
4c5023a3 PA |
543 | pushl $0 # Dummy error code, to make stack frame uniform |
544 | .endif | |
545 | pushl $i # 20(%esp) Vector number | |
425be567 | 546 | jmp early_idt_handler_common |
4c5023a3 | 547 | i = i + 1 |
425be567 | 548 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
4c5023a3 | 549 | .endr |
425be567 | 550 | ENDPROC(early_idt_handler_array) |
4c5023a3 | 551 | |
425be567 AL |
552 | early_idt_handler_common: |
553 | /* | |
554 | * The stack is the hardware frame, an error code or zero, and the | |
555 | * vector number. | |
556 | */ | |
4c5023a3 | 557 | cld |
5fa10196 | 558 | |
4c5023a3 | 559 | incl %ss:early_recursion_flag |
ec5c0926 | 560 | |
7bbcdb1c | 561 | /* The vector number is in pt_regs->gs */ |
ec5c0926 | 562 | |
7bbcdb1c AL |
563 | cld |
564 | pushl %fs /* pt_regs->fs */ | |
565 | movw $0, 2(%esp) /* clear high bits (some CPUs leave garbage) */ | |
566 | pushl %es /* pt_regs->es */ | |
567 | movw $0, 2(%esp) /* clear high bits (some CPUs leave garbage) */ | |
568 | pushl %ds /* pt_regs->ds */ | |
569 | movw $0, 2(%esp) /* clear high bits (some CPUs leave garbage) */ | |
570 | pushl %eax /* pt_regs->ax */ | |
571 | pushl %ebp /* pt_regs->bp */ | |
572 | pushl %edi /* pt_regs->di */ | |
573 | pushl %esi /* pt_regs->si */ | |
574 | pushl %edx /* pt_regs->dx */ | |
575 | pushl %ecx /* pt_regs->cx */ | |
576 | pushl %ebx /* pt_regs->bx */ | |
577 | ||
578 | /* Fix up DS and ES */ | |
579 | movl $(__KERNEL_DS), %ecx | |
580 | movl %ecx, %ds | |
581 | movl %ecx, %es | |
582 | ||
583 | /* Load the vector number into EDX */ | |
584 | movl PT_GS(%esp), %edx | |
585 | ||
586 | /* Load GS into pt_regs->gs and clear high bits */ | |
587 | movw %gs, PT_GS(%esp) | |
588 | movw $0, PT_GS+2(%esp) | |
589 | ||
7bbcdb1c AL |
590 | movl %esp, %eax /* args are pt_regs (EAX), trapnr (EDX) */ |
591 | call early_fixup_exception | |
7bbcdb1c AL |
592 | |
593 | popl %ebx /* pt_regs->bx */ | |
594 | popl %ecx /* pt_regs->cx */ | |
595 | popl %edx /* pt_regs->dx */ | |
596 | popl %esi /* pt_regs->si */ | |
597 | popl %edi /* pt_regs->di */ | |
598 | popl %ebp /* pt_regs->bp */ | |
599 | popl %eax /* pt_regs->ax */ | |
600 | popl %ds /* pt_regs->ds */ | |
601 | popl %es /* pt_regs->es */ | |
602 | popl %fs /* pt_regs->fs */ | |
603 | popl %gs /* pt_regs->gs */ | |
604 | decl %ss:early_recursion_flag | |
605 | addl $4, %esp /* pop pt_regs->orig_ax */ | |
606 | iret | |
425be567 | 607 | ENDPROC(early_idt_handler_common) |
4c5023a3 | 608 | |
1da177e4 LT |
609 | /* This is the default interrupt "handler" :-) */ |
610 | ALIGN | |
611 | ignore_int: | |
612 | cld | |
d59745ce | 613 | #ifdef CONFIG_PRINTK |
1da177e4 LT |
614 | pushl %eax |
615 | pushl %ecx | |
616 | pushl %edx | |
617 | pushl %es | |
618 | pushl %ds | |
619 | movl $(__KERNEL_DS),%eax | |
620 | movl %eax,%ds | |
621 | movl %eax,%es | |
ec5c0926 CE |
622 | cmpl $2,early_recursion_flag |
623 | je hlt_loop | |
624 | incl early_recursion_flag | |
1da177e4 LT |
625 | pushl 16(%esp) |
626 | pushl 24(%esp) | |
627 | pushl 32(%esp) | |
628 | pushl 40(%esp) | |
629 | pushl $int_msg | |
630 | call printk | |
d5e397cb IM |
631 | |
632 | call dump_stack | |
633 | ||
1da177e4 LT |
634 | addl $(5*4),%esp |
635 | popl %ds | |
636 | popl %es | |
637 | popl %edx | |
638 | popl %ecx | |
639 | popl %eax | |
d59745ce | 640 | #endif |
1da177e4 | 641 | iret |
0e861fbb AL |
642 | |
643 | hlt_loop: | |
644 | hlt | |
645 | jmp hlt_loop | |
4c5023a3 PA |
646 | ENDPROC(ignore_int) |
647 | __INITDATA | |
648 | .align 4 | |
0e861fbb | 649 | GLOBAL(early_recursion_flag) |
4c5023a3 | 650 | .long 0 |
1da177e4 | 651 | |
4c5023a3 PA |
652 | __REFDATA |
653 | .align 4 | |
583323b9 TG |
654 | ENTRY(initial_code) |
655 | .long i386_start_kernel | |
4c5023a3 PA |
656 | ENTRY(setup_once_ref) |
657 | .long setup_once | |
583323b9 | 658 | |
1da177e4 LT |
659 | /* |
660 | * BSS section | |
661 | */ | |
02b7da37 | 662 | __PAGE_ALIGNED_BSS |
7bf04be8 | 663 | .align PAGE_SIZE |
551889a6 | 664 | #ifdef CONFIG_X86_PAE |
d50d8fe1 | 665 | initial_pg_pmd: |
551889a6 IC |
666 | .fill 1024*KPMDS,4,0 |
667 | #else | |
b40827fa | 668 | ENTRY(initial_page_table) |
1da177e4 | 669 | .fill 1024,4,0 |
551889a6 | 670 | #endif |
d50d8fe1 | 671 | initial_pg_fixmap: |
b1c931e3 | 672 | .fill 1024,4,0 |
1da177e4 LT |
673 | ENTRY(empty_zero_page) |
674 | .fill 4096,1,0 | |
b40827fa BP |
675 | ENTRY(swapper_pg_dir) |
676 | .fill 1024,4,0 | |
784d5699 | 677 | EXPORT_SYMBOL(empty_zero_page) |
2bd2753f | 678 | |
1da177e4 LT |
679 | /* |
680 | * This starts the data section. | |
681 | */ | |
551889a6 | 682 | #ifdef CONFIG_X86_PAE |
abe1ee3a | 683 | __PAGE_ALIGNED_DATA |
551889a6 | 684 | /* Page-aligned for the benefit of paravirt? */ |
7bf04be8 | 685 | .align PAGE_SIZE |
b40827fa BP |
686 | ENTRY(initial_page_table) |
687 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ | |
551889a6 | 688 | # if KPMDS == 3 |
b40827fa BP |
689 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
690 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
691 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x2000),0 | |
551889a6 IC |
692 | # elif KPMDS == 2 |
693 | .long 0,0 | |
b40827fa BP |
694 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
695 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
551889a6 IC |
696 | # elif KPMDS == 1 |
697 | .long 0,0 | |
698 | .long 0,0 | |
b40827fa | 699 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
551889a6 IC |
700 | # else |
701 | # error "Kernel PMDs should be 1, 2 or 3" | |
702 | # endif | |
7bf04be8 | 703 | .align PAGE_SIZE /* needs to be page-sized too */ |
551889a6 IC |
704 | #endif |
705 | ||
1da177e4 | 706 | .data |
11d4c3f9 | 707 | .balign 4 |
1da177e4 LT |
708 | ENTRY(stack_start) |
709 | .long init_thread_union+THREAD_SIZE | |
1da177e4 | 710 | |
4c5023a3 | 711 | __INITRODATA |
1da177e4 | 712 | int_msg: |
d5e397cb | 713 | .asciz "Unknown interrupt or fault at: %p %p %p\n" |
1da177e4 | 714 | |
9702785a | 715 | #include "../../x86/xen/xen-head.S" |
5ead97c8 | 716 | |
1da177e4 LT |
717 | /* |
718 | * The IDT and GDT 'descriptors' are a strange 48-bit object | |
719 | * only used by the lidt and lgdt instructions. They are not | |
720 | * like usual segment descriptors - they consist of a 16-bit | |
721 | * segment size, and 32-bit linear address value: | |
722 | */ | |
723 | ||
4c5023a3 | 724 | .data |
1da177e4 LT |
725 | .globl boot_gdt_descr |
726 | .globl idt_descr | |
1da177e4 LT |
727 | |
728 | ALIGN | |
729 | # early boot GDT descriptor (must use 1:1 address mapping) | |
730 | .word 0 # 32 bit align gdt_desc.address | |
731 | boot_gdt_descr: | |
732 | .word __BOOT_DS+7 | |
52de74dd | 733 | .long boot_gdt - __PAGE_OFFSET |
1da177e4 LT |
734 | |
735 | .word 0 # 32-bit align idt_desc.address | |
736 | idt_descr: | |
737 | .word IDT_ENTRIES*8-1 # idt contains 256 entries | |
738 | .long idt_table | |
739 | ||
740 | # boot GDT descriptor (later on used by CPU#0): | |
741 | .word 0 # 32 bit align gdt_desc.address | |
2a57ff1a | 742 | ENTRY(early_gdt_descr) |
1da177e4 | 743 | .word GDT_ENTRIES*8-1 |
dd17c8f7 | 744 | .long gdt_page /* Overwritten for secondary CPUs */ |
1da177e4 | 745 | |
1da177e4 | 746 | /* |
52de74dd | 747 | * The boot_gdt must mirror the equivalent in setup.S and is |
1da177e4 LT |
748 | * used only for booting. |
749 | */ | |
750 | .align L1_CACHE_BYTES | |
52de74dd | 751 | ENTRY(boot_gdt) |
1da177e4 LT |
752 | .fill GDT_ENTRY_BOOT_CS,8,0 |
753 | .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */ | |
754 | .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */ |