Commit | Line | Data |
---|---|---|
6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
4722d194 | 7 | #include <linux/of.h> |
6b39ba77 | 8 | #include <linux/seq_file.h> |
6a02e710 | 9 | #include <linux/smp.h> |
7c1d7cdc | 10 | #include <linux/ftrace.h> |
ca444564 | 11 | #include <linux/delay.h> |
69c60c88 | 12 | #include <linux/export.h> |
6b39ba77 | 13 | |
7b6aa335 | 14 | #include <asm/apic.h> |
6b39ba77 | 15 | #include <asm/io_apic.h> |
c3d80000 | 16 | #include <asm/irq.h> |
7c1d7cdc | 17 | #include <asm/idle.h> |
01ca79f1 | 18 | #include <asm/mce.h> |
2c1b284e | 19 | #include <asm/hw_irq.h> |
6b39ba77 TG |
20 | |
21 | atomic_t irq_err_count; | |
22 | ||
acaabe79 | 23 | /* Function pointer for generic interrupt vector handling */ |
4a4de9c7 | 24 | void (*x86_platform_ipi_callback)(void) = NULL; |
acaabe79 | 25 | |
249f6d9e TG |
26 | /* |
27 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
28 | * each architecture has to answer this themselves. | |
29 | */ | |
30 | void ack_bad_irq(unsigned int irq) | |
31 | { | |
edea7148 CG |
32 | if (printk_ratelimit()) |
33 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 34 | |
249f6d9e TG |
35 | /* |
36 | * Currently unexpected vectors happen only on SMP and APIC. | |
37 | * We _must_ ack these because every local APIC has only N | |
38 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
39 | * holds up an irq slot - in excessive cases (when multiple | |
40 | * unexpected vectors occur) that might lock up the APIC | |
41 | * completely. | |
42 | * But only ack when the APIC is enabled -AK | |
43 | */ | |
08306ce6 | 44 | ack_APIC_irq(); |
249f6d9e TG |
45 | } |
46 | ||
1b437c8c | 47 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 | 48 | /* |
517e4981 | 49 | * /proc/interrupts printing for arch specific interrupts |
6b39ba77 | 50 | */ |
517e4981 | 51 | int arch_show_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
52 | { |
53 | int j; | |
54 | ||
7a81d9a7 | 55 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
56 | for_each_online_cpu(j) |
57 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
58 | seq_printf(p, " Non-maskable interrupts\n"); | |
59 | #ifdef CONFIG_X86_LOCAL_APIC | |
7a81d9a7 | 60 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
61 | for_each_online_cpu(j) |
62 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
63 | seq_printf(p, " Local timer interrupts\n"); | |
474e56b8 JSR |
64 | |
65 | seq_printf(p, "%*s: ", prec, "SPU"); | |
66 | for_each_online_cpu(j) | |
67 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
68 | seq_printf(p, " Spurious interrupts\n"); | |
89ccf465 | 69 | seq_printf(p, "%*s: ", prec, "PMI"); |
241771ef IM |
70 | for_each_online_cpu(j) |
71 | seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); | |
89ccf465 | 72 | seq_printf(p, " Performance monitoring interrupts\n"); |
e360adbe | 73 | seq_printf(p, "%*s: ", prec, "IWI"); |
b6276f35 | 74 | for_each_online_cpu(j) |
e360adbe PZ |
75 | seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); |
76 | seq_printf(p, " IRQ work interrupts\n"); | |
346b46be FLVC |
77 | seq_printf(p, "%*s: ", prec, "RTR"); |
78 | for_each_online_cpu(j) | |
b49d7d87 | 79 | seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count); |
346b46be | 80 | seq_printf(p, " APIC ICR read retries\n"); |
6b39ba77 | 81 | #endif |
4a4de9c7 | 82 | if (x86_platform_ipi_callback) { |
59d13812 | 83 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 | 84 | for_each_online_cpu(j) |
4a4de9c7 | 85 | seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); |
acaabe79 DS |
86 | seq_printf(p, " Platform interrupts\n"); |
87 | } | |
6b39ba77 | 88 | #ifdef CONFIG_SMP |
7a81d9a7 | 89 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
90 | for_each_online_cpu(j) |
91 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
92 | seq_printf(p, " Rescheduling interrupts\n"); | |
7a81d9a7 | 93 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 | 94 | for_each_online_cpu(j) |
fd0f5869 TS |
95 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count - |
96 | irq_stats(j)->irq_tlb_count); | |
6b39ba77 | 97 | seq_printf(p, " Function call interrupts\n"); |
7a81d9a7 | 98 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
99 | for_each_online_cpu(j) |
100 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
101 | seq_printf(p, " TLB shootdowns\n"); | |
102 | #endif | |
0444c9bd | 103 | #ifdef CONFIG_X86_THERMAL_VECTOR |
7a81d9a7 | 104 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
105 | for_each_online_cpu(j) |
106 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
107 | seq_printf(p, " Thermal event interrupts\n"); | |
0444c9bd JB |
108 | #endif |
109 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
7a81d9a7 | 110 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
111 | for_each_online_cpu(j) |
112 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
113 | seq_printf(p, " Threshold APIC interrupts\n"); | |
01ca79f1 | 114 | #endif |
c1ebf835 | 115 | #ifdef CONFIG_X86_MCE |
01ca79f1 AK |
116 | seq_printf(p, "%*s: ", prec, "MCE"); |
117 | for_each_online_cpu(j) | |
118 | seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); | |
119 | seq_printf(p, " Machine check exceptions\n"); | |
ca84f696 AK |
120 | seq_printf(p, "%*s: ", prec, "MCP"); |
121 | for_each_online_cpu(j) | |
122 | seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); | |
123 | seq_printf(p, " Machine check polls\n"); | |
6b39ba77 | 124 | #endif |
7a81d9a7 | 125 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 126 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 127 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
6b39ba77 TG |
128 | #endif |
129 | return 0; | |
130 | } | |
131 | ||
6b39ba77 TG |
132 | /* |
133 | * /proc/stat helpers | |
134 | */ | |
135 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
136 | { | |
137 | u64 sum = irq_stats(cpu)->__nmi_count; | |
138 | ||
139 | #ifdef CONFIG_X86_LOCAL_APIC | |
140 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 141 | sum += irq_stats(cpu)->irq_spurious_count; |
241771ef | 142 | sum += irq_stats(cpu)->apic_perf_irqs; |
e360adbe | 143 | sum += irq_stats(cpu)->apic_irq_work_irqs; |
b49d7d87 | 144 | sum += irq_stats(cpu)->icr_read_retry_count; |
6b39ba77 | 145 | #endif |
4a4de9c7 DS |
146 | if (x86_platform_ipi_callback) |
147 | sum += irq_stats(cpu)->x86_platform_ipis; | |
6b39ba77 TG |
148 | #ifdef CONFIG_SMP |
149 | sum += irq_stats(cpu)->irq_resched_count; | |
150 | sum += irq_stats(cpu)->irq_call_count; | |
6b39ba77 | 151 | #endif |
0444c9bd | 152 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6b39ba77 | 153 | sum += irq_stats(cpu)->irq_thermal_count; |
0444c9bd JB |
154 | #endif |
155 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
6b39ba77 | 156 | sum += irq_stats(cpu)->irq_threshold_count; |
8051dbd2 | 157 | #endif |
c1ebf835 | 158 | #ifdef CONFIG_X86_MCE |
8051dbd2 HS |
159 | sum += per_cpu(mce_exception_count, cpu); |
160 | sum += per_cpu(mce_poll_count, cpu); | |
6b39ba77 TG |
161 | #endif |
162 | return sum; | |
163 | } | |
164 | ||
165 | u64 arch_irq_stat(void) | |
166 | { | |
167 | u64 sum = atomic_read(&irq_err_count); | |
6b39ba77 TG |
168 | return sum; |
169 | } | |
c3d80000 | 170 | |
7c1d7cdc JF |
171 | |
172 | /* | |
173 | * do_IRQ handles all normal device IRQ's (the special | |
174 | * SMP cross-CPU interrupts have their own specific | |
175 | * handlers). | |
176 | */ | |
177 | unsigned int __irq_entry do_IRQ(struct pt_regs *regs) | |
178 | { | |
179 | struct pt_regs *old_regs = set_irq_regs(regs); | |
180 | ||
181 | /* high bit used in ret_from_ code */ | |
182 | unsigned vector = ~regs->orig_ax; | |
183 | unsigned irq; | |
184 | ||
7c1d7cdc | 185 | irq_enter(); |
98ad1cc1 | 186 | exit_idle(); |
7c1d7cdc | 187 | |
0a3aee0d | 188 | irq = __this_cpu_read(vector_irq[vector]); |
7c1d7cdc JF |
189 | |
190 | if (!handle_irq(irq, regs)) { | |
08306ce6 | 191 | ack_APIC_irq(); |
7c1d7cdc JF |
192 | |
193 | if (printk_ratelimit()) | |
edea7148 CG |
194 | pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", |
195 | __func__, smp_processor_id(), vector, irq); | |
7c1d7cdc JF |
196 | } |
197 | ||
198 | irq_exit(); | |
199 | ||
200 | set_irq_regs(old_regs); | |
201 | return 1; | |
202 | } | |
203 | ||
acaabe79 | 204 | /* |
4a4de9c7 | 205 | * Handler for X86_PLATFORM_IPI_VECTOR. |
acaabe79 | 206 | */ |
eddc0e92 | 207 | void __smp_x86_platform_ipi(void) |
acaabe79 | 208 | { |
4a4de9c7 | 209 | inc_irq_stat(x86_platform_ipis); |
acaabe79 | 210 | |
4a4de9c7 DS |
211 | if (x86_platform_ipi_callback) |
212 | x86_platform_ipi_callback(); | |
eddc0e92 | 213 | } |
acaabe79 | 214 | |
eddc0e92 SA |
215 | void smp_x86_platform_ipi(struct pt_regs *regs) |
216 | { | |
217 | struct pt_regs *old_regs = set_irq_regs(regs); | |
acaabe79 | 218 | |
eddc0e92 SA |
219 | entering_ack_irq(); |
220 | __smp_x86_platform_ipi(); | |
221 | exiting_irq(); | |
acaabe79 DS |
222 | set_irq_regs(old_regs); |
223 | } | |
224 | ||
d78f2664 YZ |
225 | #ifdef CONFIG_HAVE_KVM |
226 | /* | |
227 | * Handler for POSTED_INTERRUPT_VECTOR. | |
228 | */ | |
229 | void smp_kvm_posted_intr_ipi(struct pt_regs *regs) | |
230 | { | |
231 | struct pt_regs *old_regs = set_irq_regs(regs); | |
232 | ||
233 | ack_APIC_irq(); | |
234 | ||
235 | irq_enter(); | |
236 | ||
237 | exit_idle(); | |
238 | ||
239 | inc_irq_stat(kvm_posted_intr_ipis); | |
240 | ||
241 | irq_exit(); | |
242 | ||
243 | set_irq_regs(old_regs); | |
244 | } | |
245 | #endif | |
246 | ||
c3d80000 | 247 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |
7a7732bc SS |
248 | |
249 | #ifdef CONFIG_HOTPLUG_CPU | |
250 | /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ | |
251 | void fixup_irqs(void) | |
252 | { | |
5231a686 | 253 | unsigned int irq, vector; |
7a7732bc SS |
254 | static int warned; |
255 | struct irq_desc *desc; | |
a3c08e5d | 256 | struct irq_data *data; |
51c43ac6 | 257 | struct irq_chip *chip; |
7a7732bc SS |
258 | |
259 | for_each_irq_desc(irq, desc) { | |
260 | int break_affinity = 0; | |
261 | int set_affinity = 1; | |
262 | const struct cpumask *affinity; | |
263 | ||
264 | if (!desc) | |
265 | continue; | |
266 | if (irq == 2) | |
267 | continue; | |
268 | ||
269 | /* interrupt's are disabled at this point */ | |
239007b8 | 270 | raw_spin_lock(&desc->lock); |
7a7732bc | 271 | |
51c43ac6 | 272 | data = irq_desc_get_irq_data(desc); |
a3c08e5d | 273 | affinity = data->affinity; |
b87ba87c | 274 | if (!irq_has_action(irq) || irqd_is_per_cpu(data) || |
58bff947 | 275 | cpumask_subset(affinity, cpu_online_mask)) { |
239007b8 | 276 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
277 | continue; |
278 | } | |
279 | ||
a5e74b84 SS |
280 | /* |
281 | * Complete the irq move. This cpu is going down and for | |
282 | * non intr-remapping case, we can't wait till this interrupt | |
283 | * arrives at this cpu before completing the irq move. | |
284 | */ | |
285 | irq_force_complete_move(irq); | |
286 | ||
7a7732bc SS |
287 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
288 | break_affinity = 1; | |
2530cd4f | 289 | affinity = cpu_online_mask; |
7a7732bc SS |
290 | } |
291 | ||
51c43ac6 TG |
292 | chip = irq_data_get_irq_chip(data); |
293 | if (!irqd_can_move_in_process_context(data) && chip->irq_mask) | |
294 | chip->irq_mask(data); | |
7a7732bc | 295 | |
51c43ac6 TG |
296 | if (chip->irq_set_affinity) |
297 | chip->irq_set_affinity(data, affinity, true); | |
7a7732bc SS |
298 | else if (!(warned++)) |
299 | set_affinity = 0; | |
300 | ||
99dd5497 LC |
301 | /* |
302 | * We unmask if the irq was not marked masked by the | |
303 | * core code. That respects the lazy irq disable | |
304 | * behaviour. | |
305 | */ | |
983bbf1a | 306 | if (!irqd_can_move_in_process_context(data) && |
99dd5497 | 307 | !irqd_irq_masked(data) && chip->irq_unmask) |
51c43ac6 | 308 | chip->irq_unmask(data); |
7a7732bc | 309 | |
239007b8 | 310 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
311 | |
312 | if (break_affinity && set_affinity) | |
c767a54b | 313 | pr_notice("Broke affinity for irq %i\n", irq); |
7a7732bc | 314 | else if (!set_affinity) |
c767a54b | 315 | pr_notice("Cannot set affinity for irq %i\n", irq); |
7a7732bc SS |
316 | } |
317 | ||
5231a686 SS |
318 | /* |
319 | * We can remove mdelay() and then send spuriuous interrupts to | |
320 | * new cpu targets for all the irqs that were handled previously by | |
321 | * this cpu. While it works, I have seen spurious interrupt messages | |
322 | * (nothing wrong but still...). | |
323 | * | |
324 | * So for now, retain mdelay(1) and check the IRR and then send those | |
325 | * interrupts to new targets as this cpu is already offlined... | |
326 | */ | |
7a7732bc | 327 | mdelay(1); |
5231a686 SS |
328 | |
329 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
330 | unsigned int irr; | |
331 | ||
0a3aee0d | 332 | if (__this_cpu_read(vector_irq[vector]) < 0) |
5231a686 SS |
333 | continue; |
334 | ||
335 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
336 | if (irr & (1 << (vector % 32))) { | |
0a3aee0d | 337 | irq = __this_cpu_read(vector_irq[vector]); |
5231a686 | 338 | |
5117348d | 339 | desc = irq_to_desc(irq); |
51c43ac6 TG |
340 | data = irq_desc_get_irq_data(desc); |
341 | chip = irq_data_get_irq_chip(data); | |
239007b8 | 342 | raw_spin_lock(&desc->lock); |
51c43ac6 TG |
343 | if (chip->irq_retrigger) |
344 | chip->irq_retrigger(data); | |
239007b8 | 345 | raw_spin_unlock(&desc->lock); |
5231a686 | 346 | } |
1d44b30f | 347 | __this_cpu_write(vector_irq[vector], -1); |
5231a686 | 348 | } |
7a7732bc SS |
349 | } |
350 | #endif |