[deliverable/linux.git] / arch / x86 / kernel / irq.c

/*
 * Common interrupt code for 32 and 64 bit
 */
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/smp.h>
#include <linux/ftrace.h>

#include <asm/apic.h>
#include <asm/io_apic.h>
#include <asm/irq.h>
#include <asm/idle.h>
#include <asm/mce.h>
#include <asm/hw_irq.h>

atomic_t irq_err_count;

/* Function pointer for generic interrupt vector handling */
void (*x86_platform_ipi_callback)(void) = NULL;

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	if (printk_ratelimit())
		pr_err("unexpected IRQ trap at vector %02x\n", irq);

	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But only ack when the APIC is enabled -AK
	 */
	ack_APIC_irq();
}

#define irq_stats(x)		(&per_cpu(irq_stat, x))
/*
 * /proc/interrupts printing:
 */
static int show_other_interrupts(struct seq_file *p, int prec)
{
	int j;

	seq_printf(p, "%*s: ", prec, "NMI");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
	seq_printf(p, "  Non-maskable interrupts\n");
#ifdef CONFIG_X86_LOCAL_APIC
	seq_printf(p, "%*s: ", prec, "LOC");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
	seq_printf(p, "  Local timer interrupts\n");

	seq_printf(p, "%*s: ", prec, "SPU");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
	seq_printf(p, "  Spurious interrupts\n");
	seq_printf(p, "%*s: ", prec, "PMI");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
	seq_printf(p, "  Performance monitoring interrupts\n");
	seq_printf(p, "%*s: ", prec, "PND");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->apic_pending_irqs);
	seq_printf(p, "  Performance pending work\n");
#endif
	if (x86_platform_ipi_callback) {
		seq_printf(p, "%*s: ", prec, "PLT");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
		seq_printf(p, "  Platform interrupts\n");
	}
#ifdef CONFIG_SMP
	seq_printf(p, "%*s: ", prec, "RES");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
	seq_printf(p, "  Rescheduling interrupts\n");
	seq_printf(p, "%*s: ", prec, "CAL");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
	seq_printf(p, "  Function call interrupts\n");
	seq_printf(p, "%*s: ", prec, "TLB");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
	seq_printf(p, "  TLB shootdowns\n");
#endif
#ifdef CONFIG_X86_THERMAL_VECTOR
	seq_printf(p, "%*s: ", prec, "TRM");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
	seq_printf(p, "  Thermal event interrupts\n");
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	seq_printf(p, "%*s: ", prec, "THR");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
	seq_printf(p, "  Threshold APIC interrupts\n");
#endif
#ifdef CONFIG_X86_MCE
	seq_printf(p, "%*s: ", prec, "MCE");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
	seq_printf(p, "  Machine check exceptions\n");
	seq_printf(p, "%*s: ", prec, "MCP");
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
	seq_printf(p, "  Machine check polls\n");
#endif
	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
#if defined(CONFIG_X86_IO_APIC)
	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
#endif
	return 0;
}

int show_interrupts(struct seq_file *p, void *v)
{
	unsigned long flags, any_count = 0;
	int i = *(loff_t *) v, j, prec;
	struct irqaction *action;
	struct irq_desc *desc;

	if (i > nr_irqs)
		return 0;

	for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
		j *= 10;

	if (i == nr_irqs)
		return show_other_interrupts(p, prec);

	/* print header */
	if (i == 0) {
		seq_printf(p, "%*s", prec + 8, "");
		for_each_online_cpu(j)
			seq_printf(p, "CPU%-8d", j);
		seq_putc(p, '\n');
	}

	desc = irq_to_desc(i);
	if (!desc)
		return 0;

	spin_lock_irqsave(&desc->lock, flags);
	for_each_online_cpu(j)
		any_count |= kstat_irqs_cpu(i, j);
	action = desc->action;
	if (!action && !any_count)
		goto out;

	seq_printf(p, "%*d: ", prec, i);
	for_each_online_cpu(j)
		seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
	seq_printf(p, " %8s", desc->chip->name);
	seq_printf(p, "-%-8s", desc->name);

	if (action) {
		seq_printf(p, "  %s", action->name);
		while ((action = action->next) != NULL)
			seq_printf(p, ", %s", action->name);
	}

	seq_putc(p, '\n');
out:
	spin_unlock_irqrestore(&desc->lock, flags);
	return 0;
}

/*
 * /proc/stat helpers
 */
u64 arch_irq_stat_cpu(unsigned int cpu)
{
	u64 sum = irq_stats(cpu)->__nmi_count;

#ifdef CONFIG_X86_LOCAL_APIC
	sum += irq_stats(cpu)->apic_timer_irqs;
	sum += irq_stats(cpu)->irq_spurious_count;
	sum += irq_stats(cpu)->apic_perf_irqs;
	sum += irq_stats(cpu)->apic_pending_irqs;
#endif
	if (x86_platform_ipi_callback)
		sum += irq_stats(cpu)->x86_platform_ipis;
#ifdef CONFIG_SMP
	sum += irq_stats(cpu)->irq_resched_count;
	sum += irq_stats(cpu)->irq_call_count;
	sum += irq_stats(cpu)->irq_tlb_count;
#endif
#ifdef CONFIG_X86_THERMAL_VECTOR
	sum += irq_stats(cpu)->irq_thermal_count;
#endif
#ifdef CONFIG_X86_MCE_THRESHOLD
	sum += irq_stats(cpu)->irq_threshold_count;
#endif
#ifdef CONFIG_X86_MCE
	sum += per_cpu(mce_exception_count, cpu);
	sum += per_cpu(mce_poll_count, cpu);
#endif
	return sum;
}

u64 arch_irq_stat(void)
{
	u64 sum = atomic_read(&irq_err_count);

#ifdef CONFIG_X86_IO_APIC
	sum += atomic_read(&irq_mis_count);
#endif
	return sum;
}


/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/* high bit used in ret_from_ code  */
	unsigned vector = ~regs->orig_ax;
	unsigned irq;

	exit_idle();
	irq_enter();

	irq = __get_cpu_var(vector_irq)[vector];

	if (!handle_irq(irq, regs)) {
		ack_APIC_irq();

		if (printk_ratelimit())
			pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
				__func__, smp_processor_id(), vector, irq);
	}

	irq_exit();

	set_irq_regs(old_regs);
	return 1;
}

/*
 * Handler for X86_PLATFORM_IPI_VECTOR.
 */
void smp_x86_platform_ipi(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	ack_APIC_irq();

	exit_idle();

	irq_enter();

	inc_irq_stat(x86_platform_ipis);

	if (x86_platform_ipi_callback)
		x86_platform_ipi_callback();

	irq_exit();

	set_irq_regs(old_regs);
}

EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);

#ifdef CONFIG_HOTPLUG_CPU
/* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
void fixup_irqs(void)
{
	unsigned int irq, vector;
	static int warned;
	struct irq_desc *desc;

	for_each_irq_desc(irq, desc) {
		int break_affinity = 0;
		int set_affinity = 1;
		const struct cpumask *affinity;

		if (!desc)
			continue;
		if (irq == 2)
			continue;

		/* interrupt's are disabled at this point */
		spin_lock(&desc->lock);

		affinity = desc->affinity;
		if (!irq_has_action(irq) ||
		    cpumask_equal(affinity, cpu_online_mask)) {
			spin_unlock(&desc->lock);
			continue;
		}

		/*
		 * Complete the irq move. This cpu is going down and for
		 * non intr-remapping case, we can't wait till this interrupt
		 * arrives at this cpu before completing the irq move.
		 */
		irq_force_complete_move(irq);

		if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
			break_affinity = 1;
			affinity = cpu_all_mask;
		}

		if (!(desc->status & IRQ_MOVE_PCNTXT) && desc->chip->mask)
			desc->chip->mask(irq);

		if (desc->chip->set_affinity)
			desc->chip->set_affinity(irq, affinity);
		else if (!(warned++))
			set_affinity = 0;

		if (!(desc->status & IRQ_MOVE_PCNTXT) && desc->chip->unmask)
			desc->chip->unmask(irq);

		spin_unlock(&desc->lock);

		if (break_affinity && set_affinity)
			printk("Broke affinity for irq %i\n", irq);
		else if (!set_affinity)
			printk("Cannot set affinity for irq %i\n", irq);
	}

	/*
	 * We can remove mdelay() and then send spuriuous interrupts to
	 * new cpu targets for all the irqs that were handled previously by
	 * this cpu. While it works, I have seen spurious interrupt messages
	 * (nothing wrong but still...).
	 *
	 * So for now, retain mdelay(1) and check the IRR and then send those
	 * interrupts to new targets as this cpu is already offlined...
	 */
	mdelay(1);

	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
		unsigned int irr;

		if (__get_cpu_var(vector_irq)[vector] < 0)
			continue;

		irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
		if (irr  & (1 << (vector % 32))) {
			irq = __get_cpu_var(vector_irq)[vector];

			desc = irq_to_desc(irq);
			spin_lock(&desc->lock);
			if (desc->chip->retrigger)
				desc->chip->retrigger(irq);
			spin_unlock(&desc->lock);
		}
	}
}
#endif
Commit	Line	Data
6b39ba77 TG	1	/*
	2	* Common interrupt code for 32 and 64 bit
	3	*/
	4	#include <linux/cpu.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/kernel_stat.h>
	7	#include <linux/seq_file.h>
6a02e710	8	#include <linux/smp.h>
7c1d7cdc	9	#include <linux/ftrace.h>
6b39ba77	10
7b6aa335	11	#include <asm/apic.h>
6b39ba77	12	#include <asm/io_apic.h>
c3d80000	13	#include <asm/irq.h>
7c1d7cdc	14	#include <asm/idle.h>
01ca79f1	15	#include <asm/mce.h>
2c1b284e	16	#include <asm/hw_irq.h>
6b39ba77 TG	17
	18	atomic_t irq_err_count;
	19
acaabe79	20	/* Function pointer for generic interrupt vector handling */
4a4de9c7	21	void (*x86_platform_ipi_callback)(void) = NULL;
acaabe79	22
249f6d9e TG	23	/*
	24	* 'what should we do if we get a hw irq event on an illegal vector'.
	25	* each architecture has to answer this themselves.
	26	*/
	27	void ack_bad_irq(unsigned int irq)
	28	{
edea7148 CG	29	if (printk_ratelimit())
edea7148 CG	30	pr_err("unexpected IRQ trap at vector %02x\n", irq);
249f6d9e	31
249f6d9e TG	32	/*
	33	* Currently unexpected vectors happen only on SMP and APIC.
	34	* We _must_ ack these because every local APIC has only N
	35	* irq slots per priority level, and a 'hanging, unacked' IRQ
	36	* holds up an irq slot - in excessive cases (when multiple
	37	* unexpected vectors occur) that might lock up the APIC
	38	* completely.
	39	* But only ack when the APIC is enabled -AK
	40	*/
08306ce6	41	ack_APIC_irq();
249f6d9e TG	42	}
249f6d9e TG	43
1b437c8c	44	#define irq_stats(x) (&per_cpu(irq_stat, x))
6b39ba77 TG	45	/*
	46	* /proc/interrupts printing:
	47	*/
7a81d9a7	48	static int show_other_interrupts(struct seq_file *p, int prec)
6b39ba77 TG	49	{
	50	int j;
	51
7a81d9a7	52	seq_printf(p, "%*s: ", prec, "NMI");
6b39ba77 TG	53	for_each_online_cpu(j)
	54	seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
	55	seq_printf(p, " Non-maskable interrupts\n");
	56	#ifdef CONFIG_X86_LOCAL_APIC
7a81d9a7	57	seq_printf(p, "%*s: ", prec, "LOC");
6b39ba77 TG	58	for_each_online_cpu(j)
	59	seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
	60	seq_printf(p, " Local timer interrupts\n");
474e56b8 JSR	61
	62	seq_printf(p, "%*s: ", prec, "SPU");
	63	for_each_online_cpu(j)
	64	seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
	65	seq_printf(p, " Spurious interrupts\n");
89ccf465	66	seq_printf(p, "%*s: ", prec, "PMI");
241771ef IM	67	for_each_online_cpu(j)
241771ef IM	68	seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
89ccf465	69	seq_printf(p, " Performance monitoring interrupts\n");
0f3fd87c	70	seq_printf(p, "%*s: ", prec, "PND");
b6276f35 PZ	71	for_each_online_cpu(j)
	72	seq_printf(p, "%10u ", irq_stats(j)->apic_pending_irqs);
	73	seq_printf(p, " Performance pending work\n");
6b39ba77	74	#endif
4a4de9c7	75	if (x86_platform_ipi_callback) {
59d13812	76	seq_printf(p, "%*s: ", prec, "PLT");
acaabe79	77	for_each_online_cpu(j)
4a4de9c7	78	seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
acaabe79 DS	79	seq_printf(p, " Platform interrupts\n");
acaabe79 DS	80	}
6b39ba77	81	#ifdef CONFIG_SMP
7a81d9a7	82	seq_printf(p, "%*s: ", prec, "RES");
6b39ba77 TG	83	for_each_online_cpu(j)
	84	seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
	85	seq_printf(p, " Rescheduling interrupts\n");
7a81d9a7	86	seq_printf(p, "%*s: ", prec, "CAL");
6b39ba77 TG	87	for_each_online_cpu(j)
	88	seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
	89	seq_printf(p, " Function call interrupts\n");
7a81d9a7	90	seq_printf(p, "%*s: ", prec, "TLB");
6b39ba77 TG	91	for_each_online_cpu(j)
	92	seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
	93	seq_printf(p, " TLB shootdowns\n");
	94	#endif
0444c9bd	95	#ifdef CONFIG_X86_THERMAL_VECTOR
7a81d9a7	96	seq_printf(p, "%*s: ", prec, "TRM");
6b39ba77 TG	97	for_each_online_cpu(j)
	98	seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
	99	seq_printf(p, " Thermal event interrupts\n");
0444c9bd JB	100	#endif
0444c9bd JB	101	#ifdef CONFIG_X86_MCE_THRESHOLD
7a81d9a7	102	seq_printf(p, "%*s: ", prec, "THR");
6b39ba77 TG	103	for_each_online_cpu(j)
	104	seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
	105	seq_printf(p, " Threshold APIC interrupts\n");
01ca79f1	106	#endif
c1ebf835	107	#ifdef CONFIG_X86_MCE
01ca79f1 AK	108	seq_printf(p, "%*s: ", prec, "MCE");
	109	for_each_online_cpu(j)
	110	seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
	111	seq_printf(p, " Machine check exceptions\n");
ca84f696 AK	112	seq_printf(p, "%*s: ", prec, "MCP");
	113	for_each_online_cpu(j)
	114	seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
	115	seq_printf(p, " Machine check polls\n");
6b39ba77	116	#endif
7a81d9a7	117	seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
6b39ba77	118	#if defined(CONFIG_X86_IO_APIC)
7a81d9a7	119	seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
6b39ba77 TG	120	#endif
	121	return 0;
	122	}
	123
	124	int show_interrupts(struct seq_file p, void v)
	125	{
	126	unsigned long flags, any_count = 0;
7a81d9a7	127	int i = (loff_t ) v, j, prec;
6b39ba77 TG	128	struct irqaction *action;
	129	struct irq_desc *desc;
	130
	131	if (i > nr_irqs)
	132	return 0;
	133
7a81d9a7 JB	134	for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
	135	j *= 10;
	136
6b39ba77	137	if (i == nr_irqs)
7a81d9a7	138	return show_other_interrupts(p, prec);
6b39ba77 TG	139
	140	/* print header */
	141	if (i == 0) {
7a81d9a7	142	seq_printf(p, "%*s", prec + 8, "");
6b39ba77	143	for_each_online_cpu(j)
e9f95e63	144	seq_printf(p, "CPU%-8d", j);
6b39ba77 TG	145	seq_putc(p, '\n');
	146	}
	147
	148	desc = irq_to_desc(i);
0b8f1efa YL	149	if (!desc)
	150	return 0;
	151
6b39ba77	152	spin_lock_irqsave(&desc->lock, flags);
6b39ba77 TG	153	for_each_online_cpu(j)
6b39ba77 TG	154	any_count \|= kstat_irqs_cpu(i, j);
6b39ba77 TG	155	action = desc->action;
	156	if (!action && !any_count)
	157	goto out;
	158
7a81d9a7	159	seq_printf(p, "%*d: ", prec, i);
6b39ba77 TG	160	for_each_online_cpu(j)
6b39ba77 TG	161	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
6b39ba77 TG	162	seq_printf(p, " %8s", desc->chip->name);
	163	seq_printf(p, "-%-8s", desc->name);
	164
	165	if (action) {
	166	seq_printf(p, " %s", action->name);
	167	while ((action = action->next) != NULL)
	168	seq_printf(p, ", %s", action->name);
	169	}
	170
	171	seq_putc(p, '\n');
	172	out:
	173	spin_unlock_irqrestore(&desc->lock, flags);
	174	return 0;
	175	}
	176
	177	/*
	178	* /proc/stat helpers
	179	*/
	180	u64 arch_irq_stat_cpu(unsigned int cpu)
	181	{
	182	u64 sum = irq_stats(cpu)->__nmi_count;
	183
	184	#ifdef CONFIG_X86_LOCAL_APIC
	185	sum += irq_stats(cpu)->apic_timer_irqs;
474e56b8	186	sum += irq_stats(cpu)->irq_spurious_count;
241771ef	187	sum += irq_stats(cpu)->apic_perf_irqs;
b6276f35	188	sum += irq_stats(cpu)->apic_pending_irqs;
6b39ba77	189	#endif
4a4de9c7 DS	190	if (x86_platform_ipi_callback)
4a4de9c7 DS	191	sum += irq_stats(cpu)->x86_platform_ipis;
6b39ba77 TG	192	#ifdef CONFIG_SMP
	193	sum += irq_stats(cpu)->irq_resched_count;
	194	sum += irq_stats(cpu)->irq_call_count;
	195	sum += irq_stats(cpu)->irq_tlb_count;
	196	#endif
0444c9bd	197	#ifdef CONFIG_X86_THERMAL_VECTOR
6b39ba77	198	sum += irq_stats(cpu)->irq_thermal_count;
0444c9bd JB	199	#endif
0444c9bd JB	200	#ifdef CONFIG_X86_MCE_THRESHOLD
6b39ba77	201	sum += irq_stats(cpu)->irq_threshold_count;
8051dbd2	202	#endif
c1ebf835	203	#ifdef CONFIG_X86_MCE
8051dbd2 HS	204	sum += per_cpu(mce_exception_count, cpu);
8051dbd2 HS	205	sum += per_cpu(mce_poll_count, cpu);
6b39ba77 TG	206	#endif
	207	return sum;
	208	}
	209
	210	u64 arch_irq_stat(void)
	211	{
	212	u64 sum = atomic_read(&irq_err_count);
	213
	214	#ifdef CONFIG_X86_IO_APIC
	215	sum += atomic_read(&irq_mis_count);
	216	#endif
	217	return sum;
	218	}
c3d80000	219
7c1d7cdc JF	220
	221	/*
	222	* do_IRQ handles all normal device IRQ's (the special
	223	* SMP cross-CPU interrupts have their own specific
	224	* handlers).
	225	*/
	226	unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
	227	{
	228	struct pt_regs *old_regs = set_irq_regs(regs);
	229
	230	/* high bit used in ret_from_ code */
	231	unsigned vector = ~regs->orig_ax;
	232	unsigned irq;
	233
	234	exit_idle();
	235	irq_enter();
	236
	237	irq = __get_cpu_var(vector_irq)[vector];
	238
	239	if (!handle_irq(irq, regs)) {
08306ce6	240	ack_APIC_irq();
7c1d7cdc JF	241
7c1d7cdc JF	242	if (printk_ratelimit())
edea7148 CG	243	pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
edea7148 CG	244	__func__, smp_processor_id(), vector, irq);
7c1d7cdc JF	245	}
	246
	247	irq_exit();
	248
	249	set_irq_regs(old_regs);
	250	return 1;
	251	}
	252
acaabe79	253	/*
4a4de9c7	254	* Handler for X86_PLATFORM_IPI_VECTOR.
acaabe79	255	*/
4a4de9c7	256	void smp_x86_platform_ipi(struct pt_regs *regs)
acaabe79 DS	257	{
	258	struct pt_regs *old_regs = set_irq_regs(regs);
	259
	260	ack_APIC_irq();
	261
	262	exit_idle();
	263
	264	irq_enter();
	265
4a4de9c7	266	inc_irq_stat(x86_platform_ipis);
acaabe79	267
4a4de9c7 DS	268	if (x86_platform_ipi_callback)
4a4de9c7 DS	269	x86_platform_ipi_callback();
acaabe79 DS	270
	271	irq_exit();
	272
	273	set_irq_regs(old_regs);
	274	}
	275
c3d80000	276	EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
7a7732bc SS	277
	278	#ifdef CONFIG_HOTPLUG_CPU
	279	/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
	280	void fixup_irqs(void)
	281	{
5231a686	282	unsigned int irq, vector;
7a7732bc SS	283	static int warned;
	284	struct irq_desc *desc;
	285
	286	for_each_irq_desc(irq, desc) {
	287	int break_affinity = 0;
	288	int set_affinity = 1;
	289	const struct cpumask *affinity;
	290
	291	if (!desc)
	292	continue;
	293	if (irq == 2)
	294	continue;
	295
	296	/* interrupt's are disabled at this point */
	297	spin_lock(&desc->lock);
	298
	299	affinity = desc->affinity;
	300	if (!irq_has_action(irq) \|\|
	301	cpumask_equal(affinity, cpu_online_mask)) {
	302	spin_unlock(&desc->lock);
	303	continue;
	304	}
	305
a5e74b84 SS	306	/*
	307	* Complete the irq move. This cpu is going down and for
	308	* non intr-remapping case, we can't wait till this interrupt
	309	* arrives at this cpu before completing the irq move.
	310	*/
	311	irq_force_complete_move(irq);
	312
7a7732bc SS	313	if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
	314	break_affinity = 1;
	315	affinity = cpu_all_mask;
	316	}
	317
84e21493	318	if (!(desc->status & IRQ_MOVE_PCNTXT) && desc->chip->mask)
7a7732bc SS	319	desc->chip->mask(irq);
	320
	321	if (desc->chip->set_affinity)
	322	desc->chip->set_affinity(irq, affinity);
	323	else if (!(warned++))
	324	set_affinity = 0;
	325
84e21493	326	if (!(desc->status & IRQ_MOVE_PCNTXT) && desc->chip->unmask)
7a7732bc SS	327	desc->chip->unmask(irq);
	328
	329	spin_unlock(&desc->lock);
	330
	331	if (break_affinity && set_affinity)
	332	printk("Broke affinity for irq %i\n", irq);
	333	else if (!set_affinity)
	334	printk("Cannot set affinity for irq %i\n", irq);
	335	}
	336
5231a686 SS	337	/*
	338	* We can remove mdelay() and then send spuriuous interrupts to
	339	* new cpu targets for all the irqs that were handled previously by
	340	* this cpu. While it works, I have seen spurious interrupt messages
	341	* (nothing wrong but still...).
	342	*
	343	* So for now, retain mdelay(1) and check the IRR and then send those
	344	* interrupts to new targets as this cpu is already offlined...
	345	*/
7a7732bc	346	mdelay(1);
5231a686 SS	347
	348	for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
	349	unsigned int irr;
	350
	351	if (__get_cpu_var(vector_irq)[vector] < 0)
	352	continue;
	353
	354	irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
	355	if (irr & (1 << (vector % 32))) {
	356	irq = __get_cpu_var(vector_irq)[vector];
	357
	358	desc = irq_to_desc(irq);
	359	spin_lock(&desc->lock);
	360	if (desc->chip->retrigger)
	361	desc->chip->retrigger(irq);
	362	spin_unlock(&desc->lock);
	363	}
	364	}
7a7732bc SS	365	}
7a7732bc SS	366	#endif