Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
644c1541 VP |
71 | #include <asm/i387.h> |
72 | #include <asm/fpu-internal.h> | |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
48927bbb | 77 | #include <asm/realmode.h> |
646e29a1 | 78 | #include <asm/misc.h> |
48927bbb | 79 | |
a8db8453 GOC |
80 | /* State of each CPU */ |
81 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
82 | ||
a355352b GC |
83 | /* Number of siblings per CPU package */ |
84 | int smp_num_siblings = 1; | |
85 | EXPORT_SYMBOL(smp_num_siblings); | |
86 | ||
87 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 89 | |
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
0816b0f0 | 98 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 99 | |
a355352b | 100 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 101 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 102 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 103 | |
2b6163bf | 104 | atomic_t init_deasserted; |
cb3c8b90 | 105 | |
f77aa308 TG |
106 | static inline void smpboot_clear_io_apic_irqs(void) |
107 | { | |
108 | #ifdef CONFIG_X86_IO_APIC | |
109 | io_apic_irqs = 0; | |
110 | #endif | |
111 | } | |
112 | ||
113 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) | |
114 | { | |
115 | unsigned long flags; | |
116 | ||
117 | spin_lock_irqsave(&rtc_lock, flags); | |
118 | CMOS_WRITE(0xa, 0xf); | |
119 | spin_unlock_irqrestore(&rtc_lock, flags); | |
120 | local_flush_tlb(); | |
121 | pr_debug("1.\n"); | |
122 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
123 | start_eip >> 4; | |
124 | pr_debug("2.\n"); | |
125 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
126 | start_eip & 0xf; | |
127 | pr_debug("3.\n"); | |
128 | } | |
129 | ||
130 | static inline void smpboot_restore_warm_reset_vector(void) | |
131 | { | |
132 | unsigned long flags; | |
133 | ||
134 | /* | |
135 | * Install writable page 0 entry to set BIOS data area. | |
136 | */ | |
137 | local_flush_tlb(); | |
138 | ||
139 | /* | |
140 | * Paranoid: Set warm reset code and vector here back | |
141 | * to default values. | |
142 | */ | |
143 | spin_lock_irqsave(&rtc_lock, flags); | |
144 | CMOS_WRITE(0, 0xf); | |
145 | spin_unlock_irqrestore(&rtc_lock, flags); | |
146 | ||
147 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
148 | } | |
149 | ||
150 | static inline void __init smpboot_setup_io_apic(void) | |
151 | { | |
152 | #ifdef CONFIG_X86_IO_APIC | |
153 | /* | |
154 | * Here we can be sure that there is an IO-APIC in the system. Let's | |
155 | * go and set it up: | |
156 | */ | |
157 | if (!skip_ioapic_setup && nr_ioapics) | |
158 | setup_IO_APIC(); | |
159 | else | |
160 | nr_ioapics = 0; | |
161 | #endif | |
162 | } | |
163 | ||
164 | static inline void smpboot_clear_io_apic(void) | |
165 | { | |
166 | #ifdef CONFIG_X86_IO_APIC | |
167 | nr_ioapics = 0; | |
168 | #endif | |
169 | } | |
170 | ||
cb3c8b90 | 171 | /* |
30106c17 FY |
172 | * Report back to the Boot Processor during boot time or to the caller processor |
173 | * during CPU online. | |
cb3c8b90 | 174 | */ |
148f9bb8 | 175 | static void smp_callin(void) |
cb3c8b90 GOC |
176 | { |
177 | int cpuid, phys_id; | |
cb3c8b90 GOC |
178 | |
179 | /* | |
180 | * If waken up by an INIT in an 82489DX configuration | |
181 | * we may get here before an INIT-deassert IPI reaches | |
182 | * our local APIC. We have to wait for the IPI or we'll | |
183 | * lock up on an APIC access. | |
e1c467e6 FY |
184 | * |
185 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 186 | */ |
e1c467e6 | 187 | cpuid = smp_processor_id(); |
465822cf DR |
188 | if (apic->wait_for_init_deassert && cpuid) |
189 | while (!atomic_read(&init_deasserted)) | |
190 | cpu_relax(); | |
cb3c8b90 GOC |
191 | |
192 | /* | |
193 | * (This works even if the APIC is not enabled.) | |
194 | */ | |
4c9961d5 | 195 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
196 | |
197 | /* | |
198 | * the boot CPU has finished the init stage and is spinning | |
199 | * on callin_map until we finish. We are free to set up this | |
200 | * CPU, first the APIC. (this is probably redundant on most | |
201 | * boards) | |
202 | */ | |
cb3c8b90 GOC |
203 | setup_local_APIC(); |
204 | end_local_APIC_setup(); | |
cb3c8b90 | 205 | |
9d133e5d SS |
206 | /* |
207 | * Need to setup vector mappings before we enable interrupts. | |
208 | */ | |
36e9e1ea | 209 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
210 | |
211 | /* | |
212 | * Save our processor parameters. Note: this information | |
213 | * is needed for clock calibration. | |
214 | */ | |
215 | smp_store_cpu_info(cpuid); | |
216 | ||
cb3c8b90 GOC |
217 | /* |
218 | * Get our bogomips. | |
b565201c JS |
219 | * Update loops_per_jiffy in cpu_data. Previous call to |
220 | * smp_store_cpu_info() stored a value that is close but not as | |
221 | * accurate as the value just calculated. | |
cb3c8b90 | 222 | */ |
cb3c8b90 | 223 | calibrate_delay(); |
b565201c | 224 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 225 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 226 | |
5ef428c4 AK |
227 | /* |
228 | * This must be done before setting cpu_online_mask | |
229 | * or calling notify_cpu_starting. | |
230 | */ | |
231 | set_cpu_sibling_map(raw_smp_processor_id()); | |
232 | wmb(); | |
233 | ||
85257024 PZ |
234 | notify_cpu_starting(cpuid); |
235 | ||
cb3c8b90 GOC |
236 | /* |
237 | * Allow the master to continue. | |
238 | */ | |
c2d1cec1 | 239 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
240 | } |
241 | ||
e1c467e6 FY |
242 | static int cpu0_logical_apicid; |
243 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
244 | /* |
245 | * Activate a secondary processor. | |
246 | */ | |
148f9bb8 | 247 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
248 | { |
249 | /* | |
250 | * Don't put *anything* before cpu_init(), SMP booting is too | |
251 | * fragile that we want to limit the things done here to the | |
252 | * most necessary things. | |
253 | */ | |
b40827fa | 254 | cpu_init(); |
df156f90 | 255 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
256 | preempt_disable(); |
257 | smp_callin(); | |
fd89a137 | 258 | |
e1c467e6 FY |
259 | enable_start_cpu0 = 0; |
260 | ||
fd89a137 | 261 | #ifdef CONFIG_X86_32 |
b40827fa | 262 | /* switch away from the initial page table */ |
fd89a137 JR |
263 | load_cr3(swapper_pg_dir); |
264 | __flush_tlb_all(); | |
265 | #endif | |
266 | ||
bbc2ff6a GOC |
267 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
268 | barrier(); | |
269 | /* | |
270 | * Check TSC synchronization with the BP: | |
271 | */ | |
272 | check_tsc_sync_target(); | |
273 | ||
3891a04a PA |
274 | /* |
275 | * Enable the espfix hack for this CPU | |
276 | */ | |
197725de | 277 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a PA |
278 | init_espfix_ap(); |
279 | #endif | |
280 | ||
bbc2ff6a | 281 | /* |
d388e5fd EB |
282 | * We need to hold vector_lock so there the set of online cpus |
283 | * does not change while we are assigning vectors to cpus. Holding | |
284 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 285 | */ |
d388e5fd | 286 | lock_vector_lock(); |
c2d1cec1 | 287 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 288 | unlock_vector_lock(); |
bbc2ff6a | 289 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 290 | x86_platform.nmi_init(); |
bbc2ff6a | 291 | |
0cefa5b9 MS |
292 | /* enable local interrupts */ |
293 | local_irq_enable(); | |
294 | ||
35f720c5 JP |
295 | /* to prevent fake stack check failure in clock setup */ |
296 | boot_init_stack_canary(); | |
0cefa5b9 | 297 | |
736decac | 298 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
299 | |
300 | wmb(); | |
7d1a9417 | 301 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
302 | } |
303 | ||
30106c17 FY |
304 | void __init smp_store_boot_cpu_info(void) |
305 | { | |
306 | int id = 0; /* CPU 0 */ | |
307 | struct cpuinfo_x86 *c = &cpu_data(id); | |
308 | ||
309 | *c = boot_cpu_data; | |
310 | c->cpu_index = id; | |
311 | } | |
312 | ||
1d89a7f0 GOC |
313 | /* |
314 | * The bootstrap kernel entry code has set these up. Save them for | |
315 | * a given CPU | |
316 | */ | |
148f9bb8 | 317 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
318 | { |
319 | struct cpuinfo_x86 *c = &cpu_data(id); | |
320 | ||
b3d7336d | 321 | *c = boot_cpu_data; |
1d89a7f0 | 322 | c->cpu_index = id; |
30106c17 FY |
323 | /* |
324 | * During boot time, CPU0 has this setup already. Save the info when | |
325 | * bringing up AP or offlined CPU0. | |
326 | */ | |
327 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
328 | } |
329 | ||
cebf15eb DH |
330 | static bool |
331 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
332 | { | |
333 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
334 | ||
335 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
336 | } | |
337 | ||
148f9bb8 | 338 | static bool |
316ad248 | 339 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 340 | { |
316ad248 PZ |
341 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
342 | ||
cebf15eb | 343 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
344 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
345 | "[node: %d != %d]. Ignoring dependency.\n", | |
346 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
347 | } | |
348 | ||
349 | #define link_mask(_m, c1, c2) \ | |
350 | do { \ | |
351 | cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ | |
352 | cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ | |
353 | } while (0) | |
354 | ||
148f9bb8 | 355 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 356 | { |
193f3fcb | 357 | if (cpu_has_topoext) { |
316ad248 PZ |
358 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
359 | ||
360 | if (c->phys_proc_id == o->phys_proc_id && | |
361 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
362 | c->compute_unit_id == o->compute_unit_id) | |
363 | return topology_sane(c, o, "smt"); | |
364 | ||
365 | } else if (c->phys_proc_id == o->phys_proc_id && | |
366 | c->cpu_core_id == o->cpu_core_id) { | |
367 | return topology_sane(c, o, "smt"); | |
368 | } | |
369 | ||
370 | return false; | |
371 | } | |
372 | ||
148f9bb8 | 373 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
374 | { |
375 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
376 | ||
377 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
378 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
379 | return topology_sane(c, o, "llc"); | |
380 | ||
381 | return false; | |
d4fbe4f0 AH |
382 | } |
383 | ||
cebf15eb DH |
384 | /* |
385 | * Unlike the other levels, we do not enforce keeping a | |
386 | * multicore group inside a NUMA node. If this happens, we will | |
387 | * discard the MC level of the topology later. | |
388 | */ | |
389 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 390 | { |
cebf15eb DH |
391 | if (c->phys_proc_id == o->phys_proc_id) |
392 | return true; | |
316ad248 PZ |
393 | return false; |
394 | } | |
1d89a7f0 | 395 | |
cebf15eb DH |
396 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
397 | #ifdef CONFIG_SCHED_SMT | |
398 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
399 | #endif | |
400 | #ifdef CONFIG_SCHED_MC | |
401 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
402 | #endif | |
403 | { NULL, }, | |
404 | }; | |
405 | /* | |
406 | * set_sched_topology() sets the topology internal to a CPU. The | |
407 | * NUMA topologies are layered on top of it to build the full | |
408 | * system topology. | |
409 | * | |
410 | * If NUMA nodes are observed to occur within a CPU package, this | |
411 | * function should be called. It forces the sched domain code to | |
412 | * only use the SMT level for the CPU portion of the topology. | |
413 | * This essentially falls back to relying on NUMA information | |
414 | * from the SRAT table to describe the entire system topology | |
415 | * (except for hyperthreads). | |
416 | */ | |
417 | static void primarily_use_numa_for_topology(void) | |
418 | { | |
419 | set_sched_topology(numa_inside_package_topology); | |
420 | } | |
421 | ||
148f9bb8 | 422 | void set_cpu_sibling_map(int cpu) |
768d9505 | 423 | { |
316ad248 | 424 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 425 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 426 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
427 | struct cpuinfo_x86 *o; |
428 | int i; | |
768d9505 | 429 | |
c2d1cec1 | 430 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 431 | |
b0bc225d | 432 | if (!has_mp) { |
c2d1cec1 | 433 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
316ad248 PZ |
434 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
435 | cpumask_set_cpu(cpu, cpu_core_mask(cpu)); | |
768d9505 GC |
436 | c->booted_cores = 1; |
437 | return; | |
438 | } | |
439 | ||
c2d1cec1 | 440 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
441 | o = &cpu_data(i); |
442 | ||
443 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
444 | link_mask(sibling, cpu, i); | |
445 | ||
b0bc225d | 446 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
316ad248 PZ |
447 | link_mask(llc_shared, cpu, i); |
448 | ||
ceb1cbac KB |
449 | } |
450 | ||
451 | /* | |
452 | * This needs a separate iteration over the cpus because we rely on all | |
453 | * cpu_sibling_mask links to be set-up. | |
454 | */ | |
455 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
456 | o = &cpu_data(i); | |
457 | ||
cebf15eb | 458 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
316ad248 PZ |
459 | link_mask(core, cpu, i); |
460 | ||
768d9505 GC |
461 | /* |
462 | * Does this new cpu bringup a new core? | |
463 | */ | |
c2d1cec1 | 464 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
465 | /* |
466 | * for each core in package, increment | |
467 | * the booted_cores for this new cpu | |
468 | */ | |
c2d1cec1 | 469 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
470 | c->booted_cores++; |
471 | /* | |
472 | * increment the core count for all | |
473 | * the other cpus in this package | |
474 | */ | |
475 | if (i != cpu) | |
476 | cpu_data(i).booted_cores++; | |
477 | } else if (i != cpu && !c->booted_cores) | |
478 | c->booted_cores = cpu_data(i).booted_cores; | |
479 | } | |
728e5653 | 480 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 481 | primarily_use_numa_for_topology(); |
768d9505 GC |
482 | } |
483 | } | |
484 | ||
70708a18 | 485 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 486 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 487 | { |
9f646389 | 488 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
489 | } |
490 | ||
a4928cff | 491 | static void impress_friends(void) |
904541e2 GOC |
492 | { |
493 | int cpu; | |
494 | unsigned long bogosum = 0; | |
495 | /* | |
496 | * Allow the user to impress friends. | |
497 | */ | |
c767a54b | 498 | pr_debug("Before bogomips\n"); |
904541e2 | 499 | for_each_possible_cpu(cpu) |
c2d1cec1 | 500 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 501 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 502 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 503 | num_online_cpus(), |
904541e2 GOC |
504 | bogosum/(500000/HZ), |
505 | (bogosum/(5000/HZ))%100); | |
506 | ||
c767a54b | 507 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
508 | } |
509 | ||
569712b2 | 510 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
511 | { |
512 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 513 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
514 | int timeout; |
515 | u32 status; | |
516 | ||
c767a54b | 517 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
518 | |
519 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 520 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
521 | |
522 | /* | |
523 | * Wait for idle. | |
524 | */ | |
525 | status = safe_apic_wait_icr_idle(); | |
526 | if (status) | |
c767a54b | 527 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 528 | |
1b374e4d | 529 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
530 | |
531 | timeout = 0; | |
532 | do { | |
533 | udelay(100); | |
534 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
535 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
536 | ||
537 | switch (status) { | |
538 | case APIC_ICR_RR_VALID: | |
539 | status = apic_read(APIC_RRR); | |
c767a54b | 540 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
541 | break; |
542 | default: | |
c767a54b | 543 | pr_cont("failed\n"); |
cb3c8b90 GOC |
544 | } |
545 | } | |
546 | } | |
547 | ||
cb3c8b90 GOC |
548 | /* |
549 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
550 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
551 | * won't ... remember to clear down the APIC, etc later. | |
552 | */ | |
148f9bb8 | 553 | int |
e1c467e6 | 554 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
555 | { |
556 | unsigned long send_status, accept_status = 0; | |
557 | int maxlvt; | |
558 | ||
559 | /* Target chip */ | |
cb3c8b90 GOC |
560 | /* Boot on the stack */ |
561 | /* Kick the second */ | |
e1c467e6 | 562 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 563 | |
cfc1b9a6 | 564 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
565 | send_status = safe_apic_wait_icr_idle(); |
566 | ||
567 | /* | |
568 | * Give the other CPU some time to accept the IPI. | |
569 | */ | |
570 | udelay(200); | |
569712b2 | 571 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
572 | maxlvt = lapic_get_maxlvt(); |
573 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
574 | apic_write(APIC_ESR, 0); | |
575 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
576 | } | |
c767a54b | 577 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
578 | |
579 | if (send_status) | |
c767a54b | 580 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 581 | if (accept_status) |
c767a54b | 582 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
583 | |
584 | return (send_status | accept_status); | |
585 | } | |
cb3c8b90 | 586 | |
148f9bb8 | 587 | static int |
569712b2 | 588 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
589 | { |
590 | unsigned long send_status, accept_status = 0; | |
591 | int maxlvt, num_starts, j; | |
592 | ||
593f4a78 MR |
593 | maxlvt = lapic_get_maxlvt(); |
594 | ||
cb3c8b90 GOC |
595 | /* |
596 | * Be paranoid about clearing APIC errors. | |
597 | */ | |
598 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
599 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
600 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
601 | apic_read(APIC_ESR); |
602 | } | |
603 | ||
c767a54b | 604 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
605 | |
606 | /* | |
607 | * Turn INIT on target chip | |
608 | */ | |
cb3c8b90 GOC |
609 | /* |
610 | * Send IPI | |
611 | */ | |
1b374e4d SS |
612 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
613 | phys_apicid); | |
cb3c8b90 | 614 | |
cfc1b9a6 | 615 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
616 | send_status = safe_apic_wait_icr_idle(); |
617 | ||
618 | mdelay(10); | |
619 | ||
c767a54b | 620 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
621 | |
622 | /* Target chip */ | |
cb3c8b90 | 623 | /* Send IPI */ |
1b374e4d | 624 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 625 | |
cfc1b9a6 | 626 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
627 | send_status = safe_apic_wait_icr_idle(); |
628 | ||
629 | mb(); | |
630 | atomic_set(&init_deasserted, 1); | |
631 | ||
632 | /* | |
633 | * Should we send STARTUP IPIs ? | |
634 | * | |
635 | * Determine this based on the APIC version. | |
636 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
637 | */ | |
638 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
639 | num_starts = 2; | |
640 | else | |
641 | num_starts = 0; | |
642 | ||
643 | /* | |
644 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
645 | * target processor state. | |
646 | */ | |
647 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 648 | stack_start); |
cb3c8b90 GOC |
649 | |
650 | /* | |
651 | * Run STARTUP IPI loop. | |
652 | */ | |
c767a54b | 653 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 654 | |
cb3c8b90 | 655 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 656 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
657 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
658 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 659 | apic_read(APIC_ESR); |
c767a54b | 660 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
661 | |
662 | /* | |
663 | * STARTUP IPI | |
664 | */ | |
665 | ||
666 | /* Target chip */ | |
cb3c8b90 GOC |
667 | /* Boot on the stack */ |
668 | /* Kick the second */ | |
1b374e4d SS |
669 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
670 | phys_apicid); | |
cb3c8b90 GOC |
671 | |
672 | /* | |
673 | * Give the other CPU some time to accept the IPI. | |
674 | */ | |
675 | udelay(300); | |
676 | ||
c767a54b | 677 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 678 | |
cfc1b9a6 | 679 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
680 | send_status = safe_apic_wait_icr_idle(); |
681 | ||
682 | /* | |
683 | * Give the other CPU some time to accept the IPI. | |
684 | */ | |
685 | udelay(200); | |
593f4a78 | 686 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 687 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
688 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
689 | if (send_status || accept_status) | |
690 | break; | |
691 | } | |
c767a54b | 692 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
693 | |
694 | if (send_status) | |
c767a54b | 695 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 696 | if (accept_status) |
c767a54b | 697 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
698 | |
699 | return (send_status | accept_status); | |
700 | } | |
cb3c8b90 | 701 | |
a17bce4d BP |
702 | void smp_announce(void) |
703 | { | |
704 | int num_nodes = num_online_nodes(); | |
705 | ||
706 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
707 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
708 | } | |
709 | ||
2eaad1fd | 710 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 711 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
712 | { |
713 | static int current_node = -1; | |
4adc8b71 | 714 | int node = early_cpu_to_node(cpu); |
a17bce4d | 715 | static int width, node_width; |
646e29a1 BP |
716 | |
717 | if (!width) | |
718 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 719 | |
a17bce4d BP |
720 | if (!node_width) |
721 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
722 | ||
723 | if (cpu == 1) | |
724 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
725 | ||
2eaad1fd MT |
726 | if (system_state == SYSTEM_BOOTING) { |
727 | if (node != current_node) { | |
728 | if (current_node > (-1)) | |
a17bce4d | 729 | pr_cont("\n"); |
2eaad1fd | 730 | current_node = node; |
a17bce4d BP |
731 | |
732 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
733 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 734 | } |
646e29a1 BP |
735 | |
736 | /* Add padding for the BSP */ | |
737 | if (cpu == 1) | |
738 | pr_cont("%*s", width + 1, " "); | |
739 | ||
740 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
741 | ||
2eaad1fd MT |
742 | } else |
743 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
744 | node, cpu, apicid); | |
745 | } | |
746 | ||
e1c467e6 FY |
747 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
748 | { | |
749 | int cpu; | |
750 | ||
751 | cpu = smp_processor_id(); | |
752 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
753 | return NMI_HANDLED; | |
754 | ||
755 | return NMI_DONE; | |
756 | } | |
757 | ||
758 | /* | |
759 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
760 | * | |
761 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
762 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
763 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
764 | * | |
765 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
766 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
767 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
768 | * real platform and request are available. | |
769 | */ | |
148f9bb8 | 770 | static int |
e1c467e6 FY |
771 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
772 | int *cpu0_nmi_registered) | |
773 | { | |
774 | int id; | |
775 | int boot_error; | |
776 | ||
ea7bdc65 JK |
777 | preempt_disable(); |
778 | ||
e1c467e6 FY |
779 | /* |
780 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
781 | */ | |
ea7bdc65 JK |
782 | if (cpu) { |
783 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
784 | goto out; | |
785 | } | |
e1c467e6 FY |
786 | |
787 | /* | |
788 | * Wake up BSP by nmi. | |
789 | * | |
790 | * Register a NMI handler to help wake up CPU0. | |
791 | */ | |
792 | boot_error = register_nmi_handler(NMI_LOCAL, | |
793 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
794 | ||
795 | if (!boot_error) { | |
796 | enable_start_cpu0 = 1; | |
797 | *cpu0_nmi_registered = 1; | |
798 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
799 | id = cpu0_logical_apicid; | |
800 | else | |
801 | id = apicid; | |
802 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
803 | } | |
ea7bdc65 JK |
804 | |
805 | out: | |
806 | preempt_enable(); | |
e1c467e6 FY |
807 | |
808 | return boot_error; | |
809 | } | |
810 | ||
cb3c8b90 GOC |
811 | /* |
812 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
813 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
814 | * Returns zero if CPU booted OK, else error code from |
815 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 816 | */ |
148f9bb8 | 817 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 818 | { |
48927bbb | 819 | volatile u32 *trampoline_status = |
b429dbf6 | 820 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 821 | /* start_ip had better be page-aligned! */ |
f37240f1 | 822 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 823 | |
cb3c8b90 | 824 | unsigned long boot_error = 0; |
e1c467e6 | 825 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 826 | unsigned long timeout; |
cb3c8b90 | 827 | |
816afe4f RR |
828 | /* Just in case we booted with a single CPU. */ |
829 | alternatives_enable_smp(); | |
cb3c8b90 | 830 | |
7eb43a6d TG |
831 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
832 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
833 | per_cpu(current_task, cpu) = idle; | |
cb3c8b90 | 834 | |
c6f5e0ac | 835 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 836 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
837 | irq_ctx_init(cpu); |
838 | #else | |
7eb43a6d | 839 | clear_tsk_thread_flag(idle, TIF_FORK); |
004aa322 | 840 | initial_gs = per_cpu_offset(cpu); |
198d208d | 841 | #endif |
9af45651 | 842 | per_cpu(kernel_stack, cpu) = |
7eb43a6d | 843 | (unsigned long)task_stack_page(idle) - |
9af45651 | 844 | KERNEL_STACK_OFFSET + THREAD_SIZE; |
a939098a | 845 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 846 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 847 | stack_start = idle->thread.sp; |
cb3c8b90 | 848 | |
2eaad1fd MT |
849 | /* So we see what's up */ |
850 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
851 | |
852 | /* | |
853 | * This grunge runs the startup process for | |
854 | * the targeted processor. | |
855 | */ | |
856 | ||
857 | atomic_set(&init_deasserted, 0); | |
858 | ||
34d05591 | 859 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 860 | |
cfc1b9a6 | 861 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 862 | |
34d05591 JS |
863 | smpboot_setup_warm_reset_vector(start_ip); |
864 | /* | |
865 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
866 | */ |
867 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
868 | apic_write(APIC_ESR, 0); | |
869 | apic_read(APIC_ESR); | |
870 | } | |
34d05591 | 871 | } |
cb3c8b90 | 872 | |
ce4b1b16 IM |
873 | /* |
874 | * AP might wait on cpu_callout_mask in cpu_init() with | |
875 | * cpu_initialized_mask set if previous attempt to online | |
876 | * it timed-out. Clear cpu_initialized_mask so that after | |
877 | * INIT/SIPI it could start with a clean state. | |
878 | */ | |
879 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
880 | smp_mb(); | |
881 | ||
cb3c8b90 | 882 | /* |
e1c467e6 FY |
883 | * Wake up a CPU in difference cases: |
884 | * - Use the method in the APIC driver if it's defined | |
885 | * Otherwise, | |
886 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 887 | */ |
1f5bcabf IM |
888 | if (apic->wakeup_secondary_cpu) |
889 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
890 | else | |
e1c467e6 FY |
891 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
892 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
893 | |
894 | if (!boot_error) { | |
895 | /* | |
ce4b1b16 | 896 | * Wait 10s total for a response from AP |
cb3c8b90 | 897 | */ |
ce4b1b16 IM |
898 | boot_error = -1; |
899 | timeout = jiffies + 10*HZ; | |
900 | while (time_before(jiffies, timeout)) { | |
901 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
902 | /* | |
903 | * Tell AP to proceed with initialization | |
904 | */ | |
905 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
906 | boot_error = 0; | |
907 | break; | |
908 | } | |
909 | udelay(100); | |
910 | schedule(); | |
911 | } | |
912 | } | |
cb3c8b90 | 913 | |
ce4b1b16 | 914 | if (!boot_error) { |
cb3c8b90 | 915 | /* |
ce4b1b16 | 916 | * Wait till AP completes initial initialization |
cb3c8b90 | 917 | */ |
ce4b1b16 | 918 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
919 | /* |
920 | * Allow other tasks to run while we wait for the | |
921 | * AP to come online. This also gives a chance | |
922 | * for the MTRR work(triggered by the AP coming online) | |
923 | * to be completed in the stop machine context. | |
924 | */ | |
ce4b1b16 | 925 | udelay(100); |
68f202e4 | 926 | schedule(); |
cb3c8b90 | 927 | } |
cb3c8b90 GOC |
928 | } |
929 | ||
930 | /* mark "stuck" area as not stuck */ | |
48927bbb | 931 | *trampoline_status = 0; |
cb3c8b90 | 932 | |
02421f98 YL |
933 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
934 | /* | |
935 | * Cleanup possible dangling ends... | |
936 | */ | |
937 | smpboot_restore_warm_reset_vector(); | |
938 | } | |
e1c467e6 FY |
939 | /* |
940 | * Clean up the nmi handler. Do this after the callin and callout sync | |
941 | * to avoid impact of possible long unregister time. | |
942 | */ | |
943 | if (cpu0_nmi_registered) | |
944 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
945 | ||
cb3c8b90 GOC |
946 | return boot_error; |
947 | } | |
948 | ||
148f9bb8 | 949 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 950 | { |
a21769a4 | 951 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
952 | unsigned long flags; |
953 | int err; | |
954 | ||
955 | WARN_ON(irqs_disabled()); | |
956 | ||
cfc1b9a6 | 957 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 958 | |
30106c17 | 959 | if (apicid == BAD_APICID || |
c284b42a | 960 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 961 | !apic->apic_id_valid(apicid)) { |
c767a54b | 962 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
963 | return -EINVAL; |
964 | } | |
965 | ||
966 | /* | |
967 | * Already booted CPU? | |
968 | */ | |
c2d1cec1 | 969 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 970 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
971 | return -ENOSYS; |
972 | } | |
973 | ||
974 | /* | |
975 | * Save current MTRR state in case it was changed since early boot | |
976 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
977 | */ | |
978 | mtrr_save_state(); | |
979 | ||
980 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
981 | ||
644c1541 VP |
982 | /* the FPU context is blank, nobody can own it */ |
983 | __cpu_disable_lazy_restore(cpu); | |
984 | ||
7eb43a6d | 985 | err = do_boot_cpu(apicid, cpu, tidle); |
61165d7a | 986 | if (err) { |
feef1e8e | 987 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 988 | return -EIO; |
cb3c8b90 GOC |
989 | } |
990 | ||
991 | /* | |
992 | * Check TSC synchronization with the AP (keep irqs disabled | |
993 | * while doing so): | |
994 | */ | |
995 | local_irq_save(flags); | |
996 | check_tsc_sync_source(cpu); | |
997 | local_irq_restore(flags); | |
998 | ||
7c04e64a | 999 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1000 | cpu_relax(); |
1001 | touch_nmi_watchdog(); | |
1002 | } | |
1003 | ||
1004 | return 0; | |
1005 | } | |
1006 | ||
7167d08e HK |
1007 | /** |
1008 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1009 | */ | |
1010 | void arch_disable_smp_support(void) | |
1011 | { | |
1012 | disable_ioapic_support(); | |
1013 | } | |
1014 | ||
8aef135c GOC |
1015 | /* |
1016 | * Fall back to non SMP mode after errors. | |
1017 | * | |
1018 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1019 | */ | |
1020 | static __init void disable_smp(void) | |
1021 | { | |
4f062896 RR |
1022 | init_cpu_present(cpumask_of(0)); |
1023 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 1024 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 1025 | |
8aef135c | 1026 | if (smp_found_config) |
b6df1b8b | 1027 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1028 | else |
b6df1b8b | 1029 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
1030 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
1031 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
1032 | } |
1033 | ||
1034 | /* | |
1035 | * Various sanity checks. | |
1036 | */ | |
1037 | static int __init smp_sanity_check(unsigned max_cpus) | |
1038 | { | |
ac23d4ee | 1039 | preempt_disable(); |
a58f03b0 | 1040 | |
1ff2f20d | 1041 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1042 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1043 | unsigned int cpu; | |
1044 | unsigned nr; | |
1045 | ||
c767a54b JP |
1046 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1047 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1048 | |
1049 | nr = 0; | |
1050 | for_each_present_cpu(cpu) { | |
1051 | if (nr >= 8) | |
c2d1cec1 | 1052 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1053 | nr++; |
1054 | } | |
1055 | ||
1056 | nr = 0; | |
1057 | for_each_possible_cpu(cpu) { | |
1058 | if (nr >= 8) | |
c2d1cec1 | 1059 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1060 | nr++; |
1061 | } | |
1062 | ||
1063 | nr_cpu_ids = 8; | |
1064 | } | |
1065 | #endif | |
1066 | ||
8aef135c | 1067 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1068 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1069 | hard_smp_processor_id()); |
1070 | ||
8aef135c GOC |
1071 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * If we couldn't find an SMP configuration at boot time, | |
1076 | * get out of here now! | |
1077 | */ | |
1078 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1079 | preempt_enable(); |
c767a54b | 1080 | pr_notice("SMP motherboard not detected\n"); |
8aef135c GOC |
1081 | disable_smp(); |
1082 | if (APIC_init_uniprocessor()) | |
c767a54b | 1083 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
8aef135c GOC |
1084 | return -1; |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Should not be necessary because the MP table should list the boot | |
1089 | * CPU too, but we do it for the sake of robustness anyway. | |
1090 | */ | |
a27a6210 | 1091 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1092 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1093 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1094 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1095 | } | |
ac23d4ee | 1096 | preempt_enable(); |
8aef135c GOC |
1097 | |
1098 | /* | |
1099 | * If we couldn't find a local APIC, then get out of here now! | |
1100 | */ | |
1101 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1102 | !cpu_has_apic) { | |
103428e5 CG |
1103 | if (!disable_apic) { |
1104 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1105 | boot_cpu_physical_apicid); | |
c767a54b | 1106 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1107 | } |
8aef135c | 1108 | smpboot_clear_io_apic(); |
7167d08e | 1109 | disable_ioapic_support(); |
8aef135c GOC |
1110 | return -1; |
1111 | } | |
1112 | ||
1113 | verify_local_APIC(); | |
1114 | ||
1115 | /* | |
1116 | * If SMP should be disabled, then really disable it! | |
1117 | */ | |
1118 | if (!max_cpus) { | |
c767a54b | 1119 | pr_info("SMP mode deactivated\n"); |
8aef135c | 1120 | smpboot_clear_io_apic(); |
d54db1ac | 1121 | |
e90955c2 | 1122 | connect_bsp_APIC(); |
e90955c2 | 1123 | setup_local_APIC(); |
2fb270f3 | 1124 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1125 | return -1; |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
1131 | static void __init smp_cpu_index_default(void) | |
1132 | { | |
1133 | int i; | |
1134 | struct cpuinfo_x86 *c; | |
1135 | ||
7c04e64a | 1136 | for_each_possible_cpu(i) { |
8aef135c GOC |
1137 | c = &cpu_data(i); |
1138 | /* mark all to hotplug */ | |
9628937d | 1139 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1140 | } |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1145 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1146 | */ | |
1147 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1148 | { | |
7ad728f9 RR |
1149 | unsigned int i; |
1150 | ||
8aef135c | 1151 | smp_cpu_index_default(); |
792363d2 | 1152 | |
8aef135c GOC |
1153 | /* |
1154 | * Setup boot CPU information | |
1155 | */ | |
30106c17 | 1156 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1157 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1158 | mb(); | |
bd22a2f1 | 1159 | |
8aef135c | 1160 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1161 | for_each_possible_cpu(i) { |
79f55997 LZ |
1162 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1163 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1164 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1165 | } |
8aef135c GOC |
1166 | set_cpu_sibling_map(0); |
1167 | ||
1168 | if (smp_sanity_check(max_cpus) < 0) { | |
c767a54b | 1169 | pr_info("SMP disabled\n"); |
8aef135c | 1170 | disable_smp(); |
250a1ac6 | 1171 | return; |
8aef135c GOC |
1172 | } |
1173 | ||
fa47f7e5 SS |
1174 | default_setup_apic_routing(); |
1175 | ||
4c9961d5 | 1176 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1177 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1178 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1179 | /* Or can we switch back to PIC here? */ |
1180 | } | |
1181 | ||
8aef135c | 1182 | connect_bsp_APIC(); |
b5841765 | 1183 | |
8aef135c GOC |
1184 | /* |
1185 | * Switch from PIC to APIC mode. | |
1186 | */ | |
1187 | setup_local_APIC(); | |
1188 | ||
e1c467e6 FY |
1189 | if (x2apic_mode) |
1190 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1191 | else | |
1192 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1193 | ||
8aef135c GOC |
1194 | /* |
1195 | * Enable IO APIC before setting up error vector | |
1196 | */ | |
1197 | if (!skip_ioapic_setup && nr_ioapics) | |
1198 | enable_IO_APIC(); | |
88d0f550 | 1199 | |
2fb270f3 | 1200 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
1201 | smpboot_setup_io_apic(); |
1202 | /* | |
1203 | * Set up local APIC timer on boot CPU. | |
1204 | */ | |
1205 | ||
c767a54b | 1206 | pr_info("CPU%d: ", 0); |
8aef135c | 1207 | print_cpu_info(&cpu_data(0)); |
736decac | 1208 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1209 | |
1210 | if (is_uv_system()) | |
1211 | uv_system_init(); | |
d0af9eed SS |
1212 | |
1213 | set_mtrr_aps_delayed_init(); | |
8aef135c | 1214 | } |
d0af9eed SS |
1215 | |
1216 | void arch_enable_nonboot_cpus_begin(void) | |
1217 | { | |
1218 | set_mtrr_aps_delayed_init(); | |
1219 | } | |
1220 | ||
1221 | void arch_enable_nonboot_cpus_end(void) | |
1222 | { | |
1223 | mtrr_aps_init(); | |
1224 | } | |
1225 | ||
a8db8453 GOC |
1226 | /* |
1227 | * Early setup to make printk work. | |
1228 | */ | |
1229 | void __init native_smp_prepare_boot_cpu(void) | |
1230 | { | |
1231 | int me = smp_processor_id(); | |
552be871 | 1232 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1233 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1234 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1235 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1236 | } | |
1237 | ||
83f7eb9c GOC |
1238 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1239 | { | |
c767a54b | 1240 | pr_debug("Boot done\n"); |
83f7eb9c | 1241 | |
99e8b9ca | 1242 | nmi_selftest(); |
83f7eb9c | 1243 | impress_friends(); |
83f7eb9c GOC |
1244 | #ifdef CONFIG_X86_IO_APIC |
1245 | setup_ioapic_dest(); | |
1246 | #endif | |
d0af9eed | 1247 | mtrr_aps_init(); |
83f7eb9c GOC |
1248 | } |
1249 | ||
3b11ce7f MT |
1250 | static int __initdata setup_possible_cpus = -1; |
1251 | static int __init _setup_possible_cpus(char *str) | |
1252 | { | |
1253 | get_option(&str, &setup_possible_cpus); | |
1254 | return 0; | |
1255 | } | |
1256 | early_param("possible_cpus", _setup_possible_cpus); | |
1257 | ||
1258 | ||
68a1c3f8 | 1259 | /* |
4f062896 | 1260 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1261 | * are onlined, or offlined. The reason is per-cpu data-structures |
1262 | * are allocated by some modules at init time, and dont expect to | |
1263 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1264 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1265 | * In case when cpu_hotplug is not compiled, then we resort to current |
1266 | * behaviour, which is cpu_possible == cpu_present. | |
1267 | * - Ashok Raj | |
1268 | * | |
1269 | * Three ways to find out the number of additional hotplug CPUs: | |
1270 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1271 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1272 | * - Otherwise don't reserve additional CPUs. |
1273 | * We do this because additional CPUs waste a lot of memory. | |
1274 | * -AK | |
1275 | */ | |
1276 | __init void prefill_possible_map(void) | |
1277 | { | |
cb48bb59 | 1278 | int i, possible; |
68a1c3f8 | 1279 | |
329513a3 YL |
1280 | /* no processor from mptable or madt */ |
1281 | if (!num_processors) | |
1282 | num_processors = 1; | |
1283 | ||
5f2eb550 JB |
1284 | i = setup_max_cpus ?: 1; |
1285 | if (setup_possible_cpus == -1) { | |
1286 | possible = num_processors; | |
1287 | #ifdef CONFIG_HOTPLUG_CPU | |
1288 | if (setup_max_cpus) | |
1289 | possible += disabled_cpus; | |
1290 | #else | |
1291 | if (possible > i) | |
1292 | possible = i; | |
1293 | #endif | |
1294 | } else | |
3b11ce7f MT |
1295 | possible = setup_possible_cpus; |
1296 | ||
730cf272 MT |
1297 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1298 | ||
2b633e3f YL |
1299 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1300 | if (possible > nr_cpu_ids) { | |
c767a54b | 1301 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1302 | possible, nr_cpu_ids); |
1303 | possible = nr_cpu_ids; | |
3b11ce7f | 1304 | } |
68a1c3f8 | 1305 | |
5f2eb550 JB |
1306 | #ifdef CONFIG_HOTPLUG_CPU |
1307 | if (!setup_max_cpus) | |
1308 | #endif | |
1309 | if (possible > i) { | |
c767a54b | 1310 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1311 | possible, setup_max_cpus); |
1312 | possible = i; | |
1313 | } | |
1314 | ||
c767a54b | 1315 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1316 | possible, max_t(int, possible - num_processors, 0)); |
1317 | ||
1318 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1319 | set_cpu_possible(i, true); |
5f2eb550 JB |
1320 | for (; i < NR_CPUS; i++) |
1321 | set_cpu_possible(i, false); | |
3461b0af MT |
1322 | |
1323 | nr_cpu_ids = possible; | |
68a1c3f8 | 1324 | } |
69c18c15 | 1325 | |
14adf855 CE |
1326 | #ifdef CONFIG_HOTPLUG_CPU |
1327 | ||
1328 | static void remove_siblinginfo(int cpu) | |
1329 | { | |
1330 | int sibling; | |
1331 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1332 | ||
c2d1cec1 MT |
1333 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1334 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1335 | /*/ |
1336 | * last thread sibling in this cpu core going down | |
1337 | */ | |
c2d1cec1 | 1338 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1339 | cpu_data(sibling).booted_cores--; |
1340 | } | |
1341 | ||
c2d1cec1 MT |
1342 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1343 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
03bd4e1f WL |
1344 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1345 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1346 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
c2d1cec1 MT |
1347 | cpumask_clear(cpu_sibling_mask(cpu)); |
1348 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1349 | c->phys_proc_id = 0; |
1350 | c->cpu_core_id = 0; | |
c2d1cec1 | 1351 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1352 | } |
1353 | ||
69c18c15 GC |
1354 | static void __ref remove_cpu_from_maps(int cpu) |
1355 | { | |
c2d1cec1 MT |
1356 | set_cpu_online(cpu, false); |
1357 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1358 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1359 | /* was set by cpu_init() */ |
c2d1cec1 | 1360 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1361 | numa_remove_cpu(cpu); |
69c18c15 GC |
1362 | } |
1363 | ||
54279552 BO |
1364 | static DEFINE_PER_CPU(struct completion, die_complete); |
1365 | ||
8227dce7 | 1366 | void cpu_disable_common(void) |
69c18c15 GC |
1367 | { |
1368 | int cpu = smp_processor_id(); | |
69c18c15 | 1369 | |
54279552 BO |
1370 | init_completion(&per_cpu(die_complete, smp_processor_id())); |
1371 | ||
69c18c15 GC |
1372 | remove_siblinginfo(cpu); |
1373 | ||
1374 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1375 | lock_vector_lock(); |
69c18c15 | 1376 | remove_cpu_from_maps(cpu); |
d388e5fd | 1377 | unlock_vector_lock(); |
d7b381bb | 1378 | fixup_irqs(); |
8227dce7 AN |
1379 | } |
1380 | ||
1381 | int native_cpu_disable(void) | |
1382 | { | |
da6139e4 PB |
1383 | int ret; |
1384 | ||
1385 | ret = check_irq_vectors_for_cpu_disable(); | |
1386 | if (ret) | |
1387 | return ret; | |
1388 | ||
8227dce7 | 1389 | clear_local_APIC(); |
8227dce7 | 1390 | cpu_disable_common(); |
2ed53c0d | 1391 | |
69c18c15 GC |
1392 | return 0; |
1393 | } | |
1394 | ||
54279552 BO |
1395 | void cpu_die_common(unsigned int cpu) |
1396 | { | |
1397 | wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ); | |
1398 | } | |
1399 | ||
93be71b6 | 1400 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1401 | { |
1402 | /* We don't do anything here: idle task is faking death itself. */ | |
54279552 BO |
1403 | |
1404 | cpu_die_common(cpu); | |
2ed53c0d LT |
1405 | |
1406 | /* They ack this in play_dead() by setting CPU_DEAD */ | |
1407 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1408 | if (system_state == SYSTEM_RUNNING) | |
1409 | pr_info("CPU %u is now offline\n", cpu); | |
1410 | } else { | |
1411 | pr_err("CPU %u didn't die...\n", cpu); | |
69c18c15 | 1412 | } |
69c18c15 | 1413 | } |
a21f5d88 AN |
1414 | |
1415 | void play_dead_common(void) | |
1416 | { | |
1417 | idle_task_exit(); | |
1418 | reset_lazy_tlbstate(); | |
02c68a02 | 1419 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1420 | |
1421 | mb(); | |
1422 | /* Ack it */ | |
0a3aee0d | 1423 | __this_cpu_write(cpu_state, CPU_DEAD); |
2ed53c0d | 1424 | complete(&per_cpu(die_complete, smp_processor_id())); |
a21f5d88 AN |
1425 | |
1426 | /* | |
1427 | * With physical CPU hotplug, we should halt the cpu | |
1428 | */ | |
1429 | local_irq_disable(); | |
1430 | } | |
1431 | ||
e1c467e6 FY |
1432 | static bool wakeup_cpu0(void) |
1433 | { | |
1434 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1435 | return true; | |
1436 | ||
1437 | return false; | |
1438 | } | |
1439 | ||
ea530692 PA |
1440 | /* |
1441 | * We need to flush the caches before going to sleep, lest we have | |
1442 | * dirty data in our caches when we come back up. | |
1443 | */ | |
1444 | static inline void mwait_play_dead(void) | |
1445 | { | |
1446 | unsigned int eax, ebx, ecx, edx; | |
1447 | unsigned int highest_cstate = 0; | |
1448 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1449 | void *mwait_ptr; |
576cfb40 | 1450 | int i; |
ea530692 | 1451 | |
69fb3676 | 1452 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1453 | return; |
840d2830 | 1454 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1455 | return; |
7b543a53 | 1456 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1457 | return; |
1458 | ||
1459 | eax = CPUID_MWAIT_LEAF; | |
1460 | ecx = 0; | |
1461 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1462 | ||
1463 | /* | |
1464 | * eax will be 0 if EDX enumeration is not valid. | |
1465 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1466 | */ | |
1467 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1468 | eax = 0; | |
1469 | } else { | |
1470 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1471 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1472 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1473 | highest_cstate = i; | |
1474 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1475 | } | |
1476 | } | |
1477 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1478 | (highest_subcstate - 1); | |
1479 | } | |
1480 | ||
ce5f6824 PA |
1481 | /* |
1482 | * This should be a memory location in a cache line which is | |
1483 | * unlikely to be touched by other processors. The actual | |
1484 | * content is immaterial as it is not actually modified in any way. | |
1485 | */ | |
1486 | mwait_ptr = ¤t_thread_info()->flags; | |
1487 | ||
a68e5c94 PA |
1488 | wbinvd(); |
1489 | ||
ea530692 | 1490 | while (1) { |
ce5f6824 PA |
1491 | /* |
1492 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1493 | * the Xeon 7400 series. It's not clear it is actually | |
1494 | * needed, but it should be harmless in either case. | |
1495 | * The WBINVD is insufficient due to the spurious-wakeup | |
1496 | * case where we return around the loop. | |
1497 | */ | |
7d590cca | 1498 | mb(); |
ce5f6824 | 1499 | clflush(mwait_ptr); |
7d590cca | 1500 | mb(); |
ce5f6824 | 1501 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1502 | mb(); |
1503 | __mwait(eax, 0); | |
e1c467e6 FY |
1504 | /* |
1505 | * If NMI wants to wake up CPU0, start CPU0. | |
1506 | */ | |
1507 | if (wakeup_cpu0()) | |
1508 | start_cpu0(); | |
ea530692 PA |
1509 | } |
1510 | } | |
1511 | ||
1512 | static inline void hlt_play_dead(void) | |
1513 | { | |
7b543a53 | 1514 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1515 | wbinvd(); |
1516 | ||
ea530692 | 1517 | while (1) { |
ea530692 | 1518 | native_halt(); |
e1c467e6 FY |
1519 | /* |
1520 | * If NMI wants to wake up CPU0, start CPU0. | |
1521 | */ | |
1522 | if (wakeup_cpu0()) | |
1523 | start_cpu0(); | |
ea530692 PA |
1524 | } |
1525 | } | |
1526 | ||
a21f5d88 AN |
1527 | void native_play_dead(void) |
1528 | { | |
1529 | play_dead_common(); | |
86886e55 | 1530 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1531 | |
1532 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1533 | if (cpuidle_play_dead()) |
1534 | hlt_play_dead(); | |
a21f5d88 AN |
1535 | } |
1536 | ||
69c18c15 | 1537 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1538 | int native_cpu_disable(void) |
69c18c15 GC |
1539 | { |
1540 | return -ENOSYS; | |
1541 | } | |
1542 | ||
93be71b6 | 1543 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1544 | { |
1545 | /* We said "no" in __cpu_disable */ | |
1546 | BUG(); | |
1547 | } | |
a21f5d88 AN |
1548 | |
1549 | void native_play_dead(void) | |
1550 | { | |
1551 | BUG(); | |
1552 | } | |
1553 | ||
68a1c3f8 | 1554 | #endif |