Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> |
569712b2 | 72 | #include <asm/setup.h> |
bdbcdd48 | 73 | #include <asm/uv/uv.h> |
cb3c8b90 | 74 | #include <linux/mc146818rtc.h> |
b81bb373 | 75 | #include <asm/i8259.h> |
48927bbb | 76 | #include <asm/realmode.h> |
646e29a1 | 77 | #include <asm/misc.h> |
48927bbb | 78 | |
a355352b GC |
79 | /* Number of siblings per CPU package */ |
80 | int smp_num_siblings = 1; | |
81 | EXPORT_SYMBOL(smp_num_siblings); | |
82 | ||
83 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 85 | |
a355352b | 86 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
93 | ||
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 95 | |
a355352b | 96 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 99 | |
2b6163bf | 100 | atomic_t init_deasserted; |
cb3c8b90 | 101 | |
f77aa308 TG |
102 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
103 | { | |
104 | unsigned long flags; | |
105 | ||
106 | spin_lock_irqsave(&rtc_lock, flags); | |
107 | CMOS_WRITE(0xa, 0xf); | |
108 | spin_unlock_irqrestore(&rtc_lock, flags); | |
109 | local_flush_tlb(); | |
110 | pr_debug("1.\n"); | |
111 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
112 | start_eip >> 4; | |
113 | pr_debug("2.\n"); | |
114 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
115 | start_eip & 0xf; | |
116 | pr_debug("3.\n"); | |
117 | } | |
118 | ||
119 | static inline void smpboot_restore_warm_reset_vector(void) | |
120 | { | |
121 | unsigned long flags; | |
122 | ||
123 | /* | |
124 | * Install writable page 0 entry to set BIOS data area. | |
125 | */ | |
126 | local_flush_tlb(); | |
127 | ||
128 | /* | |
129 | * Paranoid: Set warm reset code and vector here back | |
130 | * to default values. | |
131 | */ | |
132 | spin_lock_irqsave(&rtc_lock, flags); | |
133 | CMOS_WRITE(0, 0xf); | |
134 | spin_unlock_irqrestore(&rtc_lock, flags); | |
135 | ||
136 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
137 | } | |
138 | ||
cb3c8b90 | 139 | /* |
30106c17 FY |
140 | * Report back to the Boot Processor during boot time or to the caller processor |
141 | * during CPU online. | |
cb3c8b90 | 142 | */ |
148f9bb8 | 143 | static void smp_callin(void) |
cb3c8b90 GOC |
144 | { |
145 | int cpuid, phys_id; | |
cb3c8b90 GOC |
146 | |
147 | /* | |
148 | * If waken up by an INIT in an 82489DX configuration | |
149 | * we may get here before an INIT-deassert IPI reaches | |
150 | * our local APIC. We have to wait for the IPI or we'll | |
151 | * lock up on an APIC access. | |
e1c467e6 FY |
152 | * |
153 | * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. | |
cb3c8b90 | 154 | */ |
e1c467e6 | 155 | cpuid = smp_processor_id(); |
465822cf DR |
156 | if (apic->wait_for_init_deassert && cpuid) |
157 | while (!atomic_read(&init_deasserted)) | |
158 | cpu_relax(); | |
cb3c8b90 GOC |
159 | |
160 | /* | |
161 | * (This works even if the APIC is not enabled.) | |
162 | */ | |
4c9961d5 | 163 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
164 | |
165 | /* | |
166 | * the boot CPU has finished the init stage and is spinning | |
167 | * on callin_map until we finish. We are free to set up this | |
168 | * CPU, first the APIC. (this is probably redundant on most | |
169 | * boards) | |
170 | */ | |
05f7e46d | 171 | apic_ap_setup(); |
cb3c8b90 | 172 | |
b565201c JS |
173 | /* |
174 | * Save our processor parameters. Note: this information | |
175 | * is needed for clock calibration. | |
176 | */ | |
177 | smp_store_cpu_info(cpuid); | |
178 | ||
cb3c8b90 GOC |
179 | /* |
180 | * Get our bogomips. | |
b565201c JS |
181 | * Update loops_per_jiffy in cpu_data. Previous call to |
182 | * smp_store_cpu_info() stored a value that is close but not as | |
183 | * accurate as the value just calculated. | |
cb3c8b90 | 184 | */ |
cb3c8b90 | 185 | calibrate_delay(); |
b565201c | 186 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 187 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 188 | |
5ef428c4 AK |
189 | /* |
190 | * This must be done before setting cpu_online_mask | |
191 | * or calling notify_cpu_starting. | |
192 | */ | |
193 | set_cpu_sibling_map(raw_smp_processor_id()); | |
194 | wmb(); | |
195 | ||
85257024 PZ |
196 | notify_cpu_starting(cpuid); |
197 | ||
cb3c8b90 GOC |
198 | /* |
199 | * Allow the master to continue. | |
200 | */ | |
c2d1cec1 | 201 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
202 | } |
203 | ||
e1c467e6 FY |
204 | static int cpu0_logical_apicid; |
205 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
206 | /* |
207 | * Activate a secondary processor. | |
208 | */ | |
148f9bb8 | 209 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
210 | { |
211 | /* | |
212 | * Don't put *anything* before cpu_init(), SMP booting is too | |
213 | * fragile that we want to limit the things done here to the | |
214 | * most necessary things. | |
215 | */ | |
b40827fa | 216 | cpu_init(); |
df156f90 | 217 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
218 | preempt_disable(); |
219 | smp_callin(); | |
fd89a137 | 220 | |
e1c467e6 FY |
221 | enable_start_cpu0 = 0; |
222 | ||
fd89a137 | 223 | #ifdef CONFIG_X86_32 |
b40827fa | 224 | /* switch away from the initial page table */ |
fd89a137 JR |
225 | load_cr3(swapper_pg_dir); |
226 | __flush_tlb_all(); | |
227 | #endif | |
228 | ||
bbc2ff6a GOC |
229 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
230 | barrier(); | |
231 | /* | |
232 | * Check TSC synchronization with the BP: | |
233 | */ | |
234 | check_tsc_sync_target(); | |
235 | ||
bbc2ff6a | 236 | /* |
5a3f75e3 TG |
237 | * Lock vector_lock and initialize the vectors on this cpu |
238 | * before setting the cpu online. We must set it online with | |
239 | * vector_lock held to prevent a concurrent setup/teardown | |
240 | * from seeing a half valid vector space. | |
bbc2ff6a | 241 | */ |
d388e5fd | 242 | lock_vector_lock(); |
5a3f75e3 | 243 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 244 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 245 | unlock_vector_lock(); |
2a442c9c | 246 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 247 | x86_platform.nmi_init(); |
bbc2ff6a | 248 | |
0cefa5b9 MS |
249 | /* enable local interrupts */ |
250 | local_irq_enable(); | |
251 | ||
35f720c5 JP |
252 | /* to prevent fake stack check failure in clock setup */ |
253 | boot_init_stack_canary(); | |
0cefa5b9 | 254 | |
736decac | 255 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
256 | |
257 | wmb(); | |
7d1a9417 | 258 | cpu_startup_entry(CPUHP_ONLINE); |
bbc2ff6a GOC |
259 | } |
260 | ||
30106c17 FY |
261 | void __init smp_store_boot_cpu_info(void) |
262 | { | |
263 | int id = 0; /* CPU 0 */ | |
264 | struct cpuinfo_x86 *c = &cpu_data(id); | |
265 | ||
266 | *c = boot_cpu_data; | |
267 | c->cpu_index = id; | |
268 | } | |
269 | ||
1d89a7f0 GOC |
270 | /* |
271 | * The bootstrap kernel entry code has set these up. Save them for | |
272 | * a given CPU | |
273 | */ | |
148f9bb8 | 274 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
275 | { |
276 | struct cpuinfo_x86 *c = &cpu_data(id); | |
277 | ||
b3d7336d | 278 | *c = boot_cpu_data; |
1d89a7f0 | 279 | c->cpu_index = id; |
30106c17 FY |
280 | /* |
281 | * During boot time, CPU0 has this setup already. Save the info when | |
282 | * bringing up AP or offlined CPU0. | |
283 | */ | |
284 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
285 | } |
286 | ||
cebf15eb DH |
287 | static bool |
288 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
289 | { | |
290 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
291 | ||
292 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
293 | } | |
294 | ||
148f9bb8 | 295 | static bool |
316ad248 | 296 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 297 | { |
316ad248 PZ |
298 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
299 | ||
cebf15eb | 300 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
301 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
302 | "[node: %d != %d]. Ignoring dependency.\n", | |
303 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
304 | } | |
305 | ||
7d79a7bd | 306 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 307 | do { \ |
7d79a7bd BG |
308 | cpumask_set_cpu((c1), mfunc(c2)); \ |
309 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
310 | } while (0) |
311 | ||
148f9bb8 | 312 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 313 | { |
193f3fcb | 314 | if (cpu_has_topoext) { |
316ad248 PZ |
315 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
316 | ||
317 | if (c->phys_proc_id == o->phys_proc_id && | |
318 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
319 | c->compute_unit_id == o->compute_unit_id) | |
320 | return topology_sane(c, o, "smt"); | |
321 | ||
322 | } else if (c->phys_proc_id == o->phys_proc_id && | |
323 | c->cpu_core_id == o->cpu_core_id) { | |
324 | return topology_sane(c, o, "smt"); | |
325 | } | |
326 | ||
327 | return false; | |
328 | } | |
329 | ||
148f9bb8 | 330 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
331 | { |
332 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
333 | ||
334 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
335 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
336 | return topology_sane(c, o, "llc"); | |
337 | ||
338 | return false; | |
d4fbe4f0 AH |
339 | } |
340 | ||
cebf15eb DH |
341 | /* |
342 | * Unlike the other levels, we do not enforce keeping a | |
343 | * multicore group inside a NUMA node. If this happens, we will | |
344 | * discard the MC level of the topology later. | |
345 | */ | |
346 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 347 | { |
cebf15eb DH |
348 | if (c->phys_proc_id == o->phys_proc_id) |
349 | return true; | |
316ad248 PZ |
350 | return false; |
351 | } | |
1d89a7f0 | 352 | |
cebf15eb DH |
353 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
354 | #ifdef CONFIG_SCHED_SMT | |
355 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
356 | #endif | |
357 | #ifdef CONFIG_SCHED_MC | |
358 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
359 | #endif | |
360 | { NULL, }, | |
361 | }; | |
362 | /* | |
363 | * set_sched_topology() sets the topology internal to a CPU. The | |
364 | * NUMA topologies are layered on top of it to build the full | |
365 | * system topology. | |
366 | * | |
367 | * If NUMA nodes are observed to occur within a CPU package, this | |
368 | * function should be called. It forces the sched domain code to | |
369 | * only use the SMT level for the CPU portion of the topology. | |
370 | * This essentially falls back to relying on NUMA information | |
371 | * from the SRAT table to describe the entire system topology | |
372 | * (except for hyperthreads). | |
373 | */ | |
374 | static void primarily_use_numa_for_topology(void) | |
375 | { | |
376 | set_sched_topology(numa_inside_package_topology); | |
377 | } | |
378 | ||
148f9bb8 | 379 | void set_cpu_sibling_map(int cpu) |
768d9505 | 380 | { |
316ad248 | 381 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 382 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 383 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
384 | struct cpuinfo_x86 *o; |
385 | int i; | |
768d9505 | 386 | |
c2d1cec1 | 387 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 388 | |
b0bc225d | 389 | if (!has_mp) { |
7d79a7bd | 390 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 391 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 392 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
393 | c->booted_cores = 1; |
394 | return; | |
395 | } | |
396 | ||
c2d1cec1 | 397 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
398 | o = &cpu_data(i); |
399 | ||
400 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 401 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 402 | |
b0bc225d | 403 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 404 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 405 | |
ceb1cbac KB |
406 | } |
407 | ||
408 | /* | |
409 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 410 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
411 | */ |
412 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
413 | o = &cpu_data(i); | |
414 | ||
cebf15eb | 415 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 416 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 417 | |
768d9505 GC |
418 | /* |
419 | * Does this new cpu bringup a new core? | |
420 | */ | |
7d79a7bd BG |
421 | if (cpumask_weight( |
422 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
423 | /* |
424 | * for each core in package, increment | |
425 | * the booted_cores for this new cpu | |
426 | */ | |
7d79a7bd BG |
427 | if (cpumask_first( |
428 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
429 | c->booted_cores++; |
430 | /* | |
431 | * increment the core count for all | |
432 | * the other cpus in this package | |
433 | */ | |
434 | if (i != cpu) | |
435 | cpu_data(i).booted_cores++; | |
436 | } else if (i != cpu && !c->booted_cores) | |
437 | c->booted_cores = cpu_data(i).booted_cores; | |
438 | } | |
728e5653 | 439 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 440 | primarily_use_numa_for_topology(); |
768d9505 GC |
441 | } |
442 | } | |
443 | ||
70708a18 | 444 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 445 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 446 | { |
9f646389 | 447 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
448 | } |
449 | ||
a4928cff | 450 | static void impress_friends(void) |
904541e2 GOC |
451 | { |
452 | int cpu; | |
453 | unsigned long bogosum = 0; | |
454 | /* | |
455 | * Allow the user to impress friends. | |
456 | */ | |
c767a54b | 457 | pr_debug("Before bogomips\n"); |
904541e2 | 458 | for_each_possible_cpu(cpu) |
c2d1cec1 | 459 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 460 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 461 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 462 | num_online_cpus(), |
904541e2 GOC |
463 | bogosum/(500000/HZ), |
464 | (bogosum/(5000/HZ))%100); | |
465 | ||
c767a54b | 466 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
467 | } |
468 | ||
569712b2 | 469 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
470 | { |
471 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 472 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
473 | int timeout; |
474 | u32 status; | |
475 | ||
c767a54b | 476 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
477 | |
478 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 479 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
480 | |
481 | /* | |
482 | * Wait for idle. | |
483 | */ | |
484 | status = safe_apic_wait_icr_idle(); | |
485 | if (status) | |
c767a54b | 486 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 487 | |
1b374e4d | 488 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
489 | |
490 | timeout = 0; | |
491 | do { | |
492 | udelay(100); | |
493 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
494 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
495 | ||
496 | switch (status) { | |
497 | case APIC_ICR_RR_VALID: | |
498 | status = apic_read(APIC_RRR); | |
c767a54b | 499 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
500 | break; |
501 | default: | |
c767a54b | 502 | pr_cont("failed\n"); |
cb3c8b90 GOC |
503 | } |
504 | } | |
505 | } | |
506 | ||
d68921f9 LB |
507 | /* |
508 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
509 | * that there should be a 10ms delay between the BSP asserting INIT | |
510 | * and de-asserting INIT, when starting a remote processor. | |
511 | * But that slows boot and resume on modern processors, which include | |
512 | * many cores and don't require that delay. | |
513 | * | |
514 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 515 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
516 | */ |
517 | #define UDELAY_10MS_DEFAULT 10000 | |
518 | ||
519 | static unsigned int init_udelay = UDELAY_10MS_DEFAULT; | |
520 | ||
521 | static int __init cpu_init_udelay(char *str) | |
522 | { | |
523 | get_option(&str, &init_udelay); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | early_param("cpu_init_udelay", cpu_init_udelay); | |
528 | ||
1a744cb3 LB |
529 | static void __init smp_quirk_init_udelay(void) |
530 | { | |
531 | /* if cmdline changed it from default, leave it alone */ | |
532 | if (init_udelay != UDELAY_10MS_DEFAULT) | |
533 | return; | |
534 | ||
535 | /* if modern processor, use no delay */ | |
536 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
537 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) | |
538 | init_udelay = 0; | |
539 | } | |
540 | ||
cb3c8b90 GOC |
541 | /* |
542 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
543 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
544 | * won't ... remember to clear down the APIC, etc later. | |
545 | */ | |
148f9bb8 | 546 | int |
e1c467e6 | 547 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
548 | { |
549 | unsigned long send_status, accept_status = 0; | |
550 | int maxlvt; | |
551 | ||
552 | /* Target chip */ | |
cb3c8b90 GOC |
553 | /* Boot on the stack */ |
554 | /* Kick the second */ | |
e1c467e6 | 555 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 556 | |
cfc1b9a6 | 557 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
558 | send_status = safe_apic_wait_icr_idle(); |
559 | ||
560 | /* | |
561 | * Give the other CPU some time to accept the IPI. | |
562 | */ | |
563 | udelay(200); | |
569712b2 | 564 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
565 | maxlvt = lapic_get_maxlvt(); |
566 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
567 | apic_write(APIC_ESR, 0); | |
568 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
569 | } | |
c767a54b | 570 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
571 | |
572 | if (send_status) | |
c767a54b | 573 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 574 | if (accept_status) |
c767a54b | 575 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
576 | |
577 | return (send_status | accept_status); | |
578 | } | |
cb3c8b90 | 579 | |
148f9bb8 | 580 | static int |
569712b2 | 581 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 582 | { |
f5d6a52f | 583 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
584 | int maxlvt, num_starts, j; |
585 | ||
593f4a78 MR |
586 | maxlvt = lapic_get_maxlvt(); |
587 | ||
cb3c8b90 GOC |
588 | /* |
589 | * Be paranoid about clearing APIC errors. | |
590 | */ | |
591 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
592 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
593 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
594 | apic_read(APIC_ESR); |
595 | } | |
596 | ||
c767a54b | 597 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
598 | |
599 | /* | |
600 | * Turn INIT on target chip | |
601 | */ | |
cb3c8b90 GOC |
602 | /* |
603 | * Send IPI | |
604 | */ | |
1b374e4d SS |
605 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
606 | phys_apicid); | |
cb3c8b90 | 607 | |
cfc1b9a6 | 608 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
609 | send_status = safe_apic_wait_icr_idle(); |
610 | ||
7cb68598 | 611 | udelay(init_udelay); |
cb3c8b90 | 612 | |
c767a54b | 613 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
614 | |
615 | /* Target chip */ | |
cb3c8b90 | 616 | /* Send IPI */ |
1b374e4d | 617 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 618 | |
cfc1b9a6 | 619 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
620 | send_status = safe_apic_wait_icr_idle(); |
621 | ||
622 | mb(); | |
623 | atomic_set(&init_deasserted, 1); | |
624 | ||
625 | /* | |
626 | * Should we send STARTUP IPIs ? | |
627 | * | |
628 | * Determine this based on the APIC version. | |
629 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
630 | */ | |
631 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
632 | num_starts = 2; | |
633 | else | |
634 | num_starts = 0; | |
635 | ||
636 | /* | |
637 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
638 | * target processor state. | |
639 | */ | |
640 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 641 | stack_start); |
cb3c8b90 GOC |
642 | |
643 | /* | |
644 | * Run STARTUP IPI loop. | |
645 | */ | |
c767a54b | 646 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 647 | |
cb3c8b90 | 648 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 649 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
650 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
651 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 652 | apic_read(APIC_ESR); |
c767a54b | 653 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
654 | |
655 | /* | |
656 | * STARTUP IPI | |
657 | */ | |
658 | ||
659 | /* Target chip */ | |
cb3c8b90 GOC |
660 | /* Boot on the stack */ |
661 | /* Kick the second */ | |
1b374e4d SS |
662 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
663 | phys_apicid); | |
cb3c8b90 GOC |
664 | |
665 | /* | |
666 | * Give the other CPU some time to accept the IPI. | |
667 | */ | |
a9bcaa02 LB |
668 | if (init_udelay) |
669 | udelay(300); | |
cb3c8b90 | 670 | |
c767a54b | 671 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 672 | |
cfc1b9a6 | 673 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
674 | send_status = safe_apic_wait_icr_idle(); |
675 | ||
676 | /* | |
677 | * Give the other CPU some time to accept the IPI. | |
678 | */ | |
a9bcaa02 LB |
679 | if (init_udelay) |
680 | udelay(200); | |
cb3c8b90 | 681 | |
593f4a78 | 682 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 683 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
684 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
685 | if (send_status || accept_status) | |
686 | break; | |
687 | } | |
c767a54b | 688 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
689 | |
690 | if (send_status) | |
c767a54b | 691 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 692 | if (accept_status) |
c767a54b | 693 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
694 | |
695 | return (send_status | accept_status); | |
696 | } | |
cb3c8b90 | 697 | |
a17bce4d BP |
698 | void smp_announce(void) |
699 | { | |
700 | int num_nodes = num_online_nodes(); | |
701 | ||
702 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
703 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
704 | } | |
705 | ||
2eaad1fd | 706 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 707 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
708 | { |
709 | static int current_node = -1; | |
4adc8b71 | 710 | int node = early_cpu_to_node(cpu); |
a17bce4d | 711 | static int width, node_width; |
646e29a1 BP |
712 | |
713 | if (!width) | |
714 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 715 | |
a17bce4d BP |
716 | if (!node_width) |
717 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
718 | ||
719 | if (cpu == 1) | |
720 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
721 | ||
2eaad1fd MT |
722 | if (system_state == SYSTEM_BOOTING) { |
723 | if (node != current_node) { | |
724 | if (current_node > (-1)) | |
a17bce4d | 725 | pr_cont("\n"); |
2eaad1fd | 726 | current_node = node; |
a17bce4d BP |
727 | |
728 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
729 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 730 | } |
646e29a1 BP |
731 | |
732 | /* Add padding for the BSP */ | |
733 | if (cpu == 1) | |
734 | pr_cont("%*s", width + 1, " "); | |
735 | ||
736 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
737 | ||
2eaad1fd MT |
738 | } else |
739 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
740 | node, cpu, apicid); | |
741 | } | |
742 | ||
e1c467e6 FY |
743 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
744 | { | |
745 | int cpu; | |
746 | ||
747 | cpu = smp_processor_id(); | |
748 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
749 | return NMI_HANDLED; | |
750 | ||
751 | return NMI_DONE; | |
752 | } | |
753 | ||
754 | /* | |
755 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
756 | * | |
757 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
758 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
759 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
760 | * | |
761 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
762 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
763 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
764 | * real platform and request are available. | |
765 | */ | |
148f9bb8 | 766 | static int |
e1c467e6 FY |
767 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
768 | int *cpu0_nmi_registered) | |
769 | { | |
770 | int id; | |
771 | int boot_error; | |
772 | ||
ea7bdc65 JK |
773 | preempt_disable(); |
774 | ||
e1c467e6 FY |
775 | /* |
776 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
777 | */ | |
ea7bdc65 JK |
778 | if (cpu) { |
779 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
780 | goto out; | |
781 | } | |
e1c467e6 FY |
782 | |
783 | /* | |
784 | * Wake up BSP by nmi. | |
785 | * | |
786 | * Register a NMI handler to help wake up CPU0. | |
787 | */ | |
788 | boot_error = register_nmi_handler(NMI_LOCAL, | |
789 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
790 | ||
791 | if (!boot_error) { | |
792 | enable_start_cpu0 = 1; | |
793 | *cpu0_nmi_registered = 1; | |
794 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
795 | id = cpu0_logical_apicid; | |
796 | else | |
797 | id = apicid; | |
798 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
799 | } | |
ea7bdc65 JK |
800 | |
801 | out: | |
802 | preempt_enable(); | |
e1c467e6 FY |
803 | |
804 | return boot_error; | |
805 | } | |
806 | ||
3f85483b BO |
807 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
808 | { | |
809 | /* Just in case we booted with a single CPU. */ | |
810 | alternatives_enable_smp(); | |
811 | ||
812 | per_cpu(current_task, cpu) = idle; | |
813 | ||
814 | #ifdef CONFIG_X86_32 | |
815 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
816 | irq_ctx_init(cpu); | |
817 | per_cpu(cpu_current_top_of_stack, cpu) = | |
818 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
819 | #else | |
820 | clear_tsk_thread_flag(idle, TIF_FORK); | |
821 | initial_gs = per_cpu_offset(cpu); | |
822 | #endif | |
3f85483b BO |
823 | } |
824 | ||
cb3c8b90 GOC |
825 | /* |
826 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
827 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
828 | * Returns zero if CPU booted OK, else error code from |
829 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 830 | */ |
148f9bb8 | 831 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 832 | { |
48927bbb | 833 | volatile u32 *trampoline_status = |
b429dbf6 | 834 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 835 | /* start_ip had better be page-aligned! */ |
f37240f1 | 836 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 837 | |
cb3c8b90 | 838 | unsigned long boot_error = 0; |
e1c467e6 | 839 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 840 | unsigned long timeout; |
cb3c8b90 | 841 | |
7eb43a6d TG |
842 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
843 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
cb3c8b90 | 844 | |
a939098a | 845 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 846 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 847 | stack_start = idle->thread.sp; |
cb3c8b90 | 848 | |
20d5e4a9 ZG |
849 | /* |
850 | * Enable the espfix hack for this CPU | |
851 | */ | |
852 | #ifdef CONFIG_X86_ESPFIX64 | |
853 | init_espfix_ap(cpu); | |
854 | #endif | |
855 | ||
2eaad1fd MT |
856 | /* So we see what's up */ |
857 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
858 | |
859 | /* | |
860 | * This grunge runs the startup process for | |
861 | * the targeted processor. | |
862 | */ | |
863 | ||
864 | atomic_set(&init_deasserted, 0); | |
865 | ||
34d05591 | 866 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 867 | |
cfc1b9a6 | 868 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 869 | |
34d05591 JS |
870 | smpboot_setup_warm_reset_vector(start_ip); |
871 | /* | |
872 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
873 | */ |
874 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
875 | apic_write(APIC_ESR, 0); | |
876 | apic_read(APIC_ESR); | |
877 | } | |
34d05591 | 878 | } |
cb3c8b90 | 879 | |
ce4b1b16 IM |
880 | /* |
881 | * AP might wait on cpu_callout_mask in cpu_init() with | |
882 | * cpu_initialized_mask set if previous attempt to online | |
883 | * it timed-out. Clear cpu_initialized_mask so that after | |
884 | * INIT/SIPI it could start with a clean state. | |
885 | */ | |
886 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
887 | smp_mb(); | |
888 | ||
cb3c8b90 | 889 | /* |
e1c467e6 FY |
890 | * Wake up a CPU in difference cases: |
891 | * - Use the method in the APIC driver if it's defined | |
892 | * Otherwise, | |
893 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 894 | */ |
1f5bcabf IM |
895 | if (apic->wakeup_secondary_cpu) |
896 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
897 | else | |
e1c467e6 FY |
898 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
899 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
900 | |
901 | if (!boot_error) { | |
902 | /* | |
6e38f1e7 | 903 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 904 | */ |
ce4b1b16 IM |
905 | boot_error = -1; |
906 | timeout = jiffies + 10*HZ; | |
907 | while (time_before(jiffies, timeout)) { | |
908 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
909 | /* | |
910 | * Tell AP to proceed with initialization | |
911 | */ | |
912 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
913 | boot_error = 0; | |
914 | break; | |
915 | } | |
ce4b1b16 IM |
916 | schedule(); |
917 | } | |
918 | } | |
cb3c8b90 | 919 | |
ce4b1b16 | 920 | if (!boot_error) { |
cb3c8b90 | 921 | /* |
ce4b1b16 | 922 | * Wait till AP completes initial initialization |
cb3c8b90 | 923 | */ |
ce4b1b16 | 924 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
925 | /* |
926 | * Allow other tasks to run while we wait for the | |
927 | * AP to come online. This also gives a chance | |
928 | * for the MTRR work(triggered by the AP coming online) | |
929 | * to be completed in the stop machine context. | |
930 | */ | |
931 | schedule(); | |
cb3c8b90 | 932 | } |
cb3c8b90 GOC |
933 | } |
934 | ||
935 | /* mark "stuck" area as not stuck */ | |
48927bbb | 936 | *trampoline_status = 0; |
cb3c8b90 | 937 | |
02421f98 YL |
938 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
939 | /* | |
940 | * Cleanup possible dangling ends... | |
941 | */ | |
942 | smpboot_restore_warm_reset_vector(); | |
943 | } | |
e1c467e6 FY |
944 | /* |
945 | * Clean up the nmi handler. Do this after the callin and callout sync | |
946 | * to avoid impact of possible long unregister time. | |
947 | */ | |
948 | if (cpu0_nmi_registered) | |
949 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
950 | ||
cb3c8b90 GOC |
951 | return boot_error; |
952 | } | |
953 | ||
148f9bb8 | 954 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 955 | { |
a21769a4 | 956 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
957 | unsigned long flags; |
958 | int err; | |
959 | ||
960 | WARN_ON(irqs_disabled()); | |
961 | ||
cfc1b9a6 | 962 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 963 | |
30106c17 | 964 | if (apicid == BAD_APICID || |
c284b42a | 965 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 966 | !apic->apic_id_valid(apicid)) { |
c767a54b | 967 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
968 | return -EINVAL; |
969 | } | |
970 | ||
971 | /* | |
972 | * Already booted CPU? | |
973 | */ | |
c2d1cec1 | 974 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 975 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
976 | return -ENOSYS; |
977 | } | |
978 | ||
979 | /* | |
980 | * Save current MTRR state in case it was changed since early boot | |
981 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
982 | */ | |
983 | mtrr_save_state(); | |
984 | ||
2a442c9c PM |
985 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
986 | err = cpu_check_up_prepare(cpu); | |
987 | if (err && err != -EBUSY) | |
988 | return err; | |
cb3c8b90 | 989 | |
644c1541 VP |
990 | /* the FPU context is blank, nobody can own it */ |
991 | __cpu_disable_lazy_restore(cpu); | |
992 | ||
3f85483b BO |
993 | common_cpu_up(cpu, tidle); |
994 | ||
ce0d3c0a TG |
995 | /* |
996 | * We have to walk the irq descriptors to setup the vector | |
997 | * space for the cpu which comes online. Prevent irq | |
998 | * alloc/free across the bringup. | |
999 | */ | |
1000 | irq_lock_sparse(); | |
1001 | ||
7eb43a6d | 1002 | err = do_boot_cpu(apicid, cpu, tidle); |
ce0d3c0a | 1003 | |
61165d7a | 1004 | if (err) { |
ce0d3c0a | 1005 | irq_unlock_sparse(); |
feef1e8e | 1006 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1007 | return -EIO; |
cb3c8b90 GOC |
1008 | } |
1009 | ||
1010 | /* | |
1011 | * Check TSC synchronization with the AP (keep irqs disabled | |
1012 | * while doing so): | |
1013 | */ | |
1014 | local_irq_save(flags); | |
1015 | check_tsc_sync_source(cpu); | |
1016 | local_irq_restore(flags); | |
1017 | ||
7c04e64a | 1018 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1019 | cpu_relax(); |
1020 | touch_nmi_watchdog(); | |
1021 | } | |
1022 | ||
ce0d3c0a TG |
1023 | irq_unlock_sparse(); |
1024 | ||
cb3c8b90 GOC |
1025 | return 0; |
1026 | } | |
1027 | ||
7167d08e HK |
1028 | /** |
1029 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1030 | */ | |
1031 | void arch_disable_smp_support(void) | |
1032 | { | |
1033 | disable_ioapic_support(); | |
1034 | } | |
1035 | ||
8aef135c GOC |
1036 | /* |
1037 | * Fall back to non SMP mode after errors. | |
1038 | * | |
1039 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1040 | */ | |
1041 | static __init void disable_smp(void) | |
1042 | { | |
613c25ef TG |
1043 | pr_info("SMP disabled\n"); |
1044 | ||
ef4c59a4 TG |
1045 | disable_ioapic_support(); |
1046 | ||
4f062896 RR |
1047 | init_cpu_present(cpumask_of(0)); |
1048 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1049 | |
8aef135c | 1050 | if (smp_found_config) |
b6df1b8b | 1051 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1052 | else |
b6df1b8b | 1053 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1054 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1055 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1056 | } |
1057 | ||
613c25ef TG |
1058 | enum { |
1059 | SMP_OK, | |
1060 | SMP_NO_CONFIG, | |
1061 | SMP_NO_APIC, | |
1062 | SMP_FORCE_UP, | |
1063 | }; | |
1064 | ||
8aef135c GOC |
1065 | /* |
1066 | * Various sanity checks. | |
1067 | */ | |
1068 | static int __init smp_sanity_check(unsigned max_cpus) | |
1069 | { | |
ac23d4ee | 1070 | preempt_disable(); |
a58f03b0 | 1071 | |
1ff2f20d | 1072 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1073 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1074 | unsigned int cpu; | |
1075 | unsigned nr; | |
1076 | ||
c767a54b JP |
1077 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1078 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1079 | |
1080 | nr = 0; | |
1081 | for_each_present_cpu(cpu) { | |
1082 | if (nr >= 8) | |
c2d1cec1 | 1083 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1084 | nr++; |
1085 | } | |
1086 | ||
1087 | nr = 0; | |
1088 | for_each_possible_cpu(cpu) { | |
1089 | if (nr >= 8) | |
c2d1cec1 | 1090 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1091 | nr++; |
1092 | } | |
1093 | ||
1094 | nr_cpu_ids = 8; | |
1095 | } | |
1096 | #endif | |
1097 | ||
8aef135c | 1098 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1099 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1100 | hard_smp_processor_id()); |
1101 | ||
8aef135c GOC |
1102 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1103 | } | |
1104 | ||
1105 | /* | |
1106 | * If we couldn't find an SMP configuration at boot time, | |
1107 | * get out of here now! | |
1108 | */ | |
1109 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1110 | preempt_enable(); |
c767a54b | 1111 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1112 | return SMP_NO_CONFIG; |
8aef135c GOC |
1113 | } |
1114 | ||
1115 | /* | |
1116 | * Should not be necessary because the MP table should list the boot | |
1117 | * CPU too, but we do it for the sake of robustness anyway. | |
1118 | */ | |
a27a6210 | 1119 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1120 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1121 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1122 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1123 | } | |
ac23d4ee | 1124 | preempt_enable(); |
8aef135c GOC |
1125 | |
1126 | /* | |
1127 | * If we couldn't find a local APIC, then get out of here now! | |
1128 | */ | |
1129 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1130 | !cpu_has_apic) { | |
103428e5 CG |
1131 | if (!disable_apic) { |
1132 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1133 | boot_cpu_physical_apicid); | |
c767a54b | 1134 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1135 | } |
613c25ef | 1136 | return SMP_NO_APIC; |
8aef135c GOC |
1137 | } |
1138 | ||
8aef135c GOC |
1139 | /* |
1140 | * If SMP should be disabled, then really disable it! | |
1141 | */ | |
1142 | if (!max_cpus) { | |
c767a54b | 1143 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1144 | return SMP_FORCE_UP; |
8aef135c GOC |
1145 | } |
1146 | ||
613c25ef | 1147 | return SMP_OK; |
8aef135c GOC |
1148 | } |
1149 | ||
1150 | static void __init smp_cpu_index_default(void) | |
1151 | { | |
1152 | int i; | |
1153 | struct cpuinfo_x86 *c; | |
1154 | ||
7c04e64a | 1155 | for_each_possible_cpu(i) { |
8aef135c GOC |
1156 | c = &cpu_data(i); |
1157 | /* mark all to hotplug */ | |
9628937d | 1158 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1159 | } |
1160 | } | |
1161 | ||
1162 | /* | |
1163 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1164 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1165 | */ | |
1166 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1167 | { | |
7ad728f9 RR |
1168 | unsigned int i; |
1169 | ||
8aef135c | 1170 | smp_cpu_index_default(); |
792363d2 | 1171 | |
8aef135c GOC |
1172 | /* |
1173 | * Setup boot CPU information | |
1174 | */ | |
30106c17 | 1175 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1176 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1177 | mb(); | |
bd22a2f1 | 1178 | |
8aef135c | 1179 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1180 | for_each_possible_cpu(i) { |
79f55997 LZ |
1181 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1182 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1183 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1184 | } |
8aef135c GOC |
1185 | set_cpu_sibling_map(0); |
1186 | ||
613c25ef TG |
1187 | switch (smp_sanity_check(max_cpus)) { |
1188 | case SMP_NO_CONFIG: | |
8aef135c | 1189 | disable_smp(); |
613c25ef TG |
1190 | if (APIC_init_uniprocessor()) |
1191 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1192 | return; | |
1193 | case SMP_NO_APIC: | |
1194 | disable_smp(); | |
1195 | return; | |
1196 | case SMP_FORCE_UP: | |
1197 | disable_smp(); | |
374aab33 | 1198 | apic_bsp_setup(false); |
250a1ac6 | 1199 | return; |
613c25ef TG |
1200 | case SMP_OK: |
1201 | break; | |
8aef135c GOC |
1202 | } |
1203 | ||
fa47f7e5 SS |
1204 | default_setup_apic_routing(); |
1205 | ||
4c9961d5 | 1206 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1207 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1208 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1209 | /* Or can we switch back to PIC here? */ |
1210 | } | |
1211 | ||
374aab33 | 1212 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1213 | |
c767a54b | 1214 | pr_info("CPU%d: ", 0); |
8aef135c | 1215 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1216 | |
1217 | if (is_uv_system()) | |
1218 | uv_system_init(); | |
d0af9eed SS |
1219 | |
1220 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1221 | |
1222 | smp_quirk_init_udelay(); | |
8aef135c | 1223 | } |
d0af9eed SS |
1224 | |
1225 | void arch_enable_nonboot_cpus_begin(void) | |
1226 | { | |
1227 | set_mtrr_aps_delayed_init(); | |
1228 | } | |
1229 | ||
1230 | void arch_enable_nonboot_cpus_end(void) | |
1231 | { | |
1232 | mtrr_aps_init(); | |
1233 | } | |
1234 | ||
a8db8453 GOC |
1235 | /* |
1236 | * Early setup to make printk work. | |
1237 | */ | |
1238 | void __init native_smp_prepare_boot_cpu(void) | |
1239 | { | |
1240 | int me = smp_processor_id(); | |
552be871 | 1241 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1242 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1243 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1244 | cpu_set_state_online(me); |
a8db8453 GOC |
1245 | } |
1246 | ||
83f7eb9c GOC |
1247 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1248 | { | |
c767a54b | 1249 | pr_debug("Boot done\n"); |
83f7eb9c | 1250 | |
99e8b9ca | 1251 | nmi_selftest(); |
83f7eb9c | 1252 | impress_friends(); |
83f7eb9c | 1253 | setup_ioapic_dest(); |
d0af9eed | 1254 | mtrr_aps_init(); |
83f7eb9c GOC |
1255 | } |
1256 | ||
3b11ce7f MT |
1257 | static int __initdata setup_possible_cpus = -1; |
1258 | static int __init _setup_possible_cpus(char *str) | |
1259 | { | |
1260 | get_option(&str, &setup_possible_cpus); | |
1261 | return 0; | |
1262 | } | |
1263 | early_param("possible_cpus", _setup_possible_cpus); | |
1264 | ||
1265 | ||
68a1c3f8 | 1266 | /* |
4f062896 | 1267 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1268 | * are onlined, or offlined. The reason is per-cpu data-structures |
1269 | * are allocated by some modules at init time, and dont expect to | |
1270 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1271 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1272 | * In case when cpu_hotplug is not compiled, then we resort to current |
1273 | * behaviour, which is cpu_possible == cpu_present. | |
1274 | * - Ashok Raj | |
1275 | * | |
1276 | * Three ways to find out the number of additional hotplug CPUs: | |
1277 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1278 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1279 | * - Otherwise don't reserve additional CPUs. |
1280 | * We do this because additional CPUs waste a lot of memory. | |
1281 | * -AK | |
1282 | */ | |
1283 | __init void prefill_possible_map(void) | |
1284 | { | |
cb48bb59 | 1285 | int i, possible; |
68a1c3f8 | 1286 | |
329513a3 YL |
1287 | /* no processor from mptable or madt */ |
1288 | if (!num_processors) | |
1289 | num_processors = 1; | |
1290 | ||
5f2eb550 JB |
1291 | i = setup_max_cpus ?: 1; |
1292 | if (setup_possible_cpus == -1) { | |
1293 | possible = num_processors; | |
1294 | #ifdef CONFIG_HOTPLUG_CPU | |
1295 | if (setup_max_cpus) | |
1296 | possible += disabled_cpus; | |
1297 | #else | |
1298 | if (possible > i) | |
1299 | possible = i; | |
1300 | #endif | |
1301 | } else | |
3b11ce7f MT |
1302 | possible = setup_possible_cpus; |
1303 | ||
730cf272 MT |
1304 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1305 | ||
2b633e3f YL |
1306 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1307 | if (possible > nr_cpu_ids) { | |
c767a54b | 1308 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1309 | possible, nr_cpu_ids); |
1310 | possible = nr_cpu_ids; | |
3b11ce7f | 1311 | } |
68a1c3f8 | 1312 | |
5f2eb550 JB |
1313 | #ifdef CONFIG_HOTPLUG_CPU |
1314 | if (!setup_max_cpus) | |
1315 | #endif | |
1316 | if (possible > i) { | |
c767a54b | 1317 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1318 | possible, setup_max_cpus); |
1319 | possible = i; | |
1320 | } | |
1321 | ||
c767a54b | 1322 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1323 | possible, max_t(int, possible - num_processors, 0)); |
1324 | ||
1325 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1326 | set_cpu_possible(i, true); |
5f2eb550 JB |
1327 | for (; i < NR_CPUS; i++) |
1328 | set_cpu_possible(i, false); | |
3461b0af MT |
1329 | |
1330 | nr_cpu_ids = possible; | |
68a1c3f8 | 1331 | } |
69c18c15 | 1332 | |
14adf855 CE |
1333 | #ifdef CONFIG_HOTPLUG_CPU |
1334 | ||
1335 | static void remove_siblinginfo(int cpu) | |
1336 | { | |
1337 | int sibling; | |
1338 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1339 | ||
7d79a7bd BG |
1340 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1341 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1342 | /*/ |
1343 | * last thread sibling in this cpu core going down | |
1344 | */ | |
7d79a7bd | 1345 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1346 | cpu_data(sibling).booted_cores--; |
1347 | } | |
1348 | ||
7d79a7bd BG |
1349 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1350 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1351 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1352 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1353 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1354 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1355 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1356 | c->phys_proc_id = 0; |
1357 | c->cpu_core_id = 0; | |
c2d1cec1 | 1358 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1359 | } |
1360 | ||
69c18c15 GC |
1361 | static void __ref remove_cpu_from_maps(int cpu) |
1362 | { | |
c2d1cec1 MT |
1363 | set_cpu_online(cpu, false); |
1364 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1365 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1366 | /* was set by cpu_init() */ |
c2d1cec1 | 1367 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1368 | numa_remove_cpu(cpu); |
69c18c15 GC |
1369 | } |
1370 | ||
8227dce7 | 1371 | void cpu_disable_common(void) |
69c18c15 GC |
1372 | { |
1373 | int cpu = smp_processor_id(); | |
69c18c15 | 1374 | |
69c18c15 GC |
1375 | remove_siblinginfo(cpu); |
1376 | ||
1377 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1378 | lock_vector_lock(); |
69c18c15 | 1379 | remove_cpu_from_maps(cpu); |
d388e5fd | 1380 | unlock_vector_lock(); |
d7b381bb | 1381 | fixup_irqs(); |
8227dce7 AN |
1382 | } |
1383 | ||
1384 | int native_cpu_disable(void) | |
1385 | { | |
da6139e4 PB |
1386 | int ret; |
1387 | ||
1388 | ret = check_irq_vectors_for_cpu_disable(); | |
1389 | if (ret) | |
1390 | return ret; | |
1391 | ||
8227dce7 | 1392 | clear_local_APIC(); |
8227dce7 | 1393 | cpu_disable_common(); |
2ed53c0d | 1394 | |
69c18c15 GC |
1395 | return 0; |
1396 | } | |
1397 | ||
2a442c9c | 1398 | int common_cpu_die(unsigned int cpu) |
54279552 | 1399 | { |
2a442c9c | 1400 | int ret = 0; |
54279552 | 1401 | |
69c18c15 | 1402 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1403 | |
2ed53c0d | 1404 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1405 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1406 | if (system_state == SYSTEM_RUNNING) |
1407 | pr_info("CPU %u is now offline\n", cpu); | |
1408 | } else { | |
1409 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1410 | ret = -1; |
69c18c15 | 1411 | } |
2a442c9c PM |
1412 | |
1413 | return ret; | |
1414 | } | |
1415 | ||
1416 | void native_cpu_die(unsigned int cpu) | |
1417 | { | |
1418 | common_cpu_die(cpu); | |
69c18c15 | 1419 | } |
a21f5d88 AN |
1420 | |
1421 | void play_dead_common(void) | |
1422 | { | |
1423 | idle_task_exit(); | |
1424 | reset_lazy_tlbstate(); | |
02c68a02 | 1425 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 | 1426 | |
a21f5d88 | 1427 | /* Ack it */ |
2a442c9c | 1428 | (void)cpu_report_death(); |
a21f5d88 AN |
1429 | |
1430 | /* | |
1431 | * With physical CPU hotplug, we should halt the cpu | |
1432 | */ | |
1433 | local_irq_disable(); | |
1434 | } | |
1435 | ||
e1c467e6 FY |
1436 | static bool wakeup_cpu0(void) |
1437 | { | |
1438 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1439 | return true; | |
1440 | ||
1441 | return false; | |
1442 | } | |
1443 | ||
ea530692 PA |
1444 | /* |
1445 | * We need to flush the caches before going to sleep, lest we have | |
1446 | * dirty data in our caches when we come back up. | |
1447 | */ | |
1448 | static inline void mwait_play_dead(void) | |
1449 | { | |
1450 | unsigned int eax, ebx, ecx, edx; | |
1451 | unsigned int highest_cstate = 0; | |
1452 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1453 | void *mwait_ptr; |
576cfb40 | 1454 | int i; |
ea530692 | 1455 | |
69fb3676 | 1456 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1457 | return; |
840d2830 | 1458 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1459 | return; |
7b543a53 | 1460 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1461 | return; |
1462 | ||
1463 | eax = CPUID_MWAIT_LEAF; | |
1464 | ecx = 0; | |
1465 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1466 | ||
1467 | /* | |
1468 | * eax will be 0 if EDX enumeration is not valid. | |
1469 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1470 | */ | |
1471 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1472 | eax = 0; | |
1473 | } else { | |
1474 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1475 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1476 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1477 | highest_cstate = i; | |
1478 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1479 | } | |
1480 | } | |
1481 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1482 | (highest_subcstate - 1); | |
1483 | } | |
1484 | ||
ce5f6824 PA |
1485 | /* |
1486 | * This should be a memory location in a cache line which is | |
1487 | * unlikely to be touched by other processors. The actual | |
1488 | * content is immaterial as it is not actually modified in any way. | |
1489 | */ | |
1490 | mwait_ptr = ¤t_thread_info()->flags; | |
1491 | ||
a68e5c94 PA |
1492 | wbinvd(); |
1493 | ||
ea530692 | 1494 | while (1) { |
ce5f6824 PA |
1495 | /* |
1496 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1497 | * the Xeon 7400 series. It's not clear it is actually | |
1498 | * needed, but it should be harmless in either case. | |
1499 | * The WBINVD is insufficient due to the spurious-wakeup | |
1500 | * case where we return around the loop. | |
1501 | */ | |
7d590cca | 1502 | mb(); |
ce5f6824 | 1503 | clflush(mwait_ptr); |
7d590cca | 1504 | mb(); |
ce5f6824 | 1505 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1506 | mb(); |
1507 | __mwait(eax, 0); | |
e1c467e6 FY |
1508 | /* |
1509 | * If NMI wants to wake up CPU0, start CPU0. | |
1510 | */ | |
1511 | if (wakeup_cpu0()) | |
1512 | start_cpu0(); | |
ea530692 PA |
1513 | } |
1514 | } | |
1515 | ||
1516 | static inline void hlt_play_dead(void) | |
1517 | { | |
7b543a53 | 1518 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1519 | wbinvd(); |
1520 | ||
ea530692 | 1521 | while (1) { |
ea530692 | 1522 | native_halt(); |
e1c467e6 FY |
1523 | /* |
1524 | * If NMI wants to wake up CPU0, start CPU0. | |
1525 | */ | |
1526 | if (wakeup_cpu0()) | |
1527 | start_cpu0(); | |
ea530692 PA |
1528 | } |
1529 | } | |
1530 | ||
a21f5d88 AN |
1531 | void native_play_dead(void) |
1532 | { | |
1533 | play_dead_common(); | |
86886e55 | 1534 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1535 | |
1536 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1537 | if (cpuidle_play_dead()) |
1538 | hlt_play_dead(); | |
a21f5d88 AN |
1539 | } |
1540 | ||
69c18c15 | 1541 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1542 | int native_cpu_disable(void) |
69c18c15 GC |
1543 | { |
1544 | return -ENOSYS; | |
1545 | } | |
1546 | ||
93be71b6 | 1547 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1548 | { |
1549 | /* We said "no" in __cpu_disable */ | |
1550 | BUG(); | |
1551 | } | |
a21f5d88 AN |
1552 | |
1553 | void native_play_dead(void) | |
1554 | { | |
1555 | BUG(); | |
1556 | } | |
1557 | ||
68a1c3f8 | 1558 | #endif |