[deliverable/linux.git] / arch / x86 / kernel / tlb_64.c

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/module.h>

#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/apic.h>
#include <asm/uv/uv.h>

DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
			= { &init_mm, 0, };

#include <mach_ipi.h>
/*
 *	Smarter SMP flushing macros.
 *		c/o Linus Torvalds.
 *
 *	These mean you can really definitely utterly forget about
 *	writing to user space from interrupts. (Its not allowed anyway).
 *
 *	Optimizations Manfred Spraul <manfred@colorfullife.com>
 *
 *	More scalable flush, from Andi Kleen
 *
 *	To avoid global state use 8 different call vectors.
 *	Each CPU uses a specific vector to trigger flushes on other
 *	CPUs. Depending on the received vector the target CPUs look into
 *	the right per cpu variable for the flush data.
 *
 *	With more than 8 CPUs they are hashed to the 8 available
 *	vectors. The limited global vector space forces us to this right now.
 *	In future when interrupts are split into per CPU domains this could be
 *	fixed, at the cost of triggering multiple IPIs in some cases.
 */

union smp_flush_state {
	struct {
		struct mm_struct *flush_mm;
		unsigned long flush_va;
		spinlock_t tlbstate_lock;
		DECLARE_BITMAP(flush_cpumask, NR_CPUS);
	};
	char pad[SMP_CACHE_BYTES];
} ____cacheline_aligned;

/* State is put into the per CPU data section, but padded
   to a full cache line because other CPUs can access it and we don't
   want false sharing in the per cpu data segment. */
static DEFINE_PER_CPU(union smp_flush_state, flush_state);

/*
 * We cannot call mmdrop() because we are in interrupt context,
 * instead update mm->cpu_vm_mask.
 */
void leave_mm(int cpu)
{
	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
		BUG();
	cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
	load_cr3(swapper_pg_dir);
}
EXPORT_SYMBOL_GPL(leave_mm);

/*
 *
 * The flush IPI assumes that a thread switch happens in this order:
 * [cpu0: the cpu that switches]
 * 1) switch_mm() either 1a) or 1b)
 * 1a) thread switch to a different mm
 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
 *	Stop ipi delivery for the old mm. This is not synchronized with
 *	the other cpus, but smp_invalidate_interrupt ignore flush ipis
 *	for the wrong mm, and in the worst case we perform a superfluous
 *	tlb flush.
 * 1a2) set cpu mmu_state to TLBSTATE_OK
 *	Now the smp_invalidate_interrupt won't call leave_mm if cpu0
 *	was in lazy tlb mode.
 * 1a3) update cpu active_mm
 *	Now cpu0 accepts tlb flushes for the new mm.
 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
 *	Now the other cpus will send tlb flush ipis.
 * 1a4) change cr3.
 * 1b) thread switch without mm change
 *	cpu active_mm is correct, cpu0 already handles
 *	flush ipis.
 * 1b1) set cpu mmu_state to TLBSTATE_OK
 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
 *	Atomically set the bit [other cpus will start sending flush ipis],
 *	and test the bit.
 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
 * 2) switch %%esp, ie current
 *
 * The interrupt must handle 2 special cases:
 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
 *   runs in kernel space, the cpu could load tlb entries for user space
 *   pages.
 *
 * The good news is that cpu mmu_state is local to each cpu, no
 * write/read ordering problems.
 */

/*
 * TLB flush IPI:
 *
 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
 * 2) Leave the mm if we are in the lazy tlb mode.
 *
 * Interrupts are disabled.
 */

asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
{
	unsigned int cpu;
	unsigned int sender;
	union smp_flush_state *f;

	cpu = smp_processor_id();
	/*
	 * orig_rax contains the negated interrupt vector.
	 * Use that to determine where the sender put the data.
	 */
	sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
	f = &per_cpu(flush_state, sender);

	if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
		goto out;
		/*
		 * This was a BUG() but until someone can quote me the
		 * line from the intel manual that guarantees an IPI to
		 * multiple CPUs is retried _only_ on the erroring CPUs
		 * its staying as a return
		 *
		 * BUG();
		 */

	if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
		if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
			if (f->flush_va == TLB_FLUSH_ALL)
				local_flush_tlb();
			else
				__flush_tlb_one(f->flush_va);
		} else
			leave_mm(cpu);
	}
out:
	ack_APIC_irq();
	smp_mb__before_clear_bit();
	cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
	smp_mb__after_clear_bit();
	inc_irq_stat(irq_tlb_count);
}

static void flush_tlb_others_ipi(const struct cpumask *cpumask,
				 struct mm_struct *mm, unsigned long va)
{
	unsigned int sender;
	union smp_flush_state *f;

	/* Caller has disabled preemption */
	sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
	f = &per_cpu(flush_state, sender);

	/*
	 * Could avoid this lock when
	 * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
	 * probably not worth checking this for a cache-hot lock.
	 */
	spin_lock(&f->tlbstate_lock);

	f->flush_mm = mm;
	f->flush_va = va;
	cpumask_andnot(to_cpumask(f->flush_cpumask),
		       cpumask, cpumask_of(smp_processor_id()));

	/*
	 * Make the above memory operations globally visible before
	 * sending the IPI.
	 */
	smp_mb();
	/*
	 * We have to send the IPI only to
	 * CPUs affected.
	 */
	send_IPI_mask(to_cpumask(f->flush_cpumask),
		      INVALIDATE_TLB_VECTOR_START + sender);

	while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
		cpu_relax();

	f->flush_mm = NULL;
	f->flush_va = 0;
	spin_unlock(&f->tlbstate_lock);
}

void native_flush_tlb_others(const struct cpumask *cpumask,
			     struct mm_struct *mm, unsigned long va)
{
	if (is_uv_system()) {
		unsigned int cpu;

		cpu = get_cpu();
		cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
		if (cpumask)
			flush_tlb_others_ipi(cpumask, mm, va);
		put_cpu();
		return;
	}
	flush_tlb_others_ipi(cpumask, mm, va);
}

static int __cpuinit init_smp_flush(void)
{
	int i;

	for_each_possible_cpu(i)
		spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);

	return 0;
}
core_initcall(init_smp_flush);

void flush_tlb_current_task(void)
{
	struct mm_struct *mm = current->mm;

	preempt_disable();

	local_flush_tlb();
	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
	preempt_enable();
}

void flush_tlb_mm(struct mm_struct *mm)
{
	preempt_disable();

	if (current->active_mm == mm) {
		if (current->mm)
			local_flush_tlb();
		else
			leave_mm(smp_processor_id());
	}
	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);

	preempt_enable();
}

void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
{
	struct mm_struct *mm = vma->vm_mm;

	preempt_disable();

	if (current->active_mm == mm) {
		if (current->mm)
			__flush_tlb_one(va);
		else
			leave_mm(smp_processor_id());
	}

	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, va);

	preempt_enable();
}

static void do_flush_tlb_all(void *info)
{
	unsigned long cpu = smp_processor_id();

	__flush_tlb_all();
	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
		leave_mm(cpu);
}

void flush_tlb_all(void)
{
	on_each_cpu(do_flush_tlb_all, NULL, 1);
}
Commit	Line	Data
c048fdfe GC	1	#include <linux/init.h>
	2
	3	#include <linux/mm.h>
c048fdfe GC	4	#include <linux/spinlock.h>
c048fdfe GC	5	#include <linux/smp.h>
c048fdfe	6	#include <linux/interrupt.h>
6dd01bed	7	#include <linux/module.h>
c048fdfe	8
c048fdfe	9	#include <asm/tlbflush.h>
c048fdfe	10	#include <asm/mmu_context.h>
6dd01bed	11	#include <asm/apic.h>
bdbcdd48	12	#include <asm/uv/uv.h>
5af5573e	13
9eb912d1 BG	14	DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
	15	= { &init_mm, 0, };
	16
5af5573e	17	#include <mach_ipi.h>
c048fdfe GC	18	/*
	19	* Smarter SMP flushing macros.
	20	* c/o Linus Torvalds.
	21	*
	22	* These mean you can really definitely utterly forget about
	23	* writing to user space from interrupts. (Its not allowed anyway).
	24	*
	25	* Optimizations Manfred Spraul <manfred@colorfullife.com>
	26	*
	27	* More scalable flush, from Andi Kleen
	28	*
	29	* To avoid global state use 8 different call vectors.
	30	* Each CPU uses a specific vector to trigger flushes on other
	31	* CPUs. Depending on the received vector the target CPUs look into
	32	* the right per cpu variable for the flush data.
	33	*
	34	* With more than 8 CPUs they are hashed to the 8 available
	35	* vectors. The limited global vector space forces us to this right now.
	36	* In future when interrupts are split into per CPU domains this could be
	37	* fixed, at the cost of triggering multiple IPIs in some cases.
	38	*/
	39
	40	union smp_flush_state {
	41	struct {
c048fdfe GC	42	struct mm_struct *flush_mm;
	43	unsigned long flush_va;
	44	spinlock_t tlbstate_lock;
4595f962	45	DECLARE_BITMAP(flush_cpumask, NR_CPUS);
c048fdfe GC	46	};
	47	char pad[SMP_CACHE_BYTES];
	48	} ____cacheline_aligned;
	49
	50	/* State is put into the per CPU data section, but padded
	51	to a full cache line because other CPUs can access it and we don't
	52	want false sharing in the per cpu data segment. */
	53	static DEFINE_PER_CPU(union smp_flush_state, flush_state);
	54
	55	/*
	56	* We cannot call mmdrop() because we are in interrupt context,
	57	* instead update mm->cpu_vm_mask.
	58	*/
	59	void leave_mm(int cpu)
	60	{
9eb912d1	61	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
c048fdfe	62	BUG();
9eb912d1	63	cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
c048fdfe GC	64	load_cr3(swapper_pg_dir);
	65	}
	66	EXPORT_SYMBOL_GPL(leave_mm);
	67
	68	/*
	69	*
	70	* The flush IPI assumes that a thread switch happens in this order:
	71	* [cpu0: the cpu that switches]
	72	* 1) switch_mm() either 1a) or 1b)
	73	* 1a) thread switch to a different mm
	74	* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
	75	* Stop ipi delivery for the old mm. This is not synchronized with
	76	* the other cpus, but smp_invalidate_interrupt ignore flush ipis
	77	* for the wrong mm, and in the worst case we perform a superfluous
	78	* tlb flush.
	79	* 1a2) set cpu mmu_state to TLBSTATE_OK
	80	* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
	81	* was in lazy tlb mode.
	82	* 1a3) update cpu active_mm
	83	* Now cpu0 accepts tlb flushes for the new mm.
	84	* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
	85	* Now the other cpus will send tlb flush ipis.
	86	* 1a4) change cr3.
	87	* 1b) thread switch without mm change
	88	* cpu active_mm is correct, cpu0 already handles
	89	* flush ipis.
	90	* 1b1) set cpu mmu_state to TLBSTATE_OK
	91	* 1b2) test_and_set the cpu bit in cpu_vm_mask.
	92	* Atomically set the bit [other cpus will start sending flush ipis],
	93	* and test the bit.
	94	* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
	95	* 2) switch %%esp, ie current
	96	*
	97	* The interrupt must handle 2 special cases:
	98	* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
	99	* - the cpu performs speculative tlb reads, i.e. even if the cpu only
	100	* runs in kernel space, the cpu could load tlb entries for user space
	101	* pages.
	102	*
	103	* The good news is that cpu mmu_state is local to each cpu, no
	104	* write/read ordering problems.
	105	*/
	106
	107	/*
	108	* TLB flush IPI:
	109	*
	110	* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
	111	* 2) Leave the mm if we are in the lazy tlb mode.
	112	*
	113	* Interrupts are disabled.
	114	*/
	115
	116	asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
	117	{
6dd01bed TH	118	unsigned int cpu;
6dd01bed TH	119	unsigned int sender;
c048fdfe GC	120	union smp_flush_state *f;
	121
	122	cpu = smp_processor_id();
	123	/*
	124	* orig_rax contains the negated interrupt vector.
	125	* Use that to determine where the sender put the data.
	126	*/
	127	sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
	128	f = &per_cpu(flush_state, sender);
	129
4595f962	130	if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
c048fdfe GC	131	goto out;
	132	/*
	133	* This was a BUG() but until someone can quote me the
	134	* line from the intel manual that guarantees an IPI to
	135	* multiple CPUs is retried _only_ on the erroring CPUs
	136	* its staying as a return
	137	*
	138	* BUG();
	139	*/
	140
9eb912d1 BG	141	if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
9eb912d1 BG	142	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
c048fdfe GC	143	if (f->flush_va == TLB_FLUSH_ALL)
	144	local_flush_tlb();
	145	else
	146	__flush_tlb_one(f->flush_va);
	147	} else
	148	leave_mm(cpu);
	149	}
	150	out:
	151	ack_APIC_irq();
6dd01bed	152	smp_mb__before_clear_bit();
4595f962	153	cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
6dd01bed	154	smp_mb__after_clear_bit();
8ae93669	155	inc_irq_stat(irq_tlb_count);
c048fdfe GC	156	}
c048fdfe GC	157
4595f962 RR	158	static void flush_tlb_others_ipi(const struct cpumask *cpumask,
4595f962 RR	159	struct mm_struct *mm, unsigned long va)
c048fdfe	160	{
6dd01bed	161	unsigned int sender;
c048fdfe	162	union smp_flush_state *f;
1812924b	163
c048fdfe GC	164	/* Caller has disabled preemption */
	165	sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
	166	f = &per_cpu(flush_state, sender);
	167
	168	/*
	169	* Could avoid this lock when
	170	* num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
	171	* probably not worth checking this for a cache-hot lock.
	172	*/
	173	spin_lock(&f->tlbstate_lock);
	174
	175	f->flush_mm = mm;
	176	f->flush_va = va;
4595f962 RR	177	cpumask_andnot(to_cpumask(f->flush_cpumask),
4595f962 RR	178	cpumask, cpumask_of(smp_processor_id()));
c048fdfe	179
d6f0f39b SS	180	/*
	181	* Make the above memory operations globally visible before
	182	* sending the IPI.
	183	*/
	184	smp_mb();
c048fdfe GC	185	/*
	186	* We have to send the IPI only to
	187	* CPUs affected.
	188	*/
54da5b3d IM	189	send_IPI_mask(to_cpumask(f->flush_cpumask),
54da5b3d IM	190	INVALIDATE_TLB_VECTOR_START + sender);
c048fdfe	191
4595f962	192	while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
c048fdfe GC	193	cpu_relax();
	194
	195	f->flush_mm = NULL;
	196	f->flush_va = 0;
	197	spin_unlock(&f->tlbstate_lock);
	198	}
	199
4595f962 RR	200	void native_flush_tlb_others(const struct cpumask *cpumask,
	201	struct mm_struct *mm, unsigned long va)
	202	{
	203	if (is_uv_system()) {
bdbcdd48	204	unsigned int cpu;
0e21990a	205
bdbcdd48 TH	206	cpu = get_cpu();
	207	cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
	208	if (cpumask)
	209	flush_tlb_others_ipi(cpumask, mm, va);
	210	put_cpu();
0e21990a	211	return;
4595f962 RR	212	}
	213	flush_tlb_others_ipi(cpumask, mm, va);
	214	}
	215
a4928cff	216	static int __cpuinit init_smp_flush(void)
c048fdfe GC	217	{
	218	int i;
	219
7c04e64a	220	for_each_possible_cpu(i)
c048fdfe	221	spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);
7c04e64a	222
c048fdfe GC	223	return 0;
	224	}
	225	core_initcall(init_smp_flush);
	226
	227	void flush_tlb_current_task(void)
	228	{
	229	struct mm_struct *mm = current->mm;
c048fdfe GC	230
c048fdfe GC	231	preempt_disable();
c048fdfe GC	232
c048fdfe GC	233	local_flush_tlb();
4595f962 RR	234	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	235	flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
c048fdfe GC	236	preempt_enable();
	237	}
	238
	239	void flush_tlb_mm(struct mm_struct *mm)
	240	{
c048fdfe	241	preempt_disable();
c048fdfe GC	242
	243	if (current->active_mm == mm) {
	244	if (current->mm)
	245	local_flush_tlb();
	246	else
	247	leave_mm(smp_processor_id());
	248	}
4595f962 RR	249	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	250	flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
c048fdfe GC	251
	252	preempt_enable();
	253	}
	254
	255	void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
	256	{
	257	struct mm_struct *mm = vma->vm_mm;
c048fdfe GC	258
c048fdfe GC	259	preempt_disable();
c048fdfe GC	260
	261	if (current->active_mm == mm) {
	262	if (current->mm)
	263	__flush_tlb_one(va);
	264	else
	265	leave_mm(smp_processor_id());
	266	}
	267
4595f962 RR	268	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	269	flush_tlb_others(&mm->cpu_vm_mask, mm, va);
c048fdfe GC	270
	271	preempt_enable();
	272	}
	273
	274	static void do_flush_tlb_all(void *info)
	275	{
	276	unsigned long cpu = smp_processor_id();
	277
	278	__flush_tlb_all();
9eb912d1	279	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
c048fdfe GC	280	leave_mm(cpu);
	281	}
	282
	283	void flush_tlb_all(void)
	284	{
15c8b6c1	285	on_each_cpu(do_flush_tlb_all, NULL, 1);
c048fdfe	286	}