[deliverable/linux.git] / arch / x86 / kernel / tlb_64.c

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/interrupt.h>

#include <asm/mtrr.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <asm/apicdef.h>
#include <asm/idle.h>
#include <asm/uv/uv.h>

DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
			= { &init_mm, 0, };

#include <mach_ipi.h>
/*
 *	Smarter SMP flushing macros.
 *		c/o Linus Torvalds.
 *
 *	These mean you can really definitely utterly forget about
 *	writing to user space from interrupts. (Its not allowed anyway).
 *
 *	Optimizations Manfred Spraul <manfred@colorfullife.com>
 *
 *	More scalable flush, from Andi Kleen
 *
 *	To avoid global state use 8 different call vectors.
 *	Each CPU uses a specific vector to trigger flushes on other
 *	CPUs. Depending on the received vector the target CPUs look into
 *	the right per cpu variable for the flush data.
 *
 *	With more than 8 CPUs they are hashed to the 8 available
 *	vectors. The limited global vector space forces us to this right now.
 *	In future when interrupts are split into per CPU domains this could be
 *	fixed, at the cost of triggering multiple IPIs in some cases.
 */

union smp_flush_state {
	struct {
		struct mm_struct *flush_mm;
		unsigned long flush_va;
		spinlock_t tlbstate_lock;
		DECLARE_BITMAP(flush_cpumask, NR_CPUS);
	};
	char pad[SMP_CACHE_BYTES];
} ____cacheline_aligned;

/* State is put into the per CPU data section, but padded
   to a full cache line because other CPUs can access it and we don't
   want false sharing in the per cpu data segment. */
static DEFINE_PER_CPU(union smp_flush_state, flush_state);

/*
 * We cannot call mmdrop() because we are in interrupt context,
 * instead update mm->cpu_vm_mask.
 */
void leave_mm(int cpu)
{
	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
		BUG();
	cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
	load_cr3(swapper_pg_dir);
}
EXPORT_SYMBOL_GPL(leave_mm);

/*
 *
 * The flush IPI assumes that a thread switch happens in this order:
 * [cpu0: the cpu that switches]
 * 1) switch_mm() either 1a) or 1b)
 * 1a) thread switch to a different mm
 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
 *	Stop ipi delivery for the old mm. This is not synchronized with
 *	the other cpus, but smp_invalidate_interrupt ignore flush ipis
 *	for the wrong mm, and in the worst case we perform a superfluous
 *	tlb flush.
 * 1a2) set cpu mmu_state to TLBSTATE_OK
 *	Now the smp_invalidate_interrupt won't call leave_mm if cpu0
 *	was in lazy tlb mode.
 * 1a3) update cpu active_mm
 *	Now cpu0 accepts tlb flushes for the new mm.
 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
 *	Now the other cpus will send tlb flush ipis.
 * 1a4) change cr3.
 * 1b) thread switch without mm change
 *	cpu active_mm is correct, cpu0 already handles
 *	flush ipis.
 * 1b1) set cpu mmu_state to TLBSTATE_OK
 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
 *	Atomically set the bit [other cpus will start sending flush ipis],
 *	and test the bit.
 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
 * 2) switch %%esp, ie current
 *
 * The interrupt must handle 2 special cases:
 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
 *   runs in kernel space, the cpu could load tlb entries for user space
 *   pages.
 *
 * The good news is that cpu mmu_state is local to each cpu, no
 * write/read ordering problems.
 */

/*
 * TLB flush IPI:
 *
 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
 * 2) Leave the mm if we are in the lazy tlb mode.
 *
 * Interrupts are disabled.
 */

asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
{
	int cpu;
	int sender;
	union smp_flush_state *f;

	cpu = smp_processor_id();
	/*
	 * orig_rax contains the negated interrupt vector.
	 * Use that to determine where the sender put the data.
	 */
	sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
	f = &per_cpu(flush_state, sender);

	if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
		goto out;
		/*
		 * This was a BUG() but until someone can quote me the
		 * line from the intel manual that guarantees an IPI to
		 * multiple CPUs is retried _only_ on the erroring CPUs
		 * its staying as a return
		 *
		 * BUG();
		 */

	if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
		if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
			if (f->flush_va == TLB_FLUSH_ALL)
				local_flush_tlb();
			else
				__flush_tlb_one(f->flush_va);
		} else
			leave_mm(cpu);
	}
out:
	ack_APIC_irq();
	cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
	inc_irq_stat(irq_tlb_count);
}

static void flush_tlb_others_ipi(const struct cpumask *cpumask,
				 struct mm_struct *mm, unsigned long va)
{
	int sender;
	union smp_flush_state *f;

	/* Caller has disabled preemption */
	sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
	f = &per_cpu(flush_state, sender);

	/*
	 * Could avoid this lock when
	 * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
	 * probably not worth checking this for a cache-hot lock.
	 */
	spin_lock(&f->tlbstate_lock);

	f->flush_mm = mm;
	f->flush_va = va;
	cpumask_andnot(to_cpumask(f->flush_cpumask),
		       cpumask, cpumask_of(smp_processor_id()));

	/*
	 * Make the above memory operations globally visible before
	 * sending the IPI.
	 */
	smp_mb();
	/*
	 * We have to send the IPI only to
	 * CPUs affected.
	 */
	send_IPI_mask(to_cpumask(f->flush_cpumask),
		      INVALIDATE_TLB_VECTOR_START + sender);

	while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
		cpu_relax();

	f->flush_mm = NULL;
	f->flush_va = 0;
	spin_unlock(&f->tlbstate_lock);
}

void native_flush_tlb_others(const struct cpumask *cpumask,
			     struct mm_struct *mm, unsigned long va)
{
	if (is_uv_system()) {
		unsigned int cpu;

		cpu = get_cpu();
		cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
		if (cpumask)
			flush_tlb_others_ipi(cpumask, mm, va);
		put_cpu();
		return;
	}
	flush_tlb_others_ipi(cpumask, mm, va);
}

static int __cpuinit init_smp_flush(void)
{
	int i;

	for_each_possible_cpu(i)
		spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);

	return 0;
}
core_initcall(init_smp_flush);

void flush_tlb_current_task(void)
{
	struct mm_struct *mm = current->mm;

	preempt_disable();

	local_flush_tlb();
	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
	preempt_enable();
}

void flush_tlb_mm(struct mm_struct *mm)
{
	preempt_disable();

	if (current->active_mm == mm) {
		if (current->mm)
			local_flush_tlb();
		else
			leave_mm(smp_processor_id());
	}
	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);

	preempt_enable();
}

void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
{
	struct mm_struct *mm = vma->vm_mm;

	preempt_disable();

	if (current->active_mm == mm) {
		if (current->mm)
			__flush_tlb_one(va);
		else
			leave_mm(smp_processor_id());
	}

	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
		flush_tlb_others(&mm->cpu_vm_mask, mm, va);

	preempt_enable();
}

static void do_flush_tlb_all(void *info)
{
	unsigned long cpu = smp_processor_id();

	__flush_tlb_all();
	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
		leave_mm(cpu);
}

void flush_tlb_all(void)
{
	on_each_cpu(do_flush_tlb_all, NULL, 1);
}
Commit	Line	Data
c048fdfe GC	1	#include <linux/init.h>
	2
	3	#include <linux/mm.h>
	4	#include <linux/delay.h>
	5	#include <linux/spinlock.h>
	6	#include <linux/smp.h>
	7	#include <linux/kernel_stat.h>
	8	#include <linux/mc146818rtc.h>
	9	#include <linux/interrupt.h>
	10
	11	#include <asm/mtrr.h>
	12	#include <asm/pgalloc.h>
	13	#include <asm/tlbflush.h>
c048fdfe GC	14	#include <asm/mmu_context.h>
	15	#include <asm/proto.h>
	16	#include <asm/apicdef.h>
	17	#include <asm/idle.h>
bdbcdd48	18	#include <asm/uv/uv.h>
5af5573e	19
9eb912d1 BG	20	DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
	21	= { &init_mm, 0, };
	22
5af5573e	23	#include <mach_ipi.h>
c048fdfe GC	24	/*
	25	* Smarter SMP flushing macros.
	26	* c/o Linus Torvalds.
	27	*
	28	* These mean you can really definitely utterly forget about
	29	* writing to user space from interrupts. (Its not allowed anyway).
	30	*
	31	* Optimizations Manfred Spraul <manfred@colorfullife.com>
	32	*
	33	* More scalable flush, from Andi Kleen
	34	*
	35	* To avoid global state use 8 different call vectors.
	36	* Each CPU uses a specific vector to trigger flushes on other
	37	* CPUs. Depending on the received vector the target CPUs look into
	38	* the right per cpu variable for the flush data.
	39	*
	40	* With more than 8 CPUs they are hashed to the 8 available
	41	* vectors. The limited global vector space forces us to this right now.
	42	* In future when interrupts are split into per CPU domains this could be
	43	* fixed, at the cost of triggering multiple IPIs in some cases.
	44	*/
	45
	46	union smp_flush_state {
	47	struct {
c048fdfe GC	48	struct mm_struct *flush_mm;
	49	unsigned long flush_va;
	50	spinlock_t tlbstate_lock;
4595f962	51	DECLARE_BITMAP(flush_cpumask, NR_CPUS);
c048fdfe GC	52	};
	53	char pad[SMP_CACHE_BYTES];
	54	} ____cacheline_aligned;
	55
	56	/* State is put into the per CPU data section, but padded
	57	to a full cache line because other CPUs can access it and we don't
	58	want false sharing in the per cpu data segment. */
	59	static DEFINE_PER_CPU(union smp_flush_state, flush_state);
	60
	61	/*
	62	* We cannot call mmdrop() because we are in interrupt context,
	63	* instead update mm->cpu_vm_mask.
	64	*/
	65	void leave_mm(int cpu)
	66	{
9eb912d1	67	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
c048fdfe	68	BUG();
9eb912d1	69	cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
c048fdfe GC	70	load_cr3(swapper_pg_dir);
	71	}
	72	EXPORT_SYMBOL_GPL(leave_mm);
	73
	74	/*
	75	*
	76	* The flush IPI assumes that a thread switch happens in this order:
	77	* [cpu0: the cpu that switches]
	78	* 1) switch_mm() either 1a) or 1b)
	79	* 1a) thread switch to a different mm
	80	* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
	81	* Stop ipi delivery for the old mm. This is not synchronized with
	82	* the other cpus, but smp_invalidate_interrupt ignore flush ipis
	83	* for the wrong mm, and in the worst case we perform a superfluous
	84	* tlb flush.
	85	* 1a2) set cpu mmu_state to TLBSTATE_OK
	86	* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
	87	* was in lazy tlb mode.
	88	* 1a3) update cpu active_mm
	89	* Now cpu0 accepts tlb flushes for the new mm.
	90	* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
	91	* Now the other cpus will send tlb flush ipis.
	92	* 1a4) change cr3.
	93	* 1b) thread switch without mm change
	94	* cpu active_mm is correct, cpu0 already handles
	95	* flush ipis.
	96	* 1b1) set cpu mmu_state to TLBSTATE_OK
	97	* 1b2) test_and_set the cpu bit in cpu_vm_mask.
	98	* Atomically set the bit [other cpus will start sending flush ipis],
	99	* and test the bit.
	100	* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
	101	* 2) switch %%esp, ie current
	102	*
	103	* The interrupt must handle 2 special cases:
	104	* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
	105	* - the cpu performs speculative tlb reads, i.e. even if the cpu only
	106	* runs in kernel space, the cpu could load tlb entries for user space
	107	* pages.
	108	*
	109	* The good news is that cpu mmu_state is local to each cpu, no
	110	* write/read ordering problems.
	111	*/
	112
	113	/*
	114	* TLB flush IPI:
	115	*
	116	* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
	117	* 2) Leave the mm if we are in the lazy tlb mode.
	118	*
	119	* Interrupts are disabled.
	120	*/
	121
	122	asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
	123	{
	124	int cpu;
	125	int sender;
	126	union smp_flush_state *f;
	127
	128	cpu = smp_processor_id();
	129	/*
	130	* orig_rax contains the negated interrupt vector.
	131	* Use that to determine where the sender put the data.
	132	*/
	133	sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
134	f = &per_cpu(flush_state, sender);
135
4595f962	136	if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
c048fdfe GC	137	goto out;
	138	/*
	139	* This was a BUG() but until someone can quote me the
	140	* line from the intel manual that guarantees an IPI to
	141	* multiple CPUs is retried _only_ on the erroring CPUs
	142	* its staying as a return
	143	*
	144	* BUG();
	145	*/
	146
9eb912d1 BG	147	if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
9eb912d1 BG	148	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
c048fdfe GC	149	if (f->flush_va == TLB_FLUSH_ALL)
	150	local_flush_tlb();
	151	else
	152	__flush_tlb_one(f->flush_va);
	153	} else
	154	leave_mm(cpu);
	155	}
	156	out:
	157	ack_APIC_irq();
4595f962	158	cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
8ae93669	159	inc_irq_stat(irq_tlb_count);
c048fdfe GC	160	}
c048fdfe GC	161
4595f962 RR	162	static void flush_tlb_others_ipi(const struct cpumask *cpumask,
4595f962 RR	163	struct mm_struct *mm, unsigned long va)
c048fdfe GC	164	{
	165	int sender;
	166	union smp_flush_state *f;
1812924b	167
c048fdfe GC	168	/* Caller has disabled preemption */
	169	sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
	170	f = &per_cpu(flush_state, sender);
	171
	172	/*
	173	* Could avoid this lock when
	174	* num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
	175	* probably not worth checking this for a cache-hot lock.
	176	*/
	177	spin_lock(&f->tlbstate_lock);
	178
	179	f->flush_mm = mm;
	180	f->flush_va = va;
4595f962 RR	181	cpumask_andnot(to_cpumask(f->flush_cpumask),
4595f962 RR	182	cpumask, cpumask_of(smp_processor_id()));
c048fdfe	183
d6f0f39b SS	184	/*
	185	* Make the above memory operations globally visible before
	186	* sending the IPI.
	187	*/
	188	smp_mb();
c048fdfe GC	189	/*
	190	* We have to send the IPI only to
	191	* CPUs affected.
	192	*/
54da5b3d IM	193	send_IPI_mask(to_cpumask(f->flush_cpumask),
54da5b3d IM	194	INVALIDATE_TLB_VECTOR_START + sender);
c048fdfe	195
4595f962	196	while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
c048fdfe GC	197	cpu_relax();
	198
	199	f->flush_mm = NULL;
	200	f->flush_va = 0;
	201	spin_unlock(&f->tlbstate_lock);
	202	}
	203
4595f962 RR	204	void native_flush_tlb_others(const struct cpumask *cpumask,
	205	struct mm_struct *mm, unsigned long va)
	206	{
	207	if (is_uv_system()) {
bdbcdd48	208	unsigned int cpu;
0e21990a	209
bdbcdd48 TH	210	cpu = get_cpu();
	211	cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
	212	if (cpumask)
	213	flush_tlb_others_ipi(cpumask, mm, va);
	214	put_cpu();
0e21990a	215	return;
4595f962 RR	216	}
	217	flush_tlb_others_ipi(cpumask, mm, va);
	218	}
	219
a4928cff	220	static int __cpuinit init_smp_flush(void)
c048fdfe GC	221	{
	222	int i;
	223
7c04e64a	224	for_each_possible_cpu(i)
c048fdfe	225	spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);
7c04e64a	226
c048fdfe GC	227	return 0;
	228	}
	229	core_initcall(init_smp_flush);
	230
	231	void flush_tlb_current_task(void)
	232	{
	233	struct mm_struct *mm = current->mm;
c048fdfe GC	234
c048fdfe GC	235	preempt_disable();
c048fdfe GC	236
c048fdfe GC	237	local_flush_tlb();
4595f962 RR	238	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	239	flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
c048fdfe GC	240	preempt_enable();
	241	}
	242
	243	void flush_tlb_mm(struct mm_struct *mm)
	244	{
c048fdfe	245	preempt_disable();
c048fdfe GC	246
	247	if (current->active_mm == mm) {
	248	if (current->mm)
	249	local_flush_tlb();
	250	else
	251	leave_mm(smp_processor_id());
	252	}
4595f962 RR	253	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	254	flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
c048fdfe GC	255
	256	preempt_enable();
	257	}
	258
	259	void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
	260	{
	261	struct mm_struct *mm = vma->vm_mm;
c048fdfe GC	262
c048fdfe GC	263	preempt_disable();
c048fdfe GC	264
	265	if (current->active_mm == mm) {
	266	if (current->mm)
	267	__flush_tlb_one(va);
	268	else
	269	leave_mm(smp_processor_id());
	270	}
	271
4595f962 RR	272	if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
4595f962 RR	273	flush_tlb_others(&mm->cpu_vm_mask, mm, va);
c048fdfe GC	274
	275	preempt_enable();
	276	}
	277
	278	static void do_flush_tlb_all(void *info)
	279	{
	280	unsigned long cpu = smp_processor_id();
	281
	282	__flush_tlb_all();
9eb912d1	283	if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
c048fdfe GC	284	leave_mm(cpu);
	285	}
	286
	287	void flush_tlb_all(void)
	288	{
15c8b6c1	289	on_each_cpu(do_flush_tlb_all, NULL, 1);
c048fdfe	290	}