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KVM: MMU: make direct mapping paths aware of mapping levels
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
6de4f3ad 21#include "kvm_cache_regs.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732
AK		 24#include <linux/types.h>
25#include <linux/string.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
05da4558 30#include <linux/hugetlb.h>
2f333bcb 31#include <linux/compiler.h>
6aa8b732 32
e495606d
AK		 33#include <asm/page.h>
34#include <asm/cmpxchg.h>
4e542370 35#include <asm/io.h>
13673a90 36#include <asm/vmx.h>
6aa8b732 37
18552672
JR		 38/*
39 * When setting this variable to true it enables Two-Dimensional-Paging
40 * where the hardware walks 2 page tables:
41 * 1. the guest-virtual to guest-physical
42 * 2. while doing 1. it walks guest-physical to host-physical
43 * If the hardware supports that we don't need to do shadow paging.
44 */
2f333bcb 45bool tdp_enabled = false;
18552672 46
37a7d8b0
AK		 47#undef MMU_DEBUG
48
49#undef AUDIT
50
51#ifdef AUDIT
52static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
53#else
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
55#endif
56
57#ifdef MMU_DEBUG
58
59#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
60#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
61
62#else
63
64#define pgprintk(x...) do { } while (0)
65#define rmap_printk(x...) do { } while (0)
66
67#endif
68
69#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 70static int dbg = 0;
71module_param(dbg, bool, 0644);
37a7d8b0 72#endif
6aa8b732 73
582801a9
MT		 74static int oos_shadow = 1;
75module_param(oos_shadow, bool, 0644);
76
d6c69ee9
YD		 77#ifndef MMU_DEBUG
78#define ASSERT(x) do { } while (0)
79#else
6aa8b732
AK		 80#define ASSERT(x) \
81 if (!(x)) { \
82 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
83 __FILE__, __LINE__, #x); \
84 }
d6c69ee9 85#endif
6aa8b732 86
6aa8b732
AK		 87#define PT_FIRST_AVAIL_BITS_SHIFT 9
88#define PT64_SECOND_AVAIL_BITS_SHIFT 52
89
6aa8b732
AK		 90#define VALID_PAGE(x) ((x) != INVALID_PAGE)
91
92#define PT64_LEVEL_BITS 9
93
94#define PT64_LEVEL_SHIFT(level) \
d77c26fc 95 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 96
97#define PT64_LEVEL_MASK(level) \
98 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
99
100#define PT64_INDEX(address, level)\
101 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
102
103
104#define PT32_LEVEL_BITS 10
105
106#define PT32_LEVEL_SHIFT(level) \
d77c26fc 107 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 108
109#define PT32_LEVEL_MASK(level) \
110 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
111
112#define PT32_INDEX(address, level)\
113 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
114
115
27aba766 116#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 117#define PT64_DIR_BASE_ADDR_MASK \
118 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
119
120#define PT32_BASE_ADDR_MASK PAGE_MASK
121#define PT32_DIR_BASE_ADDR_MASK \
122 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
123
79539cec
AK		 124#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
125 | PT64_NX_MASK)
6aa8b732
AK		 126
127#define PFERR_PRESENT_MASK (1U << 0)
128#define PFERR_WRITE_MASK (1U << 1)
129#define PFERR_USER_MASK (1U << 2)
82725b20 130#define PFERR_RSVD_MASK (1U << 3)
73b1087e 131#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 132
6aa8b732
AK		 133#define PT_DIRECTORY_LEVEL 2
134#define PT_PAGE_TABLE_LEVEL 1
135
cd4a4e53
AK		 136#define RMAP_EXT 4
137
fe135d2c
AK		 138#define ACC_EXEC_MASK 1
139#define ACC_WRITE_MASK PT_WRITABLE_MASK
140#define ACC_USER_MASK PT_USER_MASK
141#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
142
07420171
AK		 143#define CREATE_TRACE_POINTS
144#include "mmutrace.h"
145
135f8c2b
AK		 146#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
147
cd4a4e53 148struct kvm_rmap_desc {
d555c333 149 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 150 struct kvm_rmap_desc *more;
151};
152
2d11123a
AK		 153struct kvm_shadow_walk_iterator {
154 u64 addr;
155 hpa_t shadow_addr;
156 int level;
157 u64 *sptep;
158 unsigned index;
159};
160
161#define for_each_shadow_entry(_vcpu, _addr, _walker) \
162 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
163 shadow_walk_okay(&(_walker)); \
164 shadow_walk_next(&(_walker)))
165
166
4731d4c7
MT		 167struct kvm_unsync_walk {
168 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
169};
170
ad8cfbe3
MT		 171typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
172
b5a33a75
AK		 173static struct kmem_cache *pte_chain_cache;
174static struct kmem_cache *rmap_desc_cache;
d3d25b04 175static struct kmem_cache *mmu_page_header_cache;
b5a33a75 176
c7addb90
AK		 177static u64 __read_mostly shadow_trap_nonpresent_pte;
178static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 179static u64 __read_mostly shadow_base_present_pte;
180static u64 __read_mostly shadow_nx_mask;
181static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
182static u64 __read_mostly shadow_user_mask;
183static u64 __read_mostly shadow_accessed_mask;
184static u64 __read_mostly shadow_dirty_mask;
c7addb90 185
82725b20
DE		 186static inline u64 rsvd_bits(int s, int e)
187{
188 return ((1ULL << (e - s + 1)) - 1) << s;
189}
190
c7addb90
AK		 191void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
192{
193 shadow_trap_nonpresent_pte = trap_pte;
194 shadow_notrap_nonpresent_pte = notrap_pte;
195}
196EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
197
7b52345e
SY		 198void kvm_mmu_set_base_ptes(u64 base_pte)
199{
200 shadow_base_present_pte = base_pte;
201}
202EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
203
204void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 205 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 206{
207 shadow_user_mask = user_mask;
208 shadow_accessed_mask = accessed_mask;
209 shadow_dirty_mask = dirty_mask;
210 shadow_nx_mask = nx_mask;
211 shadow_x_mask = x_mask;
212}
213EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
214
6aa8b732
AK		 215static int is_write_protection(struct kvm_vcpu *vcpu)
216{
ad312c7c 217 return vcpu->arch.cr0 & X86_CR0_WP;
6aa8b732
AK		 218}
219
220static int is_cpuid_PSE36(void)
221{
222 return 1;
223}
224
73b1087e
AK		 225static int is_nx(struct kvm_vcpu *vcpu)
226{
ad312c7c 227 return vcpu->arch.shadow_efer & EFER_NX;
73b1087e
AK		 228}
229
c7addb90
AK		 230static int is_shadow_present_pte(u64 pte)
231{
c7addb90
AK		 232 return pte != shadow_trap_nonpresent_pte
233 && pte != shadow_notrap_nonpresent_pte;
234}
235
05da4558
MT		 236static int is_large_pte(u64 pte)
237{
238 return pte & PT_PAGE_SIZE_MASK;
239}
240
6aa8b732
AK		 241static int is_writeble_pte(unsigned long pte)
242{
243 return pte & PT_WRITABLE_MASK;
244}
245
43a3795a 246static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 247{
439e218a 248 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 249}
250
43a3795a 251static int is_rmap_spte(u64 pte)
cd4a4e53 252{
4b1a80fa 253 return is_shadow_present_pte(pte);
cd4a4e53
AK		 254}
255
776e6633
MT		 256static int is_last_spte(u64 pte, int level)
257{
258 if (level == PT_PAGE_TABLE_LEVEL)
259 return 1;
852e3c19 260 if (is_large_pte(pte))
776e6633
MT		 261 return 1;
262 return 0;
263}
264
35149e21 265static pfn_t spte_to_pfn(u64 pte)
0b49ea86 266{
35149e21 267 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 268}
269
da928521
AK		 270static gfn_t pse36_gfn_delta(u32 gpte)
271{
272 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
273
274 return (gpte & PT32_DIR_PSE36_MASK) << shift;
275}
276
d555c333 277static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 278{
279#ifdef CONFIG_X86_64
280 set_64bit((unsigned long *)sptep, spte);
281#else
282 set_64bit((unsigned long long *)sptep, spte);
283#endif
284}
285
e2dec939 286static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 287 struct kmem_cache *base_cache, int min)
714b93da
AK		 288{
289 void *obj;
290
291 if (cache->nobjs >= min)
e2dec939 292 return 0;
714b93da 293 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 294 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 295 if (!obj)
e2dec939 296 return -ENOMEM;
714b93da
AK		 297 cache->objects[cache->nobjs++] = obj;
298 }
e2dec939 299 return 0;
714b93da
AK		 300}
301
302static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
303{
304 while (mc->nobjs)
305 kfree(mc->objects[--mc->nobjs]);
306}
307
c1158e63 308static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 309 int min)
c1158e63
AK		 310{
311 struct page *page;
312
313 if (cache->nobjs >= min)
314 return 0;
315 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 316 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 317 if (!page)
318 return -ENOMEM;
319 set_page_private(page, 0);
320 cache->objects[cache->nobjs++] = page_address(page);
321 }
322 return 0;
323}
324
325static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
326{
327 while (mc->nobjs)
c4d198d5 328 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 329}
330
2e3e5882 331static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 332{
e2dec939
AK		 333 int r;
334
ad312c7c 335 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 336 pte_chain_cache, 4);
e2dec939
AK		 337 if (r)
338 goto out;
ad312c7c 339 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 340 rmap_desc_cache, 4);
d3d25b04
AK		 341 if (r)
342 goto out;
ad312c7c 343 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 344 if (r)
345 goto out;
ad312c7c 346 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 347 mmu_page_header_cache, 4);
e2dec939
AK		 348out:
349 return r;
714b93da
AK		 350}
351
352static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
353{
ad312c7c
ZX		 354 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
355 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
356 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
357 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 358}
359
360static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
361 size_t size)
362{
363 void *p;
364
365 BUG_ON(!mc->nobjs);
366 p = mc->objects[--mc->nobjs];
714b93da
AK		 367 return p;
368}
369
714b93da
AK		 370static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
371{
ad312c7c 372 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 373 sizeof(struct kvm_pte_chain));
374}
375
90cb0529 376static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 377{
90cb0529 378 kfree(pc);
714b93da
AK		 379}
380
381static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
382{
ad312c7c 383 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 384 sizeof(struct kvm_rmap_desc));
385}
386
90cb0529 387static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 388{
90cb0529 389 kfree(rd);
714b93da
AK		 390}
391
05da4558
MT		 392/*
393 * Return the pointer to the largepage write count for a given
394 * gfn, handling slots that are not large page aligned.
395 */
d25797b2
JR		 396static int *slot_largepage_idx(gfn_t gfn,
397 struct kvm_memory_slot *slot,
398 int level)
05da4558
MT		 399{
400 unsigned long idx;
401
d25797b2
JR		 402 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
403 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
404 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 405}
406
407static void account_shadowed(struct kvm *kvm, gfn_t gfn)
408{
d25797b2 409 struct kvm_memory_slot *slot;
05da4558 410 int *write_count;
d25797b2 411 int i;
05da4558 412
2843099f 413 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 414
415 slot = gfn_to_memslot_unaliased(kvm, gfn);
416 for (i = PT_DIRECTORY_LEVEL;
417 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
418 write_count = slot_largepage_idx(gfn, slot, i);
419 *write_count += 1;
420 }
05da4558
MT		 421}
422
423static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
424{
d25797b2 425 struct kvm_memory_slot *slot;
05da4558 426 int *write_count;
d25797b2 427 int i;
05da4558 428
2843099f 429 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 430 for (i = PT_DIRECTORY_LEVEL;
431 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
432 slot = gfn_to_memslot_unaliased(kvm, gfn);
433 write_count = slot_largepage_idx(gfn, slot, i);
434 *write_count -= 1;
435 WARN_ON(*write_count < 0);
436 }
05da4558
MT		 437}
438
d25797b2
JR		 439static int has_wrprotected_page(struct kvm *kvm,
440 gfn_t gfn,
441 int level)
05da4558 442{
2843099f 443 struct kvm_memory_slot *slot;
05da4558
MT		 444 int *largepage_idx;
445
2843099f
IE		 446 gfn = unalias_gfn(kvm, gfn);
447 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 448 if (slot) {
d25797b2 449 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 450 return *largepage_idx;
451 }
452
453 return 1;
454}
455
d25797b2 456static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 457{
d25797b2 458 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 459 struct vm_area_struct *vma;
460 unsigned long addr;
d25797b2 461 int i, ret = 0;
05da4558
MT		 462
463 addr = gfn_to_hva(kvm, gfn);
464 if (kvm_is_error_hva(addr))
d25797b2 465 return page_size;
05da4558 466
4c2155ce 467 down_read(&current->mm->mmap_sem);
05da4558 468 vma = find_vma(current->mm, addr);
d25797b2
JR		 469 if (!vma)
470 goto out;
471
472 page_size = vma_kernel_pagesize(vma);
473
474out:
4c2155ce 475 up_read(&current->mm->mmap_sem);
05da4558 476
d25797b2
JR		 477 for (i = PT_PAGE_TABLE_LEVEL;
478 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
479 if (page_size >= KVM_HPAGE_SIZE(i))
480 ret = i;
481 else
482 break;
483 }
484
4c2155ce 485 return ret;
05da4558
MT		 486}
487
d25797b2 488static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 489{
490 struct kvm_memory_slot *slot;
d25797b2
JR		 491 int host_level;
492 int level = PT_PAGE_TABLE_LEVEL;
05da4558
MT		 493
494 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
495 if (slot && slot->dirty_bitmap)
d25797b2 496 return PT_PAGE_TABLE_LEVEL;
05da4558 497
d25797b2
JR		 498 host_level = host_mapping_level(vcpu->kvm, large_gfn);
499
500 if (host_level == PT_PAGE_TABLE_LEVEL)
501 return host_level;
502
503 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level) {
504
505 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
506 break;
507 }
508
509 return level - 1;
05da4558
MT		 510}
511
290fc38d
IE		 512/*
513 * Take gfn and return the reverse mapping to it.
514 * Note: gfn must be unaliased before this function get called
515 */
516
44ad9944 517static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 518{
519 struct kvm_memory_slot *slot;
05da4558 520 unsigned long idx;
290fc38d
IE		 521
522 slot = gfn_to_memslot(kvm, gfn);
44ad9944 523 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 524 return &slot->rmap[gfn - slot->base_gfn];
525
44ad9944
JR		 526 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
527 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 528
44ad9944 529 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 530}
531
cd4a4e53
AK		 532/*
533 * Reverse mapping data structures:
534 *
290fc38d
IE		 535 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
536 * that points to page_address(page).
cd4a4e53 537 *
290fc38d
IE		 538 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
539 * containing more mappings.
53a27b39
MT		 540 *
541 * Returns the number of rmap entries before the spte was added or zero if
542 * the spte was not added.
543 *
cd4a4e53 544 */
44ad9944 545static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 546{
4db35314 547 struct kvm_mmu_page *sp;
cd4a4e53 548 struct kvm_rmap_desc *desc;
290fc38d 549 unsigned long *rmapp;
53a27b39 550 int i, count = 0;
cd4a4e53 551
43a3795a 552 if (!is_rmap_spte(*spte))
53a27b39 553 return count;
290fc38d 554 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 555 sp = page_header(__pa(spte));
556 sp->gfns[spte - sp->spt] = gfn;
44ad9944 557 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 558 if (!*rmapp) {
cd4a4e53 559 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 560 *rmapp = (unsigned long)spte;
561 } else if (!(*rmapp & 1)) {
cd4a4e53 562 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 563 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 564 desc->sptes[0] = (u64 *)*rmapp;
565 desc->sptes[1] = spte;
290fc38d 566 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 567 } else {
568 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 569 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 570 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 571 desc = desc->more;
53a27b39
MT		 572 count += RMAP_EXT;
573 }
d555c333 574 if (desc->sptes[RMAP_EXT-1]) {
714b93da 575 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 576 desc = desc->more;
577 }
d555c333 578 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 579 ;
d555c333 580 desc->sptes[i] = spte;
cd4a4e53 581 }
53a27b39 582 return count;
cd4a4e53
AK		 583}
584
290fc38d 585static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 586 struct kvm_rmap_desc *desc,
587 int i,
588 struct kvm_rmap_desc *prev_desc)
589{
590 int j;
591
d555c333 592 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 593 ;
d555c333
AK		 594 desc->sptes[i] = desc->sptes[j];
595 desc->sptes[j] = NULL;
cd4a4e53
AK		 596 if (j != 0)
597 return;
598 if (!prev_desc && !desc->more)
d555c333 599 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 600 else
601 if (prev_desc)
602 prev_desc->more = desc->more;
603 else
290fc38d 604 *rmapp = (unsigned long)desc->more | 1;
90cb0529 605 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 606}
607
290fc38d 608static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 609{
cd4a4e53
AK		 610 struct kvm_rmap_desc *desc;
611 struct kvm_rmap_desc *prev_desc;
4db35314 612 struct kvm_mmu_page *sp;
35149e21 613 pfn_t pfn;
290fc38d 614 unsigned long *rmapp;
cd4a4e53
AK		 615 int i;
616
43a3795a 617 if (!is_rmap_spte(*spte))
cd4a4e53 618 return;
4db35314 619 sp = page_header(__pa(spte));
35149e21 620 pfn = spte_to_pfn(*spte);
7b52345e 621 if (*spte & shadow_accessed_mask)
35149e21 622 kvm_set_pfn_accessed(pfn);
b4231d61 623 if (is_writeble_pte(*spte))
35149e21 624 kvm_release_pfn_dirty(pfn);
b4231d61 625 else
35149e21 626 kvm_release_pfn_clean(pfn);
44ad9944 627 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 628 if (!*rmapp) {
cd4a4e53
AK		 629 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
630 BUG();
290fc38d 631 } else if (!(*rmapp & 1)) {
cd4a4e53 632 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 633 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 634 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
635 spte, *spte);
636 BUG();
637 }
290fc38d 638 *rmapp = 0;
cd4a4e53
AK		 639 } else {
640 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 641 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 642 prev_desc = NULL;
643 while (desc) {
d555c333
AK		 644 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
645 if (desc->sptes[i] == spte) {
290fc38d 646 rmap_desc_remove_entry(rmapp,
714b93da 647 desc, i,
cd4a4e53
AK		 648 prev_desc);
649 return;
650 }
651 prev_desc = desc;
652 desc = desc->more;
653 }
654 BUG();
655 }
656}
657
98348e95 658static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 659{
374cbac0 660 struct kvm_rmap_desc *desc;
98348e95
IE		 661 struct kvm_rmap_desc *prev_desc;
662 u64 *prev_spte;
663 int i;
664
665 if (!*rmapp)
666 return NULL;
667 else if (!(*rmapp & 1)) {
668 if (!spte)
669 return (u64 *)*rmapp;
670 return NULL;
671 }
672 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
673 prev_desc = NULL;
674 prev_spte = NULL;
675 while (desc) {
d555c333 676 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 677 if (prev_spte == spte)
d555c333
AK		 678 return desc->sptes[i];
679 prev_spte = desc->sptes[i];
98348e95
IE		 680 }
681 desc = desc->more;
682 }
683 return NULL;
684}
685
b1a36821 686static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 687{
290fc38d 688 unsigned long *rmapp;
374cbac0 689 u64 *spte;
44ad9944 690 int i, write_protected = 0;
374cbac0 691
4a4c9924 692 gfn = unalias_gfn(kvm, gfn);
44ad9944 693 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 694
98348e95
IE		 695 spte = rmap_next(kvm, rmapp, NULL);
696 while (spte) {
374cbac0 697 BUG_ON(!spte);
374cbac0 698 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 699 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 700 if (is_writeble_pte(*spte)) {
d555c333 701 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 702 write_protected = 1;
703 }
9647c14c 704 spte = rmap_next(kvm, rmapp, spte);
374cbac0 705 }
855149aa 706 if (write_protected) {
35149e21 707 pfn_t pfn;
855149aa
IE		 708
709 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 710 pfn = spte_to_pfn(*spte);
711 kvm_set_pfn_dirty(pfn);
855149aa
IE		 712 }
713
05da4558 714 /* check for huge page mappings */
44ad9944
JR		 715 for (i = PT_DIRECTORY_LEVEL;
716 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
717 rmapp = gfn_to_rmap(kvm, gfn, i);
718 spte = rmap_next(kvm, rmapp, NULL);
719 while (spte) {
720 BUG_ON(!spte);
721 BUG_ON(!(*spte & PT_PRESENT_MASK));
722 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
723 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
724 if (is_writeble_pte(*spte)) {
725 rmap_remove(kvm, spte);
726 --kvm->stat.lpages;
727 __set_spte(spte, shadow_trap_nonpresent_pte);
728 spte = NULL;
729 write_protected = 1;
730 }
731 spte = rmap_next(kvm, rmapp, spte);
05da4558 732 }
05da4558
MT		 733 }
734
b1a36821 735 return write_protected;
374cbac0
AK		 736}
737
e930bffe
AA		 738static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
739{
740 u64 *spte;
741 int need_tlb_flush = 0;
742
743 while ((spte = rmap_next(kvm, rmapp, NULL))) {
744 BUG_ON(!(*spte & PT_PRESENT_MASK));
745 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
746 rmap_remove(kvm, spte);
d555c333 747 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 748 need_tlb_flush = 1;
749 }
750 return need_tlb_flush;
751}
752
753static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
754 int (*handler)(struct kvm *kvm, unsigned long *rmapp))
755{
852e3c19 756 int i, j;
e930bffe
AA		 757 int retval = 0;
758
759 /*
760 * If mmap_sem isn't taken, we can look the memslots with only
761 * the mmu_lock by skipping over the slots with userspace_addr == 0.
762 */
763 for (i = 0; i < kvm->nmemslots; i++) {
764 struct kvm_memory_slot *memslot = &kvm->memslots[i];
765 unsigned long start = memslot->userspace_addr;
766 unsigned long end;
767
768 /* mmu_lock protects userspace_addr */
769 if (!start)
770 continue;
771
772 end = start + (memslot->npages << PAGE_SHIFT);
773 if (hva >= start && hva < end) {
774 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 775
e930bffe 776 retval |= handler(kvm, &memslot->rmap[gfn_offset]);
852e3c19
JR		 777
778 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
779 int idx = gfn_offset;
780 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
781 retval |= handler(kvm,
782 &memslot->lpage_info[j][idx].rmap_pde);
783 }
e930bffe
AA		 784 }
785 }
786
787 return retval;
788}
789
790int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
791{
792 return kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
793}
794
795static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
796{
797 u64 *spte;
798 int young = 0;
799
534e38b4
SY		 800 /* always return old for EPT */
801 if (!shadow_accessed_mask)
802 return 0;
803
e930bffe
AA		 804 spte = rmap_next(kvm, rmapp, NULL);
805 while (spte) {
806 int _young;
807 u64 _spte = *spte;
808 BUG_ON(!(_spte & PT_PRESENT_MASK));
809 _young = _spte & PT_ACCESSED_MASK;
810 if (_young) {
811 young = 1;
812 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
813 }
814 spte = rmap_next(kvm, rmapp, spte);
815 }
816 return young;
817}
818
53a27b39
MT		 819#define RMAP_RECYCLE_THRESHOLD 1000
820
852e3c19 821static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 822{
823 unsigned long *rmapp;
852e3c19
JR		 824 struct kvm_mmu_page *sp;
825
826 sp = page_header(__pa(spte));
53a27b39
MT		 827
828 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 829 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39
MT		 830
831 kvm_unmap_rmapp(vcpu->kvm, rmapp);
832 kvm_flush_remote_tlbs(vcpu->kvm);
833}
834
e930bffe
AA		 835int kvm_age_hva(struct kvm *kvm, unsigned long hva)
836{
837 return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
838}
839
d6c69ee9 840#ifdef MMU_DEBUG
47ad8e68 841static int is_empty_shadow_page(u64 *spt)
6aa8b732 842{
139bdb2d
AK		 843 u64 *pos;
844 u64 *end;
845
47ad8e68 846 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 847 if (is_shadow_present_pte(*pos)) {
b8688d51 848 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 849 pos, *pos);
6aa8b732 850 return 0;
139bdb2d 851 }
6aa8b732
AK		 852 return 1;
853}
d6c69ee9 854#endif
6aa8b732 855
4db35314 856static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 857{
4db35314
AK		 858 ASSERT(is_empty_shadow_page(sp->spt));
859 list_del(&sp->link);
860 __free_page(virt_to_page(sp->spt));
861 __free_page(virt_to_page(sp->gfns));
862 kfree(sp);
f05e70ac 863 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 864}
865
cea0f0e7
AK		 866static unsigned kvm_page_table_hashfn(gfn_t gfn)
867{
1ae0a13d 868 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 869}
870
25c0de2c
AK		 871static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
872 u64 *parent_pte)
6aa8b732 873{
4db35314 874 struct kvm_mmu_page *sp;
6aa8b732 875
ad312c7c
ZX		 876 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
877 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
878 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 879 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 880 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 881 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 882 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 883 sp->multimapped = 0;
884 sp->parent_pte = parent_pte;
f05e70ac 885 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 886 return sp;
6aa8b732
AK		 887}
888
714b93da 889static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 890 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 891{
892 struct kvm_pte_chain *pte_chain;
893 struct hlist_node *node;
894 int i;
895
896 if (!parent_pte)
897 return;
4db35314
AK		 898 if (!sp->multimapped) {
899 u64 *old = sp->parent_pte;
cea0f0e7
AK		 900
901 if (!old) {
4db35314 902 sp->parent_pte = parent_pte;
cea0f0e7
AK		 903 return;
904 }
4db35314 905 sp->multimapped = 1;
714b93da 906 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 907 INIT_HLIST_HEAD(&sp->parent_ptes);
908 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 909 pte_chain->parent_ptes[0] = old;
910 }
4db35314 911 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 912 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
913 continue;
914 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
915 if (!pte_chain->parent_ptes[i]) {
916 pte_chain->parent_ptes[i] = parent_pte;
917 return;
918 }
919 }
714b93da 920 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 921 BUG_ON(!pte_chain);
4db35314 922 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 923 pte_chain->parent_ptes[0] = parent_pte;
924}
925
4db35314 926static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 927 u64 *parent_pte)
928{
929 struct kvm_pte_chain *pte_chain;
930 struct hlist_node *node;
931 int i;
932
4db35314
AK		 933 if (!sp->multimapped) {
934 BUG_ON(sp->parent_pte != parent_pte);
935 sp->parent_pte = NULL;
cea0f0e7
AK		 936 return;
937 }
4db35314 938 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 939 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
940 if (!pte_chain->parent_ptes[i])
941 break;
942 if (pte_chain->parent_ptes[i] != parent_pte)
943 continue;
697fe2e2
AK		 944 while (i + 1 < NR_PTE_CHAIN_ENTRIES
945 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 946 pte_chain->parent_ptes[i]
947 = pte_chain->parent_ptes[i + 1];
948 ++i;
949 }
950 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 951 if (i == 0) {
952 hlist_del(&pte_chain->link);
90cb0529 953 mmu_free_pte_chain(pte_chain);
4db35314
AK		 954 if (hlist_empty(&sp->parent_ptes)) {
955 sp->multimapped = 0;
956 sp->parent_pte = NULL;
697fe2e2
AK		 957 }
958 }
cea0f0e7
AK		 959 return;
960 }
961 BUG();
962}
963
ad8cfbe3
MT		 964
965static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
966 mmu_parent_walk_fn fn)
967{
968 struct kvm_pte_chain *pte_chain;
969 struct hlist_node *node;
970 struct kvm_mmu_page *parent_sp;
971 int i;
972
973 if (!sp->multimapped && sp->parent_pte) {
974 parent_sp = page_header(__pa(sp->parent_pte));
975 fn(vcpu, parent_sp);
976 mmu_parent_walk(vcpu, parent_sp, fn);
977 return;
978 }
979 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
980 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
981 if (!pte_chain->parent_ptes[i])
982 break;
983 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
984 fn(vcpu, parent_sp);
985 mmu_parent_walk(vcpu, parent_sp, fn);
986 }
987}
988
0074ff63
MT		 989static void kvm_mmu_update_unsync_bitmap(u64 *spte)
990{
991 unsigned int index;
992 struct kvm_mmu_page *sp = page_header(__pa(spte));
993
994 index = spte - sp->spt;
60c8aec6
MT		 995 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
996 sp->unsync_children++;
997 WARN_ON(!sp->unsync_children);
0074ff63
MT		 998}
999
1000static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1001{
1002 struct kvm_pte_chain *pte_chain;
1003 struct hlist_node *node;
1004 int i;
1005
1006 if (!sp->parent_pte)
1007 return;
1008
1009 if (!sp->multimapped) {
1010 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1011 return;
1012 }
1013
1014 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1015 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1016 if (!pte_chain->parent_ptes[i])
1017 break;
1018 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1019 }
1020}
1021
1022static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1023{
0074ff63
MT		 1024 kvm_mmu_update_parents_unsync(sp);
1025 return 1;
1026}
1027
1028static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1029 struct kvm_mmu_page *sp)
1030{
1031 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1032 kvm_mmu_update_parents_unsync(sp);
1033}
1034
d761a501
AK		 1035static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1036 struct kvm_mmu_page *sp)
1037{
1038 int i;
1039
1040 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1041 sp->spt[i] = shadow_trap_nonpresent_pte;
1042}
1043
e8bc217a
MT		 1044static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1045 struct kvm_mmu_page *sp)
1046{
1047 return 1;
1048}
1049
a7052897
MT		 1050static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1051{
1052}
1053
60c8aec6
MT		 1054#define KVM_PAGE_ARRAY_NR 16
1055
1056struct kvm_mmu_pages {
1057 struct mmu_page_and_offset {
1058 struct kvm_mmu_page *sp;
1059 unsigned int idx;
1060 } page[KVM_PAGE_ARRAY_NR];
1061 unsigned int nr;
1062};
1063
0074ff63
MT		 1064#define for_each_unsync_children(bitmap, idx) \
1065 for (idx = find_first_bit(bitmap, 512); \
1066 idx < 512; \
1067 idx = find_next_bit(bitmap, 512, idx+1))
1068
cded19f3
HE		 1069static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1070 int idx)
4731d4c7 1071{
60c8aec6 1072 int i;
4731d4c7 1073
60c8aec6
MT		 1074 if (sp->unsync)
1075 for (i=0; i < pvec->nr; i++)
1076 if (pvec->page[i].sp == sp)
1077 return 0;
1078
1079 pvec->page[pvec->nr].sp = sp;
1080 pvec->page[pvec->nr].idx = idx;
1081 pvec->nr++;
1082 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1083}
1084
1085static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1086 struct kvm_mmu_pages *pvec)
1087{
1088 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1089
0074ff63 1090 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1091 u64 ent = sp->spt[i];
1092
87917239 1093 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1094 struct kvm_mmu_page *child;
1095 child = page_header(ent & PT64_BASE_ADDR_MASK);
1096
1097 if (child->unsync_children) {
60c8aec6
MT		 1098 if (mmu_pages_add(pvec, child, i))
1099 return -ENOSPC;
1100
1101 ret = __mmu_unsync_walk(child, pvec);
1102 if (!ret)
1103 __clear_bit(i, sp->unsync_child_bitmap);
1104 else if (ret > 0)
1105 nr_unsync_leaf += ret;
1106 else
4731d4c7
MT		 1107 return ret;
1108 }
1109
1110 if (child->unsync) {
60c8aec6
MT		 1111 nr_unsync_leaf++;
1112 if (mmu_pages_add(pvec, child, i))
1113 return -ENOSPC;
4731d4c7
MT		 1114 }
1115 }
1116 }
1117
0074ff63 1118 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1119 sp->unsync_children = 0;
1120
60c8aec6
MT		 1121 return nr_unsync_leaf;
1122}
1123
1124static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1125 struct kvm_mmu_pages *pvec)
1126{
1127 if (!sp->unsync_children)
1128 return 0;
1129
1130 mmu_pages_add(pvec, sp, 0);
1131 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1132}
1133
4db35314 1134static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1135{
1136 unsigned index;
1137 struct hlist_head *bucket;
4db35314 1138 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1139 struct hlist_node *node;
1140
b8688d51 1141 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1142 index = kvm_page_table_hashfn(gfn);
f05e70ac 1143 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1144 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1145 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1146 && !sp->role.invalid) {
cea0f0e7 1147 pgprintk("%s: found role %x\n",
b8688d51 1148 __func__, sp->role.word);
4db35314 1149 return sp;
cea0f0e7
AK		 1150 }
1151 return NULL;
1152}
1153
4731d4c7
MT		 1154static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1155{
1156 WARN_ON(!sp->unsync);
1157 sp->unsync = 0;
1158 --kvm->stat.mmu_unsync;
1159}
1160
1161static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1162
1163static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1164{
1165 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1166 kvm_mmu_zap_page(vcpu->kvm, sp);
1167 return 1;
1168 }
1169
f691fe1d 1170 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1171 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1172 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1173 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1174 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1175 kvm_mmu_zap_page(vcpu->kvm, sp);
1176 return 1;
1177 }
1178
1179 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1180 return 0;
1181}
1182
60c8aec6
MT		 1183struct mmu_page_path {
1184 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1185 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1186};
1187
60c8aec6
MT		 1188#define for_each_sp(pvec, sp, parents, i) \
1189 for (i = mmu_pages_next(&pvec, &parents, -1), \
1190 sp = pvec.page[i].sp; \
1191 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1192 i = mmu_pages_next(&pvec, &parents, i))
1193
cded19f3
HE		 1194static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1195 struct mmu_page_path *parents,
1196 int i)
60c8aec6
MT		 1197{
1198 int n;
1199
1200 for (n = i+1; n < pvec->nr; n++) {
1201 struct kvm_mmu_page *sp = pvec->page[n].sp;
1202
1203 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1204 parents->idx[0] = pvec->page[n].idx;
1205 return n;
1206 }
1207
1208 parents->parent[sp->role.level-2] = sp;
1209 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1210 }
1211
1212 return n;
1213}
1214
cded19f3 1215static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1216{
60c8aec6
MT		 1217 struct kvm_mmu_page *sp;
1218 unsigned int level = 0;
1219
1220 do {
1221 unsigned int idx = parents->idx[level];
4731d4c7 1222
60c8aec6
MT		 1223 sp = parents->parent[level];
1224 if (!sp)
1225 return;
1226
1227 --sp->unsync_children;
1228 WARN_ON((int)sp->unsync_children < 0);
1229 __clear_bit(idx, sp->unsync_child_bitmap);
1230 level++;
1231 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1232}
1233
60c8aec6
MT		 1234static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1235 struct mmu_page_path *parents,
1236 struct kvm_mmu_pages *pvec)
4731d4c7 1237{
60c8aec6
MT		 1238 parents->parent[parent->role.level-1] = NULL;
1239 pvec->nr = 0;
1240}
4731d4c7 1241
60c8aec6
MT		 1242static void mmu_sync_children(struct kvm_vcpu *vcpu,
1243 struct kvm_mmu_page *parent)
1244{
1245 int i;
1246 struct kvm_mmu_page *sp;
1247 struct mmu_page_path parents;
1248 struct kvm_mmu_pages pages;
1249
1250 kvm_mmu_pages_init(parent, &parents, &pages);
1251 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1252 int protected = 0;
1253
1254 for_each_sp(pages, sp, parents, i)
1255 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1256
1257 if (protected)
1258 kvm_flush_remote_tlbs(vcpu->kvm);
1259
60c8aec6
MT		 1260 for_each_sp(pages, sp, parents, i) {
1261 kvm_sync_page(vcpu, sp);
1262 mmu_pages_clear_parents(&parents);
1263 }
4731d4c7 1264 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1265 kvm_mmu_pages_init(parent, &parents, &pages);
1266 }
4731d4c7
MT		 1267}
1268
cea0f0e7
AK		 1269static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1270 gfn_t gfn,
1271 gva_t gaddr,
1272 unsigned level,
f6e2c02b 1273 int direct,
41074d07 1274 unsigned access,
f7d9c7b7 1275 u64 *parent_pte)
cea0f0e7
AK		 1276{
1277 union kvm_mmu_page_role role;
1278 unsigned index;
1279 unsigned quadrant;
1280 struct hlist_head *bucket;
4db35314 1281 struct kvm_mmu_page *sp;
4731d4c7 1282 struct hlist_node *node, *tmp;
cea0f0e7 1283
a770f6f2 1284 role = vcpu->arch.mmu.base_role;
cea0f0e7 1285 role.level = level;
f6e2c02b 1286 role.direct = direct;
41074d07 1287 role.access = access;
ad312c7c 1288 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1289 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1290 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1291 role.quadrant = quadrant;
1292 }
1ae0a13d 1293 index = kvm_page_table_hashfn(gfn);
f05e70ac 1294 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1295 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1296 if (sp->gfn == gfn) {
1297 if (sp->unsync)
1298 if (kvm_sync_page(vcpu, sp))
1299 continue;
1300
1301 if (sp->role.word != role.word)
1302 continue;
1303
4db35314 1304 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1305 if (sp->unsync_children) {
1306 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1307 kvm_mmu_mark_parents_unsync(vcpu, sp);
1308 }
f691fe1d 1309 trace_kvm_mmu_get_page(sp, false);
4db35314 1310 return sp;
cea0f0e7 1311 }
dfc5aa00 1312 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1313 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1314 if (!sp)
1315 return sp;
4db35314
AK		 1316 sp->gfn = gfn;
1317 sp->role = role;
1318 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1319 if (!direct) {
b1a36821
MT		 1320 if (rmap_write_protect(vcpu->kvm, gfn))
1321 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1322 account_shadowed(vcpu->kvm, gfn);
1323 }
131d8279
AK		 1324 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1325 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1326 else
1327 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1328 trace_kvm_mmu_get_page(sp, true);
4db35314 1329 return sp;
cea0f0e7
AK		 1330}
1331
2d11123a
AK		 1332static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1333 struct kvm_vcpu *vcpu, u64 addr)
1334{
1335 iterator->addr = addr;
1336 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1337 iterator->level = vcpu->arch.mmu.shadow_root_level;
1338 if (iterator->level == PT32E_ROOT_LEVEL) {
1339 iterator->shadow_addr
1340 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1341 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1342 --iterator->level;
1343 if (!iterator->shadow_addr)
1344 iterator->level = 0;
1345 }
1346}
1347
1348static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1349{
1350 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1351 return false;
4d88954d
MT		 1352
1353 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1354 if (is_large_pte(*iterator->sptep))
1355 return false;
1356
2d11123a
AK		 1357 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1358 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1359 return true;
1360}
1361
1362static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1363{
1364 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1365 --iterator->level;
1366}
1367
90cb0529 1368static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1369 struct kvm_mmu_page *sp)
a436036b 1370{
697fe2e2
AK		 1371 unsigned i;
1372 u64 *pt;
1373 u64 ent;
1374
4db35314 1375 pt = sp->spt;
697fe2e2 1376
697fe2e2
AK		 1377 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1378 ent = pt[i];
1379
05da4558 1380 if (is_shadow_present_pte(ent)) {
776e6633 1381 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1382 ent &= PT64_BASE_ADDR_MASK;
1383 mmu_page_remove_parent_pte(page_header(ent),
1384 &pt[i]);
1385 } else {
776e6633
MT		 1386 if (is_large_pte(ent))
1387 --kvm->stat.lpages;
05da4558
MT		 1388 rmap_remove(kvm, &pt[i]);
1389 }
1390 }
c7addb90 1391 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1392 }
a436036b
AK		 1393}
1394
4db35314 1395static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1396{
4db35314 1397 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1398}
1399
12b7d28f
AK		 1400static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1401{
1402 int i;
988a2cae 1403 struct kvm_vcpu *vcpu;
12b7d28f 1404
988a2cae
GN		 1405 kvm_for_each_vcpu(i, vcpu, kvm)
1406 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1407}
1408
31aa2b44 1409static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1410{
1411 u64 *parent_pte;
1412
4db35314
AK		 1413 while (sp->multimapped || sp->parent_pte) {
1414 if (!sp->multimapped)
1415 parent_pte = sp->parent_pte;
a436036b
AK		 1416 else {
1417 struct kvm_pte_chain *chain;
1418
4db35314 1419 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1420 struct kvm_pte_chain, link);
1421 parent_pte = chain->parent_ptes[0];
1422 }
697fe2e2 1423 BUG_ON(!parent_pte);
4db35314 1424 kvm_mmu_put_page(sp, parent_pte);
d555c333 1425 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1426 }
31aa2b44
AK		 1427}
1428
60c8aec6
MT		 1429static int mmu_zap_unsync_children(struct kvm *kvm,
1430 struct kvm_mmu_page *parent)
4731d4c7 1431{
60c8aec6
MT		 1432 int i, zapped = 0;
1433 struct mmu_page_path parents;
1434 struct kvm_mmu_pages pages;
4731d4c7 1435
60c8aec6 1436 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1437 return 0;
60c8aec6
MT		 1438
1439 kvm_mmu_pages_init(parent, &parents, &pages);
1440 while (mmu_unsync_walk(parent, &pages)) {
1441 struct kvm_mmu_page *sp;
1442
1443 for_each_sp(pages, sp, parents, i) {
1444 kvm_mmu_zap_page(kvm, sp);
1445 mmu_pages_clear_parents(&parents);
1446 }
1447 zapped += pages.nr;
1448 kvm_mmu_pages_init(parent, &parents, &pages);
1449 }
1450
1451 return zapped;
4731d4c7
MT		 1452}
1453
07385413 1454static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1455{
4731d4c7 1456 int ret;
f691fe1d
AK		 1457
1458 trace_kvm_mmu_zap_page(sp);
31aa2b44 1459 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1460 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1461 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1462 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1463 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1464 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1465 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1466 if (sp->unsync)
1467 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1468 if (!sp->root_count) {
1469 hlist_del(&sp->hash_link);
1470 kvm_mmu_free_page(kvm, sp);
2e53d63a 1471 } else {
2e53d63a 1472 sp->role.invalid = 1;
5b5c6a5a 1473 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1474 kvm_reload_remote_mmus(kvm);
1475 }
12b7d28f 1476 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1477 return ret;
a436036b
AK		 1478}
1479
82ce2c96
IE		 1480/*
1481 * Changing the number of mmu pages allocated to the vm
1482 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1483 */
1484void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1485{
025dbbf3
MT		 1486 int used_pages;
1487
1488 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1489 used_pages = max(0, used_pages);
1490
82ce2c96
IE		 1491 /*
1492 * If we set the number of mmu pages to be smaller be than the
1493 * number of actived pages , we must to free some mmu pages before we
1494 * change the value
1495 */
1496
025dbbf3
MT		 1497 if (used_pages > kvm_nr_mmu_pages) {
1498 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1499 struct kvm_mmu_page *page;
1500
f05e70ac 1501 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1502 struct kvm_mmu_page, link);
1503 kvm_mmu_zap_page(kvm, page);
025dbbf3 1504 used_pages--;
82ce2c96 1505 }
f05e70ac 1506 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1507 }
1508 else
f05e70ac
ZX		 1509 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1510 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1511
f05e70ac 1512 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1513}
1514
f67a46f4 1515static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1516{
1517 unsigned index;
1518 struct hlist_head *bucket;
4db35314 1519 struct kvm_mmu_page *sp;
a436036b
AK		 1520 struct hlist_node *node, *n;
1521 int r;
1522
b8688d51 1523 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1524 r = 0;
1ae0a13d 1525 index = kvm_page_table_hashfn(gfn);
f05e70ac 1526 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1527 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1528 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1529 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1530 sp->role.word);
a436036b 1531 r = 1;
07385413
MT		 1532 if (kvm_mmu_zap_page(kvm, sp))
1533 n = bucket->first;
a436036b
AK		 1534 }
1535 return r;
cea0f0e7
AK		 1536}
1537
f67a46f4 1538static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1539{
4677a3b6
AK		 1540 unsigned index;
1541 struct hlist_head *bucket;
4db35314 1542 struct kvm_mmu_page *sp;
4677a3b6 1543 struct hlist_node *node, *nn;
97a0a01e 1544
4677a3b6
AK		 1545 index = kvm_page_table_hashfn(gfn);
1546 bucket = &kvm->arch.mmu_page_hash[index];
1547 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1548 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1549 && !sp->role.invalid) {
1550 pgprintk("%s: zap %lx %x\n",
1551 __func__, gfn, sp->role.word);
1552 kvm_mmu_zap_page(kvm, sp);
1553 }
97a0a01e
AK		 1554 }
1555}
1556
38c335f1 1557static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1558{
38c335f1 1559 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 1560 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1561
291f26bc 1562 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1563}
1564
6844dec6
MT		 1565static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1566{
1567 int i;
1568 u64 *pt = sp->spt;
1569
1570 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1571 return;
1572
1573 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1574 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1575 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1576 }
1577}
1578
039576c0
AK		 1579struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1580{
72dc67a6
IE		 1581 struct page *page;
1582
ad312c7c 1583 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1584
1585 if (gpa == UNMAPPED_GVA)
1586 return NULL;
72dc67a6 1587
72dc67a6 1588 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1589
1590 return page;
039576c0
AK		 1591}
1592
74be52e3
SY		 1593/*
1594 * The function is based on mtrr_type_lookup() in
1595 * arch/x86/kernel/cpu/mtrr/generic.c
1596 */
1597static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1598 u64 start, u64 end)
1599{
1600 int i;
1601 u64 base, mask;
1602 u8 prev_match, curr_match;
1603 int num_var_ranges = KVM_NR_VAR_MTRR;
1604
1605 if (!mtrr_state->enabled)
1606 return 0xFF;
1607
1608 /* Make end inclusive end, instead of exclusive */
1609 end--;
1610
1611 /* Look in fixed ranges. Just return the type as per start */
1612 if (mtrr_state->have_fixed && (start < 0x100000)) {
1613 int idx;
1614
1615 if (start < 0x80000) {
1616 idx = 0;
1617 idx += (start >> 16);
1618 return mtrr_state->fixed_ranges[idx];
1619 } else if (start < 0xC0000) {
1620 idx = 1 * 8;
1621 idx += ((start - 0x80000) >> 14);
1622 return mtrr_state->fixed_ranges[idx];
1623 } else if (start < 0x1000000) {
1624 idx = 3 * 8;
1625 idx += ((start - 0xC0000) >> 12);
1626 return mtrr_state->fixed_ranges[idx];
1627 }
1628 }
1629
1630 /*
1631 * Look in variable ranges
1632 * Look of multiple ranges matching this address and pick type
1633 * as per MTRR precedence
1634 */
1635 if (!(mtrr_state->enabled & 2))
1636 return mtrr_state->def_type;
1637
1638 prev_match = 0xFF;
1639 for (i = 0; i < num_var_ranges; ++i) {
1640 unsigned short start_state, end_state;
1641
1642 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1643 continue;
1644
1645 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1646 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1647 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1648 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1649
1650 start_state = ((start & mask) == (base & mask));
1651 end_state = ((end & mask) == (base & mask));
1652 if (start_state != end_state)
1653 return 0xFE;
1654
1655 if ((start & mask) != (base & mask))
1656 continue;
1657
1658 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1659 if (prev_match == 0xFF) {
1660 prev_match = curr_match;
1661 continue;
1662 }
1663
1664 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1665 curr_match == MTRR_TYPE_UNCACHABLE)
1666 return MTRR_TYPE_UNCACHABLE;
1667
1668 if ((prev_match == MTRR_TYPE_WRBACK &&
1669 curr_match == MTRR_TYPE_WRTHROUGH) ||
1670 (prev_match == MTRR_TYPE_WRTHROUGH &&
1671 curr_match == MTRR_TYPE_WRBACK)) {
1672 prev_match = MTRR_TYPE_WRTHROUGH;
1673 curr_match = MTRR_TYPE_WRTHROUGH;
1674 }
1675
1676 if (prev_match != curr_match)
1677 return MTRR_TYPE_UNCACHABLE;
1678 }
1679
1680 if (prev_match != 0xFF)
1681 return prev_match;
1682
1683 return mtrr_state->def_type;
1684}
1685
4b12f0de 1686u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1687{
1688 u8 mtrr;
1689
1690 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1691 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1692 if (mtrr == 0xfe || mtrr == 0xff)
1693 mtrr = MTRR_TYPE_WRBACK;
1694 return mtrr;
1695}
4b12f0de 1696EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1697
4731d4c7
MT		 1698static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1699{
1700 unsigned index;
1701 struct hlist_head *bucket;
1702 struct kvm_mmu_page *s;
1703 struct hlist_node *node, *n;
1704
f691fe1d 1705 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1706 index = kvm_page_table_hashfn(sp->gfn);
1707 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1708 /* don't unsync if pagetable is shadowed with multiple roles */
1709 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1710 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1711 continue;
1712 if (s->role.word != sp->role.word)
1713 return 1;
1714 }
4731d4c7
MT		 1715 ++vcpu->kvm->stat.mmu_unsync;
1716 sp->unsync = 1;
6cffe8ca 1717
c2d0ee46 1718 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1719
4731d4c7
MT		 1720 mmu_convert_notrap(sp);
1721 return 0;
1722}
1723
1724static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1725 bool can_unsync)
1726{
1727 struct kvm_mmu_page *shadow;
1728
1729 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1730 if (shadow) {
1731 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1732 return 1;
1733 if (shadow->unsync)
1734 return 0;
582801a9 1735 if (can_unsync && oos_shadow)
4731d4c7
MT		 1736 return kvm_unsync_page(vcpu, shadow);
1737 return 1;
1738 }
1739 return 0;
1740}
1741
d555c333 1742static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1743 unsigned pte_access, int user_fault,
852e3c19 1744 int write_fault, int dirty, int level,
c2d0ee46 1745 gfn_t gfn, pfn_t pfn, bool speculative,
4731d4c7 1746 bool can_unsync)
1c4f1fd6
AK		 1747{
1748 u64 spte;
1e73f9dd 1749 int ret = 0;
64d4d521 1750
1c4f1fd6
AK		 1751 /*
1752 * We don't set the accessed bit, since we sometimes want to see
1753 * whether the guest actually used the pte (in order to detect
1754 * demand paging).
1755 */
7b52345e 1756 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1757 if (!speculative)
3201b5d9 1758 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1759 if (!dirty)
1760 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1761 if (pte_access & ACC_EXEC_MASK)
1762 spte |= shadow_x_mask;
1763 else
1764 spte |= shadow_nx_mask;
1c4f1fd6 1765 if (pte_access & ACC_USER_MASK)
7b52345e 1766 spte |= shadow_user_mask;
852e3c19 1767 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1768 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1769 if (tdp_enabled)
1770 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1771 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1772
35149e21 1773 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1774
1775 if ((pte_access & ACC_WRITE_MASK)
1776 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1777
852e3c19
JR		 1778 if (level > PT_PAGE_TABLE_LEVEL &&
1779 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1780 ret = 1;
1781 spte = shadow_trap_nonpresent_pte;
1782 goto set_pte;
1783 }
1784
1c4f1fd6 1785 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1786
ecc5589f
MT		 1787 /*
1788 * Optimization: for pte sync, if spte was writable the hash
1789 * lookup is unnecessary (and expensive). Write protection
1790 * is responsibility of mmu_get_page / kvm_sync_page.
1791 * Same reasoning can be applied to dirty page accounting.
1792 */
d555c333 1793 if (!can_unsync && is_writeble_pte(*sptep))
ecc5589f
MT		 1794 goto set_pte;
1795
4731d4c7 1796 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1797 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1798 __func__, gfn);
1e73f9dd 1799 ret = 1;
1c4f1fd6 1800 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1801 if (is_writeble_pte(spte))
1c4f1fd6 1802 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1803 }
1804 }
1805
1c4f1fd6
AK		 1806 if (pte_access & ACC_WRITE_MASK)
1807 mark_page_dirty(vcpu->kvm, gfn);
1808
38187c83 1809set_pte:
d555c333 1810 __set_spte(sptep, spte);
1e73f9dd
MT		 1811 return ret;
1812}
1813
d555c333 1814static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1815 unsigned pt_access, unsigned pte_access,
1816 int user_fault, int write_fault, int dirty,
852e3c19 1817 int *ptwrite, int level, gfn_t gfn,
c2d0ee46 1818 pfn_t pfn, bool speculative)
1e73f9dd
MT		 1819{
1820 int was_rmapped = 0;
d555c333 1821 int was_writeble = is_writeble_pte(*sptep);
53a27b39 1822 int rmap_count;
1e73f9dd
MT		 1823
1824 pgprintk("%s: spte %llx access %x write_fault %d"
1825 " user_fault %d gfn %lx\n",
d555c333 1826 __func__, *sptep, pt_access,
1e73f9dd
MT		 1827 write_fault, user_fault, gfn);
1828
d555c333 1829 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1830 /*
1831 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1832 * the parent of the now unreachable PTE.
1833 */
852e3c19
JR		 1834 if (level > PT_PAGE_TABLE_LEVEL &&
1835 !is_large_pte(*sptep)) {
1e73f9dd 1836 struct kvm_mmu_page *child;
d555c333 1837 u64 pte = *sptep;
1e73f9dd
MT		 1838
1839 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1840 mmu_page_remove_parent_pte(child, sptep);
1841 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1842 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1843 spte_to_pfn(*sptep), pfn);
1844 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1845 } else
1846 was_rmapped = 1;
1e73f9dd 1847 }
852e3c19 1848
d555c333 1849 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
852e3c19 1850 dirty, level, gfn, pfn, speculative, true)) {
1e73f9dd
MT		 1851 if (write_fault)
1852 *ptwrite = 1;
a378b4e6
MT		 1853 kvm_x86_ops->tlb_flush(vcpu);
1854 }
1e73f9dd 1855
d555c333 1856 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1857 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1858 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1859 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1860 *sptep, sptep);
d555c333 1861 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1862 ++vcpu->kvm->stat.lpages;
1863
d555c333 1864 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1865 if (!was_rmapped) {
44ad9944 1866 rmap_count = rmap_add(vcpu, sptep, gfn);
d555c333 1867 if (!is_rmap_spte(*sptep))
35149e21 1868 kvm_release_pfn_clean(pfn);
53a27b39 1869 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1870 rmap_recycle(vcpu, sptep, gfn);
75e68e60
IE		 1871 } else {
1872 if (was_writeble)
35149e21 1873 kvm_release_pfn_dirty(pfn);
75e68e60 1874 else
35149e21 1875 kvm_release_pfn_clean(pfn);
1c4f1fd6 1876 }
1b7fcd32 1877 if (speculative) {
d555c333 1878 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1879 vcpu->arch.last_pte_gfn = gfn;
1880 }
1c4f1fd6
AK		 1881}
1882
6aa8b732
AK		 1883static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1884{
1885}
1886
9f652d21 1887static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1888 int level, gfn_t gfn, pfn_t pfn)
140754bc 1889{
9f652d21 1890 struct kvm_shadow_walk_iterator iterator;
140754bc 1891 struct kvm_mmu_page *sp;
9f652d21 1892 int pt_write = 0;
140754bc 1893 gfn_t pseudo_gfn;
6aa8b732 1894
9f652d21 1895 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1896 if (iterator.level == level) {
9f652d21
AK		 1897 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1898 0, write, 1, &pt_write,
852e3c19 1899 level, gfn, pfn, false);
9f652d21
AK		 1900 ++vcpu->stat.pf_fixed;
1901 break;
6aa8b732
AK		 1902 }
1903
9f652d21
AK		 1904 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1905 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1906 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1907 iterator.level - 1,
1908 1, ACC_ALL, iterator.sptep);
1909 if (!sp) {
1910 pgprintk("nonpaging_map: ENOMEM\n");
1911 kvm_release_pfn_clean(pfn);
1912 return -ENOMEM;
1913 }
140754bc 1914
d555c333
AK		 1915 __set_spte(iterator.sptep,
1916 __pa(sp->spt)
1917 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1918 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1919 }
1920 }
1921 return pt_write;
6aa8b732
AK		 1922}
1923
10589a46
MT		 1924static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1925{
1926 int r;
852e3c19 1927 int level;
35149e21 1928 pfn_t pfn;
e930bffe 1929 unsigned long mmu_seq;
aaee2c94 1930
852e3c19
JR		 1931 level = mapping_level(vcpu, gfn);
1932
1933 /*
1934 * This path builds a PAE pagetable - so we can map 2mb pages at
1935 * maximum. Therefore check if the level is larger than that.
1936 */
1937 if (level > PT_DIRECTORY_LEVEL)
1938 level = PT_DIRECTORY_LEVEL;
1939
1940 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 1941
e930bffe 1942 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 1943 smp_rmb();
35149e21 1944 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 1945
d196e343 1946 /* mmio */
35149e21
AL		 1947 if (is_error_pfn(pfn)) {
1948 kvm_release_pfn_clean(pfn);
d196e343
AK		 1949 return 1;
1950 }
1951
aaee2c94 1952 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 1953 if (mmu_notifier_retry(vcpu, mmu_seq))
1954 goto out_unlock;
eb787d10 1955 kvm_mmu_free_some_pages(vcpu);
852e3c19 1956 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 1957 spin_unlock(&vcpu->kvm->mmu_lock);
1958
aaee2c94 1959
10589a46 1960 return r;
e930bffe
AA		 1961
1962out_unlock:
1963 spin_unlock(&vcpu->kvm->mmu_lock);
1964 kvm_release_pfn_clean(pfn);
1965 return 0;
10589a46
MT		 1966}
1967
1968
17ac10ad
AK		 1969static void mmu_free_roots(struct kvm_vcpu *vcpu)
1970{
1971 int i;
4db35314 1972 struct kvm_mmu_page *sp;
17ac10ad 1973
ad312c7c 1974 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 1975 return;
aaee2c94 1976 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 1977 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1978 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 1979
4db35314
AK		 1980 sp = page_header(root);
1981 --sp->root_count;
2e53d63a
MT		 1982 if (!sp->root_count && sp->role.invalid)
1983 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 1984 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 1985 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 1986 return;
1987 }
17ac10ad 1988 for (i = 0; i < 4; ++i) {
ad312c7c 1989 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 1990
417726a3 1991 if (root) {
417726a3 1992 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 1993 sp = page_header(root);
1994 --sp->root_count;
2e53d63a
MT		 1995 if (!sp->root_count && sp->role.invalid)
1996 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 1997 }
ad312c7c 1998 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 1999 }
aaee2c94 2000 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2001 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2002}
2003
8986ecc0
MT		 2004static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2005{
2006 int ret = 0;
2007
2008 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2009 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2010 ret = 1;
2011 }
2012
2013 return ret;
2014}
2015
2016static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2017{
2018 int i;
cea0f0e7 2019 gfn_t root_gfn;
4db35314 2020 struct kvm_mmu_page *sp;
f6e2c02b 2021 int direct = 0;
6de4f3ad 2022 u64 pdptr;
3bb65a22 2023
ad312c7c 2024 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2025
ad312c7c
ZX		 2026 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2027 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2028
2029 ASSERT(!VALID_PAGE(root));
fb72d167 2030 if (tdp_enabled)
f6e2c02b 2031 direct = 1;
8986ecc0
MT		 2032 if (mmu_check_root(vcpu, root_gfn))
2033 return 1;
4db35314 2034 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2035 PT64_ROOT_LEVEL, direct,
fb72d167 2036 ACC_ALL, NULL);
4db35314
AK		 2037 root = __pa(sp->spt);
2038 ++sp->root_count;
ad312c7c 2039 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2040 return 0;
17ac10ad 2041 }
f6e2c02b 2042 direct = !is_paging(vcpu);
fb72d167 2043 if (tdp_enabled)
f6e2c02b 2044 direct = 1;
17ac10ad 2045 for (i = 0; i < 4; ++i) {
ad312c7c 2046 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2047
2048 ASSERT(!VALID_PAGE(root));
ad312c7c 2049 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2050 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2051 if (!is_present_gpte(pdptr)) {
ad312c7c 2052 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2053 continue;
2054 }
6de4f3ad 2055 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2056 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2057 root_gfn = 0;
8986ecc0
MT		 2058 if (mmu_check_root(vcpu, root_gfn))
2059 return 1;
4db35314 2060 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2061 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2062 ACC_ALL, NULL);
4db35314
AK		 2063 root = __pa(sp->spt);
2064 ++sp->root_count;
ad312c7c 2065 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2066 }
ad312c7c 2067 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2068 return 0;
17ac10ad
AK		 2069}
2070
0ba73cda
MT		 2071static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2072{
2073 int i;
2074 struct kvm_mmu_page *sp;
2075
2076 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2077 return;
2078 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2079 hpa_t root = vcpu->arch.mmu.root_hpa;
2080 sp = page_header(root);
2081 mmu_sync_children(vcpu, sp);
2082 return;
2083 }
2084 for (i = 0; i < 4; ++i) {
2085 hpa_t root = vcpu->arch.mmu.pae_root[i];
2086
8986ecc0 2087 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2088 root &= PT64_BASE_ADDR_MASK;
2089 sp = page_header(root);
2090 mmu_sync_children(vcpu, sp);
2091 }
2092 }
2093}
2094
2095void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2096{
2097 spin_lock(&vcpu->kvm->mmu_lock);
2098 mmu_sync_roots(vcpu);
6cffe8ca 2099 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2100}
2101
6aa8b732
AK		 2102static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2103{
2104 return vaddr;
2105}
2106
2107static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2108 u32 error_code)
6aa8b732 2109{
e833240f 2110 gfn_t gfn;
e2dec939 2111 int r;
6aa8b732 2112
b8688d51 2113 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2114 r = mmu_topup_memory_caches(vcpu);
2115 if (r)
2116 return r;
714b93da 2117
6aa8b732 2118 ASSERT(vcpu);
ad312c7c 2119 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2120
e833240f 2121 gfn = gva >> PAGE_SHIFT;
6aa8b732 2122
e833240f
AK		 2123 return nonpaging_map(vcpu, gva & PAGE_MASK,
2124 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2125}
2126
fb72d167
JR		 2127static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2128 u32 error_code)
2129{
35149e21 2130 pfn_t pfn;
fb72d167 2131 int r;
852e3c19 2132 int level;
05da4558 2133 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2134 unsigned long mmu_seq;
fb72d167
JR		 2135
2136 ASSERT(vcpu);
2137 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2138
2139 r = mmu_topup_memory_caches(vcpu);
2140 if (r)
2141 return r;
2142
852e3c19
JR		 2143 level = mapping_level(vcpu, gfn);
2144
2145 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2146
e930bffe 2147 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2148 smp_rmb();
35149e21 2149 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2150 if (is_error_pfn(pfn)) {
2151 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2152 return 1;
2153 }
2154 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2155 if (mmu_notifier_retry(vcpu, mmu_seq))
2156 goto out_unlock;
fb72d167
JR		 2157 kvm_mmu_free_some_pages(vcpu);
2158 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2159 level, gfn, pfn);
fb72d167 2160 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2161
2162 return r;
e930bffe
AA		 2163
2164out_unlock:
2165 spin_unlock(&vcpu->kvm->mmu_lock);
2166 kvm_release_pfn_clean(pfn);
2167 return 0;
fb72d167
JR		 2168}
2169
6aa8b732
AK		 2170static void nonpaging_free(struct kvm_vcpu *vcpu)
2171{
17ac10ad 2172 mmu_free_roots(vcpu);
6aa8b732
AK		 2173}
2174
2175static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2176{
ad312c7c 2177 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2178
2179 context->new_cr3 = nonpaging_new_cr3;
2180 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2181 context->gva_to_gpa = nonpaging_gva_to_gpa;
2182 context->free = nonpaging_free;
c7addb90 2183 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2184 context->sync_page = nonpaging_sync_page;
a7052897 2185 context->invlpg = nonpaging_invlpg;
cea0f0e7 2186 context->root_level = 0;
6aa8b732 2187 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2188 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2189 return 0;
2190}
2191
d835dfec 2192void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2193{
1165f5fe 2194 ++vcpu->stat.tlb_flush;
cbdd1bea 2195 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2196}
2197
2198static void paging_new_cr3(struct kvm_vcpu *vcpu)
2199{
b8688d51 2200 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2201 mmu_free_roots(vcpu);
6aa8b732
AK		 2202}
2203
6aa8b732
AK		 2204static void inject_page_fault(struct kvm_vcpu *vcpu,
2205 u64 addr,
2206 u32 err_code)
2207{
c3c91fee 2208 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2209}
2210
6aa8b732
AK		 2211static void paging_free(struct kvm_vcpu *vcpu)
2212{
2213 nonpaging_free(vcpu);
2214}
2215
82725b20
DE		 2216static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2217{
2218 int bit7;
2219
2220 bit7 = (gpte >> 7) & 1;
2221 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2222}
2223
6aa8b732
AK		 2224#define PTTYPE 64
2225#include "paging_tmpl.h"
2226#undef PTTYPE
2227
2228#define PTTYPE 32
2229#include "paging_tmpl.h"
2230#undef PTTYPE
2231
82725b20
DE		 2232static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2233{
2234 struct kvm_mmu *context = &vcpu->arch.mmu;
2235 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2236 u64 exb_bit_rsvd = 0;
2237
2238 if (!is_nx(vcpu))
2239 exb_bit_rsvd = rsvd_bits(63, 63);
2240 switch (level) {
2241 case PT32_ROOT_LEVEL:
2242 /* no rsvd bits for 2 level 4K page table entries */
2243 context->rsvd_bits_mask[0][1] = 0;
2244 context->rsvd_bits_mask[0][0] = 0;
2245 if (is_cpuid_PSE36())
2246 /* 36bits PSE 4MB page */
2247 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2248 else
2249 /* 32 bits PSE 4MB page */
2250 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2251 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2252 break;
2253 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2254 context->rsvd_bits_mask[0][2] =
2255 rsvd_bits(maxphyaddr, 63) |
2256 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2257 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2258 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2259 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2260 rsvd_bits(maxphyaddr, 62); /* PTE */
2261 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2262 rsvd_bits(maxphyaddr, 62) |
2263 rsvd_bits(13, 20); /* large page */
29a4b933 2264 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2265 break;
2266 case PT64_ROOT_LEVEL:
2267 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2268 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2269 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2270 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2271 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2272 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2273 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2274 rsvd_bits(maxphyaddr, 51);
2275 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2276 context->rsvd_bits_mask[1][2] = context->rsvd_bits_mask[0][2];
2277 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2278 rsvd_bits(maxphyaddr, 51) |
2279 rsvd_bits(13, 20); /* large page */
29a4b933 2280 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2281 break;
2282 }
2283}
2284
17ac10ad 2285static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2286{
ad312c7c 2287 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2288
2289 ASSERT(is_pae(vcpu));
2290 context->new_cr3 = paging_new_cr3;
2291 context->page_fault = paging64_page_fault;
6aa8b732 2292 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2293 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2294 context->sync_page = paging64_sync_page;
a7052897 2295 context->invlpg = paging64_invlpg;
6aa8b732 2296 context->free = paging_free;
17ac10ad
AK		 2297 context->root_level = level;
2298 context->shadow_root_level = level;
17c3ba9d 2299 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2300 return 0;
2301}
2302
17ac10ad
AK		 2303static int paging64_init_context(struct kvm_vcpu *vcpu)
2304{
82725b20 2305 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2306 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2307}
2308
6aa8b732
AK		 2309static int paging32_init_context(struct kvm_vcpu *vcpu)
2310{
ad312c7c 2311 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2312
82725b20 2313 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2314 context->new_cr3 = paging_new_cr3;
2315 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2316 context->gva_to_gpa = paging32_gva_to_gpa;
2317 context->free = paging_free;
c7addb90 2318 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2319 context->sync_page = paging32_sync_page;
a7052897 2320 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2321 context->root_level = PT32_ROOT_LEVEL;
2322 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2323 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2324 return 0;
2325}
2326
2327static int paging32E_init_context(struct kvm_vcpu *vcpu)
2328{
82725b20 2329 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2330 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2331}
2332
fb72d167
JR		 2333static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2334{
2335 struct kvm_mmu *context = &vcpu->arch.mmu;
2336
2337 context->new_cr3 = nonpaging_new_cr3;
2338 context->page_fault = tdp_page_fault;
2339 context->free = nonpaging_free;
2340 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2341 context->sync_page = nonpaging_sync_page;
a7052897 2342 context->invlpg = nonpaging_invlpg;
67253af5 2343 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2344 context->root_hpa = INVALID_PAGE;
2345
2346 if (!is_paging(vcpu)) {
2347 context->gva_to_gpa = nonpaging_gva_to_gpa;
2348 context->root_level = 0;
2349 } else if (is_long_mode(vcpu)) {
82725b20 2350 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2351 context->gva_to_gpa = paging64_gva_to_gpa;
2352 context->root_level = PT64_ROOT_LEVEL;
2353 } else if (is_pae(vcpu)) {
82725b20 2354 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2355 context->gva_to_gpa = paging64_gva_to_gpa;
2356 context->root_level = PT32E_ROOT_LEVEL;
2357 } else {
82725b20 2358 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2359 context->gva_to_gpa = paging32_gva_to_gpa;
2360 context->root_level = PT32_ROOT_LEVEL;
2361 }
2362
2363 return 0;
2364}
2365
2366static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2367{
a770f6f2
AK		 2368 int r;
2369
6aa8b732 2370 ASSERT(vcpu);
ad312c7c 2371 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2372
2373 if (!is_paging(vcpu))
a770f6f2 2374 r = nonpaging_init_context(vcpu);
a9058ecd 2375 else if (is_long_mode(vcpu))
a770f6f2 2376 r = paging64_init_context(vcpu);
6aa8b732 2377 else if (is_pae(vcpu))
a770f6f2 2378 r = paging32E_init_context(vcpu);
6aa8b732 2379 else
a770f6f2
AK		 2380 r = paging32_init_context(vcpu);
2381
2382 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2383
2384 return r;
6aa8b732
AK		 2385}
2386
fb72d167
JR		 2387static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2388{
35149e21
AL		 2389 vcpu->arch.update_pte.pfn = bad_pfn;
2390
fb72d167
JR		 2391 if (tdp_enabled)
2392 return init_kvm_tdp_mmu(vcpu);
2393 else
2394 return init_kvm_softmmu(vcpu);
2395}
2396
6aa8b732
AK		 2397static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2398{
2399 ASSERT(vcpu);
ad312c7c
ZX		 2400 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2401 vcpu->arch.mmu.free(vcpu);
2402 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2403 }
2404}
2405
2406int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2407{
2408 destroy_kvm_mmu(vcpu);
2409 return init_kvm_mmu(vcpu);
2410}
8668a3c4 2411EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2412
2413int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2414{
714b93da
AK		 2415 int r;
2416
e2dec939 2417 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2418 if (r)
2419 goto out;
aaee2c94 2420 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2421 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2422 r = mmu_alloc_roots(vcpu);
0ba73cda 2423 mmu_sync_roots(vcpu);
aaee2c94 2424 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2425 if (r)
2426 goto out;
3662cb1c 2427 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2428 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2429out:
2430 return r;
6aa8b732 2431}
17c3ba9d
AK		 2432EXPORT_SYMBOL_GPL(kvm_mmu_load);
2433
2434void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2435{
2436 mmu_free_roots(vcpu);
2437}
6aa8b732 2438
09072daf 2439static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2440 struct kvm_mmu_page *sp,
ac1b714e
AK		 2441 u64 *spte)
2442{
2443 u64 pte;
2444 struct kvm_mmu_page *child;
2445
2446 pte = *spte;
c7addb90 2447 if (is_shadow_present_pte(pte)) {
776e6633 2448 if (is_last_spte(pte, sp->role.level))
290fc38d 2449 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2450 else {
2451 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2452 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2453 }
2454 }
d555c333 2455 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2456 if (is_large_pte(pte))
2457 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2458}
2459
0028425f 2460static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2461 struct kvm_mmu_page *sp,
0028425f 2462 u64 *spte,
489f1d65 2463 const void *new)
0028425f 2464{
30945387 2465 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
852e3c19 2466 if (vcpu->arch.update_pte.level == PT_PAGE_TABLE_LEVEL ||
30945387
MT		 2467 sp->role.glevels == PT32_ROOT_LEVEL) {
2468 ++vcpu->kvm->stat.mmu_pde_zapped;
2469 return;
2470 }
2471 }
0028425f 2472
4cee5764 2473 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2474 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2475 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2476 else
489f1d65 2477 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2478}
2479
79539cec
AK		 2480static bool need_remote_flush(u64 old, u64 new)
2481{
2482 if (!is_shadow_present_pte(old))
2483 return false;
2484 if (!is_shadow_present_pte(new))
2485 return true;
2486 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2487 return true;
2488 old ^= PT64_NX_MASK;
2489 new ^= PT64_NX_MASK;
2490 return (old & ~new & PT64_PERM_MASK) != 0;
2491}
2492
2493static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2494{
2495 if (need_remote_flush(old, new))
2496 kvm_flush_remote_tlbs(vcpu->kvm);
2497 else
2498 kvm_mmu_flush_tlb(vcpu);
2499}
2500
12b7d28f
AK		 2501static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2502{
ad312c7c 2503 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2504
7b52345e 2505 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2506}
2507
d7824fff
AK		 2508static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2509 const u8 *new, int bytes)
2510{
2511 gfn_t gfn;
2512 int r;
2513 u64 gpte = 0;
35149e21 2514 pfn_t pfn;
d7824fff 2515
852e3c19 2516 vcpu->arch.update_pte.level = PT_PAGE_TABLE_LEVEL;
05da4558 2517
d7824fff
AK		 2518 if (bytes != 4 && bytes != 8)
2519 return;
2520
2521 /*
2522 * Assume that the pte write on a page table of the same type
2523 * as the current vcpu paging mode. This is nearly always true
2524 * (might be false while changing modes). Note it is verified later
2525 * by update_pte().
2526 */
2527 if (is_pae(vcpu)) {
2528 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2529 if ((bytes == 4) && (gpa % 4 == 0)) {
2530 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2531 if (r)
2532 return;
2533 memcpy((void *)&gpte + (gpa % 8), new, 4);
2534 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2535 memcpy((void *)&gpte, new, 8);
2536 }
2537 } else {
2538 if ((bytes == 4) && (gpa % 4 == 0))
2539 memcpy((void *)&gpte, new, 4);
2540 }
43a3795a 2541 if (!is_present_gpte(gpte))
d7824fff
AK		 2542 return;
2543 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2544
d25797b2
JR		 2545 if (is_large_pte(gpte) &&
2546 (mapping_level(vcpu, gfn) == PT_DIRECTORY_LEVEL)) {
ec04b260 2547 gfn &= ~(KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL) - 1);
852e3c19 2548 vcpu->arch.update_pte.level = PT_DIRECTORY_LEVEL;
05da4558 2549 }
e930bffe 2550 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2551 smp_rmb();
35149e21 2552 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2553
35149e21
AL		 2554 if (is_error_pfn(pfn)) {
2555 kvm_release_pfn_clean(pfn);
d196e343
AK		 2556 return;
2557 }
d7824fff 2558 vcpu->arch.update_pte.gfn = gfn;
35149e21 2559 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2560}
2561
1b7fcd32
AK		 2562static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2563{
2564 u64 *spte = vcpu->arch.last_pte_updated;
2565
2566 if (spte
2567 && vcpu->arch.last_pte_gfn == gfn
2568 && shadow_accessed_mask
2569 && !(*spte & shadow_accessed_mask)
2570 && is_shadow_present_pte(*spte))
2571 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2572}
2573
09072daf 2574void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2575 const u8 *new, int bytes,
2576 bool guest_initiated)
da4a00f0 2577{
9b7a0325 2578 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2579 struct kvm_mmu_page *sp;
0e7bc4b9 2580 struct hlist_node *node, *n;
9b7a0325
AK		 2581 struct hlist_head *bucket;
2582 unsigned index;
489f1d65 2583 u64 entry, gentry;
9b7a0325 2584 u64 *spte;
9b7a0325 2585 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2586 unsigned pte_size;
9b7a0325 2587 unsigned page_offset;
0e7bc4b9 2588 unsigned misaligned;
fce0657f 2589 unsigned quadrant;
9b7a0325 2590 int level;
86a5ba02 2591 int flooded = 0;
ac1b714e 2592 int npte;
489f1d65 2593 int r;
9b7a0325 2594
b8688d51 2595 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2596 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2597 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2598 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2599 kvm_mmu_free_some_pages(vcpu);
4cee5764 2600 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2601 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2602 if (guest_initiated) {
2603 if (gfn == vcpu->arch.last_pt_write_gfn
2604 && !last_updated_pte_accessed(vcpu)) {
2605 ++vcpu->arch.last_pt_write_count;
2606 if (vcpu->arch.last_pt_write_count >= 3)
2607 flooded = 1;
2608 } else {
2609 vcpu->arch.last_pt_write_gfn = gfn;
2610 vcpu->arch.last_pt_write_count = 1;
2611 vcpu->arch.last_pte_updated = NULL;
2612 }
86a5ba02 2613 }
1ae0a13d 2614 index = kvm_page_table_hashfn(gfn);
f05e70ac 2615 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2616 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2617 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2618 continue;
4db35314 2619 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2620 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2621 misaligned |= bytes < 4;
86a5ba02 2622 if (misaligned || flooded) {
0e7bc4b9
AK		 2623 /*
2624 * Misaligned accesses are too much trouble to fix
2625 * up; also, they usually indicate a page is not used
2626 * as a page table.
86a5ba02
AK		 2627 *
2628 * If we're seeing too many writes to a page,
2629 * it may no longer be a page table, or we may be
2630 * forking, in which case it is better to unmap the
2631 * page.
0e7bc4b9
AK		 2632 */
2633 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2634 gpa, bytes, sp->role.word);
07385413
MT		 2635 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2636 n = bucket->first;
4cee5764 2637 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2638 continue;
2639 }
9b7a0325 2640 page_offset = offset;
4db35314 2641 level = sp->role.level;
ac1b714e 2642 npte = 1;
4db35314 2643 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2644 page_offset <<= 1; /* 32->64 */
2645 /*
2646 * A 32-bit pde maps 4MB while the shadow pdes map
2647 * only 2MB. So we need to double the offset again
2648 * and zap two pdes instead of one.
2649 */
2650 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2651 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2652 page_offset <<= 1;
2653 npte = 2;
2654 }
fce0657f 2655 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2656 page_offset &= ~PAGE_MASK;
4db35314 2657 if (quadrant != sp->role.quadrant)
fce0657f 2658 continue;
9b7a0325 2659 }
4db35314 2660 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2661 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2662 gentry = 0;
2663 r = kvm_read_guest_atomic(vcpu->kvm,
2664 gpa & ~(u64)(pte_size - 1),
2665 &gentry, pte_size);
2666 new = (const void *)&gentry;
2667 if (r < 0)
2668 new = NULL;
2669 }
ac1b714e 2670 while (npte--) {
79539cec 2671 entry = *spte;
4db35314 2672 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2673 if (new)
2674 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2675 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2676 ++spte;
9b7a0325 2677 }
9b7a0325 2678 }
c7addb90 2679 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2680 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2681 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2682 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2683 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2684 }
da4a00f0
AK		 2685}
2686
a436036b
AK		 2687int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2688{
10589a46
MT		 2689 gpa_t gpa;
2690 int r;
a436036b 2691
10589a46 2692 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2693
aaee2c94 2694 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2695 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2696 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2697 return r;
a436036b 2698}
577bdc49 2699EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2700
22d95b12 2701void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2702{
f05e70ac 2703 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
4db35314 2704 struct kvm_mmu_page *sp;
ebeace86 2705
f05e70ac 2706 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2707 struct kvm_mmu_page, link);
2708 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2709 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2710 }
2711}
ebeace86 2712
3067714c
AK		 2713int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2714{
2715 int r;
2716 enum emulation_result er;
2717
ad312c7c 2718 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2719 if (r < 0)
2720 goto out;
2721
2722 if (!r) {
2723 r = 1;
2724 goto out;
2725 }
2726
b733bfb5
AK		 2727 r = mmu_topup_memory_caches(vcpu);
2728 if (r)
2729 goto out;
2730
3067714c 2731 er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
3067714c
AK		 2732
2733 switch (er) {
2734 case EMULATE_DONE:
2735 return 1;
2736 case EMULATE_DO_MMIO:
2737 ++vcpu->stat.mmio_exits;
2738 return 0;
2739 case EMULATE_FAIL:
3f5d18a9
AK		 2740 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2741 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2742 return 0;
3067714c
AK		 2743 default:
2744 BUG();
2745 }
2746out:
3067714c
AK		 2747 return r;
2748}
2749EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2750
a7052897
MT		 2751void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2752{
a7052897 2753 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2754 kvm_mmu_flush_tlb(vcpu);
2755 ++vcpu->stat.invlpg;
2756}
2757EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2758
18552672
JR		 2759void kvm_enable_tdp(void)
2760{
2761 tdp_enabled = true;
2762}
2763EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2764
5f4cb662
JR		 2765void kvm_disable_tdp(void)
2766{
2767 tdp_enabled = false;
2768}
2769EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2770
6aa8b732
AK		 2771static void free_mmu_pages(struct kvm_vcpu *vcpu)
2772{
ad312c7c 2773 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2774}
2775
2776static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2777{
17ac10ad 2778 struct page *page;
6aa8b732
AK		 2779 int i;
2780
2781 ASSERT(vcpu);
2782
6a1ac771 2783 spin_lock(&vcpu->kvm->mmu_lock);
f05e70ac
ZX		 2784 if (vcpu->kvm->arch.n_requested_mmu_pages)
2785 vcpu->kvm->arch.n_free_mmu_pages =
2786 vcpu->kvm->arch.n_requested_mmu_pages;
82ce2c96 2787 else
f05e70ac
ZX		 2788 vcpu->kvm->arch.n_free_mmu_pages =
2789 vcpu->kvm->arch.n_alloc_mmu_pages;
6a1ac771 2790 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2791 /*
2792 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2793 * Therefore we need to allocate shadow page tables in the first
2794 * 4GB of memory, which happens to fit the DMA32 zone.
2795 */
2796 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2797 if (!page)
2798 goto error_1;
ad312c7c 2799 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2800 for (i = 0; i < 4; ++i)
ad312c7c 2801 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2802
6aa8b732
AK		 2803 return 0;
2804
2805error_1:
2806 free_mmu_pages(vcpu);
2807 return -ENOMEM;
2808}
2809
8018c27b 2810int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2811{
6aa8b732 2812 ASSERT(vcpu);
ad312c7c 2813 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2814
8018c27b
IM		 2815 return alloc_mmu_pages(vcpu);
2816}
6aa8b732 2817
8018c27b
IM		 2818int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2819{
2820 ASSERT(vcpu);
ad312c7c 2821 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2822
8018c27b 2823 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2824}
2825
2826void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2827{
2828 ASSERT(vcpu);
2829
2830 destroy_kvm_mmu(vcpu);
2831 free_mmu_pages(vcpu);
714b93da 2832 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2833}
2834
90cb0529 2835void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2836{
4db35314 2837 struct kvm_mmu_page *sp;
6aa8b732 2838
f05e70ac 2839 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2840 int i;
2841 u64 *pt;
2842
291f26bc 2843 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2844 continue;
2845
4db35314 2846 pt = sp->spt;
6aa8b732
AK		 2847 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2848 /* avoid RMW */
9647c14c 2849 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2850 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2851 }
171d595d 2852 kvm_flush_remote_tlbs(kvm);
6aa8b732 2853}
37a7d8b0 2854
90cb0529 2855void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2856{
4db35314 2857 struct kvm_mmu_page *sp, *node;
e0fa826f 2858
aaee2c94 2859 spin_lock(&kvm->mmu_lock);
f05e70ac 2860 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2861 if (kvm_mmu_zap_page(kvm, sp))
2862 node = container_of(kvm->arch.active_mmu_pages.next,
2863 struct kvm_mmu_page, link);
aaee2c94 2864 spin_unlock(&kvm->mmu_lock);
e0fa826f 2865
90cb0529 2866 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2867}
2868
8b2cf73c 2869static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2870{
2871 struct kvm_mmu_page *page;
2872
2873 page = container_of(kvm->arch.active_mmu_pages.prev,
2874 struct kvm_mmu_page, link);
2875 kvm_mmu_zap_page(kvm, page);
2876}
2877
2878static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2879{
2880 struct kvm *kvm;
2881 struct kvm *kvm_freed = NULL;
2882 int cache_count = 0;
2883
2884 spin_lock(&kvm_lock);
2885
2886 list_for_each_entry(kvm, &vm_list, vm_list) {
2887 int npages;
2888
5a4c9288
MT		 2889 if (!down_read_trylock(&kvm->slots_lock))
2890 continue;
3ee16c81
IE		 2891 spin_lock(&kvm->mmu_lock);
2892 npages = kvm->arch.n_alloc_mmu_pages -
2893 kvm->arch.n_free_mmu_pages;
2894 cache_count += npages;
2895 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2896 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2897 cache_count--;
2898 kvm_freed = kvm;
2899 }
2900 nr_to_scan--;
2901
2902 spin_unlock(&kvm->mmu_lock);
5a4c9288 2903 up_read(&kvm->slots_lock);
3ee16c81
IE		 2904 }
2905 if (kvm_freed)
2906 list_move_tail(&kvm_freed->vm_list, &vm_list);
2907
2908 spin_unlock(&kvm_lock);
2909
2910 return cache_count;
2911}
2912
2913static struct shrinker mmu_shrinker = {
2914 .shrink = mmu_shrink,
2915 .seeks = DEFAULT_SEEKS * 10,
2916};
2917
2ddfd20e 2918static void mmu_destroy_caches(void)
b5a33a75
AK		 2919{
2920 if (pte_chain_cache)
2921 kmem_cache_destroy(pte_chain_cache);
2922 if (rmap_desc_cache)
2923 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2924 if (mmu_page_header_cache)
2925 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2926}
2927
3ee16c81
IE		 2928void kvm_mmu_module_exit(void)
2929{
2930 mmu_destroy_caches();
2931 unregister_shrinker(&mmu_shrinker);
2932}
2933
b5a33a75
AK		 2934int kvm_mmu_module_init(void)
2935{
2936 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2937 sizeof(struct kvm_pte_chain),
20c2df83 2938 0, 0, NULL);
b5a33a75
AK		 2939 if (!pte_chain_cache)
2940 goto nomem;
2941 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2942 sizeof(struct kvm_rmap_desc),
20c2df83 2943 0, 0, NULL);
b5a33a75
AK		 2944 if (!rmap_desc_cache)
2945 goto nomem;
2946
d3d25b04
AK		 2947 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2948 sizeof(struct kvm_mmu_page),
20c2df83 2949 0, 0, NULL);
d3d25b04
AK		 2950 if (!mmu_page_header_cache)
2951 goto nomem;
2952
3ee16c81
IE		 2953 register_shrinker(&mmu_shrinker);
2954
b5a33a75
AK		 2955 return 0;
2956
2957nomem:
3ee16c81 2958 mmu_destroy_caches();
b5a33a75
AK		 2959 return -ENOMEM;
2960}
2961
3ad82a7e
ZX		 2962/*
2963 * Caculate mmu pages needed for kvm.
2964 */
2965unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
2966{
2967 int i;
2968 unsigned int nr_mmu_pages;
2969 unsigned int nr_pages = 0;
2970
2971 for (i = 0; i < kvm->nmemslots; i++)
2972 nr_pages += kvm->memslots[i].npages;
2973
2974 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
2975 nr_mmu_pages = max(nr_mmu_pages,
2976 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
2977
2978 return nr_mmu_pages;
2979}
2980
2f333bcb
MT		 2981static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
2982 unsigned len)
2983{
2984 if (len > buffer->len)
2985 return NULL;
2986 return buffer->ptr;
2987}
2988
2989static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
2990 unsigned len)
2991{
2992 void *ret;
2993
2994 ret = pv_mmu_peek_buffer(buffer, len);
2995 if (!ret)
2996 return ret;
2997 buffer->ptr += len;
2998 buffer->len -= len;
2999 buffer->processed += len;
3000 return ret;
3001}
3002
3003static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3004 gpa_t addr, gpa_t value)
3005{
3006 int bytes = 8;
3007 int r;
3008
3009 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3010 bytes = 4;
3011
3012 r = mmu_topup_memory_caches(vcpu);
3013 if (r)
3014 return r;
3015
3200f405 3016 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3017 return -EFAULT;
3018
3019 return 1;
3020}
3021
3022static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3023{
a8cd0244 3024 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3025 return 1;
3026}
3027
3028static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3029{
3030 spin_lock(&vcpu->kvm->mmu_lock);
3031 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3032 spin_unlock(&vcpu->kvm->mmu_lock);
3033 return 1;
3034}
3035
3036static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3037 struct kvm_pv_mmu_op_buffer *buffer)
3038{
3039 struct kvm_mmu_op_header *header;
3040
3041 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3042 if (!header)
3043 return 0;
3044 switch (header->op) {
3045 case KVM_MMU_OP_WRITE_PTE: {
3046 struct kvm_mmu_op_write_pte *wpte;
3047
3048 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3049 if (!wpte)
3050 return 0;
3051 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3052 wpte->pte_val);
3053 }
3054 case KVM_MMU_OP_FLUSH_TLB: {
3055 struct kvm_mmu_op_flush_tlb *ftlb;
3056
3057 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3058 if (!ftlb)
3059 return 0;
3060 return kvm_pv_mmu_flush_tlb(vcpu);
3061 }
3062 case KVM_MMU_OP_RELEASE_PT: {
3063 struct kvm_mmu_op_release_pt *rpt;
3064
3065 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3066 if (!rpt)
3067 return 0;
3068 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3069 }
3070 default: return 0;
3071 }
3072}
3073
3074int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3075 gpa_t addr, unsigned long *ret)
3076{
3077 int r;
6ad18fba 3078 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3079
6ad18fba
DH		 3080 buffer->ptr = buffer->buf;
3081 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3082 buffer->processed = 0;
2f333bcb 3083
6ad18fba 3084 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3085 if (r)
3086 goto out;
3087
6ad18fba
DH		 3088 while (buffer->len) {
3089 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3090 if (r < 0)
3091 goto out;
3092 if (r == 0)
3093 break;
3094 }
3095
3096 r = 1;
3097out:
6ad18fba 3098 *ret = buffer->processed;
2f333bcb
MT		 3099 return r;
3100}
3101
94d8b056
MT		 3102int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3103{
3104 struct kvm_shadow_walk_iterator iterator;
3105 int nr_sptes = 0;
3106
3107 spin_lock(&vcpu->kvm->mmu_lock);
3108 for_each_shadow_entry(vcpu, addr, iterator) {
3109 sptes[iterator.level-1] = *iterator.sptep;
3110 nr_sptes++;
3111 if (!is_shadow_present_pte(*iterator.sptep))
3112 break;
3113 }
3114 spin_unlock(&vcpu->kvm->mmu_lock);
3115
3116 return nr_sptes;
3117}
3118EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3119
37a7d8b0
AK		 3120#ifdef AUDIT
3121
3122static const char *audit_msg;
3123
3124static gva_t canonicalize(gva_t gva)
3125{
3126#ifdef CONFIG_X86_64
3127 gva = (long long)(gva << 16) >> 16;
3128#endif
3129 return gva;
3130}
3131
08a3732b
MT		 3132
3133typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3134 u64 *sptep);
3135
3136static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3137 inspect_spte_fn fn)
3138{
3139 int i;
3140
3141 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3142 u64 ent = sp->spt[i];
3143
3144 if (is_shadow_present_pte(ent)) {
2920d728 3145 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3146 struct kvm_mmu_page *child;
3147 child = page_header(ent & PT64_BASE_ADDR_MASK);
3148 __mmu_spte_walk(kvm, child, fn);
2920d728 3149 } else
08a3732b
MT		 3150 fn(kvm, sp, &sp->spt[i]);
3151 }
3152 }
3153}
3154
3155static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3156{
3157 int i;
3158 struct kvm_mmu_page *sp;
3159
3160 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3161 return;
3162 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3163 hpa_t root = vcpu->arch.mmu.root_hpa;
3164 sp = page_header(root);
3165 __mmu_spte_walk(vcpu->kvm, sp, fn);
3166 return;
3167 }
3168 for (i = 0; i < 4; ++i) {
3169 hpa_t root = vcpu->arch.mmu.pae_root[i];
3170
3171 if (root && VALID_PAGE(root)) {
3172 root &= PT64_BASE_ADDR_MASK;
3173 sp = page_header(root);
3174 __mmu_spte_walk(vcpu->kvm, sp, fn);
3175 }
3176 }
3177 return;
3178}
3179
37a7d8b0
AK		 3180static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3181 gva_t va, int level)
3182{
3183 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3184 int i;
3185 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3186
3187 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3188 u64 ent = pt[i];
3189
c7addb90 3190 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3191 continue;
3192
3193 va = canonicalize(va);
2920d728
MT		 3194 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3195 audit_mappings_page(vcpu, ent, va, level - 1);
3196 else {
ad312c7c 3197 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3198 gfn_t gfn = gpa >> PAGE_SHIFT;
3199 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3200 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3201
2aaf65e8
MT		 3202 if (is_error_pfn(pfn)) {
3203 kvm_release_pfn_clean(pfn);
3204 continue;
3205 }
3206
c7addb90 3207 if (is_shadow_present_pte(ent)
37a7d8b0 3208 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3209 printk(KERN_ERR "xx audit error: (%s) levels %d"
3210 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3211 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3212 va, gpa, hpa, ent,
3213 is_shadow_present_pte(ent));
c7addb90
AK		 3214 else if (ent == shadow_notrap_nonpresent_pte
3215 && !is_error_hpa(hpa))
3216 printk(KERN_ERR "audit: (%s) notrap shadow,"
3217 " valid guest gva %lx\n", audit_msg, va);
35149e21 3218 kvm_release_pfn_clean(pfn);
c7addb90 3219
37a7d8b0
AK		 3220 }
3221 }
3222}
3223
3224static void audit_mappings(struct kvm_vcpu *vcpu)
3225{
1ea252af 3226 unsigned i;
37a7d8b0 3227
ad312c7c
ZX		 3228 if (vcpu->arch.mmu.root_level == 4)
3229 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3230 else
3231 for (i = 0; i < 4; ++i)
ad312c7c 3232 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3233 audit_mappings_page(vcpu,
ad312c7c 3234 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3235 i << 30,
3236 2);
3237}
3238
3239static int count_rmaps(struct kvm_vcpu *vcpu)
3240{
3241 int nmaps = 0;
3242 int i, j, k;
3243
3244 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3245 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3246 struct kvm_rmap_desc *d;
3247
3248 for (j = 0; j < m->npages; ++j) {
290fc38d 3249 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3250
290fc38d 3251 if (!*rmapp)
37a7d8b0 3252 continue;
290fc38d 3253 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3254 ++nmaps;
3255 continue;
3256 }
290fc38d 3257 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3258 while (d) {
3259 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3260 if (d->sptes[k])
37a7d8b0
AK		 3261 ++nmaps;
3262 else
3263 break;
3264 d = d->more;
3265 }
3266 }
3267 }
3268 return nmaps;
3269}
3270
08a3732b
MT		 3271void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3272{
3273 unsigned long *rmapp;
3274 struct kvm_mmu_page *rev_sp;
3275 gfn_t gfn;
3276
3277 if (*sptep & PT_WRITABLE_MASK) {
3278 rev_sp = page_header(__pa(sptep));
3279 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3280
3281 if (!gfn_to_memslot(kvm, gfn)) {
3282 if (!printk_ratelimit())
3283 return;
3284 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3285 audit_msg, gfn);
3286 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3287 audit_msg, sptep - rev_sp->spt,
3288 rev_sp->gfn);
3289 dump_stack();
3290 return;
3291 }
3292
2920d728
MT		 3293 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3294 is_large_pte(*sptep));
08a3732b
MT		 3295 if (!*rmapp) {
3296 if (!printk_ratelimit())
3297 return;
3298 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3299 audit_msg, *sptep);
3300 dump_stack();
3301 }
3302 }
3303
3304}
3305
3306void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3307{
3308 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3309}
3310
3311static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3312{
4db35314 3313 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3314 int i;
3315
f05e70ac 3316 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3317 u64 *pt = sp->spt;
37a7d8b0 3318
4db35314 3319 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3320 continue;
3321
3322 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3323 u64 ent = pt[i];
3324
3325 if (!(ent & PT_PRESENT_MASK))
3326 continue;
3327 if (!(ent & PT_WRITABLE_MASK))
3328 continue;
08a3732b 3329 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3330 }
3331 }
08a3732b 3332 return;
37a7d8b0
AK		 3333}
3334
3335static void audit_rmap(struct kvm_vcpu *vcpu)
3336{
08a3732b
MT		 3337 check_writable_mappings_rmap(vcpu);
3338 count_rmaps(vcpu);
37a7d8b0
AK		 3339}
3340
3341static void audit_write_protection(struct kvm_vcpu *vcpu)
3342{
4db35314 3343 struct kvm_mmu_page *sp;
290fc38d
IE		 3344 struct kvm_memory_slot *slot;
3345 unsigned long *rmapp;
e58b0f9e 3346 u64 *spte;
290fc38d 3347 gfn_t gfn;
37a7d8b0 3348
f05e70ac 3349 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3350 if (sp->role.direct)
37a7d8b0 3351 continue;
e58b0f9e
MT		 3352 if (sp->unsync)
3353 continue;
37a7d8b0 3354
4db35314 3355 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3356 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3357 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3358
3359 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3360 while (spte) {
3361 if (*spte & PT_WRITABLE_MASK)
3362 printk(KERN_ERR "%s: (%s) shadow page has "
3363 "writable mappings: gfn %lx role %x\n",
b8688d51 3364 __func__, audit_msg, sp->gfn,
4db35314 3365 sp->role.word);
e58b0f9e
MT		 3366 spte = rmap_next(vcpu->kvm, rmapp, spte);
3367 }
37a7d8b0
AK		 3368 }
3369}
3370
3371static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3372{
3373 int olddbg = dbg;
3374
3375 dbg = 0;
3376 audit_msg = msg;
3377 audit_rmap(vcpu);
3378 audit_write_protection(vcpu);
2aaf65e8
MT		 3379 if (strcmp("pre pte write", audit_msg) != 0)
3380 audit_mappings(vcpu);
08a3732b 3381 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3382 dbg = olddbg;
3383}
3384
3385#endif
Linux kernel - Deliverables
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