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KVM: nVMX: Leave VMX mode on clearing of feature control MSR
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
d77c26fc 444 } host_state;
9c8cba37 445 struct {
7ffd92c5 446 int vm86_active;
78ac8b47 447 ulong save_rflags;
f5f7b2fe
AK		 448 struct kvm_segment segs[8];
449 } rmode;
450 struct {
451 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 452 struct kvm_save_segment {
453 u16 selector;
454 unsigned long base;
455 u32 limit;
456 u32 ar;
f5f7b2fe 457 } seg[8];
2fb92db1 458 } segment_cache;
2384d2b3 459 int vpid;
04fa4d32 460 bool emulation_required;
3b86cd99
JK		 461
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked;
464 ktime_t entry_time;
465 s64 vnmi_blocked_time;
a0861c02 466 u32 exit_reason;
4e47c7a6
SY		 467
468 bool rdtscp_enabled;
ec378aee 469
01e439be
YZ		 470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc;
472
ec378aee
NHE		 473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested;
a2fa3e9f
GH		 475};
476
2fb92db1
AK		 477enum segment_cache_field {
478 SEG_FIELD_SEL = 0,
479 SEG_FIELD_BASE = 1,
480 SEG_FIELD_LIMIT = 2,
481 SEG_FIELD_AR = 3,
482
483 SEG_FIELD_NR = 4
484};
485
a2fa3e9f
GH		 486static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
487{
fb3f0f51 488 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 489}
490
22bd0358
NHE		 491#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
495
4607c2d7
AG		 496
497static const unsigned long shadow_read_only_fields[] = {
498 /*
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
509 */
510 VM_EXIT_REASON,
511 VM_EXIT_INTR_INFO,
512 VM_EXIT_INSTRUCTION_LEN,
513 IDT_VECTORING_INFO_FIELD,
514 IDT_VECTORING_ERROR_CODE,
515 VM_EXIT_INTR_ERROR_CODE,
516 EXIT_QUALIFICATION,
517 GUEST_LINEAR_ADDRESS,
518 GUEST_PHYSICAL_ADDRESS
519};
520static const int max_shadow_read_only_fields =
521 ARRAY_SIZE(shadow_read_only_fields);
522
523static const unsigned long shadow_read_write_fields[] = {
524 GUEST_RIP,
525 GUEST_RSP,
526 GUEST_CR0,
527 GUEST_CR3,
528 GUEST_CR4,
529 GUEST_INTERRUPTIBILITY_INFO,
530 GUEST_RFLAGS,
531 GUEST_CS_SELECTOR,
532 GUEST_CS_AR_BYTES,
533 GUEST_CS_LIMIT,
534 GUEST_CS_BASE,
535 GUEST_ES_BASE,
536 CR0_GUEST_HOST_MASK,
537 CR0_READ_SHADOW,
538 CR4_READ_SHADOW,
539 TSC_OFFSET,
540 EXCEPTION_BITMAP,
541 CPU_BASED_VM_EXEC_CONTROL,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 VM_ENTRY_INTR_INFO_FIELD,
544 VM_ENTRY_INSTRUCTION_LEN,
545 VM_ENTRY_EXCEPTION_ERROR_CODE,
546 HOST_FS_BASE,
547 HOST_GS_BASE,
548 HOST_FS_SELECTOR,
549 HOST_GS_SELECTOR
550};
551static const int max_shadow_read_write_fields =
552 ARRAY_SIZE(shadow_read_write_fields);
553
772e0318 554static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 555 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
556 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
557 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
558 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
559 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
560 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
561 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
562 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
563 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
564 FIELD(HOST_ES_SELECTOR, host_es_selector),
565 FIELD(HOST_CS_SELECTOR, host_cs_selector),
566 FIELD(HOST_SS_SELECTOR, host_ss_selector),
567 FIELD(HOST_DS_SELECTOR, host_ds_selector),
568 FIELD(HOST_FS_SELECTOR, host_fs_selector),
569 FIELD(HOST_GS_SELECTOR, host_gs_selector),
570 FIELD(HOST_TR_SELECTOR, host_tr_selector),
571 FIELD64(IO_BITMAP_A, io_bitmap_a),
572 FIELD64(IO_BITMAP_B, io_bitmap_b),
573 FIELD64(MSR_BITMAP, msr_bitmap),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
577 FIELD64(TSC_OFFSET, tsc_offset),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
579 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
580 FIELD64(EPT_POINTER, ept_pointer),
581 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
582 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
583 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
584 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
585 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
587 FIELD64(GUEST_PDPTR0, guest_pdptr0),
588 FIELD64(GUEST_PDPTR1, guest_pdptr1),
589 FIELD64(GUEST_PDPTR2, guest_pdptr2),
590 FIELD64(GUEST_PDPTR3, guest_pdptr3),
591 FIELD64(HOST_IA32_PAT, host_ia32_pat),
592 FIELD64(HOST_IA32_EFER, host_ia32_efer),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
596 FIELD(EXCEPTION_BITMAP, exception_bitmap),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
599 FIELD(CR3_TARGET_COUNT, cr3_target_count),
600 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
601 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
603 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
608 FIELD(TPR_THRESHOLD, tpr_threshold),
609 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
610 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
611 FIELD(VM_EXIT_REASON, vm_exit_reason),
612 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
613 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
614 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
615 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
616 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
617 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
618 FIELD(GUEST_ES_LIMIT, guest_es_limit),
619 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
620 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
621 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
622 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
623 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
624 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
625 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
626 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
627 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
628 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
629 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
630 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
631 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
632 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
633 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
634 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
635 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
637 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
638 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
639 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 640 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 641 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
642 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
643 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
644 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
645 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
646 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
647 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
648 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
649 FIELD(EXIT_QUALIFICATION, exit_qualification),
650 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
651 FIELD(GUEST_CR0, guest_cr0),
652 FIELD(GUEST_CR3, guest_cr3),
653 FIELD(GUEST_CR4, guest_cr4),
654 FIELD(GUEST_ES_BASE, guest_es_base),
655 FIELD(GUEST_CS_BASE, guest_cs_base),
656 FIELD(GUEST_SS_BASE, guest_ss_base),
657 FIELD(GUEST_DS_BASE, guest_ds_base),
658 FIELD(GUEST_FS_BASE, guest_fs_base),
659 FIELD(GUEST_GS_BASE, guest_gs_base),
660 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
661 FIELD(GUEST_TR_BASE, guest_tr_base),
662 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
663 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
664 FIELD(GUEST_DR7, guest_dr7),
665 FIELD(GUEST_RSP, guest_rsp),
666 FIELD(GUEST_RIP, guest_rip),
667 FIELD(GUEST_RFLAGS, guest_rflags),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
669 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
670 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
671 FIELD(HOST_CR0, host_cr0),
672 FIELD(HOST_CR3, host_cr3),
673 FIELD(HOST_CR4, host_cr4),
674 FIELD(HOST_FS_BASE, host_fs_base),
675 FIELD(HOST_GS_BASE, host_gs_base),
676 FIELD(HOST_TR_BASE, host_tr_base),
677 FIELD(HOST_GDTR_BASE, host_gdtr_base),
678 FIELD(HOST_IDTR_BASE, host_idtr_base),
679 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
680 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
681 FIELD(HOST_RSP, host_rsp),
682 FIELD(HOST_RIP, host_rip),
683};
684static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
685
686static inline short vmcs_field_to_offset(unsigned long field)
687{
688 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
689 return -1;
690 return vmcs_field_to_offset_table[field];
691}
692
a9d30f33
NHE		 693static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
694{
695 return to_vmx(vcpu)->nested.current_vmcs12;
696}
697
698static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
699{
700 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 701 if (is_error_page(page))
a9d30f33 702 return NULL;
32cad84f 703
a9d30f33
NHE		 704 return page;
705}
706
707static void nested_release_page(struct page *page)
708{
709 kvm_release_page_dirty(page);
710}
711
712static void nested_release_page_clean(struct page *page)
713{
714 kvm_release_page_clean(page);
715}
716
bfd0a56b 717static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 718static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 719static void kvm_cpu_vmxon(u64 addr);
720static void kvm_cpu_vmxoff(void);
776e58ea 721static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 722static void vmx_set_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724static void vmx_get_segment(struct kvm_vcpu *vcpu,
725 struct kvm_segment *var, int seg);
d99e4152
GN		 726static bool guest_state_valid(struct kvm_vcpu *vcpu);
727static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 728static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 729static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 730static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 731
6aa8b732
AK		 732static DEFINE_PER_CPU(struct vmcs *, vmxarea);
733static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 734/*
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 */
738static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 739static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 740
3e7c73e9
AK		 741static unsigned long *vmx_io_bitmap_a;
742static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 743static unsigned long *vmx_msr_bitmap_legacy;
744static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 745static unsigned long *vmx_msr_bitmap_legacy_x2apic;
746static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 747static unsigned long *vmx_vmread_bitmap;
748static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 749
110312c8 750static bool cpu_has_load_ia32_efer;
8bf00a52 751static bool cpu_has_load_perf_global_ctrl;
110312c8 752
2384d2b3
SY		 753static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
754static DEFINE_SPINLOCK(vmx_vpid_lock);
755
1c3d14fe 756static struct vmcs_config {
6aa8b732
AK		 757 int size;
758 int order;
759 u32 revision_id;
1c3d14fe
YS		 760 u32 pin_based_exec_ctrl;
761 u32 cpu_based_exec_ctrl;
f78e0e2e 762 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 763 u32 vmexit_ctrl;
764 u32 vmentry_ctrl;
765} vmcs_config;
6aa8b732 766
efff9e53 767static struct vmx_capability {
d56f546d
SY		 768 u32 ept;
769 u32 vpid;
770} vmx_capability;
771
6aa8b732
AK		 772#define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 }
779
772e0318 780static const struct kvm_vmx_segment_field {
6aa8b732
AK		 781 unsigned selector;
782 unsigned base;
783 unsigned limit;
784 unsigned ar_bytes;
785} kvm_vmx_segment_fields[] = {
786 VMX_SEGMENT_FIELD(CS),
787 VMX_SEGMENT_FIELD(DS),
788 VMX_SEGMENT_FIELD(ES),
789 VMX_SEGMENT_FIELD(FS),
790 VMX_SEGMENT_FIELD(GS),
791 VMX_SEGMENT_FIELD(SS),
792 VMX_SEGMENT_FIELD(TR),
793 VMX_SEGMENT_FIELD(LDTR),
794};
795
26bb0981
AK		 796static u64 host_efer;
797
6de4f3ad
AK		 798static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799
4d56c8a7 800/*
8c06585d 801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 802 * away by decrementing the array size.
803 */
6aa8b732 804static const u32 vmx_msr_index[] = {
05b3e0c2 805#ifdef CONFIG_X86_64
44ea2b17 806 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 807#endif
8c06585d 808 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 809};
9d8f549d 810#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 811
31299944 812static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 813{
814 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
815 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 816 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 817}
818
31299944 819static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 824}
825
31299944 826static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 831}
832
31299944 833static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
836 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837}
838
31299944 839static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 847{
04547156 848 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 852{
04547156 853 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 854}
855
31299944 856static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 857{
04547156 858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 859}
860
31299944 861static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 862{
04547156
SY		 863 return vmcs_config.cpu_based_exec_ctrl &
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 865}
866
774ead3a 867static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 868{
04547156
SY		 869 return vmcs_config.cpu_based_2nd_exec_ctrl &
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871}
872
8d14695f
YZ		 873static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874{
875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877}
878
83d4c286
YZ		 879static inline bool cpu_has_vmx_apic_register_virt(void)
880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883}
884
c7c9c56c
YZ		 885static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889}
890
01e439be
YZ		 891static inline bool cpu_has_vmx_posted_intr(void)
892{
893 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894}
895
896static inline bool cpu_has_vmx_apicv(void)
897{
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
901}
902
04547156
SY		 903static inline bool cpu_has_vmx_flexpriority(void)
904{
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 907}
908
e799794e
MT		 909static inline bool cpu_has_vmx_ept_execute_only(void)
910{
31299944 911 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 912}
913
914static inline bool cpu_has_vmx_eptp_uncacheable(void)
915{
31299944 916 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 917}
918
919static inline bool cpu_has_vmx_eptp_writeback(void)
920{
31299944 921 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 922}
923
924static inline bool cpu_has_vmx_ept_2m_page(void)
925{
31299944 926 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 927}
928
878403b7
SY		 929static inline bool cpu_has_vmx_ept_1g_page(void)
930{
31299944 931 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 932}
933
4bc9b982
SY		 934static inline bool cpu_has_vmx_ept_4levels(void)
935{
936 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937}
938
83c3a331
XH		 939static inline bool cpu_has_vmx_ept_ad_bits(void)
940{
941 return vmx_capability.ept & VMX_EPT_AD_BIT;
942}
943
31299944 944static inline bool cpu_has_vmx_invept_context(void)
d56f546d 945{
31299944 946 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 947}
948
31299944 949static inline bool cpu_has_vmx_invept_global(void)
d56f546d 950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 952}
953
518c8aee
GJ		 954static inline bool cpu_has_vmx_invvpid_single(void)
955{
956 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957}
958
b9d762fa
GJ		 959static inline bool cpu_has_vmx_invvpid_global(void)
960{
961 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962}
963
31299944 964static inline bool cpu_has_vmx_ept(void)
d56f546d 965{
04547156
SY		 966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 968}
969
31299944 970static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974}
975
31299944 976static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980}
981
31299944 982static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 983{
6d3e435e 984 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_vpid(void)
2384d2b3 988{
04547156
SY		 989 return vmcs_config.cpu_based_2nd_exec_ctrl &
990 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 991}
992
31299944 993static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 994{
995 return vmcs_config.cpu_based_2nd_exec_ctrl &
996 SECONDARY_EXEC_RDTSCP;
997}
998
ad756a16
MJ		 999static inline bool cpu_has_vmx_invpcid(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_INVPCID;
1003}
1004
31299944 1005static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1006{
1007 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008}
1009
f5f48ee1
SY		 1010static inline bool cpu_has_vmx_wbinvd_exit(void)
1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_WBINVD_EXITING;
1014}
1015
abc4fc58
AG		 1016static inline bool cpu_has_vmx_shadow_vmcs(void)
1017{
1018 u64 vmx_msr;
1019 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return false;
1023
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_SHADOW_VMCS;
1026}
1027
04547156
SY		 1028static inline bool report_flexpriority(void)
1029{
1030 return flexpriority_enabled;
1031}
1032
fe3ef05c
NHE		 1033static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034{
1035 return vmcs12->cpu_based_vm_exec_control & bit;
1036}
1037
1038static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039{
1040 return (vmcs12->cpu_based_vm_exec_control &
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042 (vmcs12->secondary_vm_exec_control & bit);
1043}
1044
f5c4368f 1045static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1062static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063 struct vmcs12 *vmcs12,
1064 u32 reason, unsigned long qualification);
1065
8b9cf98c 1066static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1067{
1068 int i;
1069
a2fa3e9f 1070 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1071 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1072 return i;
1073 return -1;
1074}
1075
2384d2b3
SY		 1076static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077{
1078 struct {
1079 u64 vpid : 16;
1080 u64 rsvd : 48;
1081 u64 gva;
1082 } operand = { vpid, 0, gva };
1083
4ecac3fd 1084 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:"
1087 : : "a"(&operand), "c"(ext) : "cc", "memory");
1088}
1089
1439442c
SY		 1090static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091{
1092 struct {
1093 u64 eptp, gpa;
1094 } operand = {eptp, gpa};
1095
4ecac3fd 1096 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1097 /* CF==1 or ZF==1 --> rc = -1 */
1098 "; ja 1f ; ud2 ; 1:\n"
1099 : : "a" (&operand), "c" (ext) : "cc", "memory");
1100}
1101
26bb0981 1102static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1103{
1104 int i;
1105
8b9cf98c 1106 i = __find_msr_index(vmx, msr);
a75beee6 1107 if (i >= 0)
a2fa3e9f 1108 return &vmx->guest_msrs[i];
8b6d44c7 1109 return NULL;
7725f0ba
AK		 1110}
1111
6aa8b732
AK		 1112static void vmcs_clear(struct vmcs *vmcs)
1113{
1114 u64 phys_addr = __pa(vmcs);
1115 u8 error;
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1118 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1119 : "cc", "memory");
1120 if (error)
1121 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122 vmcs, phys_addr);
1123}
1124
d462b819
NHE		 1125static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126{
1127 vmcs_clear(loaded_vmcs->vmcs);
1128 loaded_vmcs->cpu = -1;
1129 loaded_vmcs->launched = 0;
1130}
1131
7725b894
DX		 1132static void vmcs_load(struct vmcs *vmcs)
1133{
1134 u64 phys_addr = __pa(vmcs);
1135 u8 error;
1136
1137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1138 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1139 : "cc", "memory");
1140 if (error)
2844d849 1141 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1142 vmcs, phys_addr);
1143}
1144
8f536b76
ZY		 1145#ifdef CONFIG_KEXEC
1146/*
1147 * This bitmap is used to indicate whether the vmclear
1148 * operation is enabled on all cpus. All disabled by
1149 * default.
1150 */
1151static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153static inline void crash_enable_local_vmclear(int cpu)
1154{
1155 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156}
1157
1158static inline void crash_disable_local_vmclear(int cpu)
1159{
1160 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161}
1162
1163static inline int crash_local_vmclear_enabled(int cpu)
1164{
1165 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166}
1167
1168static void crash_vmclear_local_loaded_vmcss(void)
1169{
1170 int cpu = raw_smp_processor_id();
1171 struct loaded_vmcs *v;
1172
1173 if (!crash_local_vmclear_enabled(cpu))
1174 return;
1175
1176 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177 loaded_vmcss_on_cpu_link)
1178 vmcs_clear(v->vmcs);
1179}
1180#else
1181static inline void crash_enable_local_vmclear(int cpu) { }
1182static inline void crash_disable_local_vmclear(int cpu) { }
1183#endif /* CONFIG_KEXEC */
1184
d462b819 1185static void __loaded_vmcs_clear(void *arg)
6aa8b732 1186{
d462b819 1187 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1188 int cpu = raw_smp_processor_id();
6aa8b732 1189
d462b819
NHE		 1190 if (loaded_vmcs->cpu != cpu)
1191 return; /* vcpu migration can race with cpu offline */
1192 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1193 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1194 crash_disable_local_vmclear(cpu);
d462b819 1195 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1196
1197 /*
1198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199 * is before setting loaded_vmcs->vcpu to -1 which is done in
1200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201 * then adds the vmcs into percpu list before it is deleted.
1202 */
1203 smp_wmb();
1204
d462b819 1205 loaded_vmcs_init(loaded_vmcs);
8f536b76 1206 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1207}
1208
d462b819 1209static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1210{
e6c7d321
XG		 1211 int cpu = loaded_vmcs->cpu;
1212
1213 if (cpu != -1)
1214 smp_call_function_single(cpu,
1215 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1216}
1217
1760dd49 1218static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1219{
1220 if (vmx->vpid == 0)
1221 return;
1222
518c8aee
GJ		 1223 if (cpu_has_vmx_invvpid_single())
1224 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1225}
1226
b9d762fa
GJ		 1227static inline void vpid_sync_vcpu_global(void)
1228{
1229 if (cpu_has_vmx_invvpid_global())
1230 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231}
1232
1233static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234{
1235 if (cpu_has_vmx_invvpid_single())
1760dd49 1236 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1237 else
1238 vpid_sync_vcpu_global();
1239}
1240
1439442c
SY		 1241static inline void ept_sync_global(void)
1242{
1243 if (cpu_has_vmx_invept_global())
1244 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245}
1246
1247static inline void ept_sync_context(u64 eptp)
1248{
089d034e 1249 if (enable_ept) {
1439442c
SY		 1250 if (cpu_has_vmx_invept_context())
1251 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252 else
1253 ept_sync_global();
1254 }
1255}
1256
96304217 1257static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1258{
5e520e62 1259 unsigned long value;
6aa8b732 1260
5e520e62
AK		 1261 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1263 return value;
1264}
1265
96304217 1266static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1267{
1268 return vmcs_readl(field);
1269}
1270
96304217 1271static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1272{
1273 return vmcs_readl(field);
1274}
1275
96304217 1276static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1277{
05b3e0c2 1278#ifdef CONFIG_X86_64
6aa8b732
AK		 1279 return vmcs_readl(field);
1280#else
1281 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282#endif
1283}
1284
e52de1b8
AK		 1285static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286{
1287 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289 dump_stack();
1290}
1291
6aa8b732
AK		 1292static void vmcs_writel(unsigned long field, unsigned long value)
1293{
1294 u8 error;
1295
4ecac3fd 1296 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1297 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1298 if (unlikely(error))
1299 vmwrite_error(field, value);
6aa8b732
AK		 1300}
1301
1302static void vmcs_write16(unsigned long field, u16 value)
1303{
1304 vmcs_writel(field, value);
1305}
1306
1307static void vmcs_write32(unsigned long field, u32 value)
1308{
1309 vmcs_writel(field, value);
1310}
1311
1312static void vmcs_write64(unsigned long field, u64 value)
1313{
6aa8b732 1314 vmcs_writel(field, value);
7682f2d0 1315#ifndef CONFIG_X86_64
6aa8b732
AK		 1316 asm volatile ("");
1317 vmcs_writel(field+1, value >> 32);
1318#endif
1319}
1320
2ab455cc
AL		 1321static void vmcs_clear_bits(unsigned long field, u32 mask)
1322{
1323 vmcs_writel(field, vmcs_readl(field) & ~mask);
1324}
1325
1326static void vmcs_set_bits(unsigned long field, u32 mask)
1327{
1328 vmcs_writel(field, vmcs_readl(field) | mask);
1329}
1330
2961e876
GN		 1331static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1332{
1333 vmcs_write32(VM_ENTRY_CONTROLS, val);
1334 vmx->vm_entry_controls_shadow = val;
1335}
1336
1337static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1338{
1339 if (vmx->vm_entry_controls_shadow != val)
1340 vm_entry_controls_init(vmx, val);
1341}
1342
1343static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1344{
1345 return vmx->vm_entry_controls_shadow;
1346}
1347
1348
1349static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1350{
1351 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1352}
1353
1354static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1355{
1356 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1357}
1358
1359static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1360{
1361 vmcs_write32(VM_EXIT_CONTROLS, val);
1362 vmx->vm_exit_controls_shadow = val;
1363}
1364
1365static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1366{
1367 if (vmx->vm_exit_controls_shadow != val)
1368 vm_exit_controls_init(vmx, val);
1369}
1370
1371static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1372{
1373 return vmx->vm_exit_controls_shadow;
1374}
1375
1376
1377static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1378{
1379 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1380}
1381
1382static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1385}
1386
2fb92db1
AK		 1387static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1388{
1389 vmx->segment_cache.bitmask = 0;
1390}
1391
1392static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1393 unsigned field)
1394{
1395 bool ret;
1396 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1397
1398 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1399 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1400 vmx->segment_cache.bitmask = 0;
1401 }
1402 ret = vmx->segment_cache.bitmask & mask;
1403 vmx->segment_cache.bitmask |= mask;
1404 return ret;
1405}
1406
1407static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1408{
1409 u16 *p = &vmx->segment_cache.seg[seg].selector;
1410
1411 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1412 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1413 return *p;
1414}
1415
1416static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1417{
1418 ulong *p = &vmx->segment_cache.seg[seg].base;
1419
1420 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1421 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1422 return *p;
1423}
1424
1425static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1426{
1427 u32 *p = &vmx->segment_cache.seg[seg].limit;
1428
1429 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1430 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1431 return *p;
1432}
1433
1434static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1435{
1436 u32 *p = &vmx->segment_cache.seg[seg].ar;
1437
1438 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1439 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1440 return *p;
1441}
1442
abd3f2d6
AK		 1443static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1444{
1445 u32 eb;
1446
fd7373cc
JK		 1447 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1448 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1449 if ((vcpu->guest_debug &
1450 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1451 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1452 eb |= 1u << BP_VECTOR;
7ffd92c5 1453 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1454 eb = ~0;
089d034e 1455 if (enable_ept)
1439442c 1456 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1457 if (vcpu->fpu_active)
1458 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1459
1460 /* When we are running a nested L2 guest and L1 specified for it a
1461 * certain exception bitmap, we must trap the same exceptions and pass
1462 * them to L1. When running L2, we will only handle the exceptions
1463 * specified above if L1 did not want them.
1464 */
1465 if (is_guest_mode(vcpu))
1466 eb |= get_vmcs12(vcpu)->exception_bitmap;
1467
abd3f2d6
AK		 1468 vmcs_write32(EXCEPTION_BITMAP, eb);
1469}
1470
2961e876
GN		 1471static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1472 unsigned long entry, unsigned long exit)
8bf00a52 1473{
2961e876
GN		 1474 vm_entry_controls_clearbit(vmx, entry);
1475 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1476}
1477
61d2ef2c
AK		 1478static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1479{
1480 unsigned i;
1481 struct msr_autoload *m = &vmx->msr_autoload;
1482
8bf00a52
GN		 1483 switch (msr) {
1484 case MSR_EFER:
1485 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1486 clear_atomic_switch_msr_special(vmx,
1487 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1488 VM_EXIT_LOAD_IA32_EFER);
1489 return;
1490 }
1491 break;
1492 case MSR_CORE_PERF_GLOBAL_CTRL:
1493 if (cpu_has_load_perf_global_ctrl) {
2961e876 1494 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1495 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1496 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1497 return;
1498 }
1499 break;
110312c8
AK		 1500 }
1501
61d2ef2c
AK		 1502 for (i = 0; i < m->nr; ++i)
1503 if (m->guest[i].index == msr)
1504 break;
1505
1506 if (i == m->nr)
1507 return;
1508 --m->nr;
1509 m->guest[i] = m->guest[m->nr];
1510 m->host[i] = m->host[m->nr];
1511 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1512 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1513}
1514
2961e876
GN		 1515static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1516 unsigned long entry, unsigned long exit,
1517 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1518 u64 guest_val, u64 host_val)
8bf00a52
GN		 1519{
1520 vmcs_write64(guest_val_vmcs, guest_val);
1521 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1522 vm_entry_controls_setbit(vmx, entry);
1523 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1524}
1525
61d2ef2c
AK		 1526static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1527 u64 guest_val, u64 host_val)
1528{
1529 unsigned i;
1530 struct msr_autoload *m = &vmx->msr_autoload;
1531
8bf00a52
GN		 1532 switch (msr) {
1533 case MSR_EFER:
1534 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1535 add_atomic_switch_msr_special(vmx,
1536 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1537 VM_EXIT_LOAD_IA32_EFER,
1538 GUEST_IA32_EFER,
1539 HOST_IA32_EFER,
1540 guest_val, host_val);
1541 return;
1542 }
1543 break;
1544 case MSR_CORE_PERF_GLOBAL_CTRL:
1545 if (cpu_has_load_perf_global_ctrl) {
2961e876 1546 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1547 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1548 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1549 GUEST_IA32_PERF_GLOBAL_CTRL,
1550 HOST_IA32_PERF_GLOBAL_CTRL,
1551 guest_val, host_val);
1552 return;
1553 }
1554 break;
110312c8
AK		 1555 }
1556
61d2ef2c
AK		 1557 for (i = 0; i < m->nr; ++i)
1558 if (m->guest[i].index == msr)
1559 break;
1560
e7fc6f93 1561 if (i == NR_AUTOLOAD_MSRS) {
60266204 1562 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1563 "Can't add msr %x\n", msr);
1564 return;
1565 } else if (i == m->nr) {
61d2ef2c
AK		 1566 ++m->nr;
1567 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1568 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1569 }
1570
1571 m->guest[i].index = msr;
1572 m->guest[i].value = guest_val;
1573 m->host[i].index = msr;
1574 m->host[i].value = host_val;
1575}
1576
33ed6329
AK		 1577static void reload_tss(void)
1578{
33ed6329
AK		 1579 /*
1580 * VT restores TR but not its size. Useless.
1581 */
d359192f 1582 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1583 struct desc_struct *descs;
33ed6329 1584
d359192f 1585 descs = (void *)gdt->address;
33ed6329
AK		 1586 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1587 load_TR_desc();
33ed6329
AK		 1588}
1589
92c0d900 1590static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1591{
3a34a881 1592 u64 guest_efer;
51c6cf66
AK		 1593 u64 ignore_bits;
1594
f6801dff 1595 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1596
51c6cf66 1597 /*
0fa06071 1598 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1599 * outside long mode
1600 */
1601 ignore_bits = EFER_NX | EFER_SCE;
1602#ifdef CONFIG_X86_64
1603 ignore_bits |= EFER_LMA | EFER_LME;
1604 /* SCE is meaningful only in long mode on Intel */
1605 if (guest_efer & EFER_LMA)
1606 ignore_bits &= ~(u64)EFER_SCE;
1607#endif
51c6cf66
AK		 1608 guest_efer &= ~ignore_bits;
1609 guest_efer |= host_efer & ignore_bits;
26bb0981 1610 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1611 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1612
1613 clear_atomic_switch_msr(vmx, MSR_EFER);
1614 /* On ept, can't emulate nx, and must switch nx atomically */
1615 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1616 guest_efer = vmx->vcpu.arch.efer;
1617 if (!(guest_efer & EFER_LMA))
1618 guest_efer &= ~EFER_LME;
1619 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1620 return false;
1621 }
1622
26bb0981 1623 return true;
51c6cf66
AK		 1624}
1625
2d49ec72
GN		 1626static unsigned long segment_base(u16 selector)
1627{
d359192f 1628 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1629 struct desc_struct *d;
1630 unsigned long table_base;
1631 unsigned long v;
1632
1633 if (!(selector & ~3))
1634 return 0;
1635
d359192f 1636 table_base = gdt->address;
2d49ec72
GN		 1637
1638 if (selector & 4) { /* from ldt */
1639 u16 ldt_selector = kvm_read_ldt();
1640
1641 if (!(ldt_selector & ~3))
1642 return 0;
1643
1644 table_base = segment_base(ldt_selector);
1645 }
1646 d = (struct desc_struct *)(table_base + (selector & ~7));
1647 v = get_desc_base(d);
1648#ifdef CONFIG_X86_64
1649 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1650 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1651#endif
1652 return v;
1653}
1654
1655static inline unsigned long kvm_read_tr_base(void)
1656{
1657 u16 tr;
1658 asm("str %0" : "=g"(tr));
1659 return segment_base(tr);
1660}
1661
04d2cc77 1662static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1663{
04d2cc77 1664 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1665 int i;
04d2cc77 1666
a2fa3e9f 1667 if (vmx->host_state.loaded)
33ed6329
AK		 1668 return;
1669
a2fa3e9f 1670 vmx->host_state.loaded = 1;
33ed6329
AK		 1671 /*
1672 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1673 * allow segment selectors with cpl > 0 or ti == 1.
1674 */
d6e88aec 1675 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1676 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1677 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1678 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1679 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1680 vmx->host_state.fs_reload_needed = 0;
1681 } else {
33ed6329 1682 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1683 vmx->host_state.fs_reload_needed = 1;
33ed6329 1684 }
9581d442 1685 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1686 if (!(vmx->host_state.gs_sel & 7))
1687 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1688 else {
1689 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1690 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1691 }
1692
b2da15ac
AK		 1693#ifdef CONFIG_X86_64
1694 savesegment(ds, vmx->host_state.ds_sel);
1695 savesegment(es, vmx->host_state.es_sel);
1696#endif
1697
33ed6329
AK		 1698#ifdef CONFIG_X86_64
1699 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1700 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1701#else
a2fa3e9f
GH		 1702 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1703 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1704#endif
707c0874
AK		 1705
1706#ifdef CONFIG_X86_64
c8770e7b
AK		 1707 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1708 if (is_long_mode(&vmx->vcpu))
44ea2b17 1709 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1710#endif
26bb0981
AK		 1711 for (i = 0; i < vmx->save_nmsrs; ++i)
1712 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1713 vmx->guest_msrs[i].data,
1714 vmx->guest_msrs[i].mask);
33ed6329
AK		 1715}
1716
a9b21b62 1717static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1718{
a2fa3e9f 1719 if (!vmx->host_state.loaded)
33ed6329
AK		 1720 return;
1721
e1beb1d3 1722 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1723 vmx->host_state.loaded = 0;
c8770e7b
AK		 1724#ifdef CONFIG_X86_64
1725 if (is_long_mode(&vmx->vcpu))
1726 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1727#endif
152d3f2f 1728 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1729 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1730#ifdef CONFIG_X86_64
9581d442 1731 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1732#else
1733 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1734#endif
33ed6329 1735 }
0a77fe4c
AK		 1736 if (vmx->host_state.fs_reload_needed)
1737 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1738#ifdef CONFIG_X86_64
1739 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1740 loadsegment(ds, vmx->host_state.ds_sel);
1741 loadsegment(es, vmx->host_state.es_sel);
1742 }
b2da15ac 1743#endif
152d3f2f 1744 reload_tss();
44ea2b17 1745#ifdef CONFIG_X86_64
c8770e7b 1746 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1747#endif
b1a74bf8
SS		 1748 /*
1749 * If the FPU is not active (through the host task or
1750 * the guest vcpu), then restore the cr0.TS bit.
1751 */
1752 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1753 stts();
3444d7da 1754 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1755}
1756
a9b21b62
AK		 1757static void vmx_load_host_state(struct vcpu_vmx *vmx)
1758{
1759 preempt_disable();
1760 __vmx_load_host_state(vmx);
1761 preempt_enable();
1762}
1763
6aa8b732
AK		 1764/*
1765 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1766 * vcpu mutex is already taken.
1767 */
15ad7146 1768static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1769{
a2fa3e9f 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1771 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1772
4610c9cc
DX		 1773 if (!vmm_exclusive)
1774 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1775 else if (vmx->loaded_vmcs->cpu != cpu)
1776 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1777
d462b819
NHE		 1778 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1779 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1780 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1781 }
1782
d462b819 1783 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1784 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1785 unsigned long sysenter_esp;
1786
a8eeb04a 1787 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1788 local_irq_disable();
8f536b76 1789 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1790
1791 /*
1792 * Read loaded_vmcs->cpu should be before fetching
1793 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1794 * See the comments in __loaded_vmcs_clear().
1795 */
1796 smp_rmb();
1797
d462b819
NHE		 1798 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1799 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1800 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1801 local_irq_enable();
1802
6aa8b732
AK		 1803 /*
1804 * Linux uses per-cpu TSS and GDT, so set these when switching
1805 * processors.
1806 */
d6e88aec 1807 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1808 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1809
1810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1812 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1813 }
6aa8b732
AK		 1814}
1815
1816static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1817{
a9b21b62 1818 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1819 if (!vmm_exclusive) {
d462b819
NHE		 1820 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1821 vcpu->cpu = -1;
4610c9cc
DX		 1822 kvm_cpu_vmxoff();
1823 }
6aa8b732
AK		 1824}
1825
5fd86fcf
AK		 1826static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1827{
81231c69
AK		 1828 ulong cr0;
1829
5fd86fcf
AK		 1830 if (vcpu->fpu_active)
1831 return;
1832 vcpu->fpu_active = 1;
81231c69
AK		 1833 cr0 = vmcs_readl(GUEST_CR0);
1834 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1835 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1836 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1837 update_exception_bitmap(vcpu);
edcafe3c 1838 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1839 if (is_guest_mode(vcpu))
1840 vcpu->arch.cr0_guest_owned_bits &=
1841 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1842 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1843}
1844
edcafe3c
AK		 1845static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1846
fe3ef05c
NHE		 1847/*
1848 * Return the cr0 value that a nested guest would read. This is a combination
1849 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1850 * its hypervisor (cr0_read_shadow).
1851 */
1852static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1853{
1854 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1855 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1856}
1857static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1858{
1859 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1860 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1861}
1862
5fd86fcf
AK		 1863static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1864{
36cf24e0
NHE		 1865 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1866 * set this *before* calling this function.
1867 */
edcafe3c 1868 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1869 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1870 update_exception_bitmap(vcpu);
edcafe3c
AK		 1871 vcpu->arch.cr0_guest_owned_bits = 0;
1872 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1873 if (is_guest_mode(vcpu)) {
1874 /*
1875 * L1's specified read shadow might not contain the TS bit,
1876 * so now that we turned on shadowing of this bit, we need to
1877 * set this bit of the shadow. Like in nested_vmx_run we need
1878 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1879 * up-to-date here because we just decached cr0.TS (and we'll
1880 * only update vmcs12->guest_cr0 on nested exit).
1881 */
1882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1883 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1884 (vcpu->arch.cr0 & X86_CR0_TS);
1885 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1886 } else
1887 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1888}
1889
6aa8b732
AK		 1890static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1891{
78ac8b47 1892 unsigned long rflags, save_rflags;
345dcaa8 1893
6de12732
AK		 1894 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1895 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1896 rflags = vmcs_readl(GUEST_RFLAGS);
1897 if (to_vmx(vcpu)->rmode.vm86_active) {
1898 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1899 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1900 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1901 }
1902 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1903 }
6de12732 1904 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1905}
1906
1907static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1908{
6de12732
AK		 1909 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1910 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1911 if (to_vmx(vcpu)->rmode.vm86_active) {
1912 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1913 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1914 }
6aa8b732
AK		 1915 vmcs_writel(GUEST_RFLAGS, rflags);
1916}
1917
2809f5d2
GC		 1918static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1919{
1920 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1921 int ret = 0;
1922
1923 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1924 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1925 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1926 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1927
1928 return ret & mask;
1929}
1930
1931static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1932{
1933 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1934 u32 interruptibility = interruptibility_old;
1935
1936 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1937
48005f64 1938 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1939 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1940 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1941 interruptibility |= GUEST_INTR_STATE_STI;
1942
1943 if ((interruptibility != interruptibility_old))
1944 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1945}
1946
6aa8b732
AK		 1947static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1948{
1949 unsigned long rip;
6aa8b732 1950
5fdbf976 1951 rip = kvm_rip_read(vcpu);
6aa8b732 1952 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1953 kvm_rip_write(vcpu, rip);
6aa8b732 1954
2809f5d2
GC		 1955 /* skipping an emulated instruction also counts */
1956 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1957}
1958
0b6ac343
NHE		 1959/*
1960 * KVM wants to inject page-faults which it got to the guest. This function
1961 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1962 */
e011c663 1963static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1964{
1965 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1966
e011c663 1967 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1968 return 0;
1969
1970 nested_vmx_vmexit(vcpu);
1971 return 1;
1972}
1973
298101da 1974static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1975 bool has_error_code, u32 error_code,
1976 bool reinject)
298101da 1977{
77ab6db0 1978 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1979 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1980
e011c663
GN		 1981 if (!reinject && is_guest_mode(vcpu) &&
1982 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1983 return;
1984
8ab2d2e2 1985 if (has_error_code) {
77ab6db0 1986 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1987 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1988 }
77ab6db0 1989
7ffd92c5 1990 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1991 int inc_eip = 0;
1992 if (kvm_exception_is_soft(nr))
1993 inc_eip = vcpu->arch.event_exit_inst_len;
1994 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1996 return;
1997 }
1998
66fd3f7f
GN		 1999 if (kvm_exception_is_soft(nr)) {
2000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2001 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2002 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2003 } else
2004 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2005
2006 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2007}
2008
4e47c7a6
SY		 2009static bool vmx_rdtscp_supported(void)
2010{
2011 return cpu_has_vmx_rdtscp();
2012}
2013
ad756a16
MJ		 2014static bool vmx_invpcid_supported(void)
2015{
2016 return cpu_has_vmx_invpcid() && enable_ept;
2017}
2018
a75beee6
ED		 2019/*
2020 * Swap MSR entry in host/guest MSR entry array.
2021 */
8b9cf98c 2022static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2023{
26bb0981 2024 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2025
2026 tmp = vmx->guest_msrs[to];
2027 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2028 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2029}
2030
8d14695f
YZ		 2031static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2032{
2033 unsigned long *msr_bitmap;
2034
2035 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2036 if (is_long_mode(vcpu))
2037 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2038 else
2039 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2040 } else {
2041 if (is_long_mode(vcpu))
2042 msr_bitmap = vmx_msr_bitmap_longmode;
2043 else
2044 msr_bitmap = vmx_msr_bitmap_legacy;
2045 }
2046
2047 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2048}
2049
e38aea3e
AK		 2050/*
2051 * Set up the vmcs to automatically save and restore system
2052 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2053 * mode, as fiddling with msrs is very expensive.
2054 */
8b9cf98c 2055static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2056{
26bb0981 2057 int save_nmsrs, index;
e38aea3e 2058
a75beee6
ED		 2059 save_nmsrs = 0;
2060#ifdef CONFIG_X86_64
8b9cf98c 2061 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2062 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2063 if (index >= 0)
8b9cf98c
RR		 2064 move_msr_up(vmx, index, save_nmsrs++);
2065 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2066 if (index >= 0)
8b9cf98c
RR		 2067 move_msr_up(vmx, index, save_nmsrs++);
2068 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2069 if (index >= 0)
8b9cf98c 2070 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2071 index = __find_msr_index(vmx, MSR_TSC_AUX);
2072 if (index >= 0 && vmx->rdtscp_enabled)
2073 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2074 /*
8c06585d 2075 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2076 * if efer.sce is enabled.
2077 */
8c06585d 2078 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2079 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2080 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2081 }
2082#endif
92c0d900
AK		 2083 index = __find_msr_index(vmx, MSR_EFER);
2084 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2085 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2086
26bb0981 2087 vmx->save_nmsrs = save_nmsrs;
5897297b 2088
8d14695f
YZ		 2089 if (cpu_has_vmx_msr_bitmap())
2090 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2091}
2092
6aa8b732
AK		 2093/*
2094 * reads and returns guest's timestamp counter "register"
2095 * guest_tsc = host_tsc + tsc_offset -- 21.3
2096 */
2097static u64 guest_read_tsc(void)
2098{
2099 u64 host_tsc, tsc_offset;
2100
2101 rdtscll(host_tsc);
2102 tsc_offset = vmcs_read64(TSC_OFFSET);
2103 return host_tsc + tsc_offset;
2104}
2105
d5c1785d
NHE		 2106/*
2107 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2108 * counter, even if a nested guest (L2) is currently running.
2109 */
886b470c 2110u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2111{
886b470c 2112 u64 tsc_offset;
d5c1785d 2113
d5c1785d
NHE		 2114 tsc_offset = is_guest_mode(vcpu) ?
2115 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2116 vmcs_read64(TSC_OFFSET);
2117 return host_tsc + tsc_offset;
2118}
2119
4051b188 2120/*
cc578287
ZA		 2121 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2122 * software catchup for faster rates on slower CPUs.
4051b188 2123 */
cc578287 2124static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2125{
cc578287
ZA		 2126 if (!scale)
2127 return;
2128
2129 if (user_tsc_khz > tsc_khz) {
2130 vcpu->arch.tsc_catchup = 1;
2131 vcpu->arch.tsc_always_catchup = 1;
2132 } else
2133 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2134}
2135
ba904635
WA		 2136static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2137{
2138 return vmcs_read64(TSC_OFFSET);
2139}
2140
6aa8b732 2141/*
99e3e30a 2142 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2143 */
99e3e30a 2144static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2145{
27fc51b2 2146 if (is_guest_mode(vcpu)) {
7991825b 2147 /*
27fc51b2
NHE		 2148 * We're here if L1 chose not to trap WRMSR to TSC. According
2149 * to the spec, this should set L1's TSC; The offset that L1
2150 * set for L2 remains unchanged, and still needs to be added
2151 * to the newly set TSC to get L2's TSC.
7991825b 2152 */
27fc51b2
NHE		 2153 struct vmcs12 *vmcs12;
2154 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2155 /* recalculate vmcs02.TSC_OFFSET: */
2156 vmcs12 = get_vmcs12(vcpu);
2157 vmcs_write64(TSC_OFFSET, offset +
2158 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2159 vmcs12->tsc_offset : 0));
2160 } else {
489223ed
YY		 2161 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2162 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2163 vmcs_write64(TSC_OFFSET, offset);
2164 }
6aa8b732
AK		 2165}
2166
f1e2b260 2167static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2168{
2169 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2170
e48672fa 2171 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2172 if (is_guest_mode(vcpu)) {
2173 /* Even when running L2, the adjustment needs to apply to L1 */
2174 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2175 } else
2176 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2177 offset + adjustment);
e48672fa
ZA		 2178}
2179
857e4099
JR		 2180static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2181{
2182 return target_tsc - native_read_tsc();
2183}
2184
801d3424
NHE		 2185static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2186{
2187 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2188 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2189}
2190
2191/*
2192 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2193 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2194 * all guests if the "nested" module option is off, and can also be disabled
2195 * for a single guest by disabling its VMX cpuid bit.
2196 */
2197static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2198{
2199 return nested && guest_cpuid_has_vmx(vcpu);
2200}
2201
b87a51ae
NHE		 2202/*
2203 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2204 * returned for the various VMX controls MSRs when nested VMX is enabled.
2205 * The same values should also be used to verify that vmcs12 control fields are
2206 * valid during nested entry from L1 to L2.
2207 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2208 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2209 * bit in the high half is on if the corresponding bit in the control field
2210 * may be on. See also vmx_control_verify().
2211 * TODO: allow these variables to be modified (downgraded) by module options
2212 * or other means.
2213 */
2214static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2215static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2216static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2217static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2218static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2219static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2220static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2221static __init void nested_vmx_setup_ctls_msrs(void)
2222{
2223 /*
2224 * Note that as a general rule, the high half of the MSRs (bits in
2225 * the control fields which may be 1) should be initialized by the
2226 * intersection of the underlying hardware's MSR (i.e., features which
2227 * can be supported) and the list of features we want to expose -
2228 * because they are known to be properly supported in our code.
2229 * Also, usually, the low half of the MSRs (bits which must be 1) can
2230 * be set to 0, meaning that L1 may turn off any of these bits. The
2231 * reason is that if one of these bits is necessary, it will appear
2232 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2233 * fields of vmcs01 and vmcs02, will turn these bits off - and
2234 * nested_vmx_exit_handled() will not pass related exits to L1.
2235 * These rules have exceptions below.
2236 */
2237
2238 /* pin-based controls */
eabeaacc
JK		 2239 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2240 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2241 /*
2242 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2243 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2244 */
eabeaacc
JK		 2245 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2246 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2247 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2248 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2249 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2250
33fb20c3
JK		 2251 /*
2252 * Exit controls
2253 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2254 * 17 must be 1.
2255 */
c0dfee58
ACL		 2256 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2257 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2258 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2259 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2260 nested_vmx_exit_ctls_high &=
b87a51ae 2261#ifdef CONFIG_X86_64
c0dfee58 2262 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2263#endif
7854cbca
ACL		 2264 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2265 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2266 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2267 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2268 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2269 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2270 }
8049d651 2271 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2272 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2273
2274 /* entry controls */
2275 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2276 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2277 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2278 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2279 nested_vmx_entry_ctls_high &=
57435349
JK		 2280#ifdef CONFIG_X86_64
2281 VM_ENTRY_IA32E_MODE |
2282#endif
2283 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2284 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2285 VM_ENTRY_LOAD_IA32_EFER);
57435349 2286
b87a51ae
NHE		 2287 /* cpu-based controls */
2288 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2289 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2290 nested_vmx_procbased_ctls_low = 0;
2291 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2292 CPU_BASED_VIRTUAL_INTR_PENDING |
2293 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2294 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2295 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2296 CPU_BASED_CR3_STORE_EXITING |
2297#ifdef CONFIG_X86_64
2298 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2299#endif
2300 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2301 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2302 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2303 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2304 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2305 /*
2306 * We can allow some features even when not supported by the
2307 * hardware. For example, L1 can specify an MSR bitmap - and we
2308 * can use it to avoid exits to L1 - even when L0 runs L2
2309 * without MSR bitmaps.
2310 */
2311 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2312
2313 /* secondary cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2315 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2316 nested_vmx_secondary_ctls_low = 0;
2317 nested_vmx_secondary_ctls_high &=
d6851fbe 2318 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2319 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2320 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2321
afa61f75
NHE		 2322 if (enable_ept) {
2323 /* nested EPT: emulate EPT also to L1 */
2324 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2325 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2326 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2327 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2328 nested_vmx_ept_caps &= vmx_capability.ept;
2329 /*
2330 * Since invept is completely emulated we support both global
2331 * and context invalidation independent of what host cpu
2332 * supports
2333 */
2334 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2335 VMX_EPT_EXTENT_CONTEXT_BIT;
2336 } else
2337 nested_vmx_ept_caps = 0;
2338
c18911a2
JK		 2339 /* miscellaneous data */
2340 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2341 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2342 VMX_MISC_SAVE_EFER_LMA;
6dfacadd 2343 nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
c18911a2 2344 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2345}
2346
2347static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2348{
2349 /*
2350 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2351 */
2352 return ((control & high) | low) == control;
2353}
2354
2355static inline u64 vmx_control_msr(u32 low, u32 high)
2356{
2357 return low | ((u64)high << 32);
2358}
2359
2360/*
2361 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2362 * also let it use VMX-specific MSRs.
2363 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2364 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2365 * like all other MSRs).
2366 */
2367static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2368{
2369 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2370 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2371 /*
2372 * According to the spec, processors which do not support VMX
2373 * should throw a #GP(0) when VMX capability MSRs are read.
2374 */
2375 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2376 return 1;
2377 }
2378
2379 switch (msr_index) {
2380 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2381 if (nested_vmx_allowed(vcpu)) {
2382 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2383 break;
2384 }
2385 return 0;
b87a51ae
NHE		 2386 case MSR_IA32_VMX_BASIC:
2387 /*
2388 * This MSR reports some information about VMX support. We
2389 * should return information about the VMX we emulate for the
2390 * guest, and the VMCS structure we give it - not about the
2391 * VMX support of the underlying hardware.
2392 */
2393 *pdata = VMCS12_REVISION |
2394 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2395 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2396 break;
2397 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2398 case MSR_IA32_VMX_PINBASED_CTLS:
2399 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2400 nested_vmx_pinbased_ctls_high);
2401 break;
2402 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2403 case MSR_IA32_VMX_PROCBASED_CTLS:
2404 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2405 nested_vmx_procbased_ctls_high);
2406 break;
2407 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2408 case MSR_IA32_VMX_EXIT_CTLS:
2409 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2410 nested_vmx_exit_ctls_high);
2411 break;
2412 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2413 case MSR_IA32_VMX_ENTRY_CTLS:
2414 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2415 nested_vmx_entry_ctls_high);
2416 break;
2417 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2418 *pdata = vmx_control_msr(nested_vmx_misc_low,
2419 nested_vmx_misc_high);
b87a51ae
NHE		 2420 break;
2421 /*
2422 * These MSRs specify bits which the guest must keep fixed (on or off)
2423 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2424 * We picked the standard core2 setting.
2425 */
2426#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2427#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2428 case MSR_IA32_VMX_CR0_FIXED0:
2429 *pdata = VMXON_CR0_ALWAYSON;
2430 break;
2431 case MSR_IA32_VMX_CR0_FIXED1:
2432 *pdata = -1ULL;
2433 break;
2434 case MSR_IA32_VMX_CR4_FIXED0:
2435 *pdata = VMXON_CR4_ALWAYSON;
2436 break;
2437 case MSR_IA32_VMX_CR4_FIXED1:
2438 *pdata = -1ULL;
2439 break;
2440 case MSR_IA32_VMX_VMCS_ENUM:
2441 *pdata = 0x1f;
2442 break;
2443 case MSR_IA32_VMX_PROCBASED_CTLS2:
2444 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2445 nested_vmx_secondary_ctls_high);
2446 break;
2447 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2448 /* Currently, no nested vpid support */
2449 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2450 break;
2451 default:
2452 return 0;
2453 }
2454
2455 return 1;
2456}
2457
42124925
JK		 2458static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2459
b3897a49 2460static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2461{
b3897a49
NHE		 2462 u32 msr_index = msr_info->index;
2463 u64 data = msr_info->data;
2464 bool host_initialized = msr_info->host_initiated;
2465
b87a51ae
NHE		 2466 if (!nested_vmx_allowed(vcpu))
2467 return 0;
2468
b3897a49
NHE		 2469 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2470 if (!host_initialized &&
2471 to_vmx(vcpu)->nested.msr_ia32_feature_control
2472 & FEATURE_CONTROL_LOCKED)
2473 return 0;
2474 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
42124925
JK		 2475 if (host_initialized && data == 0)
2476 vmx_leave_nested(vcpu);
b87a51ae 2477 return 1;
b3897a49
NHE		 2478 }
2479
b87a51ae
NHE		 2480 /*
2481 * No need to treat VMX capability MSRs specially: If we don't handle
2482 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2483 */
2484 return 0;
2485}
2486
6aa8b732
AK		 2487/*
2488 * Reads an msr value (of 'msr_index') into 'pdata'.
2489 * Returns 0 on success, non-0 otherwise.
2490 * Assumes vcpu_load() was already called.
2491 */
2492static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2493{
2494 u64 data;
26bb0981 2495 struct shared_msr_entry *msr;
6aa8b732
AK		 2496
2497 if (!pdata) {
2498 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2499 return -EINVAL;
2500 }
2501
2502 switch (msr_index) {
05b3e0c2 2503#ifdef CONFIG_X86_64
6aa8b732
AK		 2504 case MSR_FS_BASE:
2505 data = vmcs_readl(GUEST_FS_BASE);
2506 break;
2507 case MSR_GS_BASE:
2508 data = vmcs_readl(GUEST_GS_BASE);
2509 break;
44ea2b17
AK		 2510 case MSR_KERNEL_GS_BASE:
2511 vmx_load_host_state(to_vmx(vcpu));
2512 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2513 break;
26bb0981 2514#endif
6aa8b732 2515 case MSR_EFER:
3bab1f5d 2516 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2517 case MSR_IA32_TSC:
6aa8b732
AK		 2518 data = guest_read_tsc();
2519 break;
2520 case MSR_IA32_SYSENTER_CS:
2521 data = vmcs_read32(GUEST_SYSENTER_CS);
2522 break;
2523 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2524 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2525 break;
2526 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2527 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2528 break;
4e47c7a6
SY		 2529 case MSR_TSC_AUX:
2530 if (!to_vmx(vcpu)->rdtscp_enabled)
2531 return 1;
2532 /* Otherwise falls through */
6aa8b732 2533 default:
b87a51ae
NHE		 2534 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2535 return 0;
8b9cf98c 2536 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2537 if (msr) {
2538 data = msr->data;
2539 break;
6aa8b732 2540 }
3bab1f5d 2541 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2542 }
2543
2544 *pdata = data;
2545 return 0;
2546}
2547
2548/*
2549 * Writes msr value into into the appropriate "register".
2550 * Returns 0 on success, non-0 otherwise.
2551 * Assumes vcpu_load() was already called.
2552 */
8fe8ab46 2553static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2554{
a2fa3e9f 2555 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2556 struct shared_msr_entry *msr;
2cc51560 2557 int ret = 0;
8fe8ab46
WA		 2558 u32 msr_index = msr_info->index;
2559 u64 data = msr_info->data;
2cc51560 2560
6aa8b732 2561 switch (msr_index) {
3bab1f5d 2562 case MSR_EFER:
8fe8ab46 2563 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2564 break;
16175a79 2565#ifdef CONFIG_X86_64
6aa8b732 2566 case MSR_FS_BASE:
2fb92db1 2567 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2568 vmcs_writel(GUEST_FS_BASE, data);
2569 break;
2570 case MSR_GS_BASE:
2fb92db1 2571 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2572 vmcs_writel(GUEST_GS_BASE, data);
2573 break;
44ea2b17
AK		 2574 case MSR_KERNEL_GS_BASE:
2575 vmx_load_host_state(vmx);
2576 vmx->msr_guest_kernel_gs_base = data;
2577 break;
6aa8b732
AK		 2578#endif
2579 case MSR_IA32_SYSENTER_CS:
2580 vmcs_write32(GUEST_SYSENTER_CS, data);
2581 break;
2582 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2583 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2584 break;
2585 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2586 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2587 break;
af24a4e4 2588 case MSR_IA32_TSC:
8fe8ab46 2589 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2590 break;
468d472f
SY		 2591 case MSR_IA32_CR_PAT:
2592 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2593 vmcs_write64(GUEST_IA32_PAT, data);
2594 vcpu->arch.pat = data;
2595 break;
2596 }
8fe8ab46 2597 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2598 break;
ba904635
WA		 2599 case MSR_IA32_TSC_ADJUST:
2600 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2601 break;
2602 case MSR_TSC_AUX:
2603 if (!vmx->rdtscp_enabled)
2604 return 1;
2605 /* Check reserved bit, higher 32 bits should be zero */
2606 if ((data >> 32) != 0)
2607 return 1;
2608 /* Otherwise falls through */
6aa8b732 2609 default:
b3897a49 2610 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2611 break;
8b9cf98c 2612 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2613 if (msr) {
2614 msr->data = data;
2225fd56
AK		 2615 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2616 preempt_disable();
9ee73970
AK		 2617 kvm_set_shared_msr(msr->index, msr->data,
2618 msr->mask);
2225fd56
AK		 2619 preempt_enable();
2620 }
3bab1f5d 2621 break;
6aa8b732 2622 }
8fe8ab46 2623 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2624 }
2625
2cc51560 2626 return ret;
6aa8b732
AK		 2627}
2628
5fdbf976 2629static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2630{
5fdbf976
MT		 2631 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2632 switch (reg) {
2633 case VCPU_REGS_RSP:
2634 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2635 break;
2636 case VCPU_REGS_RIP:
2637 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2638 break;
6de4f3ad
AK		 2639 case VCPU_EXREG_PDPTR:
2640 if (enable_ept)
2641 ept_save_pdptrs(vcpu);
2642 break;
5fdbf976
MT		 2643 default:
2644 break;
2645 }
6aa8b732
AK		 2646}
2647
6aa8b732
AK		 2648static __init int cpu_has_kvm_support(void)
2649{
6210e37b 2650 return cpu_has_vmx();
6aa8b732
AK		 2651}
2652
2653static __init int vmx_disabled_by_bios(void)
2654{
2655 u64 msr;
2656
2657 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2658 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2659 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2660 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2661 && tboot_enabled())
2662 return 1;
23f3e991 2663 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2664 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2665 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2666 && !tboot_enabled()) {
2667 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2668 "activate TXT before enabling KVM\n");
cafd6659 2669 return 1;
f9335afe 2670 }
23f3e991
JC		 2671 /* launched w/o TXT and VMX disabled */
2672 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2673 && !tboot_enabled())
2674 return 1;
cafd6659
SW		 2675 }
2676
2677 return 0;
6aa8b732
AK		 2678}
2679
7725b894
DX		 2680static void kvm_cpu_vmxon(u64 addr)
2681{
2682 asm volatile (ASM_VMX_VMXON_RAX
2683 : : "a"(&addr), "m"(addr)
2684 : "memory", "cc");
2685}
2686
10474ae8 2687static int hardware_enable(void *garbage)
6aa8b732
AK		 2688{
2689 int cpu = raw_smp_processor_id();
2690 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2691 u64 old, test_bits;
6aa8b732 2692
10474ae8
AG		 2693 if (read_cr4() & X86_CR4_VMXE)
2694 return -EBUSY;
2695
d462b819 2696 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2697
2698 /*
2699 * Now we can enable the vmclear operation in kdump
2700 * since the loaded_vmcss_on_cpu list on this cpu
2701 * has been initialized.
2702 *
2703 * Though the cpu is not in VMX operation now, there
2704 * is no problem to enable the vmclear operation
2705 * for the loaded_vmcss_on_cpu list is empty!
2706 */
2707 crash_enable_local_vmclear(cpu);
2708
6aa8b732 2709 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2710
2711 test_bits = FEATURE_CONTROL_LOCKED;
2712 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2713 if (tboot_enabled())
2714 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2715
2716 if ((old & test_bits) != test_bits) {
6aa8b732 2717 /* enable and lock */
cafd6659
SW		 2718 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2719 }
66aee91a 2720 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2721
4610c9cc
DX		 2722 if (vmm_exclusive) {
2723 kvm_cpu_vmxon(phys_addr);
2724 ept_sync_global();
2725 }
10474ae8 2726
357d1226 2727 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2728
10474ae8 2729 return 0;
6aa8b732
AK		 2730}
2731
d462b819 2732static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2733{
2734 int cpu = raw_smp_processor_id();
d462b819 2735 struct loaded_vmcs *v, *n;
543e4243 2736
d462b819
NHE		 2737 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2738 loaded_vmcss_on_cpu_link)
2739 __loaded_vmcs_clear(v);
543e4243
AK		 2740}
2741
710ff4a8
EH		 2742
2743/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2744 * tricks.
2745 */
2746static void kvm_cpu_vmxoff(void)
6aa8b732 2747{
4ecac3fd 2748 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2749}
2750
710ff4a8
EH		 2751static void hardware_disable(void *garbage)
2752{
4610c9cc 2753 if (vmm_exclusive) {
d462b819 2754 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2755 kvm_cpu_vmxoff();
2756 }
7725b894 2757 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2758}
2759
1c3d14fe 2760static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2761 u32 msr, u32 *result)
1c3d14fe
YS		 2762{
2763 u32 vmx_msr_low, vmx_msr_high;
2764 u32 ctl = ctl_min | ctl_opt;
2765
2766 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2767
2768 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2769 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2770
2771 /* Ensure minimum (required) set of control bits are supported. */
2772 if (ctl_min & ~ctl)
002c7f7c 2773 return -EIO;
1c3d14fe
YS		 2774
2775 *result = ctl;
2776 return 0;
2777}
2778
110312c8
AK		 2779static __init bool allow_1_setting(u32 msr, u32 ctl)
2780{
2781 u32 vmx_msr_low, vmx_msr_high;
2782
2783 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2784 return vmx_msr_high & ctl;
2785}
2786
002c7f7c 2787static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2788{
2789 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2790 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2791 u32 _pin_based_exec_control = 0;
2792 u32 _cpu_based_exec_control = 0;
f78e0e2e 2793 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2794 u32 _vmexit_control = 0;
2795 u32 _vmentry_control = 0;
2796
10166744 2797 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2798#ifdef CONFIG_X86_64
2799 CPU_BASED_CR8_LOAD_EXITING |
2800 CPU_BASED_CR8_STORE_EXITING |
2801#endif
d56f546d
SY		 2802 CPU_BASED_CR3_LOAD_EXITING |
2803 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2804 CPU_BASED_USE_IO_BITMAPS |
2805 CPU_BASED_MOV_DR_EXITING |
a7052897 2806 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2807 CPU_BASED_MWAIT_EXITING |
2808 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2809 CPU_BASED_INVLPG_EXITING |
2810 CPU_BASED_RDPMC_EXITING;
443381a8 2811
f78e0e2e 2812 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2813 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2814 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2815 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2816 &_cpu_based_exec_control) < 0)
002c7f7c 2817 return -EIO;
6e5d865c
YS		 2818#ifdef CONFIG_X86_64
2819 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2820 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2821 ~CPU_BASED_CR8_STORE_EXITING;
2822#endif
f78e0e2e 2823 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2824 min2 = 0;
2825 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2826 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2827 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2828 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2829 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2830 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2831 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2832 SECONDARY_EXEC_RDTSCP |
83d4c286 2833 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2834 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2835 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2836 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2837 if (adjust_vmx_controls(min2, opt2,
2838 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2839 &_cpu_based_2nd_exec_control) < 0)
2840 return -EIO;
2841 }
2842#ifndef CONFIG_X86_64
2843 if (!(_cpu_based_2nd_exec_control &
2844 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2845 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2846#endif
83d4c286
YZ		 2847
2848 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2849 _cpu_based_2nd_exec_control &= ~(
8d14695f 2850 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2851 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2852 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2853
d56f546d 2854 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2855 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2856 enabled */
5fff7d27
GN		 2857 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2858 CPU_BASED_CR3_STORE_EXITING |
2859 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2860 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2861 vmx_capability.ept, vmx_capability.vpid);
2862 }
1c3d14fe
YS		 2863
2864 min = 0;
2865#ifdef CONFIG_X86_64
2866 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2867#endif
a547c6db
YZ		 2868 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2869 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2870 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2871 &_vmexit_control) < 0)
002c7f7c 2872 return -EIO;
1c3d14fe 2873
01e439be
YZ		 2874 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2875 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2876 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2877 &_pin_based_exec_control) < 0)
2878 return -EIO;
2879
2880 if (!(_cpu_based_2nd_exec_control &
2881 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2882 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2883 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2884
468d472f
SY		 2885 min = 0;
2886 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2887 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2888 &_vmentry_control) < 0)
002c7f7c 2889 return -EIO;
6aa8b732 2890
c68876fd 2891 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2892
2893 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2894 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2895 return -EIO;
1c3d14fe
YS		 2896
2897#ifdef CONFIG_X86_64
2898 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2899 if (vmx_msr_high & (1u<<16))
002c7f7c 2900 return -EIO;
1c3d14fe
YS		 2901#endif
2902
2903 /* Require Write-Back (WB) memory type for VMCS accesses. */
2904 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2905 return -EIO;
1c3d14fe 2906
002c7f7c
YS		 2907 vmcs_conf->size = vmx_msr_high & 0x1fff;
2908 vmcs_conf->order = get_order(vmcs_config.size);
2909 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2910
002c7f7c
YS		 2911 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2912 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2913 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2914 vmcs_conf->vmexit_ctrl = _vmexit_control;
2915 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2916
110312c8
AK		 2917 cpu_has_load_ia32_efer =
2918 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2919 VM_ENTRY_LOAD_IA32_EFER)
2920 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2921 VM_EXIT_LOAD_IA32_EFER);
2922
8bf00a52
GN		 2923 cpu_has_load_perf_global_ctrl =
2924 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2925 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2926 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2927 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2928
2929 /*
2930 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2931 * but due to arrata below it can't be used. Workaround is to use
2932 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2933 *
2934 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2935 *
2936 * AAK155 (model 26)
2937 * AAP115 (model 30)
2938 * AAT100 (model 37)
2939 * BC86,AAY89,BD102 (model 44)
2940 * BA97 (model 46)
2941 *
2942 */
2943 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2944 switch (boot_cpu_data.x86_model) {
2945 case 26:
2946 case 30:
2947 case 37:
2948 case 44:
2949 case 46:
2950 cpu_has_load_perf_global_ctrl = false;
2951 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2952 "does not work properly. Using workaround\n");
2953 break;
2954 default:
2955 break;
2956 }
2957 }
2958
1c3d14fe 2959 return 0;
c68876fd 2960}
6aa8b732
AK		 2961
2962static struct vmcs *alloc_vmcs_cpu(int cpu)
2963{
2964 int node = cpu_to_node(cpu);
2965 struct page *pages;
2966 struct vmcs *vmcs;
2967
6484eb3e 2968 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2969 if (!pages)
2970 return NULL;
2971 vmcs = page_address(pages);
1c3d14fe
YS		 2972 memset(vmcs, 0, vmcs_config.size);
2973 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2974 return vmcs;
2975}
2976
2977static struct vmcs *alloc_vmcs(void)
2978{
d3b2c338 2979 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2980}
2981
2982static void free_vmcs(struct vmcs *vmcs)
2983{
1c3d14fe 2984 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2985}
2986
d462b819
NHE		 2987/*
2988 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2989 */
2990static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2991{
2992 if (!loaded_vmcs->vmcs)
2993 return;
2994 loaded_vmcs_clear(loaded_vmcs);
2995 free_vmcs(loaded_vmcs->vmcs);
2996 loaded_vmcs->vmcs = NULL;
2997}
2998
39959588 2999static void free_kvm_area(void)
6aa8b732
AK		 3000{
3001 int cpu;
3002
3230bb47 3003 for_each_possible_cpu(cpu) {
6aa8b732 3004 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3005 per_cpu(vmxarea, cpu) = NULL;
3006 }
6aa8b732
AK		 3007}
3008
6aa8b732
AK		 3009static __init int alloc_kvm_area(void)
3010{
3011 int cpu;
3012
3230bb47 3013 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3014 struct vmcs *vmcs;
3015
3016 vmcs = alloc_vmcs_cpu(cpu);
3017 if (!vmcs) {
3018 free_kvm_area();
3019 return -ENOMEM;
3020 }
3021
3022 per_cpu(vmxarea, cpu) = vmcs;
3023 }
3024 return 0;
3025}
3026
3027static __init int hardware_setup(void)
3028{
002c7f7c
YS		 3029 if (setup_vmcs_config(&vmcs_config) < 0)
3030 return -EIO;
50a37eb4
JR		 3031
3032 if (boot_cpu_has(X86_FEATURE_NX))
3033 kvm_enable_efer_bits(EFER_NX);
3034
93ba03c2
SY		 3035 if (!cpu_has_vmx_vpid())
3036 enable_vpid = 0;
abc4fc58
AG		 3037 if (!cpu_has_vmx_shadow_vmcs())
3038 enable_shadow_vmcs = 0;
93ba03c2 3039
4bc9b982
SY		 3040 if (!cpu_has_vmx_ept() ||
3041 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3042 enable_ept = 0;
3a624e29 3043 enable_unrestricted_guest = 0;
83c3a331 3044 enable_ept_ad_bits = 0;
3a624e29
NK		 3045 }
3046
83c3a331
XH		 3047 if (!cpu_has_vmx_ept_ad_bits())
3048 enable_ept_ad_bits = 0;
3049
3a624e29
NK		 3050 if (!cpu_has_vmx_unrestricted_guest())
3051 enable_unrestricted_guest = 0;
93ba03c2
SY		 3052
3053 if (!cpu_has_vmx_flexpriority())
3054 flexpriority_enabled = 0;
3055
95ba8273
GN		 3056 if (!cpu_has_vmx_tpr_shadow())
3057 kvm_x86_ops->update_cr8_intercept = NULL;
3058
54dee993
MT		 3059 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3060 kvm_disable_largepages();
3061
4b8d54f9
ZE		 3062 if (!cpu_has_vmx_ple())
3063 ple_gap = 0;
3064
01e439be
YZ		 3065 if (!cpu_has_vmx_apicv())
3066 enable_apicv = 0;
c7c9c56c 3067
01e439be 3068 if (enable_apicv)
c7c9c56c 3069 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3070 else {
c7c9c56c 3071 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3072 kvm_x86_ops->deliver_posted_interrupt = NULL;
3073 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3074 }
83d4c286 3075
b87a51ae
NHE		 3076 if (nested)
3077 nested_vmx_setup_ctls_msrs();
3078
6aa8b732
AK		 3079 return alloc_kvm_area();
3080}
3081
3082static __exit void hardware_unsetup(void)
3083{
3084 free_kvm_area();
3085}
3086
14168786
GN		 3087static bool emulation_required(struct kvm_vcpu *vcpu)
3088{
3089 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3090}
3091
91b0aa2c 3092static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3093 struct kvm_segment *save)
6aa8b732 3094{
d99e4152
GN		 3095 if (!emulate_invalid_guest_state) {
3096 /*
3097 * CS and SS RPL should be equal during guest entry according
3098 * to VMX spec, but in reality it is not always so. Since vcpu
3099 * is in the middle of the transition from real mode to
3100 * protected mode it is safe to assume that RPL 0 is a good
3101 * default value.
3102 */
3103 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3104 save->selector &= ~SELECTOR_RPL_MASK;
3105 save->dpl = save->selector & SELECTOR_RPL_MASK;
3106 save->s = 1;
6aa8b732 3107 }
d99e4152 3108 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3109}
3110
3111static void enter_pmode(struct kvm_vcpu *vcpu)
3112{
3113 unsigned long flags;
a89a8fb9 3114 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3115
d99e4152
GN		 3116 /*
3117 * Update real mode segment cache. It may be not up-to-date if sement
3118 * register was written while vcpu was in a guest mode.
3119 */
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3126
7ffd92c5 3127 vmx->rmode.vm86_active = 0;
6aa8b732 3128
2fb92db1
AK		 3129 vmx_segment_cache_clear(vmx);
3130
f5f7b2fe 3131 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3132
3133 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3134 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3135 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3136 vmcs_writel(GUEST_RFLAGS, flags);
3137
66aee91a
RR		 3138 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3139 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3140
3141 update_exception_bitmap(vcpu);
3142
91b0aa2c
GN		 3143 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3144 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3145 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3146 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3147 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3148 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3149
3150 /* CPL is always 0 when CPU enters protected mode */
3151 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3152 vmx->cpl = 0;
6aa8b732
AK		 3153}
3154
f5f7b2fe 3155static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3156{
772e0318 3157 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3158 struct kvm_segment var = *save;
3159
3160 var.dpl = 0x3;
3161 if (seg == VCPU_SREG_CS)
3162 var.type = 0x3;
3163
3164 if (!emulate_invalid_guest_state) {
3165 var.selector = var.base >> 4;
3166 var.base = var.base & 0xffff0;
3167 var.limit = 0xffff;
3168 var.g = 0;
3169 var.db = 0;
3170 var.present = 1;
3171 var.s = 1;
3172 var.l = 0;
3173 var.unusable = 0;
3174 var.type = 0x3;
3175 var.avl = 0;
3176 if (save->base & 0xf)
3177 printk_once(KERN_WARNING "kvm: segment base is not "
3178 "paragraph aligned when entering "
3179 "protected mode (seg=%d)", seg);
3180 }
6aa8b732 3181
d99e4152
GN		 3182 vmcs_write16(sf->selector, var.selector);
3183 vmcs_write32(sf->base, var.base);
3184 vmcs_write32(sf->limit, var.limit);
3185 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3186}
3187
3188static void enter_rmode(struct kvm_vcpu *vcpu)
3189{
3190 unsigned long flags;
a89a8fb9 3191 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3192
f5f7b2fe
AK		 3193 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3194 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3195 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3196 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3198 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3200
7ffd92c5 3201 vmx->rmode.vm86_active = 1;
6aa8b732 3202
776e58ea
GN		 3203 /*
3204 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3205 * vcpu. Warn the user that an update is overdue.
776e58ea 3206 */
4918c6ca 3207 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3208 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3209 "called before entering vcpu\n");
776e58ea 3210
2fb92db1
AK		 3211 vmx_segment_cache_clear(vmx);
3212
4918c6ca 3213 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3214 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3215 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3216
3217 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3218 vmx->rmode.save_rflags = flags;
6aa8b732 3219
053de044 3220 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3221
3222 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3223 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3224 update_exception_bitmap(vcpu);
3225
d99e4152
GN		 3226 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3227 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3228 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3229 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3230 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3231 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3232
8668a3c4 3233 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3234}
3235
401d10de
AS		 3236static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3237{
3238 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3239 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3240
3241 if (!msr)
3242 return;
401d10de 3243
44ea2b17
AK		 3244 /*
3245 * Force kernel_gs_base reloading before EFER changes, as control
3246 * of this msr depends on is_long_mode().
3247 */
3248 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3249 vcpu->arch.efer = efer;
401d10de 3250 if (efer & EFER_LMA) {
2961e876 3251 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3252 msr->data = efer;
3253 } else {
2961e876 3254 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3255
3256 msr->data = efer & ~EFER_LME;
3257 }
3258 setup_msrs(vmx);
3259}
3260
05b3e0c2 3261#ifdef CONFIG_X86_64
6aa8b732
AK		 3262
3263static void enter_lmode(struct kvm_vcpu *vcpu)
3264{
3265 u32 guest_tr_ar;
3266
2fb92db1
AK		 3267 vmx_segment_cache_clear(to_vmx(vcpu));
3268
6aa8b732
AK		 3269 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3270 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3271 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3272 __func__);
6aa8b732
AK		 3273 vmcs_write32(GUEST_TR_AR_BYTES,
3274 (guest_tr_ar & ~AR_TYPE_MASK)
3275 | AR_TYPE_BUSY_64_TSS);
3276 }
da38f438 3277 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3278}
3279
3280static void exit_lmode(struct kvm_vcpu *vcpu)
3281{
2961e876 3282 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3283 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3284}
3285
3286#endif
3287
2384d2b3
SY		 3288static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3289{
b9d762fa 3290 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3291 if (enable_ept) {
3292 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3293 return;
4e1096d2 3294 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3295 }
2384d2b3
SY		 3296}
3297
e8467fda
AK		 3298static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3299{
3300 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3301
3302 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3303 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3304}
3305
aff48baa
AK		 3306static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3307{
3308 if (enable_ept && is_paging(vcpu))
3309 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3310 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3311}
3312
25c4c276 3313static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3314{
fc78f519
AK		 3315 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3316
3317 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3318 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3319}
3320
1439442c
SY		 3321static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3322{
d0d538b9
GN		 3323 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3324
6de4f3ad
AK		 3325 if (!test_bit(VCPU_EXREG_PDPTR,
3326 (unsigned long *)&vcpu->arch.regs_dirty))
3327 return;
3328
1439442c 3329 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3330 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3331 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3332 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3333 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3334 }
3335}
3336
8f5d549f
AK		 3337static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3338{
d0d538b9
GN		 3339 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3340
8f5d549f 3341 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3342 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3343 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3344 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3345 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3346 }
6de4f3ad
AK		 3347
3348 __set_bit(VCPU_EXREG_PDPTR,
3349 (unsigned long *)&vcpu->arch.regs_avail);
3350 __set_bit(VCPU_EXREG_PDPTR,
3351 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3352}
3353
5e1746d6 3354static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3355
3356static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3357 unsigned long cr0,
3358 struct kvm_vcpu *vcpu)
3359{
5233dd51
MT		 3360 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3361 vmx_decache_cr3(vcpu);
1439442c
SY		 3362 if (!(cr0 & X86_CR0_PG)) {
3363 /* From paging/starting to nonpaging */
3364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3365 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3366 (CPU_BASED_CR3_LOAD_EXITING |
3367 CPU_BASED_CR3_STORE_EXITING));
3368 vcpu->arch.cr0 = cr0;
fc78f519 3369 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3370 } else if (!is_paging(vcpu)) {
3371 /* From nonpaging to paging */
3372 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3373 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3374 ~(CPU_BASED_CR3_LOAD_EXITING |
3375 CPU_BASED_CR3_STORE_EXITING));
3376 vcpu->arch.cr0 = cr0;
fc78f519 3377 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3378 }
95eb84a7
SY		 3379
3380 if (!(cr0 & X86_CR0_WP))
3381 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3382}
3383
6aa8b732
AK		 3384static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3385{
7ffd92c5 3386 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3387 unsigned long hw_cr0;
3388
5037878e 3389 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3390 if (enable_unrestricted_guest)
5037878e 3391 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3392 else {
5037878e 3393 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3394
218e763f
GN		 3395 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3396 enter_pmode(vcpu);
6aa8b732 3397
218e763f
GN		 3398 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3399 enter_rmode(vcpu);
3400 }
6aa8b732 3401
05b3e0c2 3402#ifdef CONFIG_X86_64
f6801dff 3403 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3404 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3405 enter_lmode(vcpu);
707d92fa 3406 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3407 exit_lmode(vcpu);
3408 }
3409#endif
3410
089d034e 3411 if (enable_ept)
1439442c
SY		 3412 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3413
02daab21 3414 if (!vcpu->fpu_active)
81231c69 3415 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3416
6aa8b732 3417 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3418 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3419 vcpu->arch.cr0 = cr0;
14168786
GN		 3420
3421 /* depends on vcpu->arch.cr0 to be set to a new value */
3422 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3423}
3424
1439442c
SY		 3425static u64 construct_eptp(unsigned long root_hpa)
3426{
3427 u64 eptp;
3428
3429 /* TODO write the value reading from MSR */
3430 eptp = VMX_EPT_DEFAULT_MT |
3431 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3432 if (enable_ept_ad_bits)
3433 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3434 eptp |= (root_hpa & PAGE_MASK);
3435
3436 return eptp;
3437}
3438
6aa8b732
AK		 3439static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3440{
1439442c
SY		 3441 unsigned long guest_cr3;
3442 u64 eptp;
3443
3444 guest_cr3 = cr3;
089d034e 3445 if (enable_ept) {
1439442c
SY		 3446 eptp = construct_eptp(cr3);
3447 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3448 if (is_paging(vcpu) || is_guest_mode(vcpu))
3449 guest_cr3 = kvm_read_cr3(vcpu);
3450 else
3451 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3452 ept_load_pdptrs(vcpu);
1439442c
SY		 3453 }
3454
2384d2b3 3455 vmx_flush_tlb(vcpu);
1439442c 3456 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3457}
3458
5e1746d6 3459static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3460{
7ffd92c5 3461 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3462 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3463
5e1746d6
NHE		 3464 if (cr4 & X86_CR4_VMXE) {
3465 /*
3466 * To use VMXON (and later other VMX instructions), a guest
3467 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3468 * So basically the check on whether to allow nested VMX
3469 * is here.
3470 */
3471 if (!nested_vmx_allowed(vcpu))
3472 return 1;
1a0d74e6
JK		 3473 }
3474 if (to_vmx(vcpu)->nested.vmxon &&
3475 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3476 return 1;
3477
ad312c7c 3478 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3479 if (enable_ept) {
3480 if (!is_paging(vcpu)) {
3481 hw_cr4 &= ~X86_CR4_PAE;
3482 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3483 /*
3484 * SMEP is disabled if CPU is in non-paging mode in
3485 * hardware. However KVM always uses paging mode to
3486 * emulate guest non-paging mode with TDP.
3487 * To emulate this behavior, SMEP needs to be manually
3488 * disabled when guest switches to non-paging mode.
3489 */
3490 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3491 } else if (!(cr4 & X86_CR4_PAE)) {
3492 hw_cr4 &= ~X86_CR4_PAE;
3493 }
3494 }
1439442c
SY		 3495
3496 vmcs_writel(CR4_READ_SHADOW, cr4);
3497 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3498 return 0;
6aa8b732
AK		 3499}
3500
6aa8b732
AK		 3501static void vmx_get_segment(struct kvm_vcpu *vcpu,
3502 struct kvm_segment *var, int seg)
3503{
a9179499 3504 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3505 u32 ar;
3506
c6ad1153 3507 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3508 *var = vmx->rmode.segs[seg];
a9179499 3509 if (seg == VCPU_SREG_TR
2fb92db1 3510 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3511 return;
1390a28b
AK		 3512 var->base = vmx_read_guest_seg_base(vmx, seg);
3513 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3514 return;
a9179499 3515 }
2fb92db1
AK		 3516 var->base = vmx_read_guest_seg_base(vmx, seg);
3517 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3518 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3519 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3520 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3521 var->type = ar & 15;
3522 var->s = (ar >> 4) & 1;
3523 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3524 /*
3525 * Some userspaces do not preserve unusable property. Since usable
3526 * segment has to be present according to VMX spec we can use present
3527 * property to amend userspace bug by making unusable segment always
3528 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3529 * segment as unusable.
3530 */
3531 var->present = !var->unusable;
6aa8b732
AK		 3532 var->avl = (ar >> 12) & 1;
3533 var->l = (ar >> 13) & 1;
3534 var->db = (ar >> 14) & 1;
3535 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3536}
3537
a9179499
AK		 3538static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3539{
a9179499
AK		 3540 struct kvm_segment s;
3541
3542 if (to_vmx(vcpu)->rmode.vm86_active) {
3543 vmx_get_segment(vcpu, &s, seg);
3544 return s.base;
3545 }
2fb92db1 3546 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3547}
3548
b09408d0 3549static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3550{
b09408d0
MT		 3551 struct vcpu_vmx *vmx = to_vmx(vcpu);
3552
3eeb3288 3553 if (!is_protmode(vcpu))
2e4d2653
IE		 3554 return 0;
3555
f4c63e5d
AK		 3556 if (!is_long_mode(vcpu)
3557 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3558 return 3;
3559
69c73028
AK		 3560 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3561 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3562 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3563 }
d881e6f6
AK		 3564
3565 return vmx->cpl;
69c73028
AK		 3566}
3567
3568
653e3108 3569static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3570{
6aa8b732
AK		 3571 u32 ar;
3572
f0495f9b 3573 if (var->unusable || !var->present)
6aa8b732
AK		 3574 ar = 1 << 16;
3575 else {
3576 ar = var->type & 15;
3577 ar |= (var->s & 1) << 4;
3578 ar |= (var->dpl & 3) << 5;
3579 ar |= (var->present & 1) << 7;
3580 ar |= (var->avl & 1) << 12;
3581 ar |= (var->l & 1) << 13;
3582 ar |= (var->db & 1) << 14;
3583 ar |= (var->g & 1) << 15;
3584 }
653e3108
AK		 3585
3586 return ar;
3587}
3588
3589static void vmx_set_segment(struct kvm_vcpu *vcpu,
3590 struct kvm_segment *var, int seg)
3591{
7ffd92c5 3592 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3593 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3594
2fb92db1 3595 vmx_segment_cache_clear(vmx);
2f143240
GN		 3596 if (seg == VCPU_SREG_CS)
3597 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3598
1ecd50a9
GN		 3599 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3600 vmx->rmode.segs[seg] = *var;
3601 if (seg == VCPU_SREG_TR)
3602 vmcs_write16(sf->selector, var->selector);
3603 else if (var->s)
3604 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3605 goto out;
653e3108 3606 }
1ecd50a9 3607
653e3108
AK		 3608 vmcs_writel(sf->base, var->base);
3609 vmcs_write32(sf->limit, var->limit);
3610 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3611
3612 /*
3613 * Fix the "Accessed" bit in AR field of segment registers for older
3614 * qemu binaries.
3615 * IA32 arch specifies that at the time of processor reset the
3616 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3617 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3618 * state vmexit when "unrestricted guest" mode is turned on.
3619 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3620 * tree. Newer qemu binaries with that qemu fix would not need this
3621 * kvm hack.
3622 */
3623 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3624 var->type |= 0x1; /* Accessed */
3a624e29 3625
f924d66d 3626 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3627
3628out:
14168786 3629 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3630}
3631
6aa8b732
AK		 3632static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3633{
2fb92db1 3634 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3635
3636 *db = (ar >> 14) & 1;
3637 *l = (ar >> 13) & 1;
3638}
3639
89a27f4d 3640static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3641{
89a27f4d
GN		 3642 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3643 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3644}
3645
89a27f4d 3646static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3647{
89a27f4d
GN		 3648 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3649 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3650}
3651
89a27f4d 3652static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3653{
89a27f4d
GN		 3654 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3655 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3656}
3657
89a27f4d 3658static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3659{
89a27f4d
GN		 3660 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3661 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3662}
3663
648dfaa7
MG		 3664static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3665{
3666 struct kvm_segment var;
3667 u32 ar;
3668
3669 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3670 var.dpl = 0x3;
0647f4aa
GN		 3671 if (seg == VCPU_SREG_CS)
3672 var.type = 0x3;
648dfaa7
MG		 3673 ar = vmx_segment_access_rights(&var);
3674
3675 if (var.base != (var.selector << 4))
3676 return false;
89efbed0 3677 if (var.limit != 0xffff)
648dfaa7 3678 return false;
07f42f5f 3679 if (ar != 0xf3)
648dfaa7
MG		 3680 return false;
3681
3682 return true;
3683}
3684
3685static bool code_segment_valid(struct kvm_vcpu *vcpu)
3686{
3687 struct kvm_segment cs;
3688 unsigned int cs_rpl;
3689
3690 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3691 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3692
1872a3f4
AK		 3693 if (cs.unusable)
3694 return false;
648dfaa7
MG		 3695 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3696 return false;
3697 if (!cs.s)
3698 return false;
1872a3f4 3699 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3700 if (cs.dpl > cs_rpl)
3701 return false;
1872a3f4 3702 } else {
648dfaa7
MG		 3703 if (cs.dpl != cs_rpl)
3704 return false;
3705 }
3706 if (!cs.present)
3707 return false;
3708
3709 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3710 return true;
3711}
3712
3713static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3714{
3715 struct kvm_segment ss;
3716 unsigned int ss_rpl;
3717
3718 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3719 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3720
1872a3f4
AK		 3721 if (ss.unusable)
3722 return true;
3723 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3724 return false;
3725 if (!ss.s)
3726 return false;
3727 if (ss.dpl != ss_rpl) /* DPL != RPL */
3728 return false;
3729 if (!ss.present)
3730 return false;
3731
3732 return true;
3733}
3734
3735static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3736{
3737 struct kvm_segment var;
3738 unsigned int rpl;
3739
3740 vmx_get_segment(vcpu, &var, seg);
3741 rpl = var.selector & SELECTOR_RPL_MASK;
3742
1872a3f4
AK		 3743 if (var.unusable)
3744 return true;
648dfaa7
MG		 3745 if (!var.s)
3746 return false;
3747 if (!var.present)
3748 return false;
3749 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3750 if (var.dpl < rpl) /* DPL < RPL */
3751 return false;
3752 }
3753
3754 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3755 * rights flags
3756 */
3757 return true;
3758}
3759
3760static bool tr_valid(struct kvm_vcpu *vcpu)
3761{
3762 struct kvm_segment tr;
3763
3764 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3765
1872a3f4
AK		 3766 if (tr.unusable)
3767 return false;
648dfaa7
MG		 3768 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3769 return false;
1872a3f4 3770 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3771 return false;
3772 if (!tr.present)
3773 return false;
3774
3775 return true;
3776}
3777
3778static bool ldtr_valid(struct kvm_vcpu *vcpu)
3779{
3780 struct kvm_segment ldtr;
3781
3782 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3783
1872a3f4
AK		 3784 if (ldtr.unusable)
3785 return true;
648dfaa7
MG		 3786 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3787 return false;
3788 if (ldtr.type != 2)
3789 return false;
3790 if (!ldtr.present)
3791 return false;
3792
3793 return true;
3794}
3795
3796static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3797{
3798 struct kvm_segment cs, ss;
3799
3800 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3801 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3802
3803 return ((cs.selector & SELECTOR_RPL_MASK) ==
3804 (ss.selector & SELECTOR_RPL_MASK));
3805}
3806
3807/*
3808 * Check if guest state is valid. Returns true if valid, false if
3809 * not.
3810 * We assume that registers are always usable
3811 */
3812static bool guest_state_valid(struct kvm_vcpu *vcpu)
3813{
c5e97c80
GN		 3814 if (enable_unrestricted_guest)
3815 return true;
3816
648dfaa7 3817 /* real mode guest state checks */
f13882d8 3818 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3819 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3820 return false;
3821 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3822 return false;
3823 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3824 return false;
3825 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3826 return false;
3827 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3828 return false;
3829 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3830 return false;
3831 } else {
3832 /* protected mode guest state checks */
3833 if (!cs_ss_rpl_check(vcpu))
3834 return false;
3835 if (!code_segment_valid(vcpu))
3836 return false;
3837 if (!stack_segment_valid(vcpu))
3838 return false;
3839 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3840 return false;
3841 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3842 return false;
3843 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3844 return false;
3845 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3846 return false;
3847 if (!tr_valid(vcpu))
3848 return false;
3849 if (!ldtr_valid(vcpu))
3850 return false;
3851 }
3852 /* TODO:
3853 * - Add checks on RIP
3854 * - Add checks on RFLAGS
3855 */
3856
3857 return true;
3858}
3859
d77c26fc 3860static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3861{
40dcaa9f 3862 gfn_t fn;
195aefde 3863 u16 data = 0;
40dcaa9f 3864 int r, idx, ret = 0;
6aa8b732 3865
40dcaa9f 3866 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3867 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3868 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3869 if (r < 0)
10589a46 3870 goto out;
195aefde 3871 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3872 r = kvm_write_guest_page(kvm, fn++, &data,
3873 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3874 if (r < 0)
10589a46 3875 goto out;
195aefde
IE		 3876 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3877 if (r < 0)
10589a46 3878 goto out;
195aefde
IE		 3879 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3880 if (r < 0)
10589a46 3881 goto out;
195aefde 3882 data = ~0;
10589a46
MT		 3883 r = kvm_write_guest_page(kvm, fn, &data,
3884 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3885 sizeof(u8));
195aefde 3886 if (r < 0)
10589a46
MT		 3887 goto out;
3888
3889 ret = 1;
3890out:
40dcaa9f 3891 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3892 return ret;
6aa8b732
AK		 3893}
3894
b7ebfb05
SY		 3895static int init_rmode_identity_map(struct kvm *kvm)
3896{
40dcaa9f 3897 int i, idx, r, ret;
b7ebfb05
SY		 3898 pfn_t identity_map_pfn;
3899 u32 tmp;
3900
089d034e 3901 if (!enable_ept)
b7ebfb05
SY		 3902 return 1;
3903 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3904 printk(KERN_ERR "EPT: identity-mapping pagetable "
3905 "haven't been allocated!\n");
3906 return 0;
3907 }
3908 if (likely(kvm->arch.ept_identity_pagetable_done))
3909 return 1;
3910 ret = 0;
b927a3ce 3911 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3912 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3913 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3914 if (r < 0)
3915 goto out;
3916 /* Set up identity-mapping pagetable for EPT in real mode */
3917 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3918 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3919 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3920 r = kvm_write_guest_page(kvm, identity_map_pfn,
3921 &tmp, i * sizeof(tmp), sizeof(tmp));
3922 if (r < 0)
3923 goto out;
3924 }
3925 kvm->arch.ept_identity_pagetable_done = true;
3926 ret = 1;
3927out:
40dcaa9f 3928 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3929 return ret;
3930}
3931
6aa8b732
AK		 3932static void seg_setup(int seg)
3933{
772e0318 3934 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3935 unsigned int ar;
6aa8b732
AK		 3936
3937 vmcs_write16(sf->selector, 0);
3938 vmcs_writel(sf->base, 0);
3939 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3940 ar = 0x93;
3941 if (seg == VCPU_SREG_CS)
3942 ar |= 0x08; /* code segment */
3a624e29
NK		 3943
3944 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3945}
3946
f78e0e2e
SY		 3947static int alloc_apic_access_page(struct kvm *kvm)
3948{
4484141a 3949 struct page *page;
f78e0e2e
SY		 3950 struct kvm_userspace_memory_region kvm_userspace_mem;
3951 int r = 0;
3952
79fac95e 3953 mutex_lock(&kvm->slots_lock);
bfc6d222 3954 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3955 goto out;
3956 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3957 kvm_userspace_mem.flags = 0;
3958 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3959 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3960 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3961 if (r)
3962 goto out;
72dc67a6 3963
4484141a
XG		 3964 page = gfn_to_page(kvm, 0xfee00);
3965 if (is_error_page(page)) {
3966 r = -EFAULT;
3967 goto out;
3968 }
3969
3970 kvm->arch.apic_access_page = page;
f78e0e2e 3971out:
79fac95e 3972 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3973 return r;
3974}
3975
b7ebfb05
SY		 3976static int alloc_identity_pagetable(struct kvm *kvm)
3977{
4484141a 3978 struct page *page;
b7ebfb05
SY		 3979 struct kvm_userspace_memory_region kvm_userspace_mem;
3980 int r = 0;
3981
79fac95e 3982 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3983 if (kvm->arch.ept_identity_pagetable)
3984 goto out;
3985 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3986 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3987 kvm_userspace_mem.guest_phys_addr =
3988 kvm->arch.ept_identity_map_addr;
b7ebfb05 3989 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3990 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3991 if (r)
3992 goto out;
3993
4484141a
XG		 3994 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3995 if (is_error_page(page)) {
3996 r = -EFAULT;
3997 goto out;
3998 }
3999
4000 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4001out:
79fac95e 4002 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4003 return r;
4004}
4005
2384d2b3
SY		 4006static void allocate_vpid(struct vcpu_vmx *vmx)
4007{
4008 int vpid;
4009
4010 vmx->vpid = 0;
919818ab 4011 if (!enable_vpid)
2384d2b3
SY		 4012 return;
4013 spin_lock(&vmx_vpid_lock);
4014 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4015 if (vpid < VMX_NR_VPIDS) {
4016 vmx->vpid = vpid;
4017 __set_bit(vpid, vmx_vpid_bitmap);
4018 }
4019 spin_unlock(&vmx_vpid_lock);
4020}
4021
cdbecfc3
LJ		 4022static void free_vpid(struct vcpu_vmx *vmx)
4023{
4024 if (!enable_vpid)
4025 return;
4026 spin_lock(&vmx_vpid_lock);
4027 if (vmx->vpid != 0)
4028 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4029 spin_unlock(&vmx_vpid_lock);
4030}
4031
8d14695f
YZ		 4032#define MSR_TYPE_R 1
4033#define MSR_TYPE_W 2
4034static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4035 u32 msr, int type)
25c5f225 4036{
3e7c73e9 4037 int f = sizeof(unsigned long);
25c5f225
SY		 4038
4039 if (!cpu_has_vmx_msr_bitmap())
4040 return;
4041
4042 /*
4043 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4044 * have the write-low and read-high bitmap offsets the wrong way round.
4045 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4046 */
25c5f225 4047 if (msr <= 0x1fff) {
8d14695f
YZ		 4048 if (type & MSR_TYPE_R)
4049 /* read-low */
4050 __clear_bit(msr, msr_bitmap + 0x000 / f);
4051
4052 if (type & MSR_TYPE_W)
4053 /* write-low */
4054 __clear_bit(msr, msr_bitmap + 0x800 / f);
4055
25c5f225
SY		 4056 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4057 msr &= 0x1fff;
8d14695f
YZ		 4058 if (type & MSR_TYPE_R)
4059 /* read-high */
4060 __clear_bit(msr, msr_bitmap + 0x400 / f);
4061
4062 if (type & MSR_TYPE_W)
4063 /* write-high */
4064 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4065
4066 }
4067}
4068
4069static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4070 u32 msr, int type)
4071{
4072 int f = sizeof(unsigned long);
4073
4074 if (!cpu_has_vmx_msr_bitmap())
4075 return;
4076
4077 /*
4078 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4079 * have the write-low and read-high bitmap offsets the wrong way round.
4080 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4081 */
4082 if (msr <= 0x1fff) {
4083 if (type & MSR_TYPE_R)
4084 /* read-low */
4085 __set_bit(msr, msr_bitmap + 0x000 / f);
4086
4087 if (type & MSR_TYPE_W)
4088 /* write-low */
4089 __set_bit(msr, msr_bitmap + 0x800 / f);
4090
4091 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4092 msr &= 0x1fff;
4093 if (type & MSR_TYPE_R)
4094 /* read-high */
4095 __set_bit(msr, msr_bitmap + 0x400 / f);
4096
4097 if (type & MSR_TYPE_W)
4098 /* write-high */
4099 __set_bit(msr, msr_bitmap + 0xc00 / f);
4100
25c5f225 4101 }
25c5f225
SY		 4102}
4103
5897297b
AK		 4104static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4105{
4106 if (!longmode_only)
8d14695f
YZ		 4107 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4108 msr, MSR_TYPE_R | MSR_TYPE_W);
4109 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4110 msr, MSR_TYPE_R | MSR_TYPE_W);
4111}
4112
4113static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4114{
4115 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4116 msr, MSR_TYPE_R);
4117 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4118 msr, MSR_TYPE_R);
4119}
4120
4121static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4122{
4123 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4124 msr, MSR_TYPE_R);
4125 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4126 msr, MSR_TYPE_R);
4127}
4128
4129static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4130{
4131 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4132 msr, MSR_TYPE_W);
4133 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4134 msr, MSR_TYPE_W);
5897297b
AK		 4135}
4136
01e439be
YZ		 4137static int vmx_vm_has_apicv(struct kvm *kvm)
4138{
4139 return enable_apicv && irqchip_in_kernel(kvm);
4140}
4141
a20ed54d
YZ		 4142/*
4143 * Send interrupt to vcpu via posted interrupt way.
4144 * 1. If target vcpu is running(non-root mode), send posted interrupt
4145 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4146 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4147 * interrupt from PIR in next vmentry.
4148 */
4149static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4150{
4151 struct vcpu_vmx *vmx = to_vmx(vcpu);
4152 int r;
4153
4154 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4155 return;
4156
4157 r = pi_test_and_set_on(&vmx->pi_desc);
4158 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4159#ifdef CONFIG_SMP
a20ed54d
YZ		 4160 if (!r && (vcpu->mode == IN_GUEST_MODE))
4161 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4162 POSTED_INTR_VECTOR);
4163 else
6ffbbbba 4164#endif
a20ed54d
YZ		 4165 kvm_vcpu_kick(vcpu);
4166}
4167
4168static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4169{
4170 struct vcpu_vmx *vmx = to_vmx(vcpu);
4171
4172 if (!pi_test_and_clear_on(&vmx->pi_desc))
4173 return;
4174
4175 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4176}
4177
4178static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4179{
4180 return;
4181}
4182
a3a8ff8e
NHE		 4183/*
4184 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4185 * will not change in the lifetime of the guest.
4186 * Note that host-state that does change is set elsewhere. E.g., host-state
4187 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4188 */
a547c6db 4189static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4190{
4191 u32 low32, high32;
4192 unsigned long tmpl;
4193 struct desc_ptr dt;
4194
b1a74bf8 4195 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4196 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4197 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4198
4199 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4200#ifdef CONFIG_X86_64
4201 /*
4202 * Load null selectors, so we can avoid reloading them in
4203 * __vmx_load_host_state(), in case userspace uses the null selectors
4204 * too (the expected case).
4205 */
4206 vmcs_write16(HOST_DS_SELECTOR, 0);
4207 vmcs_write16(HOST_ES_SELECTOR, 0);
4208#else
a3a8ff8e
NHE		 4209 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4210 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4211#endif
a3a8ff8e
NHE		 4212 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4213 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4214
4215 native_store_idt(&dt);
4216 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4217 vmx->host_idt_base = dt.address;
a3a8ff8e 4218
83287ea4 4219 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4220
4221 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4222 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4223 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4224 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4225
4226 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4227 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4228 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4229 }
4230}
4231
bf8179a0
NHE		 4232static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4233{
4234 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4235 if (enable_ept)
4236 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4237 if (is_guest_mode(&vmx->vcpu))
4238 vmx->vcpu.arch.cr4_guest_owned_bits &=
4239 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4240 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4241}
4242
01e439be
YZ		 4243static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4244{
4245 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4246
4247 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4248 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4249 return pin_based_exec_ctrl;
4250}
4251
bf8179a0
NHE		 4252static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4253{
4254 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4255 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4256 exec_control &= ~CPU_BASED_TPR_SHADOW;
4257#ifdef CONFIG_X86_64
4258 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4259 CPU_BASED_CR8_LOAD_EXITING;
4260#endif
4261 }
4262 if (!enable_ept)
4263 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4264 CPU_BASED_CR3_LOAD_EXITING |
4265 CPU_BASED_INVLPG_EXITING;
4266 return exec_control;
4267}
4268
4269static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4270{
4271 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4272 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4273 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4274 if (vmx->vpid == 0)
4275 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4276 if (!enable_ept) {
4277 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4278 enable_unrestricted_guest = 0;
ad756a16
MJ		 4279 /* Enable INVPCID for non-ept guests may cause performance regression. */
4280 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4281 }
4282 if (!enable_unrestricted_guest)
4283 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4284 if (!ple_gap)
4285 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4286 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4287 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4288 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4289 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4290 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4291 (handle_vmptrld).
4292 We can NOT enable shadow_vmcs here because we don't have yet
4293 a current VMCS12
4294 */
4295 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4296 return exec_control;
4297}
4298
ce88decf
XG		 4299static void ept_set_mmio_spte_mask(void)
4300{
4301 /*
4302 * EPT Misconfigurations can be generated if the value of bits 2:0
4303 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4304 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4305 * spte.
4306 */
885032b9 4307 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4308}
4309
6aa8b732
AK		 4310/*
4311 * Sets up the vmcs for emulated real mode.
4312 */
8b9cf98c 4313static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4314{
2e4ce7f5 4315#ifdef CONFIG_X86_64
6aa8b732 4316 unsigned long a;
2e4ce7f5 4317#endif
6aa8b732 4318 int i;
6aa8b732 4319
6aa8b732 4320 /* I/O */
3e7c73e9
AK		 4321 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4322 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4323
4607c2d7
AG		 4324 if (enable_shadow_vmcs) {
4325 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4326 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4327 }
25c5f225 4328 if (cpu_has_vmx_msr_bitmap())
5897297b 4329 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4330
6aa8b732
AK		 4331 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4332
6aa8b732 4333 /* Control */
01e439be 4334 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4335
bf8179a0 4336 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4337
83ff3b9d 4338 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4339 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4340 vmx_secondary_exec_control(vmx));
83ff3b9d 4341 }
f78e0e2e 4342
01e439be 4343 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4344 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4345 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4346 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4347 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4348
4349 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4350
4351 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4352 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4353 }
4354
4b8d54f9
ZE		 4355 if (ple_gap) {
4356 vmcs_write32(PLE_GAP, ple_gap);
4357 vmcs_write32(PLE_WINDOW, ple_window);
4358 }
4359
c3707958
XG		 4360 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4361 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4362 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4363
9581d442
AK		 4364 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4365 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4366 vmx_set_constant_host_state(vmx);
05b3e0c2 4367#ifdef CONFIG_X86_64
6aa8b732
AK		 4368 rdmsrl(MSR_FS_BASE, a);
4369 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4370 rdmsrl(MSR_GS_BASE, a);
4371 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4372#else
4373 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4374 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4375#endif
4376
2cc51560
ED		 4377 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4378 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4379 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4380 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4381 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4382
468d472f 4383 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4384 u32 msr_low, msr_high;
4385 u64 host_pat;
468d472f
SY		 4386 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4387 host_pat = msr_low | ((u64) msr_high << 32);
4388 /* Write the default value follow host pat */
4389 vmcs_write64(GUEST_IA32_PAT, host_pat);
4390 /* Keep arch.pat sync with GUEST_IA32_PAT */
4391 vmx->vcpu.arch.pat = host_pat;
4392 }
4393
6aa8b732
AK		 4394 for (i = 0; i < NR_VMX_MSR; ++i) {
4395 u32 index = vmx_msr_index[i];
4396 u32 data_low, data_high;
a2fa3e9f 4397 int j = vmx->nmsrs;
6aa8b732
AK		 4398
4399 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4400 continue;
432bd6cb
AK		 4401 if (wrmsr_safe(index, data_low, data_high) < 0)
4402 continue;
26bb0981
AK		 4403 vmx->guest_msrs[j].index = i;
4404 vmx->guest_msrs[j].data = 0;
d5696725 4405 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4406 ++vmx->nmsrs;
6aa8b732 4407 }
6aa8b732 4408
2961e876
GN		 4409
4410 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4411
4412 /* 22.2.1, 20.8.1 */
2961e876 4413 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4414
e00c8cf2 4415 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4416 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4417
4418 return 0;
4419}
4420
57f252f2 4421static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4422{
4423 struct vcpu_vmx *vmx = to_vmx(vcpu);
4424 u64 msr;
e00c8cf2 4425
7ffd92c5 4426 vmx->rmode.vm86_active = 0;
e00c8cf2 4427
3b86cd99
JK		 4428 vmx->soft_vnmi_blocked = 0;
4429
ad312c7c 4430 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4431 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4432 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4433 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4434 msr |= MSR_IA32_APICBASE_BSP;
4435 kvm_set_apic_base(&vmx->vcpu, msr);
4436
2fb92db1
AK		 4437 vmx_segment_cache_clear(vmx);
4438
5706be0d 4439 seg_setup(VCPU_SREG_CS);
66450a21 4440 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4441 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4442
4443 seg_setup(VCPU_SREG_DS);
4444 seg_setup(VCPU_SREG_ES);
4445 seg_setup(VCPU_SREG_FS);
4446 seg_setup(VCPU_SREG_GS);
4447 seg_setup(VCPU_SREG_SS);
4448
4449 vmcs_write16(GUEST_TR_SELECTOR, 0);
4450 vmcs_writel(GUEST_TR_BASE, 0);
4451 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4452 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4453
4454 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4455 vmcs_writel(GUEST_LDTR_BASE, 0);
4456 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4457 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4458
4459 vmcs_write32(GUEST_SYSENTER_CS, 0);
4460 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4461 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4462
4463 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4464 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4465
e00c8cf2
AK		 4466 vmcs_writel(GUEST_GDTR_BASE, 0);
4467 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4468
4469 vmcs_writel(GUEST_IDTR_BASE, 0);
4470 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4471
443381a8 4472 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4473 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4474 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4475
e00c8cf2
AK		 4476 /* Special registers */
4477 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4478
4479 setup_msrs(vmx);
4480
6aa8b732
AK		 4481 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4482
f78e0e2e
SY		 4483 if (cpu_has_vmx_tpr_shadow()) {
4484 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4485 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4486 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4487 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4488 vmcs_write32(TPR_THRESHOLD, 0);
4489 }
4490
4491 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4492 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4493 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4494
01e439be
YZ		 4495 if (vmx_vm_has_apicv(vcpu->kvm))
4496 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4497
2384d2b3
SY		 4498 if (vmx->vpid != 0)
4499 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4500
fa40052c 4501 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4502 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4503 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4504 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4505 vmx_fpu_activate(&vmx->vcpu);
4506 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4507
b9d762fa 4508 vpid_sync_context(vmx);
6aa8b732
AK		 4509}
4510
b6f1250e
NHE		 4511/*
4512 * In nested virtualization, check if L1 asked to exit on external interrupts.
4513 * For most existing hypervisors, this will always return true.
4514 */
4515static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4516{
4517 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4518 PIN_BASED_EXT_INTR_MASK;
4519}
4520
ea8ceb83
JK		 4521static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4522{
4523 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4524 PIN_BASED_NMI_EXITING;
4525}
4526
730dca42 4527static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4528{
4529 u32 cpu_based_vm_exec_control;
730dca42
JK		 4530
4531 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4532 /*
4533 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4534 * inject to L1 now because L2 must run. The caller will have
4535 * to make L2 exit right after entry, so we can inject to L1
4536 * more promptly.
b6f1250e 4537 */
730dca42 4538 return -EBUSY;
3b86cd99
JK		 4539
4540 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4541 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4542 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4543 return 0;
3b86cd99
JK		 4544}
4545
03b28f81 4546static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4547{
4548 u32 cpu_based_vm_exec_control;
4549
03b28f81
JK		 4550 if (!cpu_has_virtual_nmis())
4551 return enable_irq_window(vcpu);
4552
4553 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4554 return enable_irq_window(vcpu);
3b86cd99
JK		 4555
4556 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4557 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4558 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4559 return 0;
3b86cd99
JK		 4560}
4561
66fd3f7f 4562static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4563{
9c8cba37 4564 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4565 uint32_t intr;
4566 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4567
229456fc 4568 trace_kvm_inj_virq(irq);
2714d1d3 4569
fa89a817 4570 ++vcpu->stat.irq_injections;
7ffd92c5 4571 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4572 int inc_eip = 0;
4573 if (vcpu->arch.interrupt.soft)
4574 inc_eip = vcpu->arch.event_exit_inst_len;
4575 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4576 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4577 return;
4578 }
66fd3f7f
GN		 4579 intr = irq | INTR_INFO_VALID_MASK;
4580 if (vcpu->arch.interrupt.soft) {
4581 intr |= INTR_TYPE_SOFT_INTR;
4582 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4583 vmx->vcpu.arch.event_exit_inst_len);
4584 } else
4585 intr |= INTR_TYPE_EXT_INTR;
4586 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4587}
4588
f08864b4
SY		 4589static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4590{
66a5a347
JK		 4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
4592
0b6ac343
NHE		 4593 if (is_guest_mode(vcpu))
4594 return;
4595
3b86cd99
JK		 4596 if (!cpu_has_virtual_nmis()) {
4597 /*
4598 * Tracking the NMI-blocked state in software is built upon
4599 * finding the next open IRQ window. This, in turn, depends on
4600 * well-behaving guests: They have to keep IRQs disabled at
4601 * least as long as the NMI handler runs. Otherwise we may
4602 * cause NMI nesting, maybe breaking the guest. But as this is
4603 * highly unlikely, we can live with the residual risk.
4604 */
4605 vmx->soft_vnmi_blocked = 1;
4606 vmx->vnmi_blocked_time = 0;
4607 }
4608
487b391d 4609 ++vcpu->stat.nmi_injections;
9d58b931 4610 vmx->nmi_known_unmasked = false;
7ffd92c5 4611 if (vmx->rmode.vm86_active) {
71f9833b 4612 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4613 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4614 return;
4615 }
f08864b4
SY		 4616 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4617 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4618}
4619
3cfc3092
JK		 4620static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4621{
4622 if (!cpu_has_virtual_nmis())
4623 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4624 if (to_vmx(vcpu)->nmi_known_unmasked)
4625 return false;
c332c83a 4626 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4627}
4628
4629static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4630{
4631 struct vcpu_vmx *vmx = to_vmx(vcpu);
4632
4633 if (!cpu_has_virtual_nmis()) {
4634 if (vmx->soft_vnmi_blocked != masked) {
4635 vmx->soft_vnmi_blocked = masked;
4636 vmx->vnmi_blocked_time = 0;
4637 }
4638 } else {
9d58b931 4639 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4640 if (masked)
4641 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4642 GUEST_INTR_STATE_NMI);
4643 else
4644 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4645 GUEST_INTR_STATE_NMI);
4646 }
4647}
4648
2505dc9f
JK		 4649static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4650{
ea8ceb83
JK		 4651 if (is_guest_mode(vcpu)) {
4652 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4653
4654 if (to_vmx(vcpu)->nested.nested_run_pending)
4655 return 0;
4656 if (nested_exit_on_nmi(vcpu)) {
4657 nested_vmx_vmexit(vcpu);
4658 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4659 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4660 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4661 /*
4662 * The NMI-triggered VM exit counts as injection:
4663 * clear this one and block further NMIs.
4664 */
4665 vcpu->arch.nmi_pending = 0;
4666 vmx_set_nmi_mask(vcpu, true);
4667 return 0;
4668 }
4669 }
4670
2505dc9f
JK		 4671 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4672 return 0;
4673
4674 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4675 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4676 | GUEST_INTR_STATE_NMI));
4677}
4678
78646121
GN		 4679static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4680{
e8457c67 4681 if (is_guest_mode(vcpu)) {
51cfe38e 4682 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4683
4684 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4685 return 0;
e8457c67
JK		 4686 if (nested_exit_on_intr(vcpu)) {
4687 nested_vmx_vmexit(vcpu);
4688 vmcs12->vm_exit_reason =
4689 EXIT_REASON_EXTERNAL_INTERRUPT;
4690 vmcs12->vm_exit_intr_info = 0;
4691 /*
4692 * fall through to normal code, but now in L1, not L2
4693 */
4694 }
b6f1250e
NHE		 4695 }
4696
c4282df9
GN		 4697 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4698 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4699 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4700}
4701
cbc94022
IE		 4702static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4703{
4704 int ret;
4705 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4706 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4707 .guest_phys_addr = addr,
4708 .memory_size = PAGE_SIZE * 3,
4709 .flags = 0,
4710 };
4711
47ae31e2 4712 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4713 if (ret)
4714 return ret;
bfc6d222 4715 kvm->arch.tss_addr = addr;
93ea5388
GN		 4716 if (!init_rmode_tss(kvm))
4717 return -ENOMEM;
4718
cbc94022
IE		 4719 return 0;
4720}
4721
0ca1b4f4 4722static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4723{
77ab6db0 4724 switch (vec) {
77ab6db0 4725 case BP_VECTOR:
c573cd22
JK		 4726 /*
4727 * Update instruction length as we may reinject the exception
4728 * from user space while in guest debugging mode.
4729 */
4730 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4731 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4732 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4733 return false;
4734 /* fall through */
4735 case DB_VECTOR:
4736 if (vcpu->guest_debug &
4737 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4738 return false;
d0bfb940
JK		 4739 /* fall through */
4740 case DE_VECTOR:
77ab6db0
JK		 4741 case OF_VECTOR:
4742 case BR_VECTOR:
4743 case UD_VECTOR:
4744 case DF_VECTOR:
4745 case SS_VECTOR:
4746 case GP_VECTOR:
4747 case MF_VECTOR:
0ca1b4f4
GN		 4748 return true;
4749 break;
77ab6db0 4750 }
0ca1b4f4
GN		 4751 return false;
4752}
4753
4754static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4755 int vec, u32 err_code)
4756{
4757 /*
4758 * Instruction with address size override prefix opcode 0x67
4759 * Cause the #SS fault with 0 error code in VM86 mode.
4760 */
4761 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4762 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4763 if (vcpu->arch.halt_request) {
4764 vcpu->arch.halt_request = 0;
4765 return kvm_emulate_halt(vcpu);
4766 }
4767 return 1;
4768 }
4769 return 0;
4770 }
4771
4772 /*
4773 * Forward all other exceptions that are valid in real mode.
4774 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4775 * the required debugging infrastructure rework.
4776 */
4777 kvm_queue_exception(vcpu, vec);
4778 return 1;
6aa8b732
AK		 4779}
4780
a0861c02
AK		 4781/*
4782 * Trigger machine check on the host. We assume all the MSRs are already set up
4783 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4784 * We pass a fake environment to the machine check handler because we want
4785 * the guest to be always treated like user space, no matter what context
4786 * it used internally.
4787 */
4788static void kvm_machine_check(void)
4789{
4790#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4791 struct pt_regs regs = {
4792 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4793 .flags = X86_EFLAGS_IF,
4794 };
4795
4796 do_machine_check(&regs, 0);
4797#endif
4798}
4799
851ba692 4800static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4801{
4802 /* already handled by vcpu_run */
4803 return 1;
4804}
4805
851ba692 4806static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4807{
1155f76a 4808 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4809 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4810 u32 intr_info, ex_no, error_code;
42dbaa5a 4811 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4812 u32 vect_info;
4813 enum emulation_result er;
4814
1155f76a 4815 vect_info = vmx->idt_vectoring_info;
88786475 4816 intr_info = vmx->exit_intr_info;
6aa8b732 4817
a0861c02 4818 if (is_machine_check(intr_info))
851ba692 4819 return handle_machine_check(vcpu);
a0861c02 4820
e4a41889 4821 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4822 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4823
4824 if (is_no_device(intr_info)) {
5fd86fcf 4825 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4826 return 1;
4827 }
4828
7aa81cc0 4829 if (is_invalid_opcode(intr_info)) {
51d8b661 4830 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4831 if (er != EMULATE_DONE)
7ee5d940 4832 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4833 return 1;
4834 }
4835
6aa8b732 4836 error_code = 0;
2e11384c 4837 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4838 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4839
4840 /*
4841 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4842 * MMIO, it is better to report an internal error.
4843 * See the comments in vmx_handle_exit.
4844 */
4845 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4846 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4847 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4848 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4849 vcpu->run->internal.ndata = 2;
4850 vcpu->run->internal.data[0] = vect_info;
4851 vcpu->run->internal.data[1] = intr_info;
4852 return 0;
4853 }
4854
6aa8b732 4855 if (is_page_fault(intr_info)) {
1439442c 4856 /* EPT won't cause page fault directly */
cf3ace79 4857 BUG_ON(enable_ept);
6aa8b732 4858 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4859 trace_kvm_page_fault(cr2, error_code);
4860
3298b75c 4861 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4862 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4863 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4864 }
4865
d0bfb940 4866 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4867
4868 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4869 return handle_rmode_exception(vcpu, ex_no, error_code);
4870
42dbaa5a
JK		 4871 switch (ex_no) {
4872 case DB_VECTOR:
4873 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4874 if (!(vcpu->guest_debug &
4875 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4876 vcpu->arch.dr6 &= ~15;
4877 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4878 kvm_queue_exception(vcpu, DB_VECTOR);
4879 return 1;
4880 }
4881 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4882 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4883 /* fall through */
4884 case BP_VECTOR:
c573cd22
JK		 4885 /*
4886 * Update instruction length as we may reinject #BP from
4887 * user space while in guest debugging mode. Reading it for
4888 * #DB as well causes no harm, it is not used in that case.
4889 */
4890 vmx->vcpu.arch.event_exit_inst_len =
4891 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4892 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4893 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4894 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4895 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4896 break;
4897 default:
d0bfb940
JK		 4898 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4899 kvm_run->ex.exception = ex_no;
4900 kvm_run->ex.error_code = error_code;
42dbaa5a 4901 break;
6aa8b732 4902 }
6aa8b732
AK		 4903 return 0;
4904}
4905
851ba692 4906static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4907{
1165f5fe 4908 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4909 return 1;
4910}
4911
851ba692 4912static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4913{
851ba692 4914 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4915 return 0;
4916}
6aa8b732 4917
851ba692 4918static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4919{
bfdaab09 4920 unsigned long exit_qualification;
34c33d16 4921 int size, in, string;
039576c0 4922 unsigned port;
6aa8b732 4923
bfdaab09 4924 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4925 string = (exit_qualification & 16) != 0;
cf8f70bf 4926 in = (exit_qualification & 8) != 0;
e70669ab 4927
cf8f70bf 4928 ++vcpu->stat.io_exits;
e70669ab 4929
cf8f70bf 4930 if (string || in)
51d8b661 4931 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4932
cf8f70bf
GN		 4933 port = exit_qualification >> 16;
4934 size = (exit_qualification & 7) + 1;
e93f36bc 4935 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4936
4937 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4938}
4939
102d8325
IM		 4940static void
4941vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4942{
4943 /*
4944 * Patch in the VMCALL instruction:
4945 */
4946 hypercall[0] = 0x0f;
4947 hypercall[1] = 0x01;
4948 hypercall[2] = 0xc1;
102d8325
IM		 4949}
4950
92fbc7b1
JK		 4951static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4952{
4953 unsigned long always_on = VMXON_CR0_ALWAYSON;
4954
4955 if (nested_vmx_secondary_ctls_high &
4956 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4957 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4958 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4959 return (val & always_on) == always_on;
4960}
4961
0fa06071 4962/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4963static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4964{
eeadf9e7 4965 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4966 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4967 unsigned long orig_val = val;
4968
eeadf9e7
NHE		 4969 /*
4970 * We get here when L2 changed cr0 in a way that did not change
4971 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4972 * but did change L0 shadowed bits. So we first calculate the
4973 * effective cr0 value that L1 would like to write into the
4974 * hardware. It consists of the L2-owned bits from the new
4975 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4976 */
1a0d74e6
JK		 4977 val = (val & ~vmcs12->cr0_guest_host_mask) |
4978 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4979
92fbc7b1 4980 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4981 return 1;
1a0d74e6
JK		 4982
4983 if (kvm_set_cr0(vcpu, val))
4984 return 1;
4985 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4986 return 0;
1a0d74e6
JK		 4987 } else {
4988 if (to_vmx(vcpu)->nested.vmxon &&
4989 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4990 return 1;
eeadf9e7 4991 return kvm_set_cr0(vcpu, val);
1a0d74e6 4992 }
eeadf9e7
NHE		 4993}
4994
4995static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4996{
4997 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4998 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4999 unsigned long orig_val = val;
5000
5001 /* analogously to handle_set_cr0 */
5002 val = (val & ~vmcs12->cr4_guest_host_mask) |
5003 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5004 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5005 return 1;
1a0d74e6 5006 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5007 return 0;
5008 } else
5009 return kvm_set_cr4(vcpu, val);
5010}
5011
5012/* called to set cr0 as approriate for clts instruction exit. */
5013static void handle_clts(struct kvm_vcpu *vcpu)
5014{
5015 if (is_guest_mode(vcpu)) {
5016 /*
5017 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5018 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5019 * just pretend it's off (also in arch.cr0 for fpu_activate).
5020 */
5021 vmcs_writel(CR0_READ_SHADOW,
5022 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5023 vcpu->arch.cr0 &= ~X86_CR0_TS;
5024 } else
5025 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5026}
5027
851ba692 5028static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5029{
229456fc 5030 unsigned long exit_qualification, val;
6aa8b732
AK		 5031 int cr;
5032 int reg;
49a9b07e 5033 int err;
6aa8b732 5034
bfdaab09 5035 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5036 cr = exit_qualification & 15;
5037 reg = (exit_qualification >> 8) & 15;
5038 switch ((exit_qualification >> 4) & 3) {
5039 case 0: /* mov to cr */
229456fc
MT		 5040 val = kvm_register_read(vcpu, reg);
5041 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5042 switch (cr) {
5043 case 0:
eeadf9e7 5044 err = handle_set_cr0(vcpu, val);
db8fcefa 5045 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5046 return 1;
5047 case 3:
2390218b 5048 err = kvm_set_cr3(vcpu, val);
db8fcefa 5049 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5050 return 1;
5051 case 4:
eeadf9e7 5052 err = handle_set_cr4(vcpu, val);
db8fcefa 5053 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5054 return 1;
0a5fff19
GN		 5055 case 8: {
5056 u8 cr8_prev = kvm_get_cr8(vcpu);
5057 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5058 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5059 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5060 if (irqchip_in_kernel(vcpu->kvm))
5061 return 1;
5062 if (cr8_prev <= cr8)
5063 return 1;
851ba692 5064 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5065 return 0;
5066 }
4b8073e4 5067 }
6aa8b732 5068 break;
25c4c276 5069 case 2: /* clts */
eeadf9e7 5070 handle_clts(vcpu);
4d4ec087 5071 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5072 skip_emulated_instruction(vcpu);
6b52d186 5073 vmx_fpu_activate(vcpu);
25c4c276 5074 return 1;
6aa8b732
AK		 5075 case 1: /*mov from cr*/
5076 switch (cr) {
5077 case 3:
9f8fe504
AK		 5078 val = kvm_read_cr3(vcpu);
5079 kvm_register_write(vcpu, reg, val);
5080 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5081 skip_emulated_instruction(vcpu);
5082 return 1;
5083 case 8:
229456fc
MT		 5084 val = kvm_get_cr8(vcpu);
5085 kvm_register_write(vcpu, reg, val);
5086 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5087 skip_emulated_instruction(vcpu);
5088 return 1;
5089 }
5090 break;
5091 case 3: /* lmsw */
a1f83a74 5092 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5093 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5094 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5095
5096 skip_emulated_instruction(vcpu);
5097 return 1;
5098 default:
5099 break;
5100 }
851ba692 5101 vcpu->run->exit_reason = 0;
a737f256 5102 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5103 (int)(exit_qualification >> 4) & 3, cr);
5104 return 0;
5105}
5106
851ba692 5107static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5108{
bfdaab09 5109 unsigned long exit_qualification;
6aa8b732
AK		 5110 int dr, reg;
5111
f2483415 5112 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5113 if (!kvm_require_cpl(vcpu, 0))
5114 return 1;
42dbaa5a
JK		 5115 dr = vmcs_readl(GUEST_DR7);
5116 if (dr & DR7_GD) {
5117 /*
5118 * As the vm-exit takes precedence over the debug trap, we
5119 * need to emulate the latter, either for the host or the
5120 * guest debugging itself.
5121 */
5122 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5123 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5124 vcpu->run->debug.arch.dr7 = dr;
5125 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5126 vmcs_readl(GUEST_CS_BASE) +
5127 vmcs_readl(GUEST_RIP);
851ba692
AK		 5128 vcpu->run->debug.arch.exception = DB_VECTOR;
5129 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5130 return 0;
5131 } else {
5132 vcpu->arch.dr7 &= ~DR7_GD;
5133 vcpu->arch.dr6 |= DR6_BD;
5134 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5135 kvm_queue_exception(vcpu, DB_VECTOR);
5136 return 1;
5137 }
5138 }
5139
bfdaab09 5140 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5141 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5142 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5143 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5144 unsigned long val;
4c4d563b
JK		 5145
5146 if (kvm_get_dr(vcpu, dr, &val))
5147 return 1;
5148 kvm_register_write(vcpu, reg, val);
020df079 5149 } else
4c4d563b
JK		 5150 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5151 return 1;
5152
6aa8b732
AK		 5153 skip_emulated_instruction(vcpu);
5154 return 1;
5155}
5156
73aaf249
JK		 5157static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5158{
5159 return vcpu->arch.dr6;
5160}
5161
5162static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5163{
5164}
5165
020df079
GN		 5166static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5167{
5168 vmcs_writel(GUEST_DR7, val);
5169}
5170
851ba692 5171static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5172{
06465c5a
AK		 5173 kvm_emulate_cpuid(vcpu);
5174 return 1;
6aa8b732
AK		 5175}
5176
851ba692 5177static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5178{
ad312c7c 5179 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5180 u64 data;
5181
5182 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5183 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5184 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5185 return 1;
5186 }
5187
229456fc 5188 trace_kvm_msr_read(ecx, data);
2714d1d3 5189
6aa8b732 5190 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5191 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5192 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5193 skip_emulated_instruction(vcpu);
5194 return 1;
5195}
5196
851ba692 5197static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5198{
8fe8ab46 5199 struct msr_data msr;
ad312c7c
ZX		 5200 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5201 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5202 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5203
8fe8ab46
WA		 5204 msr.data = data;
5205 msr.index = ecx;
5206 msr.host_initiated = false;
5207 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5208 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5209 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5210 return 1;
5211 }
5212
59200273 5213 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5214 skip_emulated_instruction(vcpu);
5215 return 1;
5216}
5217
851ba692 5218static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5219{
3842d135 5220 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5221 return 1;
5222}
5223
851ba692 5224static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5225{
85f455f7
ED		 5226 u32 cpu_based_vm_exec_control;
5227
5228 /* clear pending irq */
5229 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5230 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5231 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5232
3842d135
AK		 5233 kvm_make_request(KVM_REQ_EVENT, vcpu);
5234
a26bf12a 5235 ++vcpu->stat.irq_window_exits;
2714d1d3 5236
c1150d8c
DL		 5237 /*
5238 * If the user space waits to inject interrupts, exit as soon as
5239 * possible
5240 */
8061823a 5241 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5242 vcpu->run->request_interrupt_window &&
8061823a 5243 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5244 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5245 return 0;
5246 }
6aa8b732
AK		 5247 return 1;
5248}
5249
851ba692 5250static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5251{
5252 skip_emulated_instruction(vcpu);
d3bef15f 5253 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5254}
5255
851ba692 5256static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5257{
510043da 5258 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5259 kvm_emulate_hypercall(vcpu);
5260 return 1;
c21415e8
IM		 5261}
5262
ec25d5e6
GN		 5263static int handle_invd(struct kvm_vcpu *vcpu)
5264{
51d8b661 5265 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5266}
5267
851ba692 5268static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5269{
f9c617f6 5270 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5271
5272 kvm_mmu_invlpg(vcpu, exit_qualification);
5273 skip_emulated_instruction(vcpu);
5274 return 1;
5275}
5276
fee84b07
AK		 5277static int handle_rdpmc(struct kvm_vcpu *vcpu)
5278{
5279 int err;
5280
5281 err = kvm_rdpmc(vcpu);
5282 kvm_complete_insn_gp(vcpu, err);
5283
5284 return 1;
5285}
5286
851ba692 5287static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5288{
5289 skip_emulated_instruction(vcpu);
f5f48ee1 5290 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5291 return 1;
5292}
5293
2acf923e
DC		 5294static int handle_xsetbv(struct kvm_vcpu *vcpu)
5295{
5296 u64 new_bv = kvm_read_edx_eax(vcpu);
5297 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5298
5299 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5300 skip_emulated_instruction(vcpu);
5301 return 1;
5302}
5303
851ba692 5304static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5305{
58fbbf26
KT		 5306 if (likely(fasteoi)) {
5307 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308 int access_type, offset;
5309
5310 access_type = exit_qualification & APIC_ACCESS_TYPE;
5311 offset = exit_qualification & APIC_ACCESS_OFFSET;
5312 /*
5313 * Sane guest uses MOV to write EOI, with written value
5314 * not cared. So make a short-circuit here by avoiding
5315 * heavy instruction emulation.
5316 */
5317 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5318 (offset == APIC_EOI)) {
5319 kvm_lapic_set_eoi(vcpu);
5320 skip_emulated_instruction(vcpu);
5321 return 1;
5322 }
5323 }
51d8b661 5324 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5325}
5326
c7c9c56c
YZ		 5327static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5328{
5329 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5330 int vector = exit_qualification & 0xff;
5331
5332 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5333 kvm_apic_set_eoi_accelerated(vcpu, vector);
5334 return 1;
5335}
5336
83d4c286
YZ		 5337static int handle_apic_write(struct kvm_vcpu *vcpu)
5338{
5339 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5340 u32 offset = exit_qualification & 0xfff;
5341
5342 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5343 kvm_apic_write_nodecode(vcpu, offset);
5344 return 1;
5345}
5346
851ba692 5347static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5348{
60637aac 5349 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5350 unsigned long exit_qualification;
e269fb21
JK		 5351 bool has_error_code = false;
5352 u32 error_code = 0;
37817f29 5353 u16 tss_selector;
7f3d35fd 5354 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5355
5356 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5357 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5358 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5359
5360 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5361
5362 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5363 if (reason == TASK_SWITCH_GATE && idt_v) {
5364 switch (type) {
5365 case INTR_TYPE_NMI_INTR:
5366 vcpu->arch.nmi_injected = false;
654f06fc 5367 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5368 break;
5369 case INTR_TYPE_EXT_INTR:
66fd3f7f 5370 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5371 kvm_clear_interrupt_queue(vcpu);
5372 break;
5373 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5374 if (vmx->idt_vectoring_info &
5375 VECTORING_INFO_DELIVER_CODE_MASK) {
5376 has_error_code = true;
5377 error_code =
5378 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5379 }
5380 /* fall through */
64a7ec06
GN		 5381 case INTR_TYPE_SOFT_EXCEPTION:
5382 kvm_clear_exception_queue(vcpu);
5383 break;
5384 default:
5385 break;
5386 }
60637aac 5387 }
37817f29
IE		 5388 tss_selector = exit_qualification;
5389
64a7ec06
GN		 5390 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5391 type != INTR_TYPE_EXT_INTR &&
5392 type != INTR_TYPE_NMI_INTR))
5393 skip_emulated_instruction(vcpu);
5394
7f3d35fd
KW		 5395 if (kvm_task_switch(vcpu, tss_selector,
5396 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5397 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5398 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5399 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5400 vcpu->run->internal.ndata = 0;
42dbaa5a 5401 return 0;
acb54517 5402 }
42dbaa5a
JK		 5403
5404 /* clear all local breakpoint enable flags */
5405 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5406
5407 /*
5408 * TODO: What about debug traps on tss switch?
5409 * Are we supposed to inject them and update dr6?
5410 */
5411
5412 return 1;
37817f29
IE		 5413}
5414
851ba692 5415static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5416{
f9c617f6 5417 unsigned long exit_qualification;
1439442c 5418 gpa_t gpa;
4f5982a5 5419 u32 error_code;
1439442c 5420 int gla_validity;
1439442c 5421
f9c617f6 5422 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5423
1439442c
SY		 5424 gla_validity = (exit_qualification >> 7) & 0x3;
5425 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5426 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5427 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5428 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5429 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5430 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5431 (long unsigned int)exit_qualification);
851ba692
AK		 5432 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5433 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5434 return 0;
1439442c
SY		 5435 }
5436
0be9c7a8
GN		 5437 /*
5438 * EPT violation happened while executing iret from NMI,
5439 * "blocked by NMI" bit has to be set before next VM entry.
5440 * There are errata that may cause this bit to not be set:
5441 * AAK134, BY25.
5442 */
bcd1c294
GN		 5443 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5444 cpu_has_virtual_nmis() &&
5445 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5446 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5447
1439442c 5448 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5449 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5450
5451 /* It is a write fault? */
5452 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5453 /* It is a fetch fault? */
5454 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5455 /* ept page table is present? */
5456 error_code |= (exit_qualification >> 3) & 0x1;
5457
25d92081
YZ		 5458 vcpu->arch.exit_qualification = exit_qualification;
5459
4f5982a5 5460 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5461}
5462
68f89400
MT		 5463static u64 ept_rsvd_mask(u64 spte, int level)
5464{
5465 int i;
5466 u64 mask = 0;
5467
5468 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5469 mask |= (1ULL << i);
5470
5471 if (level > 2)
5472 /* bits 7:3 reserved */
5473 mask |= 0xf8;
5474 else if (level == 2) {
5475 if (spte & (1ULL << 7))
5476 /* 2MB ref, bits 20:12 reserved */
5477 mask |= 0x1ff000;
5478 else
5479 /* bits 6:3 reserved */
5480 mask |= 0x78;
5481 }
5482
5483 return mask;
5484}
5485
5486static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5487 int level)
5488{
5489 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5490
5491 /* 010b (write-only) */
5492 WARN_ON((spte & 0x7) == 0x2);
5493
5494 /* 110b (write/execute) */
5495 WARN_ON((spte & 0x7) == 0x6);
5496
5497 /* 100b (execute-only) and value not supported by logical processor */
5498 if (!cpu_has_vmx_ept_execute_only())
5499 WARN_ON((spte & 0x7) == 0x4);
5500
5501 /* not 000b */
5502 if ((spte & 0x7)) {
5503 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5504
5505 if (rsvd_bits != 0) {
5506 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5507 __func__, rsvd_bits);
5508 WARN_ON(1);
5509 }
5510
5511 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5512 u64 ept_mem_type = (spte & 0x38) >> 3;
5513
5514 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5515 ept_mem_type == 7) {
5516 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5517 __func__, ept_mem_type);
5518 WARN_ON(1);
5519 }
5520 }
5521 }
5522}
5523
851ba692 5524static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5525{
5526 u64 sptes[4];
ce88decf 5527 int nr_sptes, i, ret;
68f89400
MT		 5528 gpa_t gpa;
5529
5530 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5531
ce88decf 5532 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5533 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5534 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5535 EMULATE_DONE;
f8f55942
XG		 5536
5537 if (unlikely(ret == RET_MMIO_PF_INVALID))
5538 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5539
b37fbea6 5540 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5541 return 1;
5542
5543 /* It is the real ept misconfig */
68f89400
MT		 5544 printk(KERN_ERR "EPT: Misconfiguration.\n");
5545 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5546
5547 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5548
5549 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5550 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5551
851ba692
AK		 5552 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5553 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5554
5555 return 0;
5556}
5557
851ba692 5558static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5559{
5560 u32 cpu_based_vm_exec_control;
5561
5562 /* clear pending NMI */
5563 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5564 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5566 ++vcpu->stat.nmi_window_exits;
3842d135 5567 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5568
5569 return 1;
5570}
5571
80ced186 5572static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5573{
8b3079a5
AK		 5574 struct vcpu_vmx *vmx = to_vmx(vcpu);
5575 enum emulation_result err = EMULATE_DONE;
80ced186 5576 int ret = 1;
49e9d557
AK		 5577 u32 cpu_exec_ctrl;
5578 bool intr_window_requested;
b8405c18 5579 unsigned count = 130;
49e9d557
AK		 5580
5581 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5583
b8405c18 5584 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5585 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5586 return handle_interrupt_window(&vmx->vcpu);
5587
de87dcdd
AK		 5588 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5589 return 1;
5590
991eebf9 5591 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5592
ac0a48c3 5593 if (err == EMULATE_USER_EXIT) {
94452b9e 5594 ++vcpu->stat.mmio_exits;
80ced186
MG		 5595 ret = 0;
5596 goto out;
5597 }
1d5a4d9b 5598
de5f70e0
AK		 5599 if (err != EMULATE_DONE) {
5600 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5601 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5602 vcpu->run->internal.ndata = 0;
6d77dbfc 5603 return 0;
de5f70e0 5604 }
ea953ef0 5605
8d76c49e
GN		 5606 if (vcpu->arch.halt_request) {
5607 vcpu->arch.halt_request = 0;
5608 ret = kvm_emulate_halt(vcpu);
5609 goto out;
5610 }
5611
ea953ef0 5612 if (signal_pending(current))
80ced186 5613 goto out;
ea953ef0
MG		 5614 if (need_resched())
5615 schedule();
5616 }
5617
14168786 5618 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5619out:
5620 return ret;
ea953ef0
MG		 5621}
5622
4b8d54f9
ZE		 5623/*
5624 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5625 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5626 */
9fb41ba8 5627static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5628{
5629 skip_emulated_instruction(vcpu);
5630 kvm_vcpu_on_spin(vcpu);
5631
5632 return 1;
5633}
5634
59708670
SY		 5635static int handle_invalid_op(struct kvm_vcpu *vcpu)
5636{
5637 kvm_queue_exception(vcpu, UD_VECTOR);
5638 return 1;
5639}
5640
ff2f6fe9
NHE		 5641/*
5642 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5643 * We could reuse a single VMCS for all the L2 guests, but we also want the
5644 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5645 * allows keeping them loaded on the processor, and in the future will allow
5646 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5647 * every entry if they never change.
5648 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5649 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5650 *
5651 * The following functions allocate and free a vmcs02 in this pool.
5652 */
5653
5654/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5655static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5656{
5657 struct vmcs02_list *item;
5658 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5659 if (item->vmptr == vmx->nested.current_vmptr) {
5660 list_move(&item->list, &vmx->nested.vmcs02_pool);
5661 return &item->vmcs02;
5662 }
5663
5664 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5665 /* Recycle the least recently used VMCS. */
5666 item = list_entry(vmx->nested.vmcs02_pool.prev,
5667 struct vmcs02_list, list);
5668 item->vmptr = vmx->nested.current_vmptr;
5669 list_move(&item->list, &vmx->nested.vmcs02_pool);
5670 return &item->vmcs02;
5671 }
5672
5673 /* Create a new VMCS */
0fa24ce3 5674 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5675 if (!item)
5676 return NULL;
5677 item->vmcs02.vmcs = alloc_vmcs();
5678 if (!item->vmcs02.vmcs) {
5679 kfree(item);
5680 return NULL;
5681 }
5682 loaded_vmcs_init(&item->vmcs02);
5683 item->vmptr = vmx->nested.current_vmptr;
5684 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5685 vmx->nested.vmcs02_num++;
5686 return &item->vmcs02;
5687}
5688
5689/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5690static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5691{
5692 struct vmcs02_list *item;
5693 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5694 if (item->vmptr == vmptr) {
5695 free_loaded_vmcs(&item->vmcs02);
5696 list_del(&item->list);
5697 kfree(item);
5698 vmx->nested.vmcs02_num--;
5699 return;
5700 }
5701}
5702
5703/*
5704 * Free all VMCSs saved for this vcpu, except the one pointed by
5705 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5706 * currently used, if running L2), and vmcs01 when running L2.
5707 */
5708static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5709{
5710 struct vmcs02_list *item, *n;
5711 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5712 if (vmx->loaded_vmcs != &item->vmcs02)
5713 free_loaded_vmcs(&item->vmcs02);
5714 list_del(&item->list);
5715 kfree(item);
5716 }
5717 vmx->nested.vmcs02_num = 0;
5718
5719 if (vmx->loaded_vmcs != &vmx->vmcs01)
5720 free_loaded_vmcs(&vmx->vmcs01);
5721}
5722
0658fbaa
ACL		 5723/*
5724 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5725 * set the success or error code of an emulated VMX instruction, as specified
5726 * by Vol 2B, VMX Instruction Reference, "Conventions".
5727 */
5728static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5729{
5730 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5731 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5732 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5733}
5734
5735static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5736{
5737 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5738 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5739 X86_EFLAGS_SF | X86_EFLAGS_OF))
5740 | X86_EFLAGS_CF);
5741}
5742
145c28dd 5743static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5744 u32 vm_instruction_error)
5745{
5746 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5747 /*
5748 * failValid writes the error number to the current VMCS, which
5749 * can't be done there isn't a current VMCS.
5750 */
5751 nested_vmx_failInvalid(vcpu);
5752 return;
5753 }
5754 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5755 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5756 X86_EFLAGS_SF | X86_EFLAGS_OF))
5757 | X86_EFLAGS_ZF);
5758 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5759 /*
5760 * We don't need to force a shadow sync because
5761 * VM_INSTRUCTION_ERROR is not shadowed
5762 */
5763}
145c28dd 5764
ec378aee
NHE		 5765/*
5766 * Emulate the VMXON instruction.
5767 * Currently, we just remember that VMX is active, and do not save or even
5768 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5769 * do not currently need to store anything in that guest-allocated memory
5770 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5771 * argument is different from the VMXON pointer (which the spec says they do).
5772 */
5773static int handle_vmon(struct kvm_vcpu *vcpu)
5774{
5775 struct kvm_segment cs;
5776 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5777 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5778 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5779 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5780
5781 /* The Intel VMX Instruction Reference lists a bunch of bits that
5782 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5783 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5784 * Otherwise, we should fail with #UD. We test these now:
5785 */
5786 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5787 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5788 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5789 kvm_queue_exception(vcpu, UD_VECTOR);
5790 return 1;
5791 }
5792
5793 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5794 if (is_long_mode(vcpu) && !cs.l) {
5795 kvm_queue_exception(vcpu, UD_VECTOR);
5796 return 1;
5797 }
5798
5799 if (vmx_get_cpl(vcpu)) {
5800 kvm_inject_gp(vcpu, 0);
5801 return 1;
5802 }
145c28dd
AG		 5803 if (vmx->nested.vmxon) {
5804 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5805 skip_emulated_instruction(vcpu);
5806 return 1;
5807 }
b3897a49
NHE		 5808
5809 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5810 != VMXON_NEEDED_FEATURES) {
5811 kvm_inject_gp(vcpu, 0);
5812 return 1;
5813 }
5814
8de48833
AG		 5815 if (enable_shadow_vmcs) {
5816 shadow_vmcs = alloc_vmcs();
5817 if (!shadow_vmcs)
5818 return -ENOMEM;
5819 /* mark vmcs as shadow */
5820 shadow_vmcs->revision_id |= (1u << 31);
5821 /* init shadow vmcs */
5822 vmcs_clear(shadow_vmcs);
5823 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5824 }
ec378aee 5825
ff2f6fe9
NHE		 5826 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5827 vmx->nested.vmcs02_num = 0;
5828
ec378aee
NHE		 5829 vmx->nested.vmxon = true;
5830
5831 skip_emulated_instruction(vcpu);
a25eb114 5832 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5833 return 1;
5834}
5835
5836/*
5837 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5838 * for running VMX instructions (except VMXON, whose prerequisites are
5839 * slightly different). It also specifies what exception to inject otherwise.
5840 */
5841static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5842{
5843 struct kvm_segment cs;
5844 struct vcpu_vmx *vmx = to_vmx(vcpu);
5845
5846 if (!vmx->nested.vmxon) {
5847 kvm_queue_exception(vcpu, UD_VECTOR);
5848 return 0;
5849 }
5850
5851 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5852 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5853 (is_long_mode(vcpu) && !cs.l)) {
5854 kvm_queue_exception(vcpu, UD_VECTOR);
5855 return 0;
5856 }
5857
5858 if (vmx_get_cpl(vcpu)) {
5859 kvm_inject_gp(vcpu, 0);
5860 return 0;
5861 }
5862
5863 return 1;
5864}
5865
e7953d7f
AG		 5866static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5867{
8a1b9dd0 5868 u32 exec_control;
012f83cb
AG		 5869 if (enable_shadow_vmcs) {
5870 if (vmx->nested.current_vmcs12 != NULL) {
5871 /* copy to memory all shadowed fields in case
5872 they were modified */
5873 copy_shadow_to_vmcs12(vmx);
5874 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5875 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5876 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5877 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5878 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5879 }
5880 }
e7953d7f
AG		 5881 kunmap(vmx->nested.current_vmcs12_page);
5882 nested_release_page(vmx->nested.current_vmcs12_page);
5883}
5884
ec378aee
NHE		 5885/*
5886 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5887 * just stops using VMX.
5888 */
5889static void free_nested(struct vcpu_vmx *vmx)
5890{
5891 if (!vmx->nested.vmxon)
5892 return;
5893 vmx->nested.vmxon = false;
a9d30f33 5894 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5895 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5896 vmx->nested.current_vmptr = -1ull;
5897 vmx->nested.current_vmcs12 = NULL;
5898 }
e7953d7f
AG		 5899 if (enable_shadow_vmcs)
5900 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5901 /* Unpin physical memory we referred to in current vmcs02 */
5902 if (vmx->nested.apic_access_page) {
5903 nested_release_page(vmx->nested.apic_access_page);
5904 vmx->nested.apic_access_page = 0;
5905 }
ff2f6fe9
NHE		 5906
5907 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5908}
5909
5910/* Emulate the VMXOFF instruction */
5911static int handle_vmoff(struct kvm_vcpu *vcpu)
5912{
5913 if (!nested_vmx_check_permission(vcpu))
5914 return 1;
5915 free_nested(to_vmx(vcpu));
5916 skip_emulated_instruction(vcpu);
a25eb114 5917 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5918 return 1;
5919}
5920
064aea77
NHE		 5921/*
5922 * Decode the memory-address operand of a vmx instruction, as recorded on an
5923 * exit caused by such an instruction (run by a guest hypervisor).
5924 * On success, returns 0. When the operand is invalid, returns 1 and throws
5925 * #UD or #GP.
5926 */
5927static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5928 unsigned long exit_qualification,
5929 u32 vmx_instruction_info, gva_t *ret)
5930{
5931 /*
5932 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5933 * Execution", on an exit, vmx_instruction_info holds most of the
5934 * addressing components of the operand. Only the displacement part
5935 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5936 * For how an actual address is calculated from all these components,
5937 * refer to Vol. 1, "Operand Addressing".
5938 */
5939 int scaling = vmx_instruction_info & 3;
5940 int addr_size = (vmx_instruction_info >> 7) & 7;
5941 bool is_reg = vmx_instruction_info & (1u << 10);
5942 int seg_reg = (vmx_instruction_info >> 15) & 7;
5943 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5944 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5945 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5946 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5947
5948 if (is_reg) {
5949 kvm_queue_exception(vcpu, UD_VECTOR);
5950 return 1;
5951 }
5952
5953 /* Addr = segment_base + offset */
5954 /* offset = base + [index * scale] + displacement */
5955 *ret = vmx_get_segment_base(vcpu, seg_reg);
5956 if (base_is_valid)
5957 *ret += kvm_register_read(vcpu, base_reg);
5958 if (index_is_valid)
5959 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5960 *ret += exit_qualification; /* holds the displacement */
5961
5962 if (addr_size == 1) /* 32 bit */
5963 *ret &= 0xffffffff;
5964
5965 /*
5966 * TODO: throw #GP (and return 1) in various cases that the VM*
5967 * instructions require it - e.g., offset beyond segment limit,
5968 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5969 * address, and so on. Currently these are not checked.
5970 */
5971 return 0;
5972}
5973
27d6c865
NHE		 5974/* Emulate the VMCLEAR instruction */
5975static int handle_vmclear(struct kvm_vcpu *vcpu)
5976{
5977 struct vcpu_vmx *vmx = to_vmx(vcpu);
5978 gva_t gva;
5979 gpa_t vmptr;
5980 struct vmcs12 *vmcs12;
5981 struct page *page;
5982 struct x86_exception e;
5983
5984 if (!nested_vmx_check_permission(vcpu))
5985 return 1;
5986
5987 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5988 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5989 return 1;
5990
5991 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5992 sizeof(vmptr), &e)) {
5993 kvm_inject_page_fault(vcpu, &e);
5994 return 1;
5995 }
5996
5997 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5998 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5999 skip_emulated_instruction(vcpu);
6000 return 1;
6001 }
6002
6003 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6004 nested_release_vmcs12(vmx);
27d6c865
NHE		 6005 vmx->nested.current_vmptr = -1ull;
6006 vmx->nested.current_vmcs12 = NULL;
6007 }
6008
6009 page = nested_get_page(vcpu, vmptr);
6010 if (page == NULL) {
6011 /*
6012 * For accurate processor emulation, VMCLEAR beyond available
6013 * physical memory should do nothing at all. However, it is
6014 * possible that a nested vmx bug, not a guest hypervisor bug,
6015 * resulted in this case, so let's shut down before doing any
6016 * more damage:
6017 */
6018 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6019 return 1;
6020 }
6021 vmcs12 = kmap(page);
6022 vmcs12->launch_state = 0;
6023 kunmap(page);
6024 nested_release_page(page);
6025
6026 nested_free_vmcs02(vmx, vmptr);
6027
6028 skip_emulated_instruction(vcpu);
6029 nested_vmx_succeed(vcpu);
6030 return 1;
6031}
6032
cd232ad0
NHE		 6033static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6034
6035/* Emulate the VMLAUNCH instruction */
6036static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6037{
6038 return nested_vmx_run(vcpu, true);
6039}
6040
6041/* Emulate the VMRESUME instruction */
6042static int handle_vmresume(struct kvm_vcpu *vcpu)
6043{
6044
6045 return nested_vmx_run(vcpu, false);
6046}
6047
49f705c5
NHE		 6048enum vmcs_field_type {
6049 VMCS_FIELD_TYPE_U16 = 0,
6050 VMCS_FIELD_TYPE_U64 = 1,
6051 VMCS_FIELD_TYPE_U32 = 2,
6052 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6053};
6054
6055static inline int vmcs_field_type(unsigned long field)
6056{
6057 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6058 return VMCS_FIELD_TYPE_U32;
6059 return (field >> 13) & 0x3 ;
6060}
6061
6062static inline int vmcs_field_readonly(unsigned long field)
6063{
6064 return (((field >> 10) & 0x3) == 1);
6065}
6066
6067/*
6068 * Read a vmcs12 field. Since these can have varying lengths and we return
6069 * one type, we chose the biggest type (u64) and zero-extend the return value
6070 * to that size. Note that the caller, handle_vmread, might need to use only
6071 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6072 * 64-bit fields are to be returned).
6073 */
6074static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6075 unsigned long field, u64 *ret)
6076{
6077 short offset = vmcs_field_to_offset(field);
6078 char *p;
6079
6080 if (offset < 0)
6081 return 0;
6082
6083 p = ((char *)(get_vmcs12(vcpu))) + offset;
6084
6085 switch (vmcs_field_type(field)) {
6086 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6087 *ret = *((natural_width *)p);
6088 return 1;
6089 case VMCS_FIELD_TYPE_U16:
6090 *ret = *((u16 *)p);
6091 return 1;
6092 case VMCS_FIELD_TYPE_U32:
6093 *ret = *((u32 *)p);
6094 return 1;
6095 case VMCS_FIELD_TYPE_U64:
6096 *ret = *((u64 *)p);
6097 return 1;
6098 default:
6099 return 0; /* can never happen. */
6100 }
6101}
6102
20b97fea
AG		 6103
6104static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6105 unsigned long field, u64 field_value){
6106 short offset = vmcs_field_to_offset(field);
6107 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6108 if (offset < 0)
6109 return false;
6110
6111 switch (vmcs_field_type(field)) {
6112 case VMCS_FIELD_TYPE_U16:
6113 *(u16 *)p = field_value;
6114 return true;
6115 case VMCS_FIELD_TYPE_U32:
6116 *(u32 *)p = field_value;
6117 return true;
6118 case VMCS_FIELD_TYPE_U64:
6119 *(u64 *)p = field_value;
6120 return true;
6121 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6122 *(natural_width *)p = field_value;
6123 return true;
6124 default:
6125 return false; /* can never happen. */
6126 }
6127
6128}
6129
16f5b903
AG		 6130static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6131{
6132 int i;
6133 unsigned long field;
6134 u64 field_value;
6135 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6136 const unsigned long *fields = shadow_read_write_fields;
6137 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6138
6139 vmcs_load(shadow_vmcs);
6140
6141 for (i = 0; i < num_fields; i++) {
6142 field = fields[i];
6143 switch (vmcs_field_type(field)) {
6144 case VMCS_FIELD_TYPE_U16:
6145 field_value = vmcs_read16(field);
6146 break;
6147 case VMCS_FIELD_TYPE_U32:
6148 field_value = vmcs_read32(field);
6149 break;
6150 case VMCS_FIELD_TYPE_U64:
6151 field_value = vmcs_read64(field);
6152 break;
6153 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6154 field_value = vmcs_readl(field);
6155 break;
6156 }
6157 vmcs12_write_any(&vmx->vcpu, field, field_value);
6158 }
6159
6160 vmcs_clear(shadow_vmcs);
6161 vmcs_load(vmx->loaded_vmcs->vmcs);
6162}
6163
c3114420
AG		 6164static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6165{
c2bae893
MK		 6166 const unsigned long *fields[] = {
6167 shadow_read_write_fields,
6168 shadow_read_only_fields
c3114420 6169 };
c2bae893 6170 const int max_fields[] = {
c3114420
AG		 6171 max_shadow_read_write_fields,
6172 max_shadow_read_only_fields
6173 };
6174 int i, q;
6175 unsigned long field;
6176 u64 field_value = 0;
6177 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6178
6179 vmcs_load(shadow_vmcs);
6180
c2bae893 6181 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6182 for (i = 0; i < max_fields[q]; i++) {
6183 field = fields[q][i];
6184 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6185
6186 switch (vmcs_field_type(field)) {
6187 case VMCS_FIELD_TYPE_U16:
6188 vmcs_write16(field, (u16)field_value);
6189 break;
6190 case VMCS_FIELD_TYPE_U32:
6191 vmcs_write32(field, (u32)field_value);
6192 break;
6193 case VMCS_FIELD_TYPE_U64:
6194 vmcs_write64(field, (u64)field_value);
6195 break;
6196 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6197 vmcs_writel(field, (long)field_value);
6198 break;
6199 }
6200 }
6201 }
6202
6203 vmcs_clear(shadow_vmcs);
6204 vmcs_load(vmx->loaded_vmcs->vmcs);
6205}
6206
49f705c5
NHE		 6207/*
6208 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6209 * used before) all generate the same failure when it is missing.
6210 */
6211static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6212{
6213 struct vcpu_vmx *vmx = to_vmx(vcpu);
6214 if (vmx->nested.current_vmptr == -1ull) {
6215 nested_vmx_failInvalid(vcpu);
6216 skip_emulated_instruction(vcpu);
6217 return 0;
6218 }
6219 return 1;
6220}
6221
6222static int handle_vmread(struct kvm_vcpu *vcpu)
6223{
6224 unsigned long field;
6225 u64 field_value;
6226 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6227 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6228 gva_t gva = 0;
6229
6230 if (!nested_vmx_check_permission(vcpu) ||
6231 !nested_vmx_check_vmcs12(vcpu))
6232 return 1;
6233
6234 /* Decode instruction info and find the field to read */
6235 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6236 /* Read the field, zero-extended to a u64 field_value */
6237 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6238 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6239 skip_emulated_instruction(vcpu);
6240 return 1;
6241 }
6242 /*
6243 * Now copy part of this value to register or memory, as requested.
6244 * Note that the number of bits actually copied is 32 or 64 depending
6245 * on the guest's mode (32 or 64 bit), not on the given field's length.
6246 */
6247 if (vmx_instruction_info & (1u << 10)) {
6248 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6249 field_value);
6250 } else {
6251 if (get_vmx_mem_address(vcpu, exit_qualification,
6252 vmx_instruction_info, &gva))
6253 return 1;
6254 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6255 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6256 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6257 }
6258
6259 nested_vmx_succeed(vcpu);
6260 skip_emulated_instruction(vcpu);
6261 return 1;
6262}
6263
6264
6265static int handle_vmwrite(struct kvm_vcpu *vcpu)
6266{
6267 unsigned long field;
6268 gva_t gva;
6269 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6270 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6271 /* The value to write might be 32 or 64 bits, depending on L1's long
6272 * mode, and eventually we need to write that into a field of several
6273 * possible lengths. The code below first zero-extends the value to 64
6274 * bit (field_value), and then copies only the approriate number of
6275 * bits into the vmcs12 field.
6276 */
6277 u64 field_value = 0;
6278 struct x86_exception e;
6279
6280 if (!nested_vmx_check_permission(vcpu) ||
6281 !nested_vmx_check_vmcs12(vcpu))
6282 return 1;
6283
6284 if (vmx_instruction_info & (1u << 10))
6285 field_value = kvm_register_read(vcpu,
6286 (((vmx_instruction_info) >> 3) & 0xf));
6287 else {
6288 if (get_vmx_mem_address(vcpu, exit_qualification,
6289 vmx_instruction_info, &gva))
6290 return 1;
6291 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6292 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6293 kvm_inject_page_fault(vcpu, &e);
6294 return 1;
6295 }
6296 }
6297
6298
6299 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6300 if (vmcs_field_readonly(field)) {
6301 nested_vmx_failValid(vcpu,
6302 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6303 skip_emulated_instruction(vcpu);
6304 return 1;
6305 }
6306
20b97fea 6307 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6308 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6309 skip_emulated_instruction(vcpu);
6310 return 1;
6311 }
6312
6313 nested_vmx_succeed(vcpu);
6314 skip_emulated_instruction(vcpu);
6315 return 1;
6316}
6317
63846663
NHE		 6318/* Emulate the VMPTRLD instruction */
6319static int handle_vmptrld(struct kvm_vcpu *vcpu)
6320{
6321 struct vcpu_vmx *vmx = to_vmx(vcpu);
6322 gva_t gva;
6323 gpa_t vmptr;
6324 struct x86_exception e;
8a1b9dd0 6325 u32 exec_control;
63846663
NHE		 6326
6327 if (!nested_vmx_check_permission(vcpu))
6328 return 1;
6329
6330 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6331 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6332 return 1;
6333
6334 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6335 sizeof(vmptr), &e)) {
6336 kvm_inject_page_fault(vcpu, &e);
6337 return 1;
6338 }
6339
6340 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6341 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6342 skip_emulated_instruction(vcpu);
6343 return 1;
6344 }
6345
6346 if (vmx->nested.current_vmptr != vmptr) {
6347 struct vmcs12 *new_vmcs12;
6348 struct page *page;
6349 page = nested_get_page(vcpu, vmptr);
6350 if (page == NULL) {
6351 nested_vmx_failInvalid(vcpu);
6352 skip_emulated_instruction(vcpu);
6353 return 1;
6354 }
6355 new_vmcs12 = kmap(page);
6356 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6357 kunmap(page);
6358 nested_release_page_clean(page);
6359 nested_vmx_failValid(vcpu,
6360 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6361 skip_emulated_instruction(vcpu);
6362 return 1;
6363 }
e7953d7f
AG		 6364 if (vmx->nested.current_vmptr != -1ull)
6365 nested_release_vmcs12(vmx);
63846663
NHE		 6366
6367 vmx->nested.current_vmptr = vmptr;
6368 vmx->nested.current_vmcs12 = new_vmcs12;
6369 vmx->nested.current_vmcs12_page = page;
012f83cb 6370 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6371 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6372 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6373 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6374 vmcs_write64(VMCS_LINK_POINTER,
6375 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6376 vmx->nested.sync_shadow_vmcs = true;
6377 }
63846663
NHE		 6378 }
6379
6380 nested_vmx_succeed(vcpu);
6381 skip_emulated_instruction(vcpu);
6382 return 1;
6383}
6384
6a4d7550
NHE		 6385/* Emulate the VMPTRST instruction */
6386static int handle_vmptrst(struct kvm_vcpu *vcpu)
6387{
6388 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6389 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6390 gva_t vmcs_gva;
6391 struct x86_exception e;
6392
6393 if (!nested_vmx_check_permission(vcpu))
6394 return 1;
6395
6396 if (get_vmx_mem_address(vcpu, exit_qualification,
6397 vmx_instruction_info, &vmcs_gva))
6398 return 1;
6399 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6400 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6401 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6402 sizeof(u64), &e)) {
6403 kvm_inject_page_fault(vcpu, &e);
6404 return 1;
6405 }
6406 nested_vmx_succeed(vcpu);
6407 skip_emulated_instruction(vcpu);
6408 return 1;
6409}
6410
bfd0a56b
NHE		 6411/* Emulate the INVEPT instruction */
6412static int handle_invept(struct kvm_vcpu *vcpu)
6413{
6414 u32 vmx_instruction_info, types;
6415 unsigned long type;
6416 gva_t gva;
6417 struct x86_exception e;
6418 struct {
6419 u64 eptp, gpa;
6420 } operand;
6421 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6422
6423 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6424 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6425 kvm_queue_exception(vcpu, UD_VECTOR);
6426 return 1;
6427 }
6428
6429 if (!nested_vmx_check_permission(vcpu))
6430 return 1;
6431
6432 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6433 kvm_queue_exception(vcpu, UD_VECTOR);
6434 return 1;
6435 }
6436
6437 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6438 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6439
6440 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6441
6442 if (!(types & (1UL << type))) {
6443 nested_vmx_failValid(vcpu,
6444 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6445 return 1;
6446 }
6447
6448 /* According to the Intel VMX instruction reference, the memory
6449 * operand is read even if it isn't needed (e.g., for type==global)
6450 */
6451 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6452 vmx_instruction_info, &gva))
6453 return 1;
6454 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6455 sizeof(operand), &e)) {
6456 kvm_inject_page_fault(vcpu, &e);
6457 return 1;
6458 }
6459
6460 switch (type) {
6461 case VMX_EPT_EXTENT_CONTEXT:
6462 if ((operand.eptp & eptp_mask) !=
6463 (nested_ept_get_cr3(vcpu) & eptp_mask))
6464 break;
6465 case VMX_EPT_EXTENT_GLOBAL:
6466 kvm_mmu_sync_roots(vcpu);
6467 kvm_mmu_flush_tlb(vcpu);
6468 nested_vmx_succeed(vcpu);
6469 break;
6470 default:
6471 BUG_ON(1);
6472 break;
6473 }
6474
6475 skip_emulated_instruction(vcpu);
6476 return 1;
6477}
6478
6aa8b732
AK		 6479/*
6480 * The exit handlers return 1 if the exit was handled fully and guest execution
6481 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6482 * to be done to userspace and return 0.
6483 */
772e0318 6484static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6485 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6486 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6487 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6488 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6489 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6490 [EXIT_REASON_CR_ACCESS] = handle_cr,
6491 [EXIT_REASON_DR_ACCESS] = handle_dr,
6492 [EXIT_REASON_CPUID] = handle_cpuid,
6493 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6494 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6495 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6496 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6497 [EXIT_REASON_INVD] = handle_invd,
a7052897 6498 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6499 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6500 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6501 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6502 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6503 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6504 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6505 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6506 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6507 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6508 [EXIT_REASON_VMOFF] = handle_vmoff,
6509 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6510 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6511 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6512 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6513 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6514 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6515 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6516 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6517 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6518 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6519 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6520 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6521 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6522 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6523 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6524};
6525
6526static const int kvm_vmx_max_exit_handlers =
50a3485c 6527 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6528
908a7bdd
JK		 6529static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6530 struct vmcs12 *vmcs12)
6531{
6532 unsigned long exit_qualification;
6533 gpa_t bitmap, last_bitmap;
6534 unsigned int port;
6535 int size;
6536 u8 b;
6537
908a7bdd 6538 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6539 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6540
6541 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6542
6543 port = exit_qualification >> 16;
6544 size = (exit_qualification & 7) + 1;
6545
6546 last_bitmap = (gpa_t)-1;
6547 b = -1;
6548
6549 while (size > 0) {
6550 if (port < 0x8000)
6551 bitmap = vmcs12->io_bitmap_a;
6552 else if (port < 0x10000)
6553 bitmap = vmcs12->io_bitmap_b;
6554 else
6555 return 1;
6556 bitmap += (port & 0x7fff) / 8;
6557
6558 if (last_bitmap != bitmap)
6559 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6560 return 1;
6561 if (b & (1 << (port & 7)))
6562 return 1;
6563
6564 port++;
6565 size--;
6566 last_bitmap = bitmap;
6567 }
6568
6569 return 0;
6570}
6571
644d711a
NHE		 6572/*
6573 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6574 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6575 * disinterest in the current event (read or write a specific MSR) by using an
6576 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6577 */
6578static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6579 struct vmcs12 *vmcs12, u32 exit_reason)
6580{
6581 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6582 gpa_t bitmap;
6583
cbd29cb6 6584 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6585 return 1;
6586
6587 /*
6588 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6589 * for the four combinations of read/write and low/high MSR numbers.
6590 * First we need to figure out which of the four to use:
6591 */
6592 bitmap = vmcs12->msr_bitmap;
6593 if (exit_reason == EXIT_REASON_MSR_WRITE)
6594 bitmap += 2048;
6595 if (msr_index >= 0xc0000000) {
6596 msr_index -= 0xc0000000;
6597 bitmap += 1024;
6598 }
6599
6600 /* Then read the msr_index'th bit from this bitmap: */
6601 if (msr_index < 1024*8) {
6602 unsigned char b;
bd31a7f5
JK		 6603 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6604 return 1;
644d711a
NHE		 6605 return 1 & (b >> (msr_index & 7));
6606 } else
6607 return 1; /* let L1 handle the wrong parameter */
6608}
6609
6610/*
6611 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6612 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6613 * intercept (via guest_host_mask etc.) the current event.
6614 */
6615static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6616 struct vmcs12 *vmcs12)
6617{
6618 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6619 int cr = exit_qualification & 15;
6620 int reg = (exit_qualification >> 8) & 15;
6621 unsigned long val = kvm_register_read(vcpu, reg);
6622
6623 switch ((exit_qualification >> 4) & 3) {
6624 case 0: /* mov to cr */
6625 switch (cr) {
6626 case 0:
6627 if (vmcs12->cr0_guest_host_mask &
6628 (val ^ vmcs12->cr0_read_shadow))
6629 return 1;
6630 break;
6631 case 3:
6632 if ((vmcs12->cr3_target_count >= 1 &&
6633 vmcs12->cr3_target_value0 == val) ||
6634 (vmcs12->cr3_target_count >= 2 &&
6635 vmcs12->cr3_target_value1 == val) ||
6636 (vmcs12->cr3_target_count >= 3 &&
6637 vmcs12->cr3_target_value2 == val) ||
6638 (vmcs12->cr3_target_count >= 4 &&
6639 vmcs12->cr3_target_value3 == val))
6640 return 0;
6641 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6642 return 1;
6643 break;
6644 case 4:
6645 if (vmcs12->cr4_guest_host_mask &
6646 (vmcs12->cr4_read_shadow ^ val))
6647 return 1;
6648 break;
6649 case 8:
6650 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6651 return 1;
6652 break;
6653 }
6654 break;
6655 case 2: /* clts */
6656 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6657 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6658 return 1;
6659 break;
6660 case 1: /* mov from cr */
6661 switch (cr) {
6662 case 3:
6663 if (vmcs12->cpu_based_vm_exec_control &
6664 CPU_BASED_CR3_STORE_EXITING)
6665 return 1;
6666 break;
6667 case 8:
6668 if (vmcs12->cpu_based_vm_exec_control &
6669 CPU_BASED_CR8_STORE_EXITING)
6670 return 1;
6671 break;
6672 }
6673 break;
6674 case 3: /* lmsw */
6675 /*
6676 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6677 * cr0. Other attempted changes are ignored, with no exit.
6678 */
6679 if (vmcs12->cr0_guest_host_mask & 0xe &
6680 (val ^ vmcs12->cr0_read_shadow))
6681 return 1;
6682 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6683 !(vmcs12->cr0_read_shadow & 0x1) &&
6684 (val & 0x1))
6685 return 1;
6686 break;
6687 }
6688 return 0;
6689}
6690
6691/*
6692 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6693 * should handle it ourselves in L0 (and then continue L2). Only call this
6694 * when in is_guest_mode (L2).
6695 */
6696static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6697{
644d711a
NHE		 6698 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6699 struct vcpu_vmx *vmx = to_vmx(vcpu);
6700 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6701 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6702
6703 if (vmx->nested.nested_run_pending)
6704 return 0;
6705
6706 if (unlikely(vmx->fail)) {
bd80158a
JK		 6707 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6708 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6709 return 1;
6710 }
6711
6712 switch (exit_reason) {
6713 case EXIT_REASON_EXCEPTION_NMI:
6714 if (!is_exception(intr_info))
6715 return 0;
6716 else if (is_page_fault(intr_info))
6717 return enable_ept;
e504c909
AB		 6718 else if (is_no_device(intr_info) &&
6719 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6720 return 0;
644d711a
NHE		 6721 return vmcs12->exception_bitmap &
6722 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6723 case EXIT_REASON_EXTERNAL_INTERRUPT:
6724 return 0;
6725 case EXIT_REASON_TRIPLE_FAULT:
6726 return 1;
6727 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6728 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6729 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6730 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6731 case EXIT_REASON_TASK_SWITCH:
6732 return 1;
6733 case EXIT_REASON_CPUID:
6734 return 1;
6735 case EXIT_REASON_HLT:
6736 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6737 case EXIT_REASON_INVD:
6738 return 1;
6739 case EXIT_REASON_INVLPG:
6740 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6741 case EXIT_REASON_RDPMC:
6742 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6743 case EXIT_REASON_RDTSC:
6744 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6745 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6746 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6747 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6748 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6749 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6750 case EXIT_REASON_INVEPT:
644d711a
NHE		 6751 /*
6752 * VMX instructions trap unconditionally. This allows L1 to
6753 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6754 */
6755 return 1;
6756 case EXIT_REASON_CR_ACCESS:
6757 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6758 case EXIT_REASON_DR_ACCESS:
6759 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6760 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6761 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6762 case EXIT_REASON_MSR_READ:
6763 case EXIT_REASON_MSR_WRITE:
6764 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6765 case EXIT_REASON_INVALID_STATE:
6766 return 1;
6767 case EXIT_REASON_MWAIT_INSTRUCTION:
6768 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6769 case EXIT_REASON_MONITOR_INSTRUCTION:
6770 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6771 case EXIT_REASON_PAUSE_INSTRUCTION:
6772 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6773 nested_cpu_has2(vmcs12,
6774 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6775 case EXIT_REASON_MCE_DURING_VMENTRY:
6776 return 0;
6777 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6778 return 1;
6779 case EXIT_REASON_APIC_ACCESS:
6780 return nested_cpu_has2(vmcs12,
6781 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6782 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6783 /*
6784 * L0 always deals with the EPT violation. If nested EPT is
6785 * used, and the nested mmu code discovers that the address is
6786 * missing in the guest EPT table (EPT12), the EPT violation
6787 * will be injected with nested_ept_inject_page_fault()
6788 */
6789 return 0;
644d711a 6790 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6791 /*
6792 * L2 never uses directly L1's EPT, but rather L0's own EPT
6793 * table (shadow on EPT) or a merged EPT table that L0 built
6794 * (EPT on EPT). So any problems with the structure of the
6795 * table is L0's fault.
6796 */
644d711a 6797 return 0;
0238ea91
JK		 6798 case EXIT_REASON_PREEMPTION_TIMER:
6799 return vmcs12->pin_based_vm_exec_control &
6800 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6801 case EXIT_REASON_WBINVD:
6802 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6803 case EXIT_REASON_XSETBV:
6804 return 1;
6805 default:
6806 return 1;
6807 }
6808}
6809
586f9607
AK		 6810static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6811{
6812 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6813 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6814}
6815
7854cbca
ACL		 6816static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6817{
6818 u64 delta_tsc_l1;
6819 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6820
6821 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6822 PIN_BASED_VMX_PREEMPTION_TIMER))
6823 return;
6824 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6825 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6826 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6827 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6828 - vcpu->arch.last_guest_tsc;
6829 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6830 if (preempt_val_l2 <= preempt_val_l1)
6831 preempt_val_l2 = 0;
6832 else
6833 preempt_val_l2 -= preempt_val_l1;
6834 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6835}
6836
6aa8b732
AK		 6837/*
6838 * The guest has exited. See if we can fix it or if we need userspace
6839 * assistance.
6840 */
851ba692 6841static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6842{
29bd8a78 6843 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6844 u32 exit_reason = vmx->exit_reason;
1155f76a 6845 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6846
80ced186 6847 /* If guest state is invalid, start emulating */
14168786 6848 if (vmx->emulation_required)
80ced186 6849 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6850
644d711a
NHE		 6851 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6852 nested_vmx_vmexit(vcpu);
6853 return 1;
6854 }
6855
5120702e
MG		 6856 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6857 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6858 vcpu->run->fail_entry.hardware_entry_failure_reason
6859 = exit_reason;
6860 return 0;
6861 }
6862
29bd8a78 6863 if (unlikely(vmx->fail)) {
851ba692
AK		 6864 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6865 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6866 = vmcs_read32(VM_INSTRUCTION_ERROR);
6867 return 0;
6868 }
6aa8b732 6869
b9bf6882
XG		 6870 /*
6871 * Note:
6872 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6873 * delivery event since it indicates guest is accessing MMIO.
6874 * The vm-exit can be triggered again after return to guest that
6875 * will cause infinite loop.
6876 */
d77c26fc 6877 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6878 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6879 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6880 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6881 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6882 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6883 vcpu->run->internal.ndata = 2;
6884 vcpu->run->internal.data[0] = vectoring_info;
6885 vcpu->run->internal.data[1] = exit_reason;
6886 return 0;
6887 }
3b86cd99 6888
644d711a
NHE		 6889 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6890 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6891 get_vmcs12(vcpu))))) {
c4282df9 6892 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6893 vmx->soft_vnmi_blocked = 0;
3b86cd99 6894 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6895 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6896 /*
6897 * This CPU don't support us in finding the end of an
6898 * NMI-blocked window if the guest runs with IRQs
6899 * disabled. So we pull the trigger after 1 s of
6900 * futile waiting, but inform the user about this.
6901 */
6902 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6903 "state on VCPU %d after 1 s timeout\n",
6904 __func__, vcpu->vcpu_id);
6905 vmx->soft_vnmi_blocked = 0;
3b86cd99 6906 }
3b86cd99
JK		 6907 }
6908
6aa8b732
AK		 6909 if (exit_reason < kvm_vmx_max_exit_handlers
6910 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6911 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6912 else {
851ba692
AK		 6913 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6914 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6915 }
6916 return 0;
6917}
6918
95ba8273 6919static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6920{
95ba8273 6921 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6922 vmcs_write32(TPR_THRESHOLD, 0);
6923 return;
6924 }
6925
95ba8273 6926 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6927}
6928
8d14695f
YZ		 6929static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6930{
6931 u32 sec_exec_control;
6932
6933 /*
6934 * There is not point to enable virtualize x2apic without enable
6935 * apicv
6936 */
c7c9c56c
YZ		 6937 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6938 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6939 return;
6940
6941 if (!vm_need_tpr_shadow(vcpu->kvm))
6942 return;
6943
6944 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6945
6946 if (set) {
6947 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6948 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6949 } else {
6950 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6951 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6952 }
6953 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6954
6955 vmx_set_msr_bitmap(vcpu);
6956}
6957
c7c9c56c
YZ		 6958static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6959{
6960 u16 status;
6961 u8 old;
6962
6963 if (!vmx_vm_has_apicv(kvm))
6964 return;
6965
6966 if (isr == -1)
6967 isr = 0;
6968
6969 status = vmcs_read16(GUEST_INTR_STATUS);
6970 old = status >> 8;
6971 if (isr != old) {
6972 status &= 0xff;
6973 status |= isr << 8;
6974 vmcs_write16(GUEST_INTR_STATUS, status);
6975 }
6976}
6977
6978static void vmx_set_rvi(int vector)
6979{
6980 u16 status;
6981 u8 old;
6982
6983 status = vmcs_read16(GUEST_INTR_STATUS);
6984 old = (u8)status & 0xff;
6985 if ((u8)vector != old) {
6986 status &= ~0xff;
6987 status |= (u8)vector;
6988 vmcs_write16(GUEST_INTR_STATUS, status);
6989 }
6990}
6991
6992static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6993{
6994 if (max_irr == -1)
6995 return;
6996
6997 vmx_set_rvi(max_irr);
6998}
6999
7000static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7001{
3d81bc7e
YZ		 7002 if (!vmx_vm_has_apicv(vcpu->kvm))
7003 return;
7004
c7c9c56c
YZ		 7005 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7006 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7007 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7008 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7009}
7010
51aa01d1 7011static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7012{
00eba012
AK		 7013 u32 exit_intr_info;
7014
7015 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7016 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7017 return;
7018
c5ca8e57 7019 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7020 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7021
7022 /* Handle machine checks before interrupts are enabled */
00eba012 7023 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7024 kvm_machine_check();
7025
20f65983 7026 /* We need to handle NMIs before interrupts are enabled */
00eba012 7027 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7028 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7029 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7030 asm("int $2");
ff9d07a0
ZY		 7031 kvm_after_handle_nmi(&vmx->vcpu);
7032 }
51aa01d1 7033}
20f65983 7034
a547c6db
YZ		 7035static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7036{
7037 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7038
7039 /*
7040 * If external interrupt exists, IF bit is set in rflags/eflags on the
7041 * interrupt stack frame, and interrupt will be enabled on a return
7042 * from interrupt handler.
7043 */
7044 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7045 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7046 unsigned int vector;
7047 unsigned long entry;
7048 gate_desc *desc;
7049 struct vcpu_vmx *vmx = to_vmx(vcpu);
7050#ifdef CONFIG_X86_64
7051 unsigned long tmp;
7052#endif
7053
7054 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7055 desc = (gate_desc *)vmx->host_idt_base + vector;
7056 entry = gate_offset(*desc);
7057 asm volatile(
7058#ifdef CONFIG_X86_64
7059 "mov %%" _ASM_SP ", %[sp]\n\t"
7060 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7061 "push $%c[ss]\n\t"
7062 "push %[sp]\n\t"
7063#endif
7064 "pushf\n\t"
7065 "orl $0x200, (%%" _ASM_SP ")\n\t"
7066 __ASM_SIZE(push) " $%c[cs]\n\t"
7067 "call *%[entry]\n\t"
7068 :
7069#ifdef CONFIG_X86_64
7070 [sp]"=&r"(tmp)
7071#endif
7072 :
7073 [entry]"r"(entry),
7074 [ss]"i"(__KERNEL_DS),
7075 [cs]"i"(__KERNEL_CS)
7076 );
7077 } else
7078 local_irq_enable();
7079}
7080
51aa01d1
AK		 7081static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7082{
c5ca8e57 7083 u32 exit_intr_info;
51aa01d1
AK		 7084 bool unblock_nmi;
7085 u8 vector;
7086 bool idtv_info_valid;
7087
7088 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7089
cf393f75 7090 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7091 if (vmx->nmi_known_unmasked)
7092 return;
c5ca8e57
AK		 7093 /*
7094 * Can't use vmx->exit_intr_info since we're not sure what
7095 * the exit reason is.
7096 */
7097 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7098 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7099 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7100 /*
7b4a25cb 7101 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7102 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7103 * a guest IRET fault.
7b4a25cb
GN		 7104 * SDM 3: 23.2.2 (September 2008)
7105 * Bit 12 is undefined in any of the following cases:
7106 * If the VM exit sets the valid bit in the IDT-vectoring
7107 * information field.
7108 * If the VM exit is due to a double fault.
cf393f75 7109 */
7b4a25cb
GN		 7110 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7111 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7112 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7113 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7114 else
7115 vmx->nmi_known_unmasked =
7116 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7117 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7118 } else if (unlikely(vmx->soft_vnmi_blocked))
7119 vmx->vnmi_blocked_time +=
7120 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7121}
7122
3ab66e8a 7123static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7124 u32 idt_vectoring_info,
7125 int instr_len_field,
7126 int error_code_field)
51aa01d1 7127{
51aa01d1
AK		 7128 u8 vector;
7129 int type;
7130 bool idtv_info_valid;
7131
7132 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7133
3ab66e8a
JK		 7134 vcpu->arch.nmi_injected = false;
7135 kvm_clear_exception_queue(vcpu);
7136 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7137
7138 if (!idtv_info_valid)
7139 return;
7140
3ab66e8a 7141 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7142
668f612f
AK		 7143 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7144 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7145
64a7ec06 7146 switch (type) {
37b96e98 7147 case INTR_TYPE_NMI_INTR:
3ab66e8a 7148 vcpu->arch.nmi_injected = true;
668f612f 7149 /*
7b4a25cb 7150 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7151 * Clear bit "block by NMI" before VM entry if a NMI
7152 * delivery faulted.
668f612f 7153 */
3ab66e8a 7154 vmx_set_nmi_mask(vcpu, false);
37b96e98 7155 break;
37b96e98 7156 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7157 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7158 /* fall through */
7159 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7160 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7161 u32 err = vmcs_read32(error_code_field);
851eb667 7162 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7163 } else
851eb667 7164 kvm_requeue_exception(vcpu, vector);
37b96e98 7165 break;
66fd3f7f 7166 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7167 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7168 /* fall through */
37b96e98 7169 case INTR_TYPE_EXT_INTR:
3ab66e8a 7170 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7171 break;
7172 default:
7173 break;
f7d9238f 7174 }
cf393f75
AK		 7175}
7176
83422e17
AK		 7177static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7178{
3ab66e8a 7179 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7180 VM_EXIT_INSTRUCTION_LEN,
7181 IDT_VECTORING_ERROR_CODE);
7182}
7183
b463a6f7
AK		 7184static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7185{
3ab66e8a 7186 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7187 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7188 VM_ENTRY_INSTRUCTION_LEN,
7189 VM_ENTRY_EXCEPTION_ERROR_CODE);
7190
7191 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7192}
7193
d7cd9796
GN		 7194static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7195{
7196 int i, nr_msrs;
7197 struct perf_guest_switch_msr *msrs;
7198
7199 msrs = perf_guest_get_msrs(&nr_msrs);
7200
7201 if (!msrs)
7202 return;
7203
7204 for (i = 0; i < nr_msrs; i++)
7205 if (msrs[i].host == msrs[i].guest)
7206 clear_atomic_switch_msr(vmx, msrs[i].msr);
7207 else
7208 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7209 msrs[i].host);
7210}
7211
a3b5ba49 7212static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7213{
a2fa3e9f 7214 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7215 unsigned long debugctlmsr;
104f226b
AK		 7216
7217 /* Record the guest's net vcpu time for enforced NMI injections. */
7218 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7219 vmx->entry_time = ktime_get();
7220
7221 /* Don't enter VMX if guest state is invalid, let the exit handler
7222 start emulation until we arrive back to a valid state */
14168786 7223 if (vmx->emulation_required)
104f226b
AK		 7224 return;
7225
012f83cb
AG		 7226 if (vmx->nested.sync_shadow_vmcs) {
7227 copy_vmcs12_to_shadow(vmx);
7228 vmx->nested.sync_shadow_vmcs = false;
7229 }
7230
104f226b
AK		 7231 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7232 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7233 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7234 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7235
7236 /* When single-stepping over STI and MOV SS, we must clear the
7237 * corresponding interruptibility bits in the guest state. Otherwise
7238 * vmentry fails as it then expects bit 14 (BS) in pending debug
7239 * exceptions being set, but that's not correct for the guest debugging
7240 * case. */
7241 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7242 vmx_set_interrupt_shadow(vcpu, 0);
7243
d7cd9796 7244 atomic_switch_perf_msrs(vmx);
2a7921b7 7245 debugctlmsr = get_debugctlmsr();
d7cd9796 7246
7854cbca
ACL		 7247 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7248 nested_adjust_preemption_timer(vcpu);
d462b819 7249 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7250 asm(
6aa8b732 7251 /* Store host registers */
b188c81f
AK		 7252 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7253 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7254 "push %%" _ASM_CX " \n\t"
7255 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7256 "je 1f \n\t"
b188c81f 7257 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7258 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7259 "1: \n\t"
d3edefc0 7260 /* Reload cr2 if changed */
b188c81f
AK		 7261 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7262 "mov %%cr2, %%" _ASM_DX " \n\t"
7263 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7264 "je 2f \n\t"
b188c81f 7265 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7266 "2: \n\t"
6aa8b732 7267 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7268 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7269 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7270 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7271 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7272 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7273 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7274 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7275 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7276#ifdef CONFIG_X86_64
e08aa78a
AK		 7277 "mov %c[r8](%0), %%r8 \n\t"
7278 "mov %c[r9](%0), %%r9 \n\t"
7279 "mov %c[r10](%0), %%r10 \n\t"
7280 "mov %c[r11](%0), %%r11 \n\t"
7281 "mov %c[r12](%0), %%r12 \n\t"
7282 "mov %c[r13](%0), %%r13 \n\t"
7283 "mov %c[r14](%0), %%r14 \n\t"
7284 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7285#endif
b188c81f 7286 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7287
6aa8b732 7288 /* Enter guest mode */
83287ea4 7289 "jne 1f \n\t"
4ecac3fd 7290 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7291 "jmp 2f \n\t"
7292 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7293 "2: "
6aa8b732 7294 /* Save guest registers, load host registers, keep flags */
b188c81f 7295 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7296 "pop %0 \n\t"
b188c81f
AK		 7297 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7298 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7299 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7300 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7301 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7302 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7303 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7304#ifdef CONFIG_X86_64
e08aa78a
AK		 7305 "mov %%r8, %c[r8](%0) \n\t"
7306 "mov %%r9, %c[r9](%0) \n\t"
7307 "mov %%r10, %c[r10](%0) \n\t"
7308 "mov %%r11, %c[r11](%0) \n\t"
7309 "mov %%r12, %c[r12](%0) \n\t"
7310 "mov %%r13, %c[r13](%0) \n\t"
7311 "mov %%r14, %c[r14](%0) \n\t"
7312 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7313#endif
b188c81f
AK		 7314 "mov %%cr2, %%" _ASM_AX " \n\t"
7315 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7316
b188c81f 7317 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7318 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7319 ".pushsection .rodata \n\t"
7320 ".global vmx_return \n\t"
7321 "vmx_return: " _ASM_PTR " 2b \n\t"
7322 ".popsection"
e08aa78a 7323 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7324 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7325 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7326 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7327 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7328 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7329 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7330 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7331 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7332 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7333 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7334#ifdef CONFIG_X86_64
ad312c7c
ZX		 7335 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7336 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7337 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7338 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7339 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7340 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7341 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7342 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7343#endif
40712fae
AK		 7344 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7345 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7346 : "cc", "memory"
7347#ifdef CONFIG_X86_64
b188c81f 7348 , "rax", "rbx", "rdi", "rsi"
c2036300 7349 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7350#else
7351 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7352#endif
7353 );
6aa8b732 7354
2a7921b7
GN		 7355 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7356 if (debugctlmsr)
7357 update_debugctlmsr(debugctlmsr);
7358
aa67f609
AK		 7359#ifndef CONFIG_X86_64
7360 /*
7361 * The sysexit path does not restore ds/es, so we must set them to
7362 * a reasonable value ourselves.
7363 *
7364 * We can't defer this to vmx_load_host_state() since that function
7365 * may be executed in interrupt context, which saves and restore segments
7366 * around it, nullifying its effect.
7367 */
7368 loadsegment(ds, __USER_DS);
7369 loadsegment(es, __USER_DS);
7370#endif
7371
6de4f3ad 7372 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7373 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7374 | (1 << VCPU_EXREG_CPL)
aff48baa 7375 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7376 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7377 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7378 vcpu->arch.regs_dirty = 0;
7379
1155f76a
AK		 7380 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7381
d462b819 7382 vmx->loaded_vmcs->launched = 1;
1b6269db 7383
51aa01d1 7384 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7385 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7386
e0b890d3
GN		 7387 /*
7388 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7389 * we did not inject a still-pending event to L1 now because of
7390 * nested_run_pending, we need to re-enable this bit.
7391 */
7392 if (vmx->nested.nested_run_pending)
7393 kvm_make_request(KVM_REQ_EVENT, vcpu);
7394
7395 vmx->nested.nested_run_pending = 0;
7396
51aa01d1
AK		 7397 vmx_complete_atomic_exit(vmx);
7398 vmx_recover_nmi_blocking(vmx);
cf393f75 7399 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7400}
7401
6aa8b732
AK		 7402static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7403{
fb3f0f51
RR		 7404 struct vcpu_vmx *vmx = to_vmx(vcpu);
7405
cdbecfc3 7406 free_vpid(vmx);
d462b819 7407 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7408 free_nested(vmx);
fb3f0f51
RR		 7409 kfree(vmx->guest_msrs);
7410 kvm_vcpu_uninit(vcpu);
a4770347 7411 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7412}
7413
fb3f0f51 7414static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7415{
fb3f0f51 7416 int err;
c16f862d 7417 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7418 int cpu;
6aa8b732 7419
a2fa3e9f 7420 if (!vmx)
fb3f0f51
RR		 7421 return ERR_PTR(-ENOMEM);
7422
2384d2b3
SY		 7423 allocate_vpid(vmx);
7424
fb3f0f51
RR		 7425 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7426 if (err)
7427 goto free_vcpu;
965b58a5 7428
a2fa3e9f 7429 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7430 err = -ENOMEM;
fb3f0f51 7431 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7432 goto uninit_vcpu;
7433 }
965b58a5 7434
d462b819
NHE		 7435 vmx->loaded_vmcs = &vmx->vmcs01;
7436 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7437 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7438 goto free_msrs;
d462b819
NHE		 7439 if (!vmm_exclusive)
7440 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7441 loaded_vmcs_init(vmx->loaded_vmcs);
7442 if (!vmm_exclusive)
7443 kvm_cpu_vmxoff();
a2fa3e9f 7444
15ad7146
AK		 7445 cpu = get_cpu();
7446 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7447 vmx->vcpu.cpu = cpu;
8b9cf98c 7448 err = vmx_vcpu_setup(vmx);
fb3f0f51 7449 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7450 put_cpu();
fb3f0f51
RR		 7451 if (err)
7452 goto free_vmcs;
a63cb560 7453 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7454 err = alloc_apic_access_page(kvm);
7455 if (err)
5e4a0b3c 7456 goto free_vmcs;
a63cb560 7457 }
fb3f0f51 7458
b927a3ce
SY		 7459 if (enable_ept) {
7460 if (!kvm->arch.ept_identity_map_addr)
7461 kvm->arch.ept_identity_map_addr =
7462 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7463 err = -ENOMEM;
b7ebfb05
SY		 7464 if (alloc_identity_pagetable(kvm) != 0)
7465 goto free_vmcs;
93ea5388
GN		 7466 if (!init_rmode_identity_map(kvm))
7467 goto free_vmcs;
b927a3ce 7468 }
b7ebfb05 7469
a9d30f33
NHE		 7470 vmx->nested.current_vmptr = -1ull;
7471 vmx->nested.current_vmcs12 = NULL;
7472
fb3f0f51
RR		 7473 return &vmx->vcpu;
7474
7475free_vmcs:
5f3fbc34 7476 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7477free_msrs:
fb3f0f51
RR		 7478 kfree(vmx->guest_msrs);
7479uninit_vcpu:
7480 kvm_vcpu_uninit(&vmx->vcpu);
7481free_vcpu:
cdbecfc3 7482 free_vpid(vmx);
a4770347 7483 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7484 return ERR_PTR(err);
6aa8b732
AK		 7485}
7486
002c7f7c
YS		 7487static void __init vmx_check_processor_compat(void *rtn)
7488{
7489 struct vmcs_config vmcs_conf;
7490
7491 *(int *)rtn = 0;
7492 if (setup_vmcs_config(&vmcs_conf) < 0)
7493 *(int *)rtn = -EIO;
7494 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7495 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7496 smp_processor_id());
7497 *(int *)rtn = -EIO;
7498 }
7499}
7500
67253af5
SY		 7501static int get_ept_level(void)
7502{
7503 return VMX_EPT_DEFAULT_GAW + 1;
7504}
7505
4b12f0de 7506static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7507{
4b12f0de
SY		 7508 u64 ret;
7509
522c68c4
SY		 7510 /* For VT-d and EPT combination
7511 * 1. MMIO: always map as UC
7512 * 2. EPT with VT-d:
7513 * a. VT-d without snooping control feature: can't guarantee the
7514 * result, try to trust guest.
7515 * b. VT-d with snooping control feature: snooping control feature of
7516 * VT-d engine can guarantee the cache correctness. Just set it
7517 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7518 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7519 * consistent with host MTRR
7520 */
4b12f0de
SY		 7521 if (is_mmio)
7522 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7523 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7524 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7525 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7526 else
522c68c4 7527 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7528 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7529
7530 return ret;
64d4d521
SY		 7531}
7532
17cc3935 7533static int vmx_get_lpage_level(void)
344f414f 7534{
878403b7
SY		 7535 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7536 return PT_DIRECTORY_LEVEL;
7537 else
7538 /* For shadow and EPT supported 1GB page */
7539 return PT_PDPE_LEVEL;
344f414f
JR		 7540}
7541
0e851880
SY		 7542static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7543{
4e47c7a6
SY		 7544 struct kvm_cpuid_entry2 *best;
7545 struct vcpu_vmx *vmx = to_vmx(vcpu);
7546 u32 exec_control;
7547
7548 vmx->rdtscp_enabled = false;
7549 if (vmx_rdtscp_supported()) {
7550 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7551 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7552 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7553 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7554 vmx->rdtscp_enabled = true;
7555 else {
7556 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7557 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7558 exec_control);
7559 }
7560 }
7561 }
ad756a16 7562
ad756a16
MJ		 7563 /* Exposing INVPCID only when PCID is exposed */
7564 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7565 if (vmx_invpcid_supported() &&
4f977045 7566 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7567 guest_cpuid_has_pcid(vcpu)) {
29282fde 7568 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7569 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7570 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7571 exec_control);
7572 } else {
29282fde
TI		 7573 if (cpu_has_secondary_exec_ctrls()) {
7574 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7575 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7576 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7577 exec_control);
7578 }
ad756a16 7579 if (best)
4f977045 7580 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7581 }
0e851880
SY		 7582}
7583
d4330ef2
JR		 7584static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7585{
7b8050f5
NHE		 7586 if (func == 1 && nested)
7587 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7588}
7589
25d92081
YZ		 7590static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7591 struct x86_exception *fault)
7592{
7593 struct vmcs12 *vmcs12;
7594 nested_vmx_vmexit(vcpu);
7595 vmcs12 = get_vmcs12(vcpu);
7596
7597 if (fault->error_code & PFERR_RSVD_MASK)
7598 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7599 else
7600 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7601 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7602 vmcs12->guest_physical_address = fault->address;
7603}
7604
155a97a3
NHE		 7605/* Callbacks for nested_ept_init_mmu_context: */
7606
7607static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7608{
7609 /* return the page table to be shadowed - in our case, EPT12 */
7610 return get_vmcs12(vcpu)->ept_pointer;
7611}
7612
8a3c1a33 7613static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7614{
8a3c1a33 7615 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7616 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7617
7618 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7619 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7620 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7621
7622 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7623}
7624
7625static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7626{
7627 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7628}
7629
feaf0c7d
GN		 7630static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7631 struct x86_exception *fault)
7632{
7633 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7634
7635 WARN_ON(!is_guest_mode(vcpu));
7636
7637 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7638 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7639 nested_vmx_vmexit(vcpu);
7640 else
7641 kvm_inject_page_fault(vcpu, fault);
7642}
7643
fe3ef05c
NHE		 7644/*
7645 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7646 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7647 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7648 * guest in a way that will both be appropriate to L1's requests, and our
7649 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7650 * function also has additional necessary side-effects, like setting various
7651 * vcpu->arch fields.
7652 */
7653static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7654{
7655 struct vcpu_vmx *vmx = to_vmx(vcpu);
7656 u32 exec_control;
7854cbca 7657 u32 exit_control;
fe3ef05c
NHE		 7658
7659 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7660 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7661 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7662 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7663 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7664 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7665 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7666 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7667 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7668 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7669 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7670 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7671 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7672 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7673 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7674 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7675 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7676 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7677 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7678 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7679 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7680 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7681 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7682 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7683 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7684 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7685 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7686 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7687 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7688 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7689 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7690 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7691 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7692 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7693 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7694 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7695
7696 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7697 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7698 vmcs12->vm_entry_intr_info_field);
7699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7700 vmcs12->vm_entry_exception_error_code);
7701 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7702 vmcs12->vm_entry_instruction_len);
7703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7704 vmcs12->guest_interruptibility_info);
fe3ef05c 7705 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7706 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7707 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7708 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7709 vmcs12->guest_pending_dbg_exceptions);
7710 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7711 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7712
7713 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7714
7715 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7716 (vmcs_config.pin_based_exec_ctrl |
7717 vmcs12->pin_based_vm_exec_control));
7718
0238ea91
JK		 7719 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7720 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7721 vmcs12->vmx_preemption_timer_value);
7722
fe3ef05c
NHE		 7723 /*
7724 * Whether page-faults are trapped is determined by a combination of
7725 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7726 * If enable_ept, L0 doesn't care about page faults and we should
7727 * set all of these to L1's desires. However, if !enable_ept, L0 does
7728 * care about (at least some) page faults, and because it is not easy
7729 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7730 * to exit on each and every L2 page fault. This is done by setting
7731 * MASK=MATCH=0 and (see below) EB.PF=1.
7732 * Note that below we don't need special code to set EB.PF beyond the
7733 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7734 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7735 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7736 *
7737 * A problem with this approach (when !enable_ept) is that L1 may be
7738 * injected with more page faults than it asked for. This could have
7739 * caused problems, but in practice existing hypervisors don't care.
7740 * To fix this, we will need to emulate the PFEC checking (on the L1
7741 * page tables), using walk_addr(), when injecting PFs to L1.
7742 */
7743 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7744 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7745 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7746 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7747
7748 if (cpu_has_secondary_exec_ctrls()) {
7749 u32 exec_control = vmx_secondary_exec_control(vmx);
7750 if (!vmx->rdtscp_enabled)
7751 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7752 /* Take the following fields only from vmcs12 */
7753 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7754 if (nested_cpu_has(vmcs12,
7755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7756 exec_control |= vmcs12->secondary_vm_exec_control;
7757
7758 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7759 /*
7760 * Translate L1 physical address to host physical
7761 * address for vmcs02. Keep the page pinned, so this
7762 * physical address remains valid. We keep a reference
7763 * to it so we can release it later.
7764 */
7765 if (vmx->nested.apic_access_page) /* shouldn't happen */
7766 nested_release_page(vmx->nested.apic_access_page);
7767 vmx->nested.apic_access_page =
7768 nested_get_page(vcpu, vmcs12->apic_access_addr);
7769 /*
7770 * If translation failed, no matter: This feature asks
7771 * to exit when accessing the given address, and if it
7772 * can never be accessed, this feature won't do
7773 * anything anyway.
7774 */
7775 if (!vmx->nested.apic_access_page)
7776 exec_control &=
7777 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7778 else
7779 vmcs_write64(APIC_ACCESS_ADDR,
7780 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7781 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7782 exec_control |=
7783 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7784 vmcs_write64(APIC_ACCESS_ADDR,
7785 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7786 }
7787
7788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7789 }
7790
7791
7792 /*
7793 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7794 * Some constant fields are set here by vmx_set_constant_host_state().
7795 * Other fields are different per CPU, and will be set later when
7796 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7797 */
a547c6db 7798 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7799
7800 /*
7801 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7802 * entry, but only if the current (host) sp changed from the value
7803 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7804 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7805 * here we just force the write to happen on entry.
7806 */
7807 vmx->host_rsp = 0;
7808
7809 exec_control = vmx_exec_control(vmx); /* L0's desires */
7810 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7811 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7812 exec_control &= ~CPU_BASED_TPR_SHADOW;
7813 exec_control |= vmcs12->cpu_based_vm_exec_control;
7814 /*
7815 * Merging of IO and MSR bitmaps not currently supported.
7816 * Rather, exit every time.
7817 */
7818 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7819 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7820 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7821
7822 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7823
7824 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7825 * bitwise-or of what L1 wants to trap for L2, and what we want to
7826 * trap. Note that CR0.TS also needs updating - we do this later.
7827 */
7828 update_exception_bitmap(vcpu);
7829 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7830 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7831
8049d651
NHE		 7832 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7833 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7834 * bits are further modified by vmx_set_efer() below.
7835 */
7854cbca
ACL		 7836 exit_control = vmcs_config.vmexit_ctrl;
7837 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7838 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7839 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7840
7841 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7842 * emulated by vmx_set_efer(), below.
7843 */
2961e876 7844 vm_entry_controls_init(vmx,
8049d651
NHE		 7845 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7846 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7847 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7848
44811c02 7849 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7850 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7851 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7852 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7853 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7854
7855
7856 set_cr4_guest_host_mask(vmx);
7857
27fc51b2
NHE		 7858 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7859 vmcs_write64(TSC_OFFSET,
7860 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7861 else
7862 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7863
7864 if (enable_vpid) {
7865 /*
7866 * Trivially support vpid by letting L2s share their parent
7867 * L1's vpid. TODO: move to a more elaborate solution, giving
7868 * each L2 its own vpid and exposing the vpid feature to L1.
7869 */
7870 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7871 vmx_flush_tlb(vcpu);
7872 }
7873
155a97a3
NHE		 7874 if (nested_cpu_has_ept(vmcs12)) {
7875 kvm_mmu_unload(vcpu);
7876 nested_ept_init_mmu_context(vcpu);
7877 }
7878
fe3ef05c
NHE		 7879 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7880 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7881 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7882 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7883 else
7884 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7885 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7886 vmx_set_efer(vcpu, vcpu->arch.efer);
7887
7888 /*
7889 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7890 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7891 * The CR0_READ_SHADOW is what L2 should have expected to read given
7892 * the specifications by L1; It's not enough to take
7893 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7894 * have more bits than L1 expected.
7895 */
7896 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7897 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7898
7899 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7900 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7901
7902 /* shadow page tables on either EPT or shadow page tables */
7903 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7904 kvm_mmu_reset_context(vcpu);
7905
feaf0c7d
GN		 7906 if (!enable_ept)
7907 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7908
3633cfc3
NHE		 7909 /*
7910 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7911 */
7912 if (enable_ept) {
7913 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7914 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7915 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7916 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7917 }
7918
fe3ef05c
NHE		 7919 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7920 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7921}
7922
cd232ad0
NHE		 7923/*
7924 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7925 * for running an L2 nested guest.
7926 */
7927static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7928{
7929 struct vmcs12 *vmcs12;
7930 struct vcpu_vmx *vmx = to_vmx(vcpu);
7931 int cpu;
7932 struct loaded_vmcs *vmcs02;
384bb783 7933 bool ia32e;
cd232ad0
NHE		 7934
7935 if (!nested_vmx_check_permission(vcpu) ||
7936 !nested_vmx_check_vmcs12(vcpu))
7937 return 1;
7938
7939 skip_emulated_instruction(vcpu);
7940 vmcs12 = get_vmcs12(vcpu);
7941
012f83cb
AG		 7942 if (enable_shadow_vmcs)
7943 copy_shadow_to_vmcs12(vmx);
7944
7c177938
NHE		 7945 /*
7946 * The nested entry process starts with enforcing various prerequisites
7947 * on vmcs12 as required by the Intel SDM, and act appropriately when
7948 * they fail: As the SDM explains, some conditions should cause the
7949 * instruction to fail, while others will cause the instruction to seem
7950 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7951 * To speed up the normal (success) code path, we should avoid checking
7952 * for misconfigurations which will anyway be caught by the processor
7953 * when using the merged vmcs02.
7954 */
7955 if (vmcs12->launch_state == launch) {
7956 nested_vmx_failValid(vcpu,
7957 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7958 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7959 return 1;
7960 }
7961
6dfacadd
JK		 7962 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7963 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7964 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7965 return 1;
7966 }
7967
7c177938
NHE		 7968 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7969 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7970 /*TODO: Also verify bits beyond physical address width are 0*/
7971 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7972 return 1;
7973 }
7974
7975 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7976 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7977 /*TODO: Also verify bits beyond physical address width are 0*/
7978 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7979 return 1;
7980 }
7981
7982 if (vmcs12->vm_entry_msr_load_count > 0 ||
7983 vmcs12->vm_exit_msr_load_count > 0 ||
7984 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7985 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7986 __func__);
7c177938
NHE		 7987 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7988 return 1;
7989 }
7990
7991 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7992 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7993 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7994 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7995 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7996 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7997 !vmx_control_verify(vmcs12->vm_exit_controls,
7998 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7999 !vmx_control_verify(vmcs12->vm_entry_controls,
8000 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8001 {
8002 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8003 return 1;
8004 }
8005
8006 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8007 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8008 nested_vmx_failValid(vcpu,
8009 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8010 return 1;
8011 }
8012
92fbc7b1 8013 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8014 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8015 nested_vmx_entry_failure(vcpu, vmcs12,
8016 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8017 return 1;
8018 }
8019 if (vmcs12->vmcs_link_pointer != -1ull) {
8020 nested_vmx_entry_failure(vcpu, vmcs12,
8021 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8022 return 1;
8023 }
8024
384bb783 8025 /*
cb0c8cda 8026 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8027 * are performed on the field for the IA32_EFER MSR:
8028 * - Bits reserved in the IA32_EFER MSR must be 0.
8029 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8030 * the IA-32e mode guest VM-exit control. It must also be identical
8031 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8032 * CR0.PG) is 1.
8033 */
8034 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8035 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8036 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8037 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8038 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8039 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8040 nested_vmx_entry_failure(vcpu, vmcs12,
8041 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8042 return 1;
8043 }
8044 }
8045
8046 /*
8047 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8048 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8049 * the values of the LMA and LME bits in the field must each be that of
8050 * the host address-space size VM-exit control.
8051 */
8052 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8053 ia32e = (vmcs12->vm_exit_controls &
8054 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8055 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8056 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8057 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8058 nested_vmx_entry_failure(vcpu, vmcs12,
8059 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8060 return 1;
8061 }
8062 }
8063
7c177938
NHE		 8064 /*
8065 * We're finally done with prerequisite checking, and can start with
8066 * the nested entry.
8067 */
8068
cd232ad0
NHE		 8069 vmcs02 = nested_get_current_vmcs02(vmx);
8070 if (!vmcs02)
8071 return -ENOMEM;
8072
8073 enter_guest_mode(vcpu);
8074
e0b890d3
GN		 8075 vmx->nested.nested_run_pending = 1;
8076
cd232ad0
NHE		 8077 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8078
8079 cpu = get_cpu();
8080 vmx->loaded_vmcs = vmcs02;
8081 vmx_vcpu_put(vcpu);
8082 vmx_vcpu_load(vcpu, cpu);
8083 vcpu->cpu = cpu;
8084 put_cpu();
8085
36c3cc42
JK		 8086 vmx_segment_cache_clear(vmx);
8087
cd232ad0
NHE		 8088 vmcs12->launch_state = 1;
8089
8090 prepare_vmcs02(vcpu, vmcs12);
8091
6dfacadd
JK		 8092 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8093 return kvm_emulate_halt(vcpu);
8094
cd232ad0
NHE		 8095 /*
8096 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8097 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8098 * returned as far as L1 is concerned. It will only return (and set
8099 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8100 */
8101 return 1;
8102}
8103
4704d0be
NHE		 8104/*
8105 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8106 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8107 * This function returns the new value we should put in vmcs12.guest_cr0.
8108 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8109 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8110 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8111 * didn't trap the bit, because if L1 did, so would L0).
8112 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8113 * been modified by L2, and L1 knows it. So just leave the old value of
8114 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8115 * isn't relevant, because if L0 traps this bit it can set it to anything.
8116 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8117 * changed these bits, and therefore they need to be updated, but L0
8118 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8119 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8120 */
8121static inline unsigned long
8122vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8123{
8124 return
8125 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8126 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8127 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8128 vcpu->arch.cr0_guest_owned_bits));
8129}
8130
8131static inline unsigned long
8132vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8133{
8134 return
8135 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8136 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8137 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8138 vcpu->arch.cr4_guest_owned_bits));
8139}
8140
5f3d5799
JK		 8141static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8142 struct vmcs12 *vmcs12)
8143{
8144 u32 idt_vectoring;
8145 unsigned int nr;
8146
851eb667 8147 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8148 nr = vcpu->arch.exception.nr;
8149 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8150
8151 if (kvm_exception_is_soft(nr)) {
8152 vmcs12->vm_exit_instruction_len =
8153 vcpu->arch.event_exit_inst_len;
8154 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8155 } else
8156 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8157
8158 if (vcpu->arch.exception.has_error_code) {
8159 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8160 vmcs12->idt_vectoring_error_code =
8161 vcpu->arch.exception.error_code;
8162 }
8163
8164 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8165 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8166 vmcs12->idt_vectoring_info_field =
8167 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8168 } else if (vcpu->arch.interrupt.pending) {
8169 nr = vcpu->arch.interrupt.nr;
8170 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8171
8172 if (vcpu->arch.interrupt.soft) {
8173 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8174 vmcs12->vm_entry_instruction_len =
8175 vcpu->arch.event_exit_inst_len;
8176 } else
8177 idt_vectoring |= INTR_TYPE_EXT_INTR;
8178
8179 vmcs12->idt_vectoring_info_field = idt_vectoring;
8180 }
8181}
8182
4704d0be
NHE		 8183/*
8184 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8185 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8186 * and this function updates it to reflect the changes to the guest state while
8187 * L2 was running (and perhaps made some exits which were handled directly by L0
8188 * without going back to L1), and to reflect the exit reason.
8189 * Note that we do not have to copy here all VMCS fields, just those that
8190 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8191 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8192 * which already writes to vmcs12 directly.
8193 */
733568f9 8194static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8195{
8196 /* update guest state fields: */
8197 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8198 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8199
8200 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8201 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8202 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8203 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8204
8205 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8206 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8207 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8208 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8209 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8210 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8211 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8212 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8213 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8214 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8215 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8216 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8217 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8218 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8219 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8220 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8221 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8222 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8223 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8224 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8225 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8226 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8227 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8228 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8229 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8230 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8231 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8232 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8233 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8234 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8235 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8236 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8237 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8238 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8239 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8240 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8241
4704d0be
NHE		 8242 vmcs12->guest_interruptibility_info =
8243 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8244 vmcs12->guest_pending_dbg_exceptions =
8245 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8246
7854cbca
ACL		 8247 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8248 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8249 vmcs12->vmx_preemption_timer_value =
8250 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8251
3633cfc3
NHE		 8252 /*
8253 * In some cases (usually, nested EPT), L2 is allowed to change its
8254 * own CR3 without exiting. If it has changed it, we must keep it.
8255 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8256 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8257 *
8258 * Additionally, restore L2's PDPTR to vmcs12.
8259 */
8260 if (enable_ept) {
8261 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8262 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8263 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8264 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8265 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8266 }
8267
c18911a2
JK		 8268 vmcs12->vm_entry_controls =
8269 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8270 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8271
4704d0be
NHE		 8272 /* TODO: These cannot have changed unless we have MSR bitmaps and
8273 * the relevant bit asks not to trap the change */
8274 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8275 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8276 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8277 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8278 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8279 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8280 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8281 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8282
8283 /* update exit information fields: */
8284
957c897e 8285 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8286 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8287
8288 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8289 if ((vmcs12->vm_exit_intr_info &
8290 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8291 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8292 vmcs12->vm_exit_intr_error_code =
8293 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8294 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8295 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8296 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8297
5f3d5799
JK		 8298 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8299 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8300 * instead of reading the real value. */
4704d0be 8301 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8302
8303 /*
8304 * Transfer the event that L0 or L1 may wanted to inject into
8305 * L2 to IDT_VECTORING_INFO_FIELD.
8306 */
8307 vmcs12_save_pending_event(vcpu, vmcs12);
8308 }
8309
8310 /*
8311 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8312 * preserved above and would only end up incorrectly in L1.
8313 */
8314 vcpu->arch.nmi_injected = false;
8315 kvm_clear_exception_queue(vcpu);
8316 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8317}
8318
8319/*
8320 * A part of what we need to when the nested L2 guest exits and we want to
8321 * run its L1 parent, is to reset L1's guest state to the host state specified
8322 * in vmcs12.
8323 * This function is to be called not only on normal nested exit, but also on
8324 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8325 * Failures During or After Loading Guest State").
8326 * This function should be called when the active VMCS is L1's (vmcs01).
8327 */
733568f9
JK		 8328static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8329 struct vmcs12 *vmcs12)
4704d0be 8330{
21feb4eb
ACL		 8331 struct kvm_segment seg;
8332
4704d0be
NHE		 8333 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8334 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8335 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8336 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8337 else
8338 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8339 vmx_set_efer(vcpu, vcpu->arch.efer);
8340
8341 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8342 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8343 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8344 /*
8345 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8346 * actually changed, because it depends on the current state of
8347 * fpu_active (which may have changed).
8348 * Note that vmx_set_cr0 refers to efer set above.
8349 */
9e3e4dbf 8350 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8351 /*
8352 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8353 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8354 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8355 */
8356 update_exception_bitmap(vcpu);
8357 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8358 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8359
8360 /*
8361 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8362 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8363 */
8364 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8365 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8366
155a97a3
NHE		 8367 if (nested_cpu_has_ept(vmcs12))
8368 nested_ept_uninit_mmu_context(vcpu);
8369
4704d0be
NHE		 8370 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8371 kvm_mmu_reset_context(vcpu);
8372
feaf0c7d
GN		 8373 if (!enable_ept)
8374 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8375
4704d0be
NHE		 8376 if (enable_vpid) {
8377 /*
8378 * Trivially support vpid by letting L2s share their parent
8379 * L1's vpid. TODO: move to a more elaborate solution, giving
8380 * each L2 its own vpid and exposing the vpid feature to L1.
8381 */
8382 vmx_flush_tlb(vcpu);
8383 }
8384
8385
8386 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8387 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8388 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8389 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8390 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8391
44811c02 8392 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8393 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8394 vcpu->arch.pat = vmcs12->host_ia32_pat;
8395 }
4704d0be
NHE		 8396 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8397 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8398 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8399
21feb4eb
ACL		 8400 /* Set L1 segment info according to Intel SDM
8401 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8402 seg = (struct kvm_segment) {
8403 .base = 0,
8404 .limit = 0xFFFFFFFF,
8405 .selector = vmcs12->host_cs_selector,
8406 .type = 11,
8407 .present = 1,
8408 .s = 1,
8409 .g = 1
8410 };
8411 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8412 seg.l = 1;
8413 else
8414 seg.db = 1;
8415 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8416 seg = (struct kvm_segment) {
8417 .base = 0,
8418 .limit = 0xFFFFFFFF,
8419 .type = 3,
8420 .present = 1,
8421 .s = 1,
8422 .db = 1,
8423 .g = 1
8424 };
8425 seg.selector = vmcs12->host_ds_selector;
8426 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8427 seg.selector = vmcs12->host_es_selector;
8428 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8429 seg.selector = vmcs12->host_ss_selector;
8430 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8431 seg.selector = vmcs12->host_fs_selector;
8432 seg.base = vmcs12->host_fs_base;
8433 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8434 seg.selector = vmcs12->host_gs_selector;
8435 seg.base = vmcs12->host_gs_base;
8436 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8437 seg = (struct kvm_segment) {
205befd9 8438 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8439 .limit = 0x67,
8440 .selector = vmcs12->host_tr_selector,
8441 .type = 11,
8442 .present = 1
8443 };
8444 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8445
503cd0c5
JK		 8446 kvm_set_dr(vcpu, 7, 0x400);
8447 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8448}
8449
8450/*
8451 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8452 * and modify vmcs12 to make it see what it would expect to see there if
8453 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8454 */
8455static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8456{
8457 struct vcpu_vmx *vmx = to_vmx(vcpu);
8458 int cpu;
8459 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8460
5f3d5799
JK		 8461 /* trying to cancel vmlaunch/vmresume is a bug */
8462 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8463
4704d0be
NHE		 8464 leave_guest_mode(vcpu);
8465 prepare_vmcs12(vcpu, vmcs12);
8466
8467 cpu = get_cpu();
8468 vmx->loaded_vmcs = &vmx->vmcs01;
8469 vmx_vcpu_put(vcpu);
8470 vmx_vcpu_load(vcpu, cpu);
8471 vcpu->cpu = cpu;
8472 put_cpu();
8473
2961e876
GN		 8474 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8475 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8476 vmx_segment_cache_clear(vmx);
8477
4704d0be
NHE		 8478 /* if no vmcs02 cache requested, remove the one we used */
8479 if (VMCS02_POOL_SIZE == 0)
8480 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8481
8482 load_vmcs12_host_state(vcpu, vmcs12);
8483
27fc51b2 8484 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8485 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8486
8487 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8488 vmx->host_rsp = 0;
8489
8490 /* Unpin physical memory we referred to in vmcs02 */
8491 if (vmx->nested.apic_access_page) {
8492 nested_release_page(vmx->nested.apic_access_page);
8493 vmx->nested.apic_access_page = 0;
8494 }
8495
8496 /*
8497 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8498 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8499 * success or failure flag accordingly.
8500 */
8501 if (unlikely(vmx->fail)) {
8502 vmx->fail = 0;
8503 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8504 } else
8505 nested_vmx_succeed(vcpu);
012f83cb
AG		 8506 if (enable_shadow_vmcs)
8507 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8508}
8509
42124925
JK		 8510/*
8511 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8512 */
8513static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8514{
8515 if (is_guest_mode(vcpu))
8516 nested_vmx_vmexit(vcpu);
8517 free_nested(to_vmx(vcpu));
8518}
8519
7c177938
NHE		 8520/*
8521 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8522 * 23.7 "VM-entry failures during or after loading guest state" (this also
8523 * lists the acceptable exit-reason and exit-qualification parameters).
8524 * It should only be called before L2 actually succeeded to run, and when
8525 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8526 */
8527static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8528 struct vmcs12 *vmcs12,
8529 u32 reason, unsigned long qualification)
8530{
8531 load_vmcs12_host_state(vcpu, vmcs12);
8532 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8533 vmcs12->exit_qualification = qualification;
8534 nested_vmx_succeed(vcpu);
012f83cb
AG		 8535 if (enable_shadow_vmcs)
8536 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8537}
8538
8a76d7f2
JR		 8539static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8540 struct x86_instruction_info *info,
8541 enum x86_intercept_stage stage)
8542{
8543 return X86EMUL_CONTINUE;
8544}
8545
cbdd1bea 8546static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8547 .cpu_has_kvm_support = cpu_has_kvm_support,
8548 .disabled_by_bios = vmx_disabled_by_bios,
8549 .hardware_setup = hardware_setup,
8550 .hardware_unsetup = hardware_unsetup,
002c7f7c 8551 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8552 .hardware_enable = hardware_enable,
8553 .hardware_disable = hardware_disable,
04547156 8554 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8555
8556 .vcpu_create = vmx_create_vcpu,
8557 .vcpu_free = vmx_free_vcpu,
04d2cc77 8558 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8559
04d2cc77 8560 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8561 .vcpu_load = vmx_vcpu_load,
8562 .vcpu_put = vmx_vcpu_put,
8563
c8639010 8564 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8565 .get_msr = vmx_get_msr,
8566 .set_msr = vmx_set_msr,
8567 .get_segment_base = vmx_get_segment_base,
8568 .get_segment = vmx_get_segment,
8569 .set_segment = vmx_set_segment,
2e4d2653 8570 .get_cpl = vmx_get_cpl,
6aa8b732 8571 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8572 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8573 .decache_cr3 = vmx_decache_cr3,
25c4c276 8574 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8575 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8576 .set_cr3 = vmx_set_cr3,
8577 .set_cr4 = vmx_set_cr4,
6aa8b732 8578 .set_efer = vmx_set_efer,
6aa8b732
AK		 8579 .get_idt = vmx_get_idt,
8580 .set_idt = vmx_set_idt,
8581 .get_gdt = vmx_get_gdt,
8582 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8583 .get_dr6 = vmx_get_dr6,
8584 .set_dr6 = vmx_set_dr6,
020df079 8585 .set_dr7 = vmx_set_dr7,
5fdbf976 8586 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8587 .get_rflags = vmx_get_rflags,
8588 .set_rflags = vmx_set_rflags,
ebcbab4c 8589 .fpu_activate = vmx_fpu_activate,
02daab21 8590 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8591
8592 .tlb_flush = vmx_flush_tlb,
6aa8b732 8593
6aa8b732 8594 .run = vmx_vcpu_run,
6062d012 8595 .handle_exit = vmx_handle_exit,
6aa8b732 8596 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8597 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8598 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8599 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8600 .set_irq = vmx_inject_irq,
95ba8273 8601 .set_nmi = vmx_inject_nmi,
298101da 8602 .queue_exception = vmx_queue_exception,
b463a6f7 8603 .cancel_injection = vmx_cancel_injection,
78646121 8604 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8605 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8606 .get_nmi_mask = vmx_get_nmi_mask,
8607 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8608 .enable_nmi_window = enable_nmi_window,
8609 .enable_irq_window = enable_irq_window,
8610 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8611 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8612 .vm_has_apicv = vmx_vm_has_apicv,
8613 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8614 .hwapic_irr_update = vmx_hwapic_irr_update,
8615 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8616 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8617 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8618
cbc94022 8619 .set_tss_addr = vmx_set_tss_addr,
67253af5 8620 .get_tdp_level = get_ept_level,
4b12f0de 8621 .get_mt_mask = vmx_get_mt_mask,
229456fc 8622
586f9607 8623 .get_exit_info = vmx_get_exit_info,
586f9607 8624
17cc3935 8625 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8626
8627 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8628
8629 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8630 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8631
8632 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8633
8634 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8635
4051b188 8636 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8637 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8638 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8639 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8640 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8641 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8642
8643 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8644
8645 .check_intercept = vmx_check_intercept,
a547c6db 8646 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8647};
8648
8649static int __init vmx_init(void)
8650{
8d14695f 8651 int r, i, msr;
26bb0981
AK		 8652
8653 rdmsrl_safe(MSR_EFER, &host_efer);
8654
8655 for (i = 0; i < NR_VMX_MSR; ++i)
8656 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8657
3e7c73e9 8658 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8659 if (!vmx_io_bitmap_a)
8660 return -ENOMEM;
8661
2106a548
GC		 8662 r = -ENOMEM;
8663
3e7c73e9 8664 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8665 if (!vmx_io_bitmap_b)
fdef3ad1 8666 goto out;
fdef3ad1 8667
5897297b 8668 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8669 if (!vmx_msr_bitmap_legacy)
25c5f225 8670 goto out1;
2106a548 8671
8d14695f
YZ		 8672 vmx_msr_bitmap_legacy_x2apic =
8673 (unsigned long *)__get_free_page(GFP_KERNEL);
8674 if (!vmx_msr_bitmap_legacy_x2apic)
8675 goto out2;
25c5f225 8676
5897297b 8677 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8678 if (!vmx_msr_bitmap_longmode)
8d14695f 8679 goto out3;
2106a548 8680
8d14695f
YZ		 8681 vmx_msr_bitmap_longmode_x2apic =
8682 (unsigned long *)__get_free_page(GFP_KERNEL);
8683 if (!vmx_msr_bitmap_longmode_x2apic)
8684 goto out4;
4607c2d7
AG		 8685 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8686 if (!vmx_vmread_bitmap)
8687 goto out5;
8688
8689 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8690 if (!vmx_vmwrite_bitmap)
8691 goto out6;
8692
8693 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8694 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8695 /* shadowed read/write fields */
8696 for (i = 0; i < max_shadow_read_write_fields; i++) {
8697 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8698 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8699 }
8700 /* shadowed read only fields */
8701 for (i = 0; i < max_shadow_read_only_fields; i++)
8702 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8703
fdef3ad1
HQ		 8704 /*
8705 * Allow direct access to the PC debug port (it is often used for I/O
8706 * delays, but the vmexits simply slow things down).
8707 */
3e7c73e9
AK		 8708 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8709 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8710
3e7c73e9 8711 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8712
5897297b
AK		 8713 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8714 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8715
2384d2b3
SY		 8716 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8717
0ee75bea
AK		 8718 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8719 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8720 if (r)
4607c2d7 8721 goto out7;
25c5f225 8722
8f536b76
ZY		 8723#ifdef CONFIG_KEXEC
8724 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8725 crash_vmclear_local_loaded_vmcss);
8726#endif
8727
5897297b
AK		 8728 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8729 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8730 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8731 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8732 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8733 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8734 memcpy(vmx_msr_bitmap_legacy_x2apic,
8735 vmx_msr_bitmap_legacy, PAGE_SIZE);
8736 memcpy(vmx_msr_bitmap_longmode_x2apic,
8737 vmx_msr_bitmap_longmode, PAGE_SIZE);
8738
01e439be 8739 if (enable_apicv) {
8d14695f
YZ		 8740 for (msr = 0x800; msr <= 0x8ff; msr++)
8741 vmx_disable_intercept_msr_read_x2apic(msr);
8742
8743 /* According SDM, in x2apic mode, the whole id reg is used.
8744 * But in KVM, it only use the highest eight bits. Need to
8745 * intercept it */
8746 vmx_enable_intercept_msr_read_x2apic(0x802);
8747 /* TMCCT */
8748 vmx_enable_intercept_msr_read_x2apic(0x839);
8749 /* TPR */
8750 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8751 /* EOI */
8752 vmx_disable_intercept_msr_write_x2apic(0x80b);
8753 /* SELF-IPI */
8754 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8755 }
fdef3ad1 8756
089d034e 8757 if (enable_ept) {
3f6d8c8a
XH		 8758 kvm_mmu_set_mask_ptes(0ull,
8759 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8760 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8761 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8762 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8763 kvm_enable_tdp();
8764 } else
8765 kvm_disable_tdp();
1439442c 8766
fdef3ad1
HQ		 8767 return 0;
8768
4607c2d7
AG		 8769out7:
8770 free_page((unsigned long)vmx_vmwrite_bitmap);
8771out6:
8772 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8773out5:
8774 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8775out4:
5897297b 8776 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8777out3:
8778 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8779out2:
5897297b 8780 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8781out1:
3e7c73e9 8782 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8783out:
3e7c73e9 8784 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8785 return r;
6aa8b732
AK		 8786}
8787
8788static void __exit vmx_exit(void)
8789{
8d14695f
YZ		 8790 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8791 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8792 free_page((unsigned long)vmx_msr_bitmap_legacy);
8793 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8794 free_page((unsigned long)vmx_io_bitmap_b);
8795 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8796 free_page((unsigned long)vmx_vmwrite_bitmap);
8797 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8798
8f536b76
ZY		 8799#ifdef CONFIG_KEXEC
8800 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8801 synchronize_rcu();
8802#endif
8803
cb498ea2 8804 kvm_exit();
6aa8b732
AK		 8805}
8806
8807module_init(vmx_init)
8808module_exit(vmx_exit)
Linux kernel - Deliverables
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