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[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
476bc001 77static bool __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
8bf00a52 130#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 131#define VMCS02_POOL_SIZE 1
61d2ef2c 132
a2fa3e9f
GH		 133struct vmcs {
134 u32 revision_id;
135 u32 abort;
136 char data[0];
137};
138
d462b819
NHE		 139/*
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
143 */
144struct loaded_vmcs {
145 struct vmcs *vmcs;
146 int cpu;
147 int launched;
148 struct list_head loaded_vmcss_on_cpu_link;
149};
150
26bb0981
AK		 151struct shared_msr_entry {
152 unsigned index;
153 u64 data;
d5696725 154 u64 mask;
26bb0981
AK		 155};
156
a9d30f33
NHE		 157/*
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
169 */
22bd0358 170typedef u64 natural_width;
a9d30f33
NHE		 171struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
174 */
175 u32 revision_id;
176 u32 abort;
22bd0358 177
27d6c865
NHE		 178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
180
22bd0358
NHE		 181 u64 io_bitmap_a;
182 u64 io_bitmap_b;
183 u64 msr_bitmap;
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
187 u64 tsc_offset;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
190 u64 ept_pointer;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
194 u64 guest_ia32_pat;
195 u64 guest_ia32_efer;
196 u64 guest_ia32_perf_global_ctrl;
197 u64 guest_pdptr0;
198 u64 guest_pdptr1;
199 u64 guest_pdptr2;
200 u64 guest_pdptr3;
201 u64 host_ia32_pat;
202 u64 host_ia32_efer;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
205 /*
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
210 */
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
268 u32 tpr_threshold;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
271 u32 vm_exit_reason;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
278 u32 guest_es_limit;
279 u32 guest_cs_limit;
280 u32 guest_ss_limit;
281 u32 guest_ds_limit;
282 u32 guest_fs_limit;
283 u32 guest_gs_limit;
284 u32 guest_ldtr_limit;
285 u32 guest_tr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
a9d30f33
NHE		 317};
318
319/*
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323 */
324#define VMCS12_REVISION 0x11e57ed0
325
326/*
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
330 */
331#define VMCS12_SIZE 0x1000
332
ff2f6fe9
NHE		 333/* Used to remember the last vmcs02 used for some recently used vmcs12s */
334struct vmcs02_list {
335 struct list_head list;
336 gpa_t vmptr;
337 struct loaded_vmcs vmcs02;
338};
339
ec378aee
NHE		 340/*
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343 */
344struct nested_vmx {
345 /* Has the level1 guest done vmxon? */
346 bool vmxon;
a9d30f33
NHE		 347
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
349 gpa_t current_vmptr;
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 353
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
356 int vmcs02_num;
fe3ef05c 357 u64 vmcs01_tsc_offset;
644d711a
NHE		 358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
fe3ef05c
NHE		 360 /*
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
363 */
364 struct page *apic_access_page;
ec378aee
NHE		 365};
366
a2fa3e9f 367struct vcpu_vmx {
fb3f0f51 368 struct kvm_vcpu vcpu;
313dbd49 369 unsigned long host_rsp;
29bd8a78 370 u8 fail;
69c73028 371 u8 cpl;
9d58b931 372 bool nmi_known_unmasked;
51aa01d1 373 u32 exit_intr_info;
1155f76a 374 u32 idt_vectoring_info;
6de12732 375 ulong rflags;
26bb0981 376 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 377 int nmsrs;
378 int save_nmsrs;
a2fa3e9f 379#ifdef CONFIG_X86_64
44ea2b17
AK		 380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
a2fa3e9f 382#endif
d462b819
NHE		 383 /*
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
387 */
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 391 struct msr_autoload {
392 unsigned nr;
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395 } msr_autoload;
a2fa3e9f
GH		 396 struct {
397 int loaded;
398 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 399#ifdef CONFIG_X86_64
400 u16 ds_sel, es_sel;
401#endif
152d3f2f
LV		 402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
d77c26fc 404 } host_state;
9c8cba37 405 struct {
7ffd92c5 406 int vm86_active;
78ac8b47 407 ulong save_rflags;
7ffd92c5
AK		 408 struct kvm_save_segment {
409 u16 selector;
410 unsigned long base;
411 u32 limit;
412 u32 ar;
413 } tr, es, ds, fs, gs;
9c8cba37 414 } rmode;
2fb92db1
AK		 415 struct {
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
418 } segment_cache;
2384d2b3 419 int vpid;
04fa4d32 420 bool emulation_required;
3b86cd99
JK		 421
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
424 ktime_t entry_time;
425 s64 vnmi_blocked_time;
a0861c02 426 u32 exit_reason;
4e47c7a6
SY		 427
428 bool rdtscp_enabled;
ec378aee
NHE		 429
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
a2fa3e9f
GH		 432};
433
2fb92db1
AK		 434enum segment_cache_field {
435 SEG_FIELD_SEL = 0,
436 SEG_FIELD_BASE = 1,
437 SEG_FIELD_LIMIT = 2,
438 SEG_FIELD_AR = 3,
439
440 SEG_FIELD_NR = 4
441};
442
a2fa3e9f
GH		 443static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444{
fb3f0f51 445 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 446}
447
22bd0358
NHE		 448#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
581};
582static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584static inline short vmcs_field_to_offset(unsigned long field)
585{
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587 return -1;
588 return vmcs_field_to_offset_table[field];
589}
590
a9d30f33
NHE		 591static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592{
593 return to_vmx(vcpu)->nested.current_vmcs12;
594}
595
596static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597{
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
599 if (is_error_page(page)) {
600 kvm_release_page_clean(page);
601 return NULL;
602 }
603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
75880a01 625
6aa8b732
AK		 626static DEFINE_PER_CPU(struct vmcs *, vmxarea);
627static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 628/*
629 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
630 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
631 */
632static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 633static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 634
3e7c73e9
AK		 635static unsigned long *vmx_io_bitmap_a;
636static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 637static unsigned long *vmx_msr_bitmap_legacy;
638static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 639
110312c8 640static bool cpu_has_load_ia32_efer;
8bf00a52 641static bool cpu_has_load_perf_global_ctrl;
110312c8 642
2384d2b3
SY		 643static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
644static DEFINE_SPINLOCK(vmx_vpid_lock);
645
1c3d14fe 646static struct vmcs_config {
6aa8b732
AK		 647 int size;
648 int order;
649 u32 revision_id;
1c3d14fe
YS		 650 u32 pin_based_exec_ctrl;
651 u32 cpu_based_exec_ctrl;
f78e0e2e 652 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 653 u32 vmexit_ctrl;
654 u32 vmentry_ctrl;
655} vmcs_config;
6aa8b732 656
efff9e53 657static struct vmx_capability {
d56f546d
SY		 658 u32 ept;
659 u32 vpid;
660} vmx_capability;
661
6aa8b732
AK		 662#define VMX_SEGMENT_FIELD(seg) \
663 [VCPU_SREG_##seg] = { \
664 .selector = GUEST_##seg##_SELECTOR, \
665 .base = GUEST_##seg##_BASE, \
666 .limit = GUEST_##seg##_LIMIT, \
667 .ar_bytes = GUEST_##seg##_AR_BYTES, \
668 }
669
670static struct kvm_vmx_segment_field {
671 unsigned selector;
672 unsigned base;
673 unsigned limit;
674 unsigned ar_bytes;
675} kvm_vmx_segment_fields[] = {
676 VMX_SEGMENT_FIELD(CS),
677 VMX_SEGMENT_FIELD(DS),
678 VMX_SEGMENT_FIELD(ES),
679 VMX_SEGMENT_FIELD(FS),
680 VMX_SEGMENT_FIELD(GS),
681 VMX_SEGMENT_FIELD(SS),
682 VMX_SEGMENT_FIELD(TR),
683 VMX_SEGMENT_FIELD(LDTR),
684};
685
26bb0981
AK		 686static u64 host_efer;
687
6de4f3ad
AK		 688static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
689
4d56c8a7 690/*
8c06585d 691 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 692 * away by decrementing the array size.
693 */
6aa8b732 694static const u32 vmx_msr_index[] = {
05b3e0c2 695#ifdef CONFIG_X86_64
44ea2b17 696 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 697#endif
8c06585d 698 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 699};
9d8f549d 700#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 701
31299944 702static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 703{
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 706 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 707}
708
31299944 709static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 713 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 714}
715
31299944 716static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 717{
718 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 720 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 721}
722
31299944 723static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 724{
725 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
726 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
727}
728
31299944 729static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 730{
731 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
732 INTR_INFO_VALID_MASK)) ==
733 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
734}
735
31299944 736static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 737{
04547156 738 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 739}
740
31299944 741static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 742{
04547156 743 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 744}
745
31299944 746static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 747{
04547156 748 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 749}
750
31299944 751static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 752{
04547156
SY		 753 return vmcs_config.cpu_based_exec_ctrl &
754 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 755}
756
774ead3a 757static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 758{
04547156
SY		 759 return vmcs_config.cpu_based_2nd_exec_ctrl &
760 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
761}
762
763static inline bool cpu_has_vmx_flexpriority(void)
764{
765 return cpu_has_vmx_tpr_shadow() &&
766 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 767}
768
e799794e
MT		 769static inline bool cpu_has_vmx_ept_execute_only(void)
770{
31299944 771 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 772}
773
774static inline bool cpu_has_vmx_eptp_uncacheable(void)
775{
31299944 776 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 777}
778
779static inline bool cpu_has_vmx_eptp_writeback(void)
780{
31299944 781 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 782}
783
784static inline bool cpu_has_vmx_ept_2m_page(void)
785{
31299944 786 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 787}
788
878403b7
SY		 789static inline bool cpu_has_vmx_ept_1g_page(void)
790{
31299944 791 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 792}
793
4bc9b982
SY		 794static inline bool cpu_has_vmx_ept_4levels(void)
795{
796 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
797}
798
83c3a331
XH		 799static inline bool cpu_has_vmx_ept_ad_bits(void)
800{
801 return vmx_capability.ept & VMX_EPT_AD_BIT;
802}
803
31299944 804static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 805{
31299944 806 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 807}
808
31299944 809static inline bool cpu_has_vmx_invept_context(void)
d56f546d 810{
31299944 811 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 812}
813
31299944 814static inline bool cpu_has_vmx_invept_global(void)
d56f546d 815{
31299944 816 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 817}
818
518c8aee
GJ		 819static inline bool cpu_has_vmx_invvpid_single(void)
820{
821 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
822}
823
b9d762fa
GJ		 824static inline bool cpu_has_vmx_invvpid_global(void)
825{
826 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
827}
828
31299944 829static inline bool cpu_has_vmx_ept(void)
d56f546d 830{
04547156
SY		 831 return vmcs_config.cpu_based_2nd_exec_ctrl &
832 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 833}
834
31299944 835static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 836{
837 return vmcs_config.cpu_based_2nd_exec_ctrl &
838 SECONDARY_EXEC_UNRESTRICTED_GUEST;
839}
840
31299944 841static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 842{
843 return vmcs_config.cpu_based_2nd_exec_ctrl &
844 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
845}
846
31299944 847static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 848{
6d3e435e 849 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_vpid(void)
2384d2b3 853{
04547156
SY		 854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 856}
857
31299944 858static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_RDTSCP;
862}
863
31299944 864static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 865{
866 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
867}
868
f5f48ee1
SY		 869static inline bool cpu_has_vmx_wbinvd_exit(void)
870{
871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_WBINVD_EXITING;
873}
874
04547156
SY		 875static inline bool report_flexpriority(void)
876{
877 return flexpriority_enabled;
878}
879
fe3ef05c
NHE		 880static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
881{
882 return vmcs12->cpu_based_vm_exec_control & bit;
883}
884
885static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
886{
887 return (vmcs12->cpu_based_vm_exec_control &
888 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
889 (vmcs12->secondary_vm_exec_control & bit);
890}
891
644d711a
NHE		 892static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
893 struct kvm_vcpu *vcpu)
894{
895 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
896}
897
898static inline bool is_exception(u32 intr_info)
899{
900 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
901 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
902}
903
904static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 905static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
906 struct vmcs12 *vmcs12,
907 u32 reason, unsigned long qualification);
908
8b9cf98c 909static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 910{
911 int i;
912
a2fa3e9f 913 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 914 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 915 return i;
916 return -1;
917}
918
2384d2b3
SY		 919static inline void __invvpid(int ext, u16 vpid, gva_t gva)
920{
921 struct {
922 u64 vpid : 16;
923 u64 rsvd : 48;
924 u64 gva;
925 } operand = { vpid, 0, gva };
926
4ecac3fd 927 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 928 /* CF==1 or ZF==1 --> rc = -1 */
929 "; ja 1f ; ud2 ; 1:"
930 : : "a"(&operand), "c"(ext) : "cc", "memory");
931}
932
1439442c
SY		 933static inline void __invept(int ext, u64 eptp, gpa_t gpa)
934{
935 struct {
936 u64 eptp, gpa;
937 } operand = {eptp, gpa};
938
4ecac3fd 939 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 940 /* CF==1 or ZF==1 --> rc = -1 */
941 "; ja 1f ; ud2 ; 1:\n"
942 : : "a" (&operand), "c" (ext) : "cc", "memory");
943}
944
26bb0981 945static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 946{
947 int i;
948
8b9cf98c 949 i = __find_msr_index(vmx, msr);
a75beee6 950 if (i >= 0)
a2fa3e9f 951 return &vmx->guest_msrs[i];
8b6d44c7 952 return NULL;
7725f0ba
AK		 953}
954
6aa8b732
AK		 955static void vmcs_clear(struct vmcs *vmcs)
956{
957 u64 phys_addr = __pa(vmcs);
958 u8 error;
959
4ecac3fd 960 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 962 : "cc", "memory");
963 if (error)
964 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
965 vmcs, phys_addr);
966}
967
d462b819
NHE		 968static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
969{
970 vmcs_clear(loaded_vmcs->vmcs);
971 loaded_vmcs->cpu = -1;
972 loaded_vmcs->launched = 0;
973}
974
7725b894
DX		 975static void vmcs_load(struct vmcs *vmcs)
976{
977 u64 phys_addr = __pa(vmcs);
978 u8 error;
979
980 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 981 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 982 : "cc", "memory");
983 if (error)
2844d849 984 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 985 vmcs, phys_addr);
986}
987
d462b819 988static void __loaded_vmcs_clear(void *arg)
6aa8b732 989{
d462b819 990 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 991 int cpu = raw_smp_processor_id();
6aa8b732 992
d462b819
NHE		 993 if (loaded_vmcs->cpu != cpu)
994 return; /* vcpu migration can race with cpu offline */
995 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 996 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 997 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
998 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 999}
1000
d462b819 1001static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1002{
d462b819
NHE		 1003 if (loaded_vmcs->cpu != -1)
1004 smp_call_function_single(
1005 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1006}
1007
1760dd49 1008static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1009{
1010 if (vmx->vpid == 0)
1011 return;
1012
518c8aee
GJ		 1013 if (cpu_has_vmx_invvpid_single())
1014 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1015}
1016
b9d762fa
GJ		 1017static inline void vpid_sync_vcpu_global(void)
1018{
1019 if (cpu_has_vmx_invvpid_global())
1020 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1021}
1022
1023static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1024{
1025 if (cpu_has_vmx_invvpid_single())
1760dd49 1026 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1027 else
1028 vpid_sync_vcpu_global();
1029}
1030
1439442c
SY		 1031static inline void ept_sync_global(void)
1032{
1033 if (cpu_has_vmx_invept_global())
1034 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1035}
1036
1037static inline void ept_sync_context(u64 eptp)
1038{
089d034e 1039 if (enable_ept) {
1439442c
SY		 1040 if (cpu_has_vmx_invept_context())
1041 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1042 else
1043 ept_sync_global();
1044 }
1045}
1046
1047static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1048{
089d034e 1049 if (enable_ept) {
1439442c
SY		 1050 if (cpu_has_vmx_invept_individual_addr())
1051 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1052 eptp, gpa);
1053 else
1054 ept_sync_context(eptp);
1055 }
1056}
1057
96304217 1058static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1059{
5e520e62 1060 unsigned long value;
6aa8b732 1061
5e520e62
AK		 1062 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1063 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1064 return value;
1065}
1066
96304217 1067static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1068{
1069 return vmcs_readl(field);
1070}
1071
96304217 1072static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1073{
1074 return vmcs_readl(field);
1075}
1076
96304217 1077static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1078{
05b3e0c2 1079#ifdef CONFIG_X86_64
6aa8b732
AK		 1080 return vmcs_readl(field);
1081#else
1082 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1083#endif
1084}
1085
e52de1b8
AK		 1086static noinline void vmwrite_error(unsigned long field, unsigned long value)
1087{
1088 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1089 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1090 dump_stack();
1091}
1092
6aa8b732
AK		 1093static void vmcs_writel(unsigned long field, unsigned long value)
1094{
1095 u8 error;
1096
4ecac3fd 1097 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1098 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1099 if (unlikely(error))
1100 vmwrite_error(field, value);
6aa8b732
AK		 1101}
1102
1103static void vmcs_write16(unsigned long field, u16 value)
1104{
1105 vmcs_writel(field, value);
1106}
1107
1108static void vmcs_write32(unsigned long field, u32 value)
1109{
1110 vmcs_writel(field, value);
1111}
1112
1113static void vmcs_write64(unsigned long field, u64 value)
1114{
6aa8b732 1115 vmcs_writel(field, value);
7682f2d0 1116#ifndef CONFIG_X86_64
6aa8b732
AK		 1117 asm volatile ("");
1118 vmcs_writel(field+1, value >> 32);
1119#endif
1120}
1121
2ab455cc
AL		 1122static void vmcs_clear_bits(unsigned long field, u32 mask)
1123{
1124 vmcs_writel(field, vmcs_readl(field) & ~mask);
1125}
1126
1127static void vmcs_set_bits(unsigned long field, u32 mask)
1128{
1129 vmcs_writel(field, vmcs_readl(field) | mask);
1130}
1131
2fb92db1
AK		 1132static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1133{
1134 vmx->segment_cache.bitmask = 0;
1135}
1136
1137static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1138 unsigned field)
1139{
1140 bool ret;
1141 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1142
1143 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1144 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1145 vmx->segment_cache.bitmask = 0;
1146 }
1147 ret = vmx->segment_cache.bitmask & mask;
1148 vmx->segment_cache.bitmask |= mask;
1149 return ret;
1150}
1151
1152static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1153{
1154 u16 *p = &vmx->segment_cache.seg[seg].selector;
1155
1156 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1157 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1158 return *p;
1159}
1160
1161static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1162{
1163 ulong *p = &vmx->segment_cache.seg[seg].base;
1164
1165 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1166 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1167 return *p;
1168}
1169
1170static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1171{
1172 u32 *p = &vmx->segment_cache.seg[seg].limit;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1175 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1176 return *p;
1177}
1178
1179static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1180{
1181 u32 *p = &vmx->segment_cache.seg[seg].ar;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1184 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1185 return *p;
1186}
1187
abd3f2d6
AK		 1188static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1189{
1190 u32 eb;
1191
fd7373cc
JK		 1192 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1193 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1194 if ((vcpu->guest_debug &
1195 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1196 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1197 eb |= 1u << BP_VECTOR;
7ffd92c5 1198 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1199 eb = ~0;
089d034e 1200 if (enable_ept)
1439442c 1201 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1202 if (vcpu->fpu_active)
1203 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1204
1205 /* When we are running a nested L2 guest and L1 specified for it a
1206 * certain exception bitmap, we must trap the same exceptions and pass
1207 * them to L1. When running L2, we will only handle the exceptions
1208 * specified above if L1 did not want them.
1209 */
1210 if (is_guest_mode(vcpu))
1211 eb |= get_vmcs12(vcpu)->exception_bitmap;
1212
abd3f2d6
AK		 1213 vmcs_write32(EXCEPTION_BITMAP, eb);
1214}
1215
8bf00a52
GN		 1216static void clear_atomic_switch_msr_special(unsigned long entry,
1217 unsigned long exit)
1218{
1219 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1220 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1221}
1222
61d2ef2c
AK		 1223static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1224{
1225 unsigned i;
1226 struct msr_autoload *m = &vmx->msr_autoload;
1227
8bf00a52
GN		 1228 switch (msr) {
1229 case MSR_EFER:
1230 if (cpu_has_load_ia32_efer) {
1231 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1232 VM_EXIT_LOAD_IA32_EFER);
1233 return;
1234 }
1235 break;
1236 case MSR_CORE_PERF_GLOBAL_CTRL:
1237 if (cpu_has_load_perf_global_ctrl) {
1238 clear_atomic_switch_msr_special(
1239 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1240 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1241 return;
1242 }
1243 break;
110312c8
AK		 1244 }
1245
61d2ef2c
AK		 1246 for (i = 0; i < m->nr; ++i)
1247 if (m->guest[i].index == msr)
1248 break;
1249
1250 if (i == m->nr)
1251 return;
1252 --m->nr;
1253 m->guest[i] = m->guest[m->nr];
1254 m->host[i] = m->host[m->nr];
1255 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1256 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1257}
1258
8bf00a52
GN		 1259static void add_atomic_switch_msr_special(unsigned long entry,
1260 unsigned long exit, unsigned long guest_val_vmcs,
1261 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1262{
1263 vmcs_write64(guest_val_vmcs, guest_val);
1264 vmcs_write64(host_val_vmcs, host_val);
1265 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1266 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1267}
1268
61d2ef2c
AK		 1269static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1270 u64 guest_val, u64 host_val)
1271{
1272 unsigned i;
1273 struct msr_autoload *m = &vmx->msr_autoload;
1274
8bf00a52
GN		 1275 switch (msr) {
1276 case MSR_EFER:
1277 if (cpu_has_load_ia32_efer) {
1278 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1279 VM_EXIT_LOAD_IA32_EFER,
1280 GUEST_IA32_EFER,
1281 HOST_IA32_EFER,
1282 guest_val, host_val);
1283 return;
1284 }
1285 break;
1286 case MSR_CORE_PERF_GLOBAL_CTRL:
1287 if (cpu_has_load_perf_global_ctrl) {
1288 add_atomic_switch_msr_special(
1289 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1290 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1291 GUEST_IA32_PERF_GLOBAL_CTRL,
1292 HOST_IA32_PERF_GLOBAL_CTRL,
1293 guest_val, host_val);
1294 return;
1295 }
1296 break;
110312c8
AK		 1297 }
1298
61d2ef2c
AK		 1299 for (i = 0; i < m->nr; ++i)
1300 if (m->guest[i].index == msr)
1301 break;
1302
e7fc6f93
GN		 1303 if (i == NR_AUTOLOAD_MSRS) {
1304 printk_once(KERN_WARNING"Not enough mst switch entries. "
1305 "Can't add msr %x\n", msr);
1306 return;
1307 } else if (i == m->nr) {
61d2ef2c
AK		 1308 ++m->nr;
1309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1310 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1311 }
1312
1313 m->guest[i].index = msr;
1314 m->guest[i].value = guest_val;
1315 m->host[i].index = msr;
1316 m->host[i].value = host_val;
1317}
1318
33ed6329
AK		 1319static void reload_tss(void)
1320{
33ed6329
AK		 1321 /*
1322 * VT restores TR but not its size. Useless.
1323 */
d359192f 1324 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1325 struct desc_struct *descs;
33ed6329 1326
d359192f 1327 descs = (void *)gdt->address;
33ed6329
AK		 1328 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1329 load_TR_desc();
33ed6329
AK		 1330}
1331
92c0d900 1332static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1333{
3a34a881 1334 u64 guest_efer;
51c6cf66
AK		 1335 u64 ignore_bits;
1336
f6801dff 1337 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1338
51c6cf66
AK		 1339 /*
1340 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1341 * outside long mode
1342 */
1343 ignore_bits = EFER_NX | EFER_SCE;
1344#ifdef CONFIG_X86_64
1345 ignore_bits |= EFER_LMA | EFER_LME;
1346 /* SCE is meaningful only in long mode on Intel */
1347 if (guest_efer & EFER_LMA)
1348 ignore_bits &= ~(u64)EFER_SCE;
1349#endif
51c6cf66
AK		 1350 guest_efer &= ~ignore_bits;
1351 guest_efer |= host_efer & ignore_bits;
26bb0981 1352 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1353 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1354
1355 clear_atomic_switch_msr(vmx, MSR_EFER);
1356 /* On ept, can't emulate nx, and must switch nx atomically */
1357 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1358 guest_efer = vmx->vcpu.arch.efer;
1359 if (!(guest_efer & EFER_LMA))
1360 guest_efer &= ~EFER_LME;
1361 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1362 return false;
1363 }
1364
26bb0981 1365 return true;
51c6cf66
AK		 1366}
1367
2d49ec72
GN		 1368static unsigned long segment_base(u16 selector)
1369{
d359192f 1370 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1371 struct desc_struct *d;
1372 unsigned long table_base;
1373 unsigned long v;
1374
1375 if (!(selector & ~3))
1376 return 0;
1377
d359192f 1378 table_base = gdt->address;
2d49ec72
GN		 1379
1380 if (selector & 4) { /* from ldt */
1381 u16 ldt_selector = kvm_read_ldt();
1382
1383 if (!(ldt_selector & ~3))
1384 return 0;
1385
1386 table_base = segment_base(ldt_selector);
1387 }
1388 d = (struct desc_struct *)(table_base + (selector & ~7));
1389 v = get_desc_base(d);
1390#ifdef CONFIG_X86_64
1391 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1392 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1393#endif
1394 return v;
1395}
1396
1397static inline unsigned long kvm_read_tr_base(void)
1398{
1399 u16 tr;
1400 asm("str %0" : "=g"(tr));
1401 return segment_base(tr);
1402}
1403
04d2cc77 1404static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1405{
04d2cc77 1406 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1407 int i;
04d2cc77 1408
a2fa3e9f 1409 if (vmx->host_state.loaded)
33ed6329
AK		 1410 return;
1411
a2fa3e9f 1412 vmx->host_state.loaded = 1;
33ed6329
AK		 1413 /*
1414 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1415 * allow segment selectors with cpl > 0 or ti == 1.
1416 */
d6e88aec 1417 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1418 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1419 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1420 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1421 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1422 vmx->host_state.fs_reload_needed = 0;
1423 } else {
33ed6329 1424 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1425 vmx->host_state.fs_reload_needed = 1;
33ed6329 1426 }
9581d442 1427 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1428 if (!(vmx->host_state.gs_sel & 7))
1429 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1430 else {
1431 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1432 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1433 }
1434
b2da15ac
AK		 1435#ifdef CONFIG_X86_64
1436 savesegment(ds, vmx->host_state.ds_sel);
1437 savesegment(es, vmx->host_state.es_sel);
1438#endif
1439
33ed6329
AK		 1440#ifdef CONFIG_X86_64
1441 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1442 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1443#else
a2fa3e9f
GH		 1444 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1445 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1446#endif
707c0874
AK		 1447
1448#ifdef CONFIG_X86_64
c8770e7b
AK		 1449 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1450 if (is_long_mode(&vmx->vcpu))
44ea2b17 1451 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1452#endif
26bb0981
AK		 1453 for (i = 0; i < vmx->save_nmsrs; ++i)
1454 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1455 vmx->guest_msrs[i].data,
1456 vmx->guest_msrs[i].mask);
33ed6329
AK		 1457}
1458
a9b21b62 1459static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1460{
a2fa3e9f 1461 if (!vmx->host_state.loaded)
33ed6329
AK		 1462 return;
1463
e1beb1d3 1464 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1465 vmx->host_state.loaded = 0;
c8770e7b
AK		 1466#ifdef CONFIG_X86_64
1467 if (is_long_mode(&vmx->vcpu))
1468 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1469#endif
152d3f2f 1470 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1471 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1472#ifdef CONFIG_X86_64
9581d442 1473 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1474#else
1475 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1476#endif
33ed6329 1477 }
0a77fe4c
AK		 1478 if (vmx->host_state.fs_reload_needed)
1479 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1480#ifdef CONFIG_X86_64
1481 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1482 loadsegment(ds, vmx->host_state.ds_sel);
1483 loadsegment(es, vmx->host_state.es_sel);
1484 }
1485#else
1486 /*
1487 * The sysexit path does not restore ds/es, so we must set them to
1488 * a reasonable value ourselves.
1489 */
1490 loadsegment(ds, __USER_DS);
1491 loadsegment(es, __USER_DS);
1492#endif
152d3f2f 1493 reload_tss();
44ea2b17 1494#ifdef CONFIG_X86_64
c8770e7b 1495 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1496#endif
1361b83a 1497 if (user_has_fpu())
1c11e713 1498 clts();
3444d7da 1499 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1500}
1501
a9b21b62
AK		 1502static void vmx_load_host_state(struct vcpu_vmx *vmx)
1503{
1504 preempt_disable();
1505 __vmx_load_host_state(vmx);
1506 preempt_enable();
1507}
1508
6aa8b732
AK		 1509/*
1510 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1511 * vcpu mutex is already taken.
1512 */
15ad7146 1513static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1514{
a2fa3e9f 1515 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1516 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1517
4610c9cc
DX		 1518 if (!vmm_exclusive)
1519 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1520 else if (vmx->loaded_vmcs->cpu != cpu)
1521 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1522
d462b819
NHE		 1523 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1524 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1525 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1526 }
1527
d462b819 1528 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1529 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1530 unsigned long sysenter_esp;
1531
a8eeb04a 1532 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1533 local_irq_disable();
d462b819
NHE		 1534 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1535 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1536 local_irq_enable();
1537
6aa8b732
AK		 1538 /*
1539 * Linux uses per-cpu TSS and GDT, so set these when switching
1540 * processors.
1541 */
d6e88aec 1542 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1543 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1544
1545 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1546 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1547 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1548 }
6aa8b732
AK		 1549}
1550
1551static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1552{
a9b21b62 1553 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1554 if (!vmm_exclusive) {
d462b819
NHE		 1555 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1556 vcpu->cpu = -1;
4610c9cc
DX		 1557 kvm_cpu_vmxoff();
1558 }
6aa8b732
AK		 1559}
1560
5fd86fcf
AK		 1561static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1562{
81231c69
AK		 1563 ulong cr0;
1564
5fd86fcf
AK		 1565 if (vcpu->fpu_active)
1566 return;
1567 vcpu->fpu_active = 1;
81231c69
AK		 1568 cr0 = vmcs_readl(GUEST_CR0);
1569 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1570 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1571 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1572 update_exception_bitmap(vcpu);
edcafe3c 1573 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1574 if (is_guest_mode(vcpu))
1575 vcpu->arch.cr0_guest_owned_bits &=
1576 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1577 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1578}
1579
edcafe3c
AK		 1580static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1581
fe3ef05c
NHE		 1582/*
1583 * Return the cr0 value that a nested guest would read. This is a combination
1584 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1585 * its hypervisor (cr0_read_shadow).
1586 */
1587static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1588{
1589 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1590 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1591}
1592static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1593{
1594 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1595 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1596}
1597
5fd86fcf
AK		 1598static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1599{
36cf24e0
NHE		 1600 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1601 * set this *before* calling this function.
1602 */
edcafe3c 1603 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1604 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1605 update_exception_bitmap(vcpu);
edcafe3c
AK		 1606 vcpu->arch.cr0_guest_owned_bits = 0;
1607 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1608 if (is_guest_mode(vcpu)) {
1609 /*
1610 * L1's specified read shadow might not contain the TS bit,
1611 * so now that we turned on shadowing of this bit, we need to
1612 * set this bit of the shadow. Like in nested_vmx_run we need
1613 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1614 * up-to-date here because we just decached cr0.TS (and we'll
1615 * only update vmcs12->guest_cr0 on nested exit).
1616 */
1617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1618 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1619 (vcpu->arch.cr0 & X86_CR0_TS);
1620 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1621 } else
1622 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1623}
1624
6aa8b732
AK		 1625static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1626{
78ac8b47 1627 unsigned long rflags, save_rflags;
345dcaa8 1628
6de12732
AK		 1629 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1630 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1631 rflags = vmcs_readl(GUEST_RFLAGS);
1632 if (to_vmx(vcpu)->rmode.vm86_active) {
1633 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1634 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1635 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1636 }
1637 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1638 }
6de12732 1639 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1640}
1641
1642static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1643{
6de12732 1644 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1645 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1646 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1647 if (to_vmx(vcpu)->rmode.vm86_active) {
1648 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1649 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1650 }
6aa8b732
AK		 1651 vmcs_writel(GUEST_RFLAGS, rflags);
1652}
1653
2809f5d2
GC		 1654static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1655{
1656 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1657 int ret = 0;
1658
1659 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1660 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1661 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1662 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1663
1664 return ret & mask;
1665}
1666
1667static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1668{
1669 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1670 u32 interruptibility = interruptibility_old;
1671
1672 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1673
48005f64 1674 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1675 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1676 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1677 interruptibility |= GUEST_INTR_STATE_STI;
1678
1679 if ((interruptibility != interruptibility_old))
1680 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1681}
1682
6aa8b732
AK		 1683static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1684{
1685 unsigned long rip;
6aa8b732 1686
5fdbf976 1687 rip = kvm_rip_read(vcpu);
6aa8b732 1688 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1689 kvm_rip_write(vcpu, rip);
6aa8b732 1690
2809f5d2
GC		 1691 /* skipping an emulated instruction also counts */
1692 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1693}
1694
0b6ac343
NHE		 1695/*
1696 * KVM wants to inject page-faults which it got to the guest. This function
1697 * checks whether in a nested guest, we need to inject them to L1 or L2.
1698 * This function assumes it is called with the exit reason in vmcs02 being
1699 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1700 * is running).
1701 */
1702static int nested_pf_handled(struct kvm_vcpu *vcpu)
1703{
1704 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1705
1706 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1707 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1708 return 0;
1709
1710 nested_vmx_vmexit(vcpu);
1711 return 1;
1712}
1713
298101da 1714static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1715 bool has_error_code, u32 error_code,
1716 bool reinject)
298101da 1717{
77ab6db0 1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1719 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1720
0b6ac343
NHE		 1721 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1722 nested_pf_handled(vcpu))
1723 return;
1724
8ab2d2e2 1725 if (has_error_code) {
77ab6db0 1726 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1727 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1728 }
77ab6db0 1729
7ffd92c5 1730 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1731 int inc_eip = 0;
1732 if (kvm_exception_is_soft(nr))
1733 inc_eip = vcpu->arch.event_exit_inst_len;
1734 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1735 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1736 return;
1737 }
1738
66fd3f7f
GN		 1739 if (kvm_exception_is_soft(nr)) {
1740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1741 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1742 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1743 } else
1744 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1745
1746 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1747}
1748
4e47c7a6
SY		 1749static bool vmx_rdtscp_supported(void)
1750{
1751 return cpu_has_vmx_rdtscp();
1752}
1753
a75beee6
ED		 1754/*
1755 * Swap MSR entry in host/guest MSR entry array.
1756 */
8b9cf98c 1757static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1758{
26bb0981 1759 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1760
1761 tmp = vmx->guest_msrs[to];
1762 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1763 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1764}
1765
e38aea3e
AK		 1766/*
1767 * Set up the vmcs to automatically save and restore system
1768 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1769 * mode, as fiddling with msrs is very expensive.
1770 */
8b9cf98c 1771static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1772{
26bb0981 1773 int save_nmsrs, index;
5897297b 1774 unsigned long *msr_bitmap;
e38aea3e 1775
a75beee6
ED		 1776 save_nmsrs = 0;
1777#ifdef CONFIG_X86_64
8b9cf98c 1778 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1779 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1780 if (index >= 0)
8b9cf98c
RR		 1781 move_msr_up(vmx, index, save_nmsrs++);
1782 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1783 if (index >= 0)
8b9cf98c
RR		 1784 move_msr_up(vmx, index, save_nmsrs++);
1785 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1786 if (index >= 0)
8b9cf98c 1787 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1788 index = __find_msr_index(vmx, MSR_TSC_AUX);
1789 if (index >= 0 && vmx->rdtscp_enabled)
1790 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1791 /*
8c06585d 1792 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1793 * if efer.sce is enabled.
1794 */
8c06585d 1795 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1796 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1797 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1798 }
1799#endif
92c0d900
AK		 1800 index = __find_msr_index(vmx, MSR_EFER);
1801 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1802 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1803
26bb0981 1804 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1805
1806 if (cpu_has_vmx_msr_bitmap()) {
1807 if (is_long_mode(&vmx->vcpu))
1808 msr_bitmap = vmx_msr_bitmap_longmode;
1809 else
1810 msr_bitmap = vmx_msr_bitmap_legacy;
1811
1812 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1813 }
e38aea3e
AK		 1814}
1815
6aa8b732
AK		 1816/*
1817 * reads and returns guest's timestamp counter "register"
1818 * guest_tsc = host_tsc + tsc_offset -- 21.3
1819 */
1820static u64 guest_read_tsc(void)
1821{
1822 u64 host_tsc, tsc_offset;
1823
1824 rdtscll(host_tsc);
1825 tsc_offset = vmcs_read64(TSC_OFFSET);
1826 return host_tsc + tsc_offset;
1827}
1828
d5c1785d
NHE		 1829/*
1830 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1831 * counter, even if a nested guest (L2) is currently running.
1832 */
1833u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1834{
1835 u64 host_tsc, tsc_offset;
1836
1837 rdtscll(host_tsc);
1838 tsc_offset = is_guest_mode(vcpu) ?
1839 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1840 vmcs_read64(TSC_OFFSET);
1841 return host_tsc + tsc_offset;
1842}
1843
4051b188 1844/*
cc578287
ZA		 1845 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1846 * software catchup for faster rates on slower CPUs.
4051b188 1847 */
cc578287 1848static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1849{
cc578287
ZA		 1850 if (!scale)
1851 return;
1852
1853 if (user_tsc_khz > tsc_khz) {
1854 vcpu->arch.tsc_catchup = 1;
1855 vcpu->arch.tsc_always_catchup = 1;
1856 } else
1857 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1858}
1859
6aa8b732 1860/*
99e3e30a 1861 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1862 */
99e3e30a 1863static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1864{
27fc51b2 1865 if (is_guest_mode(vcpu)) {
7991825b 1866 /*
27fc51b2
NHE		 1867 * We're here if L1 chose not to trap WRMSR to TSC. According
1868 * to the spec, this should set L1's TSC; The offset that L1
1869 * set for L2 remains unchanged, and still needs to be added
1870 * to the newly set TSC to get L2's TSC.
7991825b 1871 */
27fc51b2
NHE		 1872 struct vmcs12 *vmcs12;
1873 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1874 /* recalculate vmcs02.TSC_OFFSET: */
1875 vmcs12 = get_vmcs12(vcpu);
1876 vmcs_write64(TSC_OFFSET, offset +
1877 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1878 vmcs12->tsc_offset : 0));
1879 } else {
1880 vmcs_write64(TSC_OFFSET, offset);
1881 }
6aa8b732
AK		 1882}
1883
f1e2b260 1884static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1885{
1886 u64 offset = vmcs_read64(TSC_OFFSET);
1887 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1888 if (is_guest_mode(vcpu)) {
1889 /* Even when running L2, the adjustment needs to apply to L1 */
1890 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1891 }
e48672fa
ZA		 1892}
1893
857e4099
JR		 1894static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1895{
1896 return target_tsc - native_read_tsc();
1897}
1898
801d3424
NHE		 1899static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1900{
1901 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1902 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1903}
1904
1905/*
1906 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1907 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1908 * all guests if the "nested" module option is off, and can also be disabled
1909 * for a single guest by disabling its VMX cpuid bit.
1910 */
1911static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1912{
1913 return nested && guest_cpuid_has_vmx(vcpu);
1914}
1915
b87a51ae
NHE		 1916/*
1917 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1918 * returned for the various VMX controls MSRs when nested VMX is enabled.
1919 * The same values should also be used to verify that vmcs12 control fields are
1920 * valid during nested entry from L1 to L2.
1921 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1922 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1923 * bit in the high half is on if the corresponding bit in the control field
1924 * may be on. See also vmx_control_verify().
1925 * TODO: allow these variables to be modified (downgraded) by module options
1926 * or other means.
1927 */
1928static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1929static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1930static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1931static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1932static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1933static __init void nested_vmx_setup_ctls_msrs(void)
1934{
1935 /*
1936 * Note that as a general rule, the high half of the MSRs (bits in
1937 * the control fields which may be 1) should be initialized by the
1938 * intersection of the underlying hardware's MSR (i.e., features which
1939 * can be supported) and the list of features we want to expose -
1940 * because they are known to be properly supported in our code.
1941 * Also, usually, the low half of the MSRs (bits which must be 1) can
1942 * be set to 0, meaning that L1 may turn off any of these bits. The
1943 * reason is that if one of these bits is necessary, it will appear
1944 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1945 * fields of vmcs01 and vmcs02, will turn these bits off - and
1946 * nested_vmx_exit_handled() will not pass related exits to L1.
1947 * These rules have exceptions below.
1948 */
1949
1950 /* pin-based controls */
1951 /*
1952 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1953 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1954 */
1955 nested_vmx_pinbased_ctls_low = 0x16 ;
1956 nested_vmx_pinbased_ctls_high = 0x16 |
1957 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1958 PIN_BASED_VIRTUAL_NMIS;
1959
1960 /* exit controls */
1961 nested_vmx_exit_ctls_low = 0;
b6f1250e 1962 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1963#ifdef CONFIG_X86_64
1964 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1965#else
1966 nested_vmx_exit_ctls_high = 0;
1967#endif
1968
1969 /* entry controls */
1970 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1971 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1972 nested_vmx_entry_ctls_low = 0;
1973 nested_vmx_entry_ctls_high &=
1974 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1975
1976 /* cpu-based controls */
1977 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1978 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1979 nested_vmx_procbased_ctls_low = 0;
1980 nested_vmx_procbased_ctls_high &=
1981 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1982 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1983 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1984 CPU_BASED_CR3_STORE_EXITING |
1985#ifdef CONFIG_X86_64
1986 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1987#endif
1988 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1989 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 1990 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 1991 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1992 /*
1993 * We can allow some features even when not supported by the
1994 * hardware. For example, L1 can specify an MSR bitmap - and we
1995 * can use it to avoid exits to L1 - even when L0 runs L2
1996 * without MSR bitmaps.
1997 */
1998 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1999
2000 /* secondary cpu-based controls */
2001 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2002 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2003 nested_vmx_secondary_ctls_low = 0;
2004 nested_vmx_secondary_ctls_high &=
2005 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2006}
2007
2008static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2009{
2010 /*
2011 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2012 */
2013 return ((control & high) | low) == control;
2014}
2015
2016static inline u64 vmx_control_msr(u32 low, u32 high)
2017{
2018 return low | ((u64)high << 32);
2019}
2020
2021/*
2022 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2023 * also let it use VMX-specific MSRs.
2024 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2025 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2026 * like all other MSRs).
2027 */
2028static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2029{
2030 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2031 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2032 /*
2033 * According to the spec, processors which do not support VMX
2034 * should throw a #GP(0) when VMX capability MSRs are read.
2035 */
2036 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2037 return 1;
2038 }
2039
2040 switch (msr_index) {
2041 case MSR_IA32_FEATURE_CONTROL:
2042 *pdata = 0;
2043 break;
2044 case MSR_IA32_VMX_BASIC:
2045 /*
2046 * This MSR reports some information about VMX support. We
2047 * should return information about the VMX we emulate for the
2048 * guest, and the VMCS structure we give it - not about the
2049 * VMX support of the underlying hardware.
2050 */
2051 *pdata = VMCS12_REVISION |
2052 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2053 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2054 break;
2055 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2056 case MSR_IA32_VMX_PINBASED_CTLS:
2057 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2058 nested_vmx_pinbased_ctls_high);
2059 break;
2060 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2061 case MSR_IA32_VMX_PROCBASED_CTLS:
2062 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2063 nested_vmx_procbased_ctls_high);
2064 break;
2065 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2066 case MSR_IA32_VMX_EXIT_CTLS:
2067 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2068 nested_vmx_exit_ctls_high);
2069 break;
2070 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2071 case MSR_IA32_VMX_ENTRY_CTLS:
2072 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2073 nested_vmx_entry_ctls_high);
2074 break;
2075 case MSR_IA32_VMX_MISC:
2076 *pdata = 0;
2077 break;
2078 /*
2079 * These MSRs specify bits which the guest must keep fixed (on or off)
2080 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2081 * We picked the standard core2 setting.
2082 */
2083#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2084#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2085 case MSR_IA32_VMX_CR0_FIXED0:
2086 *pdata = VMXON_CR0_ALWAYSON;
2087 break;
2088 case MSR_IA32_VMX_CR0_FIXED1:
2089 *pdata = -1ULL;
2090 break;
2091 case MSR_IA32_VMX_CR4_FIXED0:
2092 *pdata = VMXON_CR4_ALWAYSON;
2093 break;
2094 case MSR_IA32_VMX_CR4_FIXED1:
2095 *pdata = -1ULL;
2096 break;
2097 case MSR_IA32_VMX_VMCS_ENUM:
2098 *pdata = 0x1f;
2099 break;
2100 case MSR_IA32_VMX_PROCBASED_CTLS2:
2101 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2102 nested_vmx_secondary_ctls_high);
2103 break;
2104 case MSR_IA32_VMX_EPT_VPID_CAP:
2105 /* Currently, no nested ept or nested vpid */
2106 *pdata = 0;
2107 break;
2108 default:
2109 return 0;
2110 }
2111
2112 return 1;
2113}
2114
2115static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2116{
2117 if (!nested_vmx_allowed(vcpu))
2118 return 0;
2119
2120 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2121 /* TODO: the right thing. */
2122 return 1;
2123 /*
2124 * No need to treat VMX capability MSRs specially: If we don't handle
2125 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2126 */
2127 return 0;
2128}
2129
6aa8b732
AK		 2130/*
2131 * Reads an msr value (of 'msr_index') into 'pdata'.
2132 * Returns 0 on success, non-0 otherwise.
2133 * Assumes vcpu_load() was already called.
2134 */
2135static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2136{
2137 u64 data;
26bb0981 2138 struct shared_msr_entry *msr;
6aa8b732
AK		 2139
2140 if (!pdata) {
2141 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2142 return -EINVAL;
2143 }
2144
2145 switch (msr_index) {
05b3e0c2 2146#ifdef CONFIG_X86_64
6aa8b732
AK		 2147 case MSR_FS_BASE:
2148 data = vmcs_readl(GUEST_FS_BASE);
2149 break;
2150 case MSR_GS_BASE:
2151 data = vmcs_readl(GUEST_GS_BASE);
2152 break;
44ea2b17
AK		 2153 case MSR_KERNEL_GS_BASE:
2154 vmx_load_host_state(to_vmx(vcpu));
2155 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2156 break;
26bb0981 2157#endif
6aa8b732 2158 case MSR_EFER:
3bab1f5d 2159 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2160 case MSR_IA32_TSC:
6aa8b732
AK		 2161 data = guest_read_tsc();
2162 break;
2163 case MSR_IA32_SYSENTER_CS:
2164 data = vmcs_read32(GUEST_SYSENTER_CS);
2165 break;
2166 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2167 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2168 break;
2169 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2170 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2171 break;
4e47c7a6
SY		 2172 case MSR_TSC_AUX:
2173 if (!to_vmx(vcpu)->rdtscp_enabled)
2174 return 1;
2175 /* Otherwise falls through */
6aa8b732 2176 default:
b87a51ae
NHE		 2177 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2178 return 0;
8b9cf98c 2179 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2180 if (msr) {
2181 data = msr->data;
2182 break;
6aa8b732 2183 }
3bab1f5d 2184 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2185 }
2186
2187 *pdata = data;
2188 return 0;
2189}
2190
2191/*
2192 * Writes msr value into into the appropriate "register".
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2195 */
2196static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2197{
a2fa3e9f 2198 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2199 struct shared_msr_entry *msr;
2cc51560
ED		 2200 int ret = 0;
2201
6aa8b732 2202 switch (msr_index) {
3bab1f5d 2203 case MSR_EFER:
2cc51560 2204 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2205 break;
16175a79 2206#ifdef CONFIG_X86_64
6aa8b732 2207 case MSR_FS_BASE:
2fb92db1 2208 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2209 vmcs_writel(GUEST_FS_BASE, data);
2210 break;
2211 case MSR_GS_BASE:
2fb92db1 2212 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2213 vmcs_writel(GUEST_GS_BASE, data);
2214 break;
44ea2b17
AK		 2215 case MSR_KERNEL_GS_BASE:
2216 vmx_load_host_state(vmx);
2217 vmx->msr_guest_kernel_gs_base = data;
2218 break;
6aa8b732
AK		 2219#endif
2220 case MSR_IA32_SYSENTER_CS:
2221 vmcs_write32(GUEST_SYSENTER_CS, data);
2222 break;
2223 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2224 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2225 break;
2226 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2227 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2228 break;
af24a4e4 2229 case MSR_IA32_TSC:
99e3e30a 2230 kvm_write_tsc(vcpu, data);
6aa8b732 2231 break;
468d472f
SY		 2232 case MSR_IA32_CR_PAT:
2233 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2234 vmcs_write64(GUEST_IA32_PAT, data);
2235 vcpu->arch.pat = data;
2236 break;
2237 }
4e47c7a6
SY		 2238 ret = kvm_set_msr_common(vcpu, msr_index, data);
2239 break;
2240 case MSR_TSC_AUX:
2241 if (!vmx->rdtscp_enabled)
2242 return 1;
2243 /* Check reserved bit, higher 32 bits should be zero */
2244 if ((data >> 32) != 0)
2245 return 1;
2246 /* Otherwise falls through */
6aa8b732 2247 default:
b87a51ae
NHE		 2248 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2249 break;
8b9cf98c 2250 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2251 if (msr) {
2252 msr->data = data;
2225fd56
AK		 2253 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2254 preempt_disable();
9ee73970
AK		 2255 kvm_set_shared_msr(msr->index, msr->data,
2256 msr->mask);
2225fd56
AK		 2257 preempt_enable();
2258 }
3bab1f5d 2259 break;
6aa8b732 2260 }
2cc51560 2261 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2262 }
2263
2cc51560 2264 return ret;
6aa8b732
AK		 2265}
2266
5fdbf976 2267static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2268{
5fdbf976
MT		 2269 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2270 switch (reg) {
2271 case VCPU_REGS_RSP:
2272 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2273 break;
2274 case VCPU_REGS_RIP:
2275 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2276 break;
6de4f3ad
AK		 2277 case VCPU_EXREG_PDPTR:
2278 if (enable_ept)
2279 ept_save_pdptrs(vcpu);
2280 break;
5fdbf976
MT		 2281 default:
2282 break;
2283 }
6aa8b732
AK		 2284}
2285
355be0b9 2286static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2287{
ae675ef0
JK		 2288 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2289 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2290 else
2291 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2292
abd3f2d6 2293 update_exception_bitmap(vcpu);
6aa8b732
AK		 2294}
2295
2296static __init int cpu_has_kvm_support(void)
2297{
6210e37b 2298 return cpu_has_vmx();
6aa8b732
AK		 2299}
2300
2301static __init int vmx_disabled_by_bios(void)
2302{
2303 u64 msr;
2304
2305 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2306 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2307 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2309 && tboot_enabled())
2310 return 1;
23f3e991 2311 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2312 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2313 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2314 && !tboot_enabled()) {
2315 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2316 "activate TXT before enabling KVM\n");
cafd6659 2317 return 1;
f9335afe 2318 }
23f3e991
JC		 2319 /* launched w/o TXT and VMX disabled */
2320 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2321 && !tboot_enabled())
2322 return 1;
cafd6659
SW		 2323 }
2324
2325 return 0;
6aa8b732
AK		 2326}
2327
7725b894
DX		 2328static void kvm_cpu_vmxon(u64 addr)
2329{
2330 asm volatile (ASM_VMX_VMXON_RAX
2331 : : "a"(&addr), "m"(addr)
2332 : "memory", "cc");
2333}
2334
10474ae8 2335static int hardware_enable(void *garbage)
6aa8b732
AK		 2336{
2337 int cpu = raw_smp_processor_id();
2338 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2339 u64 old, test_bits;
6aa8b732 2340
10474ae8
AG		 2341 if (read_cr4() & X86_CR4_VMXE)
2342 return -EBUSY;
2343
d462b819 2344 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2345 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2346
2347 test_bits = FEATURE_CONTROL_LOCKED;
2348 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2349 if (tboot_enabled())
2350 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2351
2352 if ((old & test_bits) != test_bits) {
6aa8b732 2353 /* enable and lock */
cafd6659
SW		 2354 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2355 }
66aee91a 2356 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2357
4610c9cc
DX		 2358 if (vmm_exclusive) {
2359 kvm_cpu_vmxon(phys_addr);
2360 ept_sync_global();
2361 }
10474ae8 2362
3444d7da
AK		 2363 store_gdt(&__get_cpu_var(host_gdt));
2364
10474ae8 2365 return 0;
6aa8b732
AK		 2366}
2367
d462b819 2368static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2369{
2370 int cpu = raw_smp_processor_id();
d462b819 2371 struct loaded_vmcs *v, *n;
543e4243 2372
d462b819
NHE		 2373 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2374 loaded_vmcss_on_cpu_link)
2375 __loaded_vmcs_clear(v);
543e4243
AK		 2376}
2377
710ff4a8
EH		 2378
2379/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2380 * tricks.
2381 */
2382static void kvm_cpu_vmxoff(void)
6aa8b732 2383{
4ecac3fd 2384 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2385}
2386
710ff4a8
EH		 2387static void hardware_disable(void *garbage)
2388{
4610c9cc 2389 if (vmm_exclusive) {
d462b819 2390 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2391 kvm_cpu_vmxoff();
2392 }
7725b894 2393 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2394}
2395
1c3d14fe 2396static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2397 u32 msr, u32 *result)
1c3d14fe
YS		 2398{
2399 u32 vmx_msr_low, vmx_msr_high;
2400 u32 ctl = ctl_min | ctl_opt;
2401
2402 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2403
2404 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2405 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2406
2407 /* Ensure minimum (required) set of control bits are supported. */
2408 if (ctl_min & ~ctl)
002c7f7c 2409 return -EIO;
1c3d14fe
YS		 2410
2411 *result = ctl;
2412 return 0;
2413}
2414
110312c8
AK		 2415static __init bool allow_1_setting(u32 msr, u32 ctl)
2416{
2417 u32 vmx_msr_low, vmx_msr_high;
2418
2419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420 return vmx_msr_high & ctl;
2421}
2422
002c7f7c 2423static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2424{
2425 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2426 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2427 u32 _pin_based_exec_control = 0;
2428 u32 _cpu_based_exec_control = 0;
f78e0e2e 2429 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2430 u32 _vmexit_control = 0;
2431 u32 _vmentry_control = 0;
2432
2433 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2434 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2435 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2436 &_pin_based_exec_control) < 0)
002c7f7c 2437 return -EIO;
1c3d14fe 2438
10166744 2439 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2440#ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING |
2442 CPU_BASED_CR8_STORE_EXITING |
2443#endif
d56f546d
SY		 2444 CPU_BASED_CR3_LOAD_EXITING |
2445 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2446 CPU_BASED_USE_IO_BITMAPS |
2447 CPU_BASED_MOV_DR_EXITING |
a7052897 2448 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2449 CPU_BASED_MWAIT_EXITING |
2450 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2451 CPU_BASED_INVLPG_EXITING |
2452 CPU_BASED_RDPMC_EXITING;
443381a8 2453
f78e0e2e 2454 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2455 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2458 &_cpu_based_exec_control) < 0)
002c7f7c 2459 return -EIO;
6e5d865c
YS		 2460#ifdef CONFIG_X86_64
2461 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2462 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2463 ~CPU_BASED_CR8_STORE_EXITING;
2464#endif
f78e0e2e 2465 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2466 min2 = 0;
2467 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2468 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2469 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2470 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2471 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2472 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2473 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2474 if (adjust_vmx_controls(min2, opt2,
2475 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2476 &_cpu_based_2nd_exec_control) < 0)
2477 return -EIO;
2478 }
2479#ifndef CONFIG_X86_64
2480 if (!(_cpu_based_2nd_exec_control &
2481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2482 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2483#endif
d56f546d 2484 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2486 enabled */
5fff7d27
GN		 2487 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2488 CPU_BASED_CR3_STORE_EXITING |
2489 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2491 vmx_capability.ept, vmx_capability.vpid);
2492 }
1c3d14fe
YS		 2493
2494 min = 0;
2495#ifdef CONFIG_X86_64
2496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2497#endif
468d472f 2498 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2500 &_vmexit_control) < 0)
002c7f7c 2501 return -EIO;
1c3d14fe 2502
468d472f
SY		 2503 min = 0;
2504 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2506 &_vmentry_control) < 0)
002c7f7c 2507 return -EIO;
6aa8b732 2508
c68876fd 2509 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2510
2511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2512 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2513 return -EIO;
1c3d14fe
YS		 2514
2515#ifdef CONFIG_X86_64
2516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2517 if (vmx_msr_high & (1u<<16))
002c7f7c 2518 return -EIO;
1c3d14fe
YS		 2519#endif
2520
2521 /* Require Write-Back (WB) memory type for VMCS accesses. */
2522 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2523 return -EIO;
1c3d14fe 2524
002c7f7c
YS		 2525 vmcs_conf->size = vmx_msr_high & 0x1fff;
2526 vmcs_conf->order = get_order(vmcs_config.size);
2527 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2528
002c7f7c
YS		 2529 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2530 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2531 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2532 vmcs_conf->vmexit_ctrl = _vmexit_control;
2533 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2534
110312c8
AK		 2535 cpu_has_load_ia32_efer =
2536 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2537 VM_ENTRY_LOAD_IA32_EFER)
2538 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2539 VM_EXIT_LOAD_IA32_EFER);
2540
8bf00a52
GN		 2541 cpu_has_load_perf_global_ctrl =
2542 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2543 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2544 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2545 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2546
2547 /*
2548 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2549 * but due to arrata below it can't be used. Workaround is to use
2550 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2551 *
2552 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2553 *
2554 * AAK155 (model 26)
2555 * AAP115 (model 30)
2556 * AAT100 (model 37)
2557 * BC86,AAY89,BD102 (model 44)
2558 * BA97 (model 46)
2559 *
2560 */
2561 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2562 switch (boot_cpu_data.x86_model) {
2563 case 26:
2564 case 30:
2565 case 37:
2566 case 44:
2567 case 46:
2568 cpu_has_load_perf_global_ctrl = false;
2569 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2570 "does not work properly. Using workaround\n");
2571 break;
2572 default:
2573 break;
2574 }
2575 }
2576
1c3d14fe 2577 return 0;
c68876fd 2578}
6aa8b732
AK		 2579
2580static struct vmcs *alloc_vmcs_cpu(int cpu)
2581{
2582 int node = cpu_to_node(cpu);
2583 struct page *pages;
2584 struct vmcs *vmcs;
2585
6484eb3e 2586 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2587 if (!pages)
2588 return NULL;
2589 vmcs = page_address(pages);
1c3d14fe
YS		 2590 memset(vmcs, 0, vmcs_config.size);
2591 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2592 return vmcs;
2593}
2594
2595static struct vmcs *alloc_vmcs(void)
2596{
d3b2c338 2597 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2598}
2599
2600static void free_vmcs(struct vmcs *vmcs)
2601{
1c3d14fe 2602 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2603}
2604
d462b819
NHE		 2605/*
2606 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2607 */
2608static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2609{
2610 if (!loaded_vmcs->vmcs)
2611 return;
2612 loaded_vmcs_clear(loaded_vmcs);
2613 free_vmcs(loaded_vmcs->vmcs);
2614 loaded_vmcs->vmcs = NULL;
2615}
2616
39959588 2617static void free_kvm_area(void)
6aa8b732
AK		 2618{
2619 int cpu;
2620
3230bb47 2621 for_each_possible_cpu(cpu) {
6aa8b732 2622 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2623 per_cpu(vmxarea, cpu) = NULL;
2624 }
6aa8b732
AK		 2625}
2626
6aa8b732
AK		 2627static __init int alloc_kvm_area(void)
2628{
2629 int cpu;
2630
3230bb47 2631 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2632 struct vmcs *vmcs;
2633
2634 vmcs = alloc_vmcs_cpu(cpu);
2635 if (!vmcs) {
2636 free_kvm_area();
2637 return -ENOMEM;
2638 }
2639
2640 per_cpu(vmxarea, cpu) = vmcs;
2641 }
2642 return 0;
2643}
2644
2645static __init int hardware_setup(void)
2646{
002c7f7c
YS		 2647 if (setup_vmcs_config(&vmcs_config) < 0)
2648 return -EIO;
50a37eb4
JR		 2649
2650 if (boot_cpu_has(X86_FEATURE_NX))
2651 kvm_enable_efer_bits(EFER_NX);
2652
93ba03c2
SY		 2653 if (!cpu_has_vmx_vpid())
2654 enable_vpid = 0;
2655
4bc9b982
SY		 2656 if (!cpu_has_vmx_ept() ||
2657 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2658 enable_ept = 0;
3a624e29 2659 enable_unrestricted_guest = 0;
83c3a331 2660 enable_ept_ad_bits = 0;
3a624e29
NK		 2661 }
2662
83c3a331
XH		 2663 if (!cpu_has_vmx_ept_ad_bits())
2664 enable_ept_ad_bits = 0;
2665
3a624e29
NK		 2666 if (!cpu_has_vmx_unrestricted_guest())
2667 enable_unrestricted_guest = 0;
93ba03c2
SY		 2668
2669 if (!cpu_has_vmx_flexpriority())
2670 flexpriority_enabled = 0;
2671
95ba8273
GN		 2672 if (!cpu_has_vmx_tpr_shadow())
2673 kvm_x86_ops->update_cr8_intercept = NULL;
2674
54dee993
MT		 2675 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2676 kvm_disable_largepages();
2677
4b8d54f9
ZE		 2678 if (!cpu_has_vmx_ple())
2679 ple_gap = 0;
2680
b87a51ae
NHE		 2681 if (nested)
2682 nested_vmx_setup_ctls_msrs();
2683
6aa8b732
AK		 2684 return alloc_kvm_area();
2685}
2686
2687static __exit void hardware_unsetup(void)
2688{
2689 free_kvm_area();
2690}
2691
6aa8b732
AK		 2692static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2693{
2694 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2695
6af11b9e 2696 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2697 vmcs_write16(sf->selector, save->selector);
2698 vmcs_writel(sf->base, save->base);
2699 vmcs_write32(sf->limit, save->limit);
2700 vmcs_write32(sf->ar_bytes, save->ar);
2701 } else {
2702 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2703 << AR_DPL_SHIFT;
2704 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2705 }
2706}
2707
2708static void enter_pmode(struct kvm_vcpu *vcpu)
2709{
2710 unsigned long flags;
a89a8fb9 2711 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2712
a89a8fb9 2713 vmx->emulation_required = 1;
7ffd92c5 2714 vmx->rmode.vm86_active = 0;
6aa8b732 2715
2fb92db1
AK		 2716 vmx_segment_cache_clear(vmx);
2717
d0ba64f9 2718 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2719 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2720 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2721 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2722
2723 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2724 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2725 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2726 vmcs_writel(GUEST_RFLAGS, flags);
2727
66aee91a
RR		 2728 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2729 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2730
2731 update_exception_bitmap(vcpu);
2732
a89a8fb9
MG		 2733 if (emulate_invalid_guest_state)
2734 return;
2735
7ffd92c5
AK		 2736 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2737 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2738 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2739 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2740
2fb92db1
AK		 2741 vmx_segment_cache_clear(vmx);
2742
6aa8b732
AK		 2743 vmcs_write16(GUEST_SS_SELECTOR, 0);
2744 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2745
2746 vmcs_write16(GUEST_CS_SELECTOR,
2747 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2748 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2749}
2750
d77c26fc 2751static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2752{
bfc6d222 2753 if (!kvm->arch.tss_addr) {
bc6678a3 2754 struct kvm_memslots *slots;
28a37544 2755 struct kvm_memory_slot *slot;
bc6678a3
MT		 2756 gfn_t base_gfn;
2757
90d83dc3 2758 slots = kvm_memslots(kvm);
28a37544
XG		 2759 slot = id_to_memslot(slots, 0);
2760 base_gfn = slot->base_gfn + slot->npages - 3;
2761
cbc94022
IE		 2762 return base_gfn << PAGE_SHIFT;
2763 }
bfc6d222 2764 return kvm->arch.tss_addr;
6aa8b732
AK		 2765}
2766
2767static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2768{
2769 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2770
2771 save->selector = vmcs_read16(sf->selector);
2772 save->base = vmcs_readl(sf->base);
2773 save->limit = vmcs_read32(sf->limit);
2774 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2775 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2776 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2777 vmcs_write32(sf->limit, 0xffff);
2778 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2779 if (save->base & 0xf)
2780 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2781 " aligned when entering protected mode (seg=%d)",
2782 seg);
6aa8b732
AK		 2783}
2784
2785static void enter_rmode(struct kvm_vcpu *vcpu)
2786{
2787 unsigned long flags;
a89a8fb9 2788 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2789 struct kvm_segment var;
6aa8b732 2790
3a624e29
NK		 2791 if (enable_unrestricted_guest)
2792 return;
2793
a89a8fb9 2794 vmx->emulation_required = 1;
7ffd92c5 2795 vmx->rmode.vm86_active = 1;
6aa8b732 2796
776e58ea
GN		 2797 /*
2798 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2799 * vcpu. Call it here with phys address pointing 16M below 4G.
2800 */
2801 if (!vcpu->kvm->arch.tss_addr) {
2802 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2803 "called before entering vcpu\n");
2804 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2805 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2806 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2807 }
2808
2fb92db1
AK		 2809 vmx_segment_cache_clear(vmx);
2810
d0ba64f9 2811 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2812 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2813 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2814
7ffd92c5 2815 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2816 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2817
7ffd92c5 2818 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2819 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2820
2821 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2822 vmx->rmode.save_rflags = flags;
6aa8b732 2823
053de044 2824 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2825
2826 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2827 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2828 update_exception_bitmap(vcpu);
2829
a89a8fb9
MG		 2830 if (emulate_invalid_guest_state)
2831 goto continue_rmode;
2832
b246dd5d
OW		 2833 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2834 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2835
2836 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2837 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2838
2839 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2840 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2841
2842 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2843 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2844
b246dd5d
OW		 2845 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2847
b246dd5d
OW		 2848 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2850
a89a8fb9 2851continue_rmode:
8668a3c4 2852 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2853}
2854
401d10de
AS		 2855static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2856{
2857 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2858 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2859
2860 if (!msr)
2861 return;
401d10de 2862
44ea2b17
AK		 2863 /*
2864 * Force kernel_gs_base reloading before EFER changes, as control
2865 * of this msr depends on is_long_mode().
2866 */
2867 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2868 vcpu->arch.efer = efer;
401d10de
AS		 2869 if (efer & EFER_LMA) {
2870 vmcs_write32(VM_ENTRY_CONTROLS,
2871 vmcs_read32(VM_ENTRY_CONTROLS) |
2872 VM_ENTRY_IA32E_MODE);
2873 msr->data = efer;
2874 } else {
2875 vmcs_write32(VM_ENTRY_CONTROLS,
2876 vmcs_read32(VM_ENTRY_CONTROLS) &
2877 ~VM_ENTRY_IA32E_MODE);
2878
2879 msr->data = efer & ~EFER_LME;
2880 }
2881 setup_msrs(vmx);
2882}
2883
05b3e0c2 2884#ifdef CONFIG_X86_64
6aa8b732
AK		 2885
2886static void enter_lmode(struct kvm_vcpu *vcpu)
2887{
2888 u32 guest_tr_ar;
2889
2fb92db1
AK		 2890 vmx_segment_cache_clear(to_vmx(vcpu));
2891
6aa8b732
AK		 2892 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2893 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2894 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2895 __func__);
6aa8b732
AK		 2896 vmcs_write32(GUEST_TR_AR_BYTES,
2897 (guest_tr_ar & ~AR_TYPE_MASK)
2898 | AR_TYPE_BUSY_64_TSS);
2899 }
da38f438 2900 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2901}
2902
2903static void exit_lmode(struct kvm_vcpu *vcpu)
2904{
6aa8b732
AK		 2905 vmcs_write32(VM_ENTRY_CONTROLS,
2906 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2907 & ~VM_ENTRY_IA32E_MODE);
da38f438 2908 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2909}
2910
2911#endif
2912
2384d2b3
SY		 2913static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2914{
b9d762fa 2915 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2916 if (enable_ept) {
2917 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2918 return;
4e1096d2 2919 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2920 }
2384d2b3
SY		 2921}
2922
e8467fda
AK		 2923static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2924{
2925 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2926
2927 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2928 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2929}
2930
aff48baa
AK		 2931static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2932{
2933 if (enable_ept && is_paging(vcpu))
2934 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2935 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2936}
2937
25c4c276 2938static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2939{
fc78f519
AK		 2940 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2941
2942 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2943 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2944}
2945
1439442c
SY		 2946static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2947{
6de4f3ad
AK		 2948 if (!test_bit(VCPU_EXREG_PDPTR,
2949 (unsigned long *)&vcpu->arch.regs_dirty))
2950 return;
2951
1439442c 2952 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2953 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2954 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2955 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2956 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2957 }
2958}
2959
8f5d549f
AK		 2960static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2961{
2962 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2963 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2964 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2965 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2966 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2967 }
6de4f3ad
AK		 2968
2969 __set_bit(VCPU_EXREG_PDPTR,
2970 (unsigned long *)&vcpu->arch.regs_avail);
2971 __set_bit(VCPU_EXREG_PDPTR,
2972 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2973}
2974
5e1746d6 2975static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2976
2977static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2978 unsigned long cr0,
2979 struct kvm_vcpu *vcpu)
2980{
5233dd51
MT		 2981 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2982 vmx_decache_cr3(vcpu);
1439442c
SY		 2983 if (!(cr0 & X86_CR0_PG)) {
2984 /* From paging/starting to nonpaging */
2985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2986 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2987 (CPU_BASED_CR3_LOAD_EXITING |
2988 CPU_BASED_CR3_STORE_EXITING));
2989 vcpu->arch.cr0 = cr0;
fc78f519 2990 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2991 } else if (!is_paging(vcpu)) {
2992 /* From nonpaging to paging */
2993 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2994 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2995 ~(CPU_BASED_CR3_LOAD_EXITING |
2996 CPU_BASED_CR3_STORE_EXITING));
2997 vcpu->arch.cr0 = cr0;
fc78f519 2998 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2999 }
95eb84a7
SY		 3000
3001 if (!(cr0 & X86_CR0_WP))
3002 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3003}
3004
6aa8b732
AK		 3005static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3006{
7ffd92c5 3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3008 unsigned long hw_cr0;
3009
3010 if (enable_unrestricted_guest)
3011 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3012 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3013 else
3014 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3015
7ffd92c5 3016 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3017 enter_pmode(vcpu);
3018
7ffd92c5 3019 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3020 enter_rmode(vcpu);
3021
05b3e0c2 3022#ifdef CONFIG_X86_64
f6801dff 3023 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3024 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3025 enter_lmode(vcpu);
707d92fa 3026 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3027 exit_lmode(vcpu);
3028 }
3029#endif
3030
089d034e 3031 if (enable_ept)
1439442c
SY		 3032 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3033
02daab21 3034 if (!vcpu->fpu_active)
81231c69 3035 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3036
6aa8b732 3037 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3038 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3039 vcpu->arch.cr0 = cr0;
69c73028 3040 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3041}
3042
1439442c
SY		 3043static u64 construct_eptp(unsigned long root_hpa)
3044{
3045 u64 eptp;
3046
3047 /* TODO write the value reading from MSR */
3048 eptp = VMX_EPT_DEFAULT_MT |
3049 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3050 if (enable_ept_ad_bits)
3051 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3052 eptp |= (root_hpa & PAGE_MASK);
3053
3054 return eptp;
3055}
3056
6aa8b732
AK		 3057static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3058{
1439442c
SY		 3059 unsigned long guest_cr3;
3060 u64 eptp;
3061
3062 guest_cr3 = cr3;
089d034e 3063 if (enable_ept) {
1439442c
SY		 3064 eptp = construct_eptp(cr3);
3065 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3066 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3067 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3068 ept_load_pdptrs(vcpu);
1439442c
SY		 3069 }
3070
2384d2b3 3071 vmx_flush_tlb(vcpu);
1439442c 3072 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3073}
3074
5e1746d6 3075static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3076{
7ffd92c5 3077 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3078 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3079
5e1746d6
NHE		 3080 if (cr4 & X86_CR4_VMXE) {
3081 /*
3082 * To use VMXON (and later other VMX instructions), a guest
3083 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3084 * So basically the check on whether to allow nested VMX
3085 * is here.
3086 */
3087 if (!nested_vmx_allowed(vcpu))
3088 return 1;
3089 } else if (to_vmx(vcpu)->nested.vmxon)
3090 return 1;
3091
ad312c7c 3092 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3093 if (enable_ept) {
3094 if (!is_paging(vcpu)) {
3095 hw_cr4 &= ~X86_CR4_PAE;
3096 hw_cr4 |= X86_CR4_PSE;
3097 } else if (!(cr4 & X86_CR4_PAE)) {
3098 hw_cr4 &= ~X86_CR4_PAE;
3099 }
3100 }
1439442c
SY		 3101
3102 vmcs_writel(CR4_READ_SHADOW, cr4);
3103 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3104 return 0;
6aa8b732
AK		 3105}
3106
6aa8b732
AK		 3107static void vmx_get_segment(struct kvm_vcpu *vcpu,
3108 struct kvm_segment *var, int seg)
3109{
a9179499 3110 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3111 struct kvm_save_segment *save;
6aa8b732
AK		 3112 u32 ar;
3113
a9179499
AK		 3114 if (vmx->rmode.vm86_active
3115 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3116 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3117 || seg == VCPU_SREG_GS)
3118 && !emulate_invalid_guest_state) {
3119 switch (seg) {
3120 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3121 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3122 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3123 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3124 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3125 default: BUG();
3126 }
3127 var->selector = save->selector;
3128 var->base = save->base;
3129 var->limit = save->limit;
3130 ar = save->ar;
3131 if (seg == VCPU_SREG_TR
2fb92db1 3132 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3133 goto use_saved_rmode_seg;
3134 }
2fb92db1
AK		 3135 var->base = vmx_read_guest_seg_base(vmx, seg);
3136 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3137 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3138 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3139use_saved_rmode_seg:
9fd4a3b7 3140 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3141 ar = 0;
3142 var->type = ar & 15;
3143 var->s = (ar >> 4) & 1;
3144 var->dpl = (ar >> 5) & 3;
3145 var->present = (ar >> 7) & 1;
3146 var->avl = (ar >> 12) & 1;
3147 var->l = (ar >> 13) & 1;
3148 var->db = (ar >> 14) & 1;
3149 var->g = (ar >> 15) & 1;
3150 var->unusable = (ar >> 16) & 1;
3151}
3152
a9179499
AK		 3153static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3154{
a9179499
AK		 3155 struct kvm_segment s;
3156
3157 if (to_vmx(vcpu)->rmode.vm86_active) {
3158 vmx_get_segment(vcpu, &s, seg);
3159 return s.base;
3160 }
2fb92db1 3161 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3162}
3163
69c73028 3164static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3165{
3eeb3288 3166 if (!is_protmode(vcpu))
2e4d2653
IE		 3167 return 0;
3168
f4c63e5d
AK		 3169 if (!is_long_mode(vcpu)
3170 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3171 return 3;
3172
2fb92db1 3173 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3174}
3175
69c73028
AK		 3176static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3177{
3178 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3179 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3180 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3181 }
3182 return to_vmx(vcpu)->cpl;
3183}
3184
3185
653e3108 3186static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3187{
6aa8b732
AK		 3188 u32 ar;
3189
653e3108 3190 if (var->unusable)
6aa8b732
AK		 3191 ar = 1 << 16;
3192 else {
3193 ar = var->type & 15;
3194 ar |= (var->s & 1) << 4;
3195 ar |= (var->dpl & 3) << 5;
3196 ar |= (var->present & 1) << 7;
3197 ar |= (var->avl & 1) << 12;
3198 ar |= (var->l & 1) << 13;
3199 ar |= (var->db & 1) << 14;
3200 ar |= (var->g & 1) << 15;
3201 }
f7fbf1fd
UL		 3202 if (ar == 0) /* a 0 value means unusable */
3203 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3204
3205 return ar;
3206}
3207
3208static void vmx_set_segment(struct kvm_vcpu *vcpu,
3209 struct kvm_segment *var, int seg)
3210{
7ffd92c5 3211 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3212 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3213 u32 ar;
3214
2fb92db1
AK		 3215 vmx_segment_cache_clear(vmx);
3216
7ffd92c5 3217 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3218 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3219 vmx->rmode.tr.selector = var->selector;
3220 vmx->rmode.tr.base = var->base;
3221 vmx->rmode.tr.limit = var->limit;
3222 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3223 return;
3224 }
3225 vmcs_writel(sf->base, var->base);
3226 vmcs_write32(sf->limit, var->limit);
3227 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3228 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3229 /*
3230 * Hack real-mode segments into vm86 compatibility.
3231 */
3232 if (var->base == 0xffff0000 && var->selector == 0xf000)
3233 vmcs_writel(sf->base, 0xf0000);
3234 ar = 0xf3;
3235 } else
3236 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3237
3238 /*
3239 * Fix the "Accessed" bit in AR field of segment registers for older
3240 * qemu binaries.
3241 * IA32 arch specifies that at the time of processor reset the
3242 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3243 * is setting it to 0 in the usedland code. This causes invalid guest
3244 * state vmexit when "unrestricted guest" mode is turned on.
3245 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3246 * tree. Newer qemu binaries with that qemu fix would not need this
3247 * kvm hack.
3248 */
3249 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3250 ar |= 0x1; /* Accessed */
3251
6aa8b732 3252 vmcs_write32(sf->ar_bytes, ar);
69c73028 3253 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3254
3255 /*
3256 * Fix segments for real mode guest in hosts that don't have
3257 * "unrestricted_mode" or it was disabled.
3258 * This is done to allow migration of the guests from hosts with
3259 * unrestricted guest like Westmere to older host that don't have
3260 * unrestricted guest like Nehelem.
3261 */
3262 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3263 switch (seg) {
3264 case VCPU_SREG_CS:
3265 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3266 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3267 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3268 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3269 vmcs_write16(GUEST_CS_SELECTOR,
3270 vmcs_readl(GUEST_CS_BASE) >> 4);
3271 break;
3272 case VCPU_SREG_ES:
3273 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3274 break;
3275 case VCPU_SREG_DS:
3276 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3277 break;
3278 case VCPU_SREG_GS:
3279 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3280 break;
3281 case VCPU_SREG_FS:
3282 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3283 break;
3284 case VCPU_SREG_SS:
3285 vmcs_write16(GUEST_SS_SELECTOR,
3286 vmcs_readl(GUEST_SS_BASE) >> 4);
3287 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3288 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3289 break;
3290 }
3291 }
6aa8b732
AK		 3292}
3293
6aa8b732
AK		 3294static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3295{
2fb92db1 3296 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3297
3298 *db = (ar >> 14) & 1;
3299 *l = (ar >> 13) & 1;
3300}
3301
89a27f4d 3302static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3303{
89a27f4d
GN		 3304 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3305 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3306}
3307
89a27f4d 3308static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3309{
89a27f4d
GN		 3310 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3311 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3312}
3313
89a27f4d 3314static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3315{
89a27f4d
GN		 3316 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3317 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3318}
3319
89a27f4d 3320static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3321{
89a27f4d
GN		 3322 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3323 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3324}
3325
648dfaa7
MG		 3326static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3327{
3328 struct kvm_segment var;
3329 u32 ar;
3330
3331 vmx_get_segment(vcpu, &var, seg);
3332 ar = vmx_segment_access_rights(&var);
3333
3334 if (var.base != (var.selector << 4))
3335 return false;
3336 if (var.limit != 0xffff)
3337 return false;
3338 if (ar != 0xf3)
3339 return false;
3340
3341 return true;
3342}
3343
3344static bool code_segment_valid(struct kvm_vcpu *vcpu)
3345{
3346 struct kvm_segment cs;
3347 unsigned int cs_rpl;
3348
3349 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3350 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3351
1872a3f4
AK		 3352 if (cs.unusable)
3353 return false;
648dfaa7
MG		 3354 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3355 return false;
3356 if (!cs.s)
3357 return false;
1872a3f4 3358 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3359 if (cs.dpl > cs_rpl)
3360 return false;
1872a3f4 3361 } else {
648dfaa7
MG		 3362 if (cs.dpl != cs_rpl)
3363 return false;
3364 }
3365 if (!cs.present)
3366 return false;
3367
3368 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3369 return true;
3370}
3371
3372static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3373{
3374 struct kvm_segment ss;
3375 unsigned int ss_rpl;
3376
3377 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3378 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3379
1872a3f4
AK		 3380 if (ss.unusable)
3381 return true;
3382 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3383 return false;
3384 if (!ss.s)
3385 return false;
3386 if (ss.dpl != ss_rpl) /* DPL != RPL */
3387 return false;
3388 if (!ss.present)
3389 return false;
3390
3391 return true;
3392}
3393
3394static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3395{
3396 struct kvm_segment var;
3397 unsigned int rpl;
3398
3399 vmx_get_segment(vcpu, &var, seg);
3400 rpl = var.selector & SELECTOR_RPL_MASK;
3401
1872a3f4
AK		 3402 if (var.unusable)
3403 return true;
648dfaa7
MG		 3404 if (!var.s)
3405 return false;
3406 if (!var.present)
3407 return false;
3408 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3409 if (var.dpl < rpl) /* DPL < RPL */
3410 return false;
3411 }
3412
3413 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3414 * rights flags
3415 */
3416 return true;
3417}
3418
3419static bool tr_valid(struct kvm_vcpu *vcpu)
3420{
3421 struct kvm_segment tr;
3422
3423 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3424
1872a3f4
AK		 3425 if (tr.unusable)
3426 return false;
648dfaa7
MG		 3427 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3428 return false;
1872a3f4 3429 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3430 return false;
3431 if (!tr.present)
3432 return false;
3433
3434 return true;
3435}
3436
3437static bool ldtr_valid(struct kvm_vcpu *vcpu)
3438{
3439 struct kvm_segment ldtr;
3440
3441 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3442
1872a3f4
AK		 3443 if (ldtr.unusable)
3444 return true;
648dfaa7
MG		 3445 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3446 return false;
3447 if (ldtr.type != 2)
3448 return false;
3449 if (!ldtr.present)
3450 return false;
3451
3452 return true;
3453}
3454
3455static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3456{
3457 struct kvm_segment cs, ss;
3458
3459 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3460 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3461
3462 return ((cs.selector & SELECTOR_RPL_MASK) ==
3463 (ss.selector & SELECTOR_RPL_MASK));
3464}
3465
3466/*
3467 * Check if guest state is valid. Returns true if valid, false if
3468 * not.
3469 * We assume that registers are always usable
3470 */
3471static bool guest_state_valid(struct kvm_vcpu *vcpu)
3472{
3473 /* real mode guest state checks */
3eeb3288 3474 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3475 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3476 return false;
3477 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3478 return false;
3479 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3480 return false;
3481 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3482 return false;
3483 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3484 return false;
3485 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3486 return false;
3487 } else {
3488 /* protected mode guest state checks */
3489 if (!cs_ss_rpl_check(vcpu))
3490 return false;
3491 if (!code_segment_valid(vcpu))
3492 return false;
3493 if (!stack_segment_valid(vcpu))
3494 return false;
3495 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3496 return false;
3497 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3498 return false;
3499 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3500 return false;
3501 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3502 return false;
3503 if (!tr_valid(vcpu))
3504 return false;
3505 if (!ldtr_valid(vcpu))
3506 return false;
3507 }
3508 /* TODO:
3509 * - Add checks on RIP
3510 * - Add checks on RFLAGS
3511 */
3512
3513 return true;
3514}
3515
d77c26fc 3516static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3517{
40dcaa9f 3518 gfn_t fn;
195aefde 3519 u16 data = 0;
40dcaa9f 3520 int r, idx, ret = 0;
6aa8b732 3521
40dcaa9f
XG		 3522 idx = srcu_read_lock(&kvm->srcu);
3523 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3524 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3525 if (r < 0)
10589a46 3526 goto out;
195aefde 3527 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3528 r = kvm_write_guest_page(kvm, fn++, &data,
3529 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3530 if (r < 0)
10589a46 3531 goto out;
195aefde
IE		 3532 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3533 if (r < 0)
10589a46 3534 goto out;
195aefde
IE		 3535 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3536 if (r < 0)
10589a46 3537 goto out;
195aefde 3538 data = ~0;
10589a46
MT		 3539 r = kvm_write_guest_page(kvm, fn, &data,
3540 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3541 sizeof(u8));
195aefde 3542 if (r < 0)
10589a46
MT		 3543 goto out;
3544
3545 ret = 1;
3546out:
40dcaa9f 3547 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3548 return ret;
6aa8b732
AK		 3549}
3550
b7ebfb05
SY		 3551static int init_rmode_identity_map(struct kvm *kvm)
3552{
40dcaa9f 3553 int i, idx, r, ret;
b7ebfb05
SY		 3554 pfn_t identity_map_pfn;
3555 u32 tmp;
3556
089d034e 3557 if (!enable_ept)
b7ebfb05
SY		 3558 return 1;
3559 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3560 printk(KERN_ERR "EPT: identity-mapping pagetable "
3561 "haven't been allocated!\n");
3562 return 0;
3563 }
3564 if (likely(kvm->arch.ept_identity_pagetable_done))
3565 return 1;
3566 ret = 0;
b927a3ce 3567 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3568 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3569 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3570 if (r < 0)
3571 goto out;
3572 /* Set up identity-mapping pagetable for EPT in real mode */
3573 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3574 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3575 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3576 r = kvm_write_guest_page(kvm, identity_map_pfn,
3577 &tmp, i * sizeof(tmp), sizeof(tmp));
3578 if (r < 0)
3579 goto out;
3580 }
3581 kvm->arch.ept_identity_pagetable_done = true;
3582 ret = 1;
3583out:
40dcaa9f 3584 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3585 return ret;
3586}
3587
6aa8b732
AK		 3588static void seg_setup(int seg)
3589{
3590 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3591 unsigned int ar;
6aa8b732
AK		 3592
3593 vmcs_write16(sf->selector, 0);
3594 vmcs_writel(sf->base, 0);
3595 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3596 if (enable_unrestricted_guest) {
3597 ar = 0x93;
3598 if (seg == VCPU_SREG_CS)
3599 ar |= 0x08; /* code segment */
3600 } else
3601 ar = 0xf3;
3602
3603 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3604}
3605
f78e0e2e
SY		 3606static int alloc_apic_access_page(struct kvm *kvm)
3607{
3608 struct kvm_userspace_memory_region kvm_userspace_mem;
3609 int r = 0;
3610
79fac95e 3611 mutex_lock(&kvm->slots_lock);
bfc6d222 3612 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3613 goto out;
3614 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3615 kvm_userspace_mem.flags = 0;
3616 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3617 kvm_userspace_mem.memory_size = PAGE_SIZE;
3618 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3619 if (r)
3620 goto out;
72dc67a6 3621
bfc6d222 3622 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3623out:
79fac95e 3624 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3625 return r;
3626}
3627
b7ebfb05
SY		 3628static int alloc_identity_pagetable(struct kvm *kvm)
3629{
3630 struct kvm_userspace_memory_region kvm_userspace_mem;
3631 int r = 0;
3632
79fac95e 3633 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3634 if (kvm->arch.ept_identity_pagetable)
3635 goto out;
3636 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3637 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3638 kvm_userspace_mem.guest_phys_addr =
3639 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3640 kvm_userspace_mem.memory_size = PAGE_SIZE;
3641 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3642 if (r)
3643 goto out;
3644
b7ebfb05 3645 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3646 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3647out:
79fac95e 3648 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3649 return r;
3650}
3651
2384d2b3
SY		 3652static void allocate_vpid(struct vcpu_vmx *vmx)
3653{
3654 int vpid;
3655
3656 vmx->vpid = 0;
919818ab 3657 if (!enable_vpid)
2384d2b3
SY		 3658 return;
3659 spin_lock(&vmx_vpid_lock);
3660 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3661 if (vpid < VMX_NR_VPIDS) {
3662 vmx->vpid = vpid;
3663 __set_bit(vpid, vmx_vpid_bitmap);
3664 }
3665 spin_unlock(&vmx_vpid_lock);
3666}
3667
cdbecfc3
LJ		 3668static void free_vpid(struct vcpu_vmx *vmx)
3669{
3670 if (!enable_vpid)
3671 return;
3672 spin_lock(&vmx_vpid_lock);
3673 if (vmx->vpid != 0)
3674 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3675 spin_unlock(&vmx_vpid_lock);
3676}
3677
5897297b 3678static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3679{
3e7c73e9 3680 int f = sizeof(unsigned long);
25c5f225
SY		 3681
3682 if (!cpu_has_vmx_msr_bitmap())
3683 return;
3684
3685 /*
3686 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3687 * have the write-low and read-high bitmap offsets the wrong way round.
3688 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3689 */
25c5f225 3690 if (msr <= 0x1fff) {
3e7c73e9
AK		 3691 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3692 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3693 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3694 msr &= 0x1fff;
3e7c73e9
AK		 3695 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3696 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3697 }
25c5f225
SY		 3698}
3699
5897297b
AK		 3700static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3701{
3702 if (!longmode_only)
3703 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3704 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3705}
3706
a3a8ff8e
NHE		 3707/*
3708 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3709 * will not change in the lifetime of the guest.
3710 * Note that host-state that does change is set elsewhere. E.g., host-state
3711 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3712 */
3713static void vmx_set_constant_host_state(void)
3714{
3715 u32 low32, high32;
3716 unsigned long tmpl;
3717 struct desc_ptr dt;
3718
3719 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3720 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3721 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3722
3723 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3724#ifdef CONFIG_X86_64
3725 /*
3726 * Load null selectors, so we can avoid reloading them in
3727 * __vmx_load_host_state(), in case userspace uses the null selectors
3728 * too (the expected case).
3729 */
3730 vmcs_write16(HOST_DS_SELECTOR, 0);
3731 vmcs_write16(HOST_ES_SELECTOR, 0);
3732#else
a3a8ff8e
NHE		 3733 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3734 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3735#endif
a3a8ff8e
NHE		 3736 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3737 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3738
3739 native_store_idt(&dt);
3740 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3741
3742 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3743 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3744
3745 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3746 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3747 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3748 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3749
3750 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3751 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3752 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3753 }
3754}
3755
bf8179a0
NHE		 3756static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3757{
3758 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3759 if (enable_ept)
3760 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3761 if (is_guest_mode(&vmx->vcpu))
3762 vmx->vcpu.arch.cr4_guest_owned_bits &=
3763 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3764 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3765}
3766
3767static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3768{
3769 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3770 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3771 exec_control &= ~CPU_BASED_TPR_SHADOW;
3772#ifdef CONFIG_X86_64
3773 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3774 CPU_BASED_CR8_LOAD_EXITING;
3775#endif
3776 }
3777 if (!enable_ept)
3778 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3779 CPU_BASED_CR3_LOAD_EXITING |
3780 CPU_BASED_INVLPG_EXITING;
3781 return exec_control;
3782}
3783
3784static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3785{
3786 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3787 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3788 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3789 if (vmx->vpid == 0)
3790 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3791 if (!enable_ept) {
3792 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3793 enable_unrestricted_guest = 0;
3794 }
3795 if (!enable_unrestricted_guest)
3796 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3797 if (!ple_gap)
3798 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3799 return exec_control;
3800}
3801
ce88decf
XG		 3802static void ept_set_mmio_spte_mask(void)
3803{
3804 /*
3805 * EPT Misconfigurations can be generated if the value of bits 2:0
3806 * of an EPT paging-structure entry is 110b (write/execute).
3807 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3808 * spte.
3809 */
3810 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3811}
3812
6aa8b732
AK		 3813/*
3814 * Sets up the vmcs for emulated real mode.
3815 */
8b9cf98c 3816static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3817{
2e4ce7f5 3818#ifdef CONFIG_X86_64
6aa8b732 3819 unsigned long a;
2e4ce7f5 3820#endif
6aa8b732 3821 int i;
6aa8b732 3822
6aa8b732 3823 /* I/O */
3e7c73e9
AK		 3824 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3825 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3826
25c5f225 3827 if (cpu_has_vmx_msr_bitmap())
5897297b 3828 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3829
6aa8b732
AK		 3830 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3831
6aa8b732 3832 /* Control */
1c3d14fe
YS		 3833 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3834 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3835
bf8179a0 3836 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3837
83ff3b9d 3838 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3839 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3840 vmx_secondary_exec_control(vmx));
83ff3b9d 3841 }
f78e0e2e 3842
4b8d54f9
ZE		 3843 if (ple_gap) {
3844 vmcs_write32(PLE_GAP, ple_gap);
3845 vmcs_write32(PLE_WINDOW, ple_window);
3846 }
3847
c3707958
XG		 3848 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3849 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3850 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3851
9581d442
AK		 3852 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3853 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3854 vmx_set_constant_host_state();
05b3e0c2 3855#ifdef CONFIG_X86_64
6aa8b732
AK		 3856 rdmsrl(MSR_FS_BASE, a);
3857 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3858 rdmsrl(MSR_GS_BASE, a);
3859 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3860#else
3861 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3862 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3863#endif
3864
2cc51560
ED		 3865 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3866 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3867 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3868 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3869 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3870
468d472f 3871 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3872 u32 msr_low, msr_high;
3873 u64 host_pat;
468d472f
SY		 3874 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3875 host_pat = msr_low | ((u64) msr_high << 32);
3876 /* Write the default value follow host pat */
3877 vmcs_write64(GUEST_IA32_PAT, host_pat);
3878 /* Keep arch.pat sync with GUEST_IA32_PAT */
3879 vmx->vcpu.arch.pat = host_pat;
3880 }
3881
6aa8b732
AK		 3882 for (i = 0; i < NR_VMX_MSR; ++i) {
3883 u32 index = vmx_msr_index[i];
3884 u32 data_low, data_high;
a2fa3e9f 3885 int j = vmx->nmsrs;
6aa8b732
AK		 3886
3887 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3888 continue;
432bd6cb
AK		 3889 if (wrmsr_safe(index, data_low, data_high) < 0)
3890 continue;
26bb0981
AK		 3891 vmx->guest_msrs[j].index = i;
3892 vmx->guest_msrs[j].data = 0;
d5696725 3893 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3894 ++vmx->nmsrs;
6aa8b732 3895 }
6aa8b732 3896
1c3d14fe 3897 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3898
3899 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3900 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3901
e00c8cf2 3902 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3903 set_cr4_guest_host_mask(vmx);
e00c8cf2 3904
99e3e30a 3905 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3906
e00c8cf2
AK		 3907 return 0;
3908}
3909
3910static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3911{
3912 struct vcpu_vmx *vmx = to_vmx(vcpu);
3913 u64 msr;
4b9d3a04 3914 int ret;
e00c8cf2 3915
5fdbf976 3916 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3917
7ffd92c5 3918 vmx->rmode.vm86_active = 0;
e00c8cf2 3919
3b86cd99
JK		 3920 vmx->soft_vnmi_blocked = 0;
3921
ad312c7c 3922 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3923 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3924 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3925 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3926 msr |= MSR_IA32_APICBASE_BSP;
3927 kvm_set_apic_base(&vmx->vcpu, msr);
3928
10ab25cd
JK		 3929 ret = fx_init(&vmx->vcpu);
3930 if (ret != 0)
3931 goto out;
e00c8cf2 3932
2fb92db1
AK		 3933 vmx_segment_cache_clear(vmx);
3934
5706be0d 3935 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3936 /*
3937 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3938 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3939 */
c5af89b6 3940 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3941 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3942 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3943 } else {
ad312c7c
ZX		 3944 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3945 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3946 }
e00c8cf2
AK		 3947
3948 seg_setup(VCPU_SREG_DS);
3949 seg_setup(VCPU_SREG_ES);
3950 seg_setup(VCPU_SREG_FS);
3951 seg_setup(VCPU_SREG_GS);
3952 seg_setup(VCPU_SREG_SS);
3953
3954 vmcs_write16(GUEST_TR_SELECTOR, 0);
3955 vmcs_writel(GUEST_TR_BASE, 0);
3956 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3957 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3958
3959 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3960 vmcs_writel(GUEST_LDTR_BASE, 0);
3961 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3962 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3963
3964 vmcs_write32(GUEST_SYSENTER_CS, 0);
3965 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3966 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3967
3968 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3969 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3970 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3971 else
5fdbf976
MT		 3972 kvm_rip_write(vcpu, 0);
3973 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3974
e00c8cf2
AK		 3975 vmcs_writel(GUEST_DR7, 0x400);
3976
3977 vmcs_writel(GUEST_GDTR_BASE, 0);
3978 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3979
3980 vmcs_writel(GUEST_IDTR_BASE, 0);
3981 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3982
443381a8 3983 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3984 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3985 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3986
e00c8cf2
AK		 3987 /* Special registers */
3988 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3989
3990 setup_msrs(vmx);
3991
6aa8b732
AK		 3992 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3993
f78e0e2e
SY		 3994 if (cpu_has_vmx_tpr_shadow()) {
3995 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3996 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3997 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3998 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3999 vmcs_write32(TPR_THRESHOLD, 0);
4000 }
4001
4002 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4003 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4004 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4005
2384d2b3
SY		 4006 if (vmx->vpid != 0)
4007 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4008
fa40052c 4009 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4010 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4011 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4012 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4013 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4014 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4015 vmx_fpu_activate(&vmx->vcpu);
4016 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4017
b9d762fa 4018 vpid_sync_context(vmx);
2384d2b3 4019
3200f405 4020 ret = 0;
6aa8b732 4021
a89a8fb9
MG		 4022 /* HACK: Don't enable emulation on guest boot/reset */
4023 vmx->emulation_required = 0;
4024
6aa8b732
AK		 4025out:
4026 return ret;
4027}
4028
b6f1250e
NHE		 4029/*
4030 * In nested virtualization, check if L1 asked to exit on external interrupts.
4031 * For most existing hypervisors, this will always return true.
4032 */
4033static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4034{
4035 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4036 PIN_BASED_EXT_INTR_MASK;
4037}
4038
3b86cd99
JK		 4039static void enable_irq_window(struct kvm_vcpu *vcpu)
4040{
4041 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4042 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4043 /*
4044 * We get here if vmx_interrupt_allowed() said we can't
4045 * inject to L1 now because L2 must run. Ask L2 to exit
4046 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4047 */
d6185f20 4048 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4049 return;
d6185f20 4050 }
3b86cd99
JK		 4051
4052 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4053 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4054 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4055}
4056
4057static void enable_nmi_window(struct kvm_vcpu *vcpu)
4058{
4059 u32 cpu_based_vm_exec_control;
4060
4061 if (!cpu_has_virtual_nmis()) {
4062 enable_irq_window(vcpu);
4063 return;
4064 }
4065
30bd0c4c
AK		 4066 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4067 enable_irq_window(vcpu);
4068 return;
4069 }
3b86cd99
JK		 4070 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4071 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4072 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4073}
4074
66fd3f7f 4075static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4076{
9c8cba37 4077 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4078 uint32_t intr;
4079 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4080
229456fc 4081 trace_kvm_inj_virq(irq);
2714d1d3 4082
fa89a817 4083 ++vcpu->stat.irq_injections;
7ffd92c5 4084 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4085 int inc_eip = 0;
4086 if (vcpu->arch.interrupt.soft)
4087 inc_eip = vcpu->arch.event_exit_inst_len;
4088 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4089 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4090 return;
4091 }
66fd3f7f
GN		 4092 intr = irq | INTR_INFO_VALID_MASK;
4093 if (vcpu->arch.interrupt.soft) {
4094 intr |= INTR_TYPE_SOFT_INTR;
4095 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4096 vmx->vcpu.arch.event_exit_inst_len);
4097 } else
4098 intr |= INTR_TYPE_EXT_INTR;
4099 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4100}
4101
f08864b4
SY		 4102static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4103{
66a5a347
JK		 4104 struct vcpu_vmx *vmx = to_vmx(vcpu);
4105
0b6ac343
NHE		 4106 if (is_guest_mode(vcpu))
4107 return;
4108
3b86cd99
JK		 4109 if (!cpu_has_virtual_nmis()) {
4110 /*
4111 * Tracking the NMI-blocked state in software is built upon
4112 * finding the next open IRQ window. This, in turn, depends on
4113 * well-behaving guests: They have to keep IRQs disabled at
4114 * least as long as the NMI handler runs. Otherwise we may
4115 * cause NMI nesting, maybe breaking the guest. But as this is
4116 * highly unlikely, we can live with the residual risk.
4117 */
4118 vmx->soft_vnmi_blocked = 1;
4119 vmx->vnmi_blocked_time = 0;
4120 }
4121
487b391d 4122 ++vcpu->stat.nmi_injections;
9d58b931 4123 vmx->nmi_known_unmasked = false;
7ffd92c5 4124 if (vmx->rmode.vm86_active) {
71f9833b 4125 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4126 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4127 return;
4128 }
f08864b4
SY		 4129 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4130 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4131}
4132
c4282df9 4133static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4134{
3b86cd99 4135 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4136 return 0;
33f089ca 4137
c4282df9 4138 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4139 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4140 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4141}
4142
3cfc3092
JK		 4143static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4144{
4145 if (!cpu_has_virtual_nmis())
4146 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4147 if (to_vmx(vcpu)->nmi_known_unmasked)
4148 return false;
c332c83a 4149 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4150}
4151
4152static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4153{
4154 struct vcpu_vmx *vmx = to_vmx(vcpu);
4155
4156 if (!cpu_has_virtual_nmis()) {
4157 if (vmx->soft_vnmi_blocked != masked) {
4158 vmx->soft_vnmi_blocked = masked;
4159 vmx->vnmi_blocked_time = 0;
4160 }
4161 } else {
9d58b931 4162 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4163 if (masked)
4164 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4165 GUEST_INTR_STATE_NMI);
4166 else
4167 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4168 GUEST_INTR_STATE_NMI);
4169 }
4170}
4171
78646121
GN		 4172static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4173{
b6f1250e 4174 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4175 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4176 if (to_vmx(vcpu)->nested.nested_run_pending ||
4177 (vmcs12->idt_vectoring_info_field &
4178 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4179 return 0;
4180 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4181 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4182 vmcs12->vm_exit_intr_info = 0;
4183 /* fall through to normal code, but now in L1, not L2 */
4184 }
4185
c4282df9
GN		 4186 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4187 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4188 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4189}
4190
cbc94022
IE		 4191static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4192{
4193 int ret;
4194 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4195 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4196 .guest_phys_addr = addr,
4197 .memory_size = PAGE_SIZE * 3,
4198 .flags = 0,
4199 };
4200
4201 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4202 if (ret)
4203 return ret;
bfc6d222 4204 kvm->arch.tss_addr = addr;
93ea5388
GN		 4205 if (!init_rmode_tss(kvm))
4206 return -ENOMEM;
4207
cbc94022
IE		 4208 return 0;
4209}
4210
6aa8b732
AK		 4211static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4212 int vec, u32 err_code)
4213{
b3f37707
NK		 4214 /*
4215 * Instruction with address size override prefix opcode 0x67
4216 * Cause the #SS fault with 0 error code in VM86 mode.
4217 */
4218 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4219 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4220 return 1;
77ab6db0
JK		 4221 /*
4222 * Forward all other exceptions that are valid in real mode.
4223 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4224 * the required debugging infrastructure rework.
4225 */
4226 switch (vec) {
77ab6db0 4227 case DB_VECTOR:
d0bfb940
JK		 4228 if (vcpu->guest_debug &
4229 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4230 return 0;
4231 kvm_queue_exception(vcpu, vec);
4232 return 1;
77ab6db0 4233 case BP_VECTOR:
c573cd22
JK		 4234 /*
4235 * Update instruction length as we may reinject the exception
4236 * from user space while in guest debugging mode.
4237 */
4238 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4239 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4240 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4241 return 0;
4242 /* fall through */
4243 case DE_VECTOR:
77ab6db0
JK		 4244 case OF_VECTOR:
4245 case BR_VECTOR:
4246 case UD_VECTOR:
4247 case DF_VECTOR:
4248 case SS_VECTOR:
4249 case GP_VECTOR:
4250 case MF_VECTOR:
4251 kvm_queue_exception(vcpu, vec);
4252 return 1;
4253 }
6aa8b732
AK		 4254 return 0;
4255}
4256
a0861c02
AK		 4257/*
4258 * Trigger machine check on the host. We assume all the MSRs are already set up
4259 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4260 * We pass a fake environment to the machine check handler because we want
4261 * the guest to be always treated like user space, no matter what context
4262 * it used internally.
4263 */
4264static void kvm_machine_check(void)
4265{
4266#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4267 struct pt_regs regs = {
4268 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4269 .flags = X86_EFLAGS_IF,
4270 };
4271
4272 do_machine_check(&regs, 0);
4273#endif
4274}
4275
851ba692 4276static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4277{
4278 /* already handled by vcpu_run */
4279 return 1;
4280}
4281
851ba692 4282static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4283{
1155f76a 4284 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4285 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4286 u32 intr_info, ex_no, error_code;
42dbaa5a 4287 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4288 u32 vect_info;
4289 enum emulation_result er;
4290
1155f76a 4291 vect_info = vmx->idt_vectoring_info;
88786475 4292 intr_info = vmx->exit_intr_info;
6aa8b732 4293
a0861c02 4294 if (is_machine_check(intr_info))
851ba692 4295 return handle_machine_check(vcpu);
a0861c02 4296
6aa8b732 4297 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4298 !is_page_fault(intr_info)) {
4299 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4300 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4301 vcpu->run->internal.ndata = 2;
4302 vcpu->run->internal.data[0] = vect_info;
4303 vcpu->run->internal.data[1] = intr_info;
4304 return 0;
4305 }
6aa8b732 4306
e4a41889 4307 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4308 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4309
4310 if (is_no_device(intr_info)) {
5fd86fcf 4311 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4312 return 1;
4313 }
4314
7aa81cc0 4315 if (is_invalid_opcode(intr_info)) {
51d8b661 4316 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4317 if (er != EMULATE_DONE)
7ee5d940 4318 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4319 return 1;
4320 }
4321
6aa8b732 4322 error_code = 0;
2e11384c 4323 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4324 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4325 if (is_page_fault(intr_info)) {
1439442c 4326 /* EPT won't cause page fault directly */
cf3ace79 4327 BUG_ON(enable_ept);
6aa8b732 4328 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4329 trace_kvm_page_fault(cr2, error_code);
4330
3298b75c 4331 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4332 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4333 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4334 }
4335
7ffd92c5 4336 if (vmx->rmode.vm86_active &&
6aa8b732 4337 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4338 error_code)) {
ad312c7c
ZX		 4339 if (vcpu->arch.halt_request) {
4340 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4341 return kvm_emulate_halt(vcpu);
4342 }
6aa8b732 4343 return 1;
72d6e5a0 4344 }
6aa8b732 4345
d0bfb940 4346 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4347 switch (ex_no) {
4348 case DB_VECTOR:
4349 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4350 if (!(vcpu->guest_debug &
4351 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4352 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4353 kvm_queue_exception(vcpu, DB_VECTOR);
4354 return 1;
4355 }
4356 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4357 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4358 /* fall through */
4359 case BP_VECTOR:
c573cd22
JK		 4360 /*
4361 * Update instruction length as we may reinject #BP from
4362 * user space while in guest debugging mode. Reading it for
4363 * #DB as well causes no harm, it is not used in that case.
4364 */
4365 vmx->vcpu.arch.event_exit_inst_len =
4366 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4367 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4368 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4369 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4370 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4371 break;
4372 default:
d0bfb940
JK		 4373 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4374 kvm_run->ex.exception = ex_no;
4375 kvm_run->ex.error_code = error_code;
42dbaa5a 4376 break;
6aa8b732 4377 }
6aa8b732
AK		 4378 return 0;
4379}
4380
851ba692 4381static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4382{
1165f5fe 4383 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4384 return 1;
4385}
4386
851ba692 4387static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4388{
851ba692 4389 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4390 return 0;
4391}
6aa8b732 4392
851ba692 4393static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4394{
bfdaab09 4395 unsigned long exit_qualification;
34c33d16 4396 int size, in, string;
039576c0 4397 unsigned port;
6aa8b732 4398
bfdaab09 4399 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4400 string = (exit_qualification & 16) != 0;
cf8f70bf 4401 in = (exit_qualification & 8) != 0;
e70669ab 4402
cf8f70bf 4403 ++vcpu->stat.io_exits;
e70669ab 4404
cf8f70bf 4405 if (string || in)
51d8b661 4406 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4407
cf8f70bf
GN		 4408 port = exit_qualification >> 16;
4409 size = (exit_qualification & 7) + 1;
e93f36bc 4410 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4411
4412 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4413}
4414
102d8325
IM		 4415static void
4416vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4417{
4418 /*
4419 * Patch in the VMCALL instruction:
4420 */
4421 hypercall[0] = 0x0f;
4422 hypercall[1] = 0x01;
4423 hypercall[2] = 0xc1;
102d8325
IM		 4424}
4425
eeadf9e7
NHE		 4426/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4427static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4428{
4429 if (to_vmx(vcpu)->nested.vmxon &&
4430 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4431 return 1;
4432
4433 if (is_guest_mode(vcpu)) {
4434 /*
4435 * We get here when L2 changed cr0 in a way that did not change
4436 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4437 * but did change L0 shadowed bits. This can currently happen
4438 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4439 * loading) while pretending to allow the guest to change it.
4440 */
4441 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4442 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4443 return 1;
4444 vmcs_writel(CR0_READ_SHADOW, val);
4445 return 0;
4446 } else
4447 return kvm_set_cr0(vcpu, val);
4448}
4449
4450static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4451{
4452 if (is_guest_mode(vcpu)) {
4453 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4454 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4455 return 1;
4456 vmcs_writel(CR4_READ_SHADOW, val);
4457 return 0;
4458 } else
4459 return kvm_set_cr4(vcpu, val);
4460}
4461
4462/* called to set cr0 as approriate for clts instruction exit. */
4463static void handle_clts(struct kvm_vcpu *vcpu)
4464{
4465 if (is_guest_mode(vcpu)) {
4466 /*
4467 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4468 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4469 * just pretend it's off (also in arch.cr0 for fpu_activate).
4470 */
4471 vmcs_writel(CR0_READ_SHADOW,
4472 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4473 vcpu->arch.cr0 &= ~X86_CR0_TS;
4474 } else
4475 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4476}
4477
851ba692 4478static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4479{
229456fc 4480 unsigned long exit_qualification, val;
6aa8b732
AK		 4481 int cr;
4482 int reg;
49a9b07e 4483 int err;
6aa8b732 4484
bfdaab09 4485 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4486 cr = exit_qualification & 15;
4487 reg = (exit_qualification >> 8) & 15;
4488 switch ((exit_qualification >> 4) & 3) {
4489 case 0: /* mov to cr */
229456fc
MT		 4490 val = kvm_register_read(vcpu, reg);
4491 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4492 switch (cr) {
4493 case 0:
eeadf9e7 4494 err = handle_set_cr0(vcpu, val);
db8fcefa 4495 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4496 return 1;
4497 case 3:
2390218b 4498 err = kvm_set_cr3(vcpu, val);
db8fcefa 4499 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4500 return 1;
4501 case 4:
eeadf9e7 4502 err = handle_set_cr4(vcpu, val);
db8fcefa 4503 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4504 return 1;
0a5fff19
GN		 4505 case 8: {
4506 u8 cr8_prev = kvm_get_cr8(vcpu);
4507 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4508 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4509 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4510 if (irqchip_in_kernel(vcpu->kvm))
4511 return 1;
4512 if (cr8_prev <= cr8)
4513 return 1;
851ba692 4514 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4515 return 0;
4516 }
6aa8b732
AK		 4517 };
4518 break;
25c4c276 4519 case 2: /* clts */
eeadf9e7 4520 handle_clts(vcpu);
4d4ec087 4521 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4522 skip_emulated_instruction(vcpu);
6b52d186 4523 vmx_fpu_activate(vcpu);
25c4c276 4524 return 1;
6aa8b732
AK		 4525 case 1: /*mov from cr*/
4526 switch (cr) {
4527 case 3:
9f8fe504
AK		 4528 val = kvm_read_cr3(vcpu);
4529 kvm_register_write(vcpu, reg, val);
4530 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4531 skip_emulated_instruction(vcpu);
4532 return 1;
4533 case 8:
229456fc
MT		 4534 val = kvm_get_cr8(vcpu);
4535 kvm_register_write(vcpu, reg, val);
4536 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4537 skip_emulated_instruction(vcpu);
4538 return 1;
4539 }
4540 break;
4541 case 3: /* lmsw */
a1f83a74 4542 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4543 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4544 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4545
4546 skip_emulated_instruction(vcpu);
4547 return 1;
4548 default:
4549 break;
4550 }
851ba692 4551 vcpu->run->exit_reason = 0;
f0242478 4552 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4553 (int)(exit_qualification >> 4) & 3, cr);
4554 return 0;
4555}
4556
851ba692 4557static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4558{
bfdaab09 4559 unsigned long exit_qualification;
6aa8b732
AK		 4560 int dr, reg;
4561
f2483415 4562 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4563 if (!kvm_require_cpl(vcpu, 0))
4564 return 1;
42dbaa5a
JK		 4565 dr = vmcs_readl(GUEST_DR7);
4566 if (dr & DR7_GD) {
4567 /*
4568 * As the vm-exit takes precedence over the debug trap, we
4569 * need to emulate the latter, either for the host or the
4570 * guest debugging itself.
4571 */
4572 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4573 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4574 vcpu->run->debug.arch.dr7 = dr;
4575 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4576 vmcs_readl(GUEST_CS_BASE) +
4577 vmcs_readl(GUEST_RIP);
851ba692
AK		 4578 vcpu->run->debug.arch.exception = DB_VECTOR;
4579 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4580 return 0;
4581 } else {
4582 vcpu->arch.dr7 &= ~DR7_GD;
4583 vcpu->arch.dr6 |= DR6_BD;
4584 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4585 kvm_queue_exception(vcpu, DB_VECTOR);
4586 return 1;
4587 }
4588 }
4589
bfdaab09 4590 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4591 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4592 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4593 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4594 unsigned long val;
4595 if (!kvm_get_dr(vcpu, dr, &val))
4596 kvm_register_write(vcpu, reg, val);
4597 } else
4598 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4599 skip_emulated_instruction(vcpu);
4600 return 1;
4601}
4602
020df079
GN		 4603static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4604{
4605 vmcs_writel(GUEST_DR7, val);
4606}
4607
851ba692 4608static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4609{
06465c5a
AK		 4610 kvm_emulate_cpuid(vcpu);
4611 return 1;
6aa8b732
AK		 4612}
4613
851ba692 4614static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4615{
ad312c7c 4616 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4617 u64 data;
4618
4619 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4620 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4621 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4622 return 1;
4623 }
4624
229456fc 4625 trace_kvm_msr_read(ecx, data);
2714d1d3 4626
6aa8b732 4627 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4628 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4629 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4630 skip_emulated_instruction(vcpu);
4631 return 1;
4632}
4633
851ba692 4634static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4635{
ad312c7c
ZX		 4636 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4637 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4638 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4639
4640 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4641 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4642 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4643 return 1;
4644 }
4645
59200273 4646 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4647 skip_emulated_instruction(vcpu);
4648 return 1;
4649}
4650
851ba692 4651static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4652{
3842d135 4653 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4654 return 1;
4655}
4656
851ba692 4657static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4658{
85f455f7
ED		 4659 u32 cpu_based_vm_exec_control;
4660
4661 /* clear pending irq */
4662 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4663 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4664 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4665
3842d135
AK		 4666 kvm_make_request(KVM_REQ_EVENT, vcpu);
4667
a26bf12a 4668 ++vcpu->stat.irq_window_exits;
2714d1d3 4669
c1150d8c
DL		 4670 /*
4671 * If the user space waits to inject interrupts, exit as soon as
4672 * possible
4673 */
8061823a 4674 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4675 vcpu->run->request_interrupt_window &&
8061823a 4676 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4677 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4678 return 0;
4679 }
6aa8b732
AK		 4680 return 1;
4681}
4682
851ba692 4683static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4684{
4685 skip_emulated_instruction(vcpu);
d3bef15f 4686 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4687}
4688
851ba692 4689static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4690{
510043da 4691 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4692 kvm_emulate_hypercall(vcpu);
4693 return 1;
c21415e8
IM		 4694}
4695
ec25d5e6
GN		 4696static int handle_invd(struct kvm_vcpu *vcpu)
4697{
51d8b661 4698 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4699}
4700
851ba692 4701static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4702{
f9c617f6 4703 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4704
4705 kvm_mmu_invlpg(vcpu, exit_qualification);
4706 skip_emulated_instruction(vcpu);
4707 return 1;
4708}
4709
fee84b07
AK		 4710static int handle_rdpmc(struct kvm_vcpu *vcpu)
4711{
4712 int err;
4713
4714 err = kvm_rdpmc(vcpu);
4715 kvm_complete_insn_gp(vcpu, err);
4716
4717 return 1;
4718}
4719
851ba692 4720static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4721{
4722 skip_emulated_instruction(vcpu);
f5f48ee1 4723 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4724 return 1;
4725}
4726
2acf923e
DC		 4727static int handle_xsetbv(struct kvm_vcpu *vcpu)
4728{
4729 u64 new_bv = kvm_read_edx_eax(vcpu);
4730 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4731
4732 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4733 skip_emulated_instruction(vcpu);
4734 return 1;
4735}
4736
851ba692 4737static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4738{
58fbbf26
KT		 4739 if (likely(fasteoi)) {
4740 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4741 int access_type, offset;
4742
4743 access_type = exit_qualification & APIC_ACCESS_TYPE;
4744 offset = exit_qualification & APIC_ACCESS_OFFSET;
4745 /*
4746 * Sane guest uses MOV to write EOI, with written value
4747 * not cared. So make a short-circuit here by avoiding
4748 * heavy instruction emulation.
4749 */
4750 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4751 (offset == APIC_EOI)) {
4752 kvm_lapic_set_eoi(vcpu);
4753 skip_emulated_instruction(vcpu);
4754 return 1;
4755 }
4756 }
51d8b661 4757 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4758}
4759
851ba692 4760static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4761{
60637aac 4762 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4763 unsigned long exit_qualification;
e269fb21
JK		 4764 bool has_error_code = false;
4765 u32 error_code = 0;
37817f29 4766 u16 tss_selector;
7f3d35fd 4767 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4768
4769 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4770 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4771 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4772
4773 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4774
4775 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4776 if (reason == TASK_SWITCH_GATE && idt_v) {
4777 switch (type) {
4778 case INTR_TYPE_NMI_INTR:
4779 vcpu->arch.nmi_injected = false;
654f06fc 4780 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4781 break;
4782 case INTR_TYPE_EXT_INTR:
66fd3f7f 4783 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4784 kvm_clear_interrupt_queue(vcpu);
4785 break;
4786 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4787 if (vmx->idt_vectoring_info &
4788 VECTORING_INFO_DELIVER_CODE_MASK) {
4789 has_error_code = true;
4790 error_code =
4791 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4792 }
4793 /* fall through */
64a7ec06
GN		 4794 case INTR_TYPE_SOFT_EXCEPTION:
4795 kvm_clear_exception_queue(vcpu);
4796 break;
4797 default:
4798 break;
4799 }
60637aac 4800 }
37817f29
IE		 4801 tss_selector = exit_qualification;
4802
64a7ec06
GN		 4803 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4804 type != INTR_TYPE_EXT_INTR &&
4805 type != INTR_TYPE_NMI_INTR))
4806 skip_emulated_instruction(vcpu);
4807
7f3d35fd
KW		 4808 if (kvm_task_switch(vcpu, tss_selector,
4809 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4810 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4811 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4812 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4813 vcpu->run->internal.ndata = 0;
42dbaa5a 4814 return 0;
acb54517 4815 }
42dbaa5a
JK		 4816
4817 /* clear all local breakpoint enable flags */
4818 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4819
4820 /*
4821 * TODO: What about debug traps on tss switch?
4822 * Are we supposed to inject them and update dr6?
4823 */
4824
4825 return 1;
37817f29
IE		 4826}
4827
851ba692 4828static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4829{
f9c617f6 4830 unsigned long exit_qualification;
1439442c 4831 gpa_t gpa;
1439442c 4832 int gla_validity;
1439442c 4833
f9c617f6 4834 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4835
4836 if (exit_qualification & (1 << 6)) {
4837 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4838 return -EINVAL;
1439442c
SY		 4839 }
4840
4841 gla_validity = (exit_qualification >> 7) & 0x3;
4842 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4843 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4844 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4845 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4846 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4847 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4848 (long unsigned int)exit_qualification);
851ba692
AK		 4849 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4850 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4851 return 0;
1439442c
SY		 4852 }
4853
4854 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4855 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4856 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4857}
4858
68f89400
MT		 4859static u64 ept_rsvd_mask(u64 spte, int level)
4860{
4861 int i;
4862 u64 mask = 0;
4863
4864 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4865 mask |= (1ULL << i);
4866
4867 if (level > 2)
4868 /* bits 7:3 reserved */
4869 mask |= 0xf8;
4870 else if (level == 2) {
4871 if (spte & (1ULL << 7))
4872 /* 2MB ref, bits 20:12 reserved */
4873 mask |= 0x1ff000;
4874 else
4875 /* bits 6:3 reserved */
4876 mask |= 0x78;
4877 }
4878
4879 return mask;
4880}
4881
4882static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4883 int level)
4884{
4885 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4886
4887 /* 010b (write-only) */
4888 WARN_ON((spte & 0x7) == 0x2);
4889
4890 /* 110b (write/execute) */
4891 WARN_ON((spte & 0x7) == 0x6);
4892
4893 /* 100b (execute-only) and value not supported by logical processor */
4894 if (!cpu_has_vmx_ept_execute_only())
4895 WARN_ON((spte & 0x7) == 0x4);
4896
4897 /* not 000b */
4898 if ((spte & 0x7)) {
4899 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4900
4901 if (rsvd_bits != 0) {
4902 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4903 __func__, rsvd_bits);
4904 WARN_ON(1);
4905 }
4906
4907 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4908 u64 ept_mem_type = (spte & 0x38) >> 3;
4909
4910 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4911 ept_mem_type == 7) {
4912 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4913 __func__, ept_mem_type);
4914 WARN_ON(1);
4915 }
4916 }
4917 }
4918}
4919
851ba692 4920static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4921{
4922 u64 sptes[4];
ce88decf 4923 int nr_sptes, i, ret;
68f89400
MT		 4924 gpa_t gpa;
4925
4926 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4927
ce88decf
XG		 4928 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4929 if (likely(ret == 1))
4930 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4931 EMULATE_DONE;
4932 if (unlikely(!ret))
4933 return 1;
4934
4935 /* It is the real ept misconfig */
68f89400
MT		 4936 printk(KERN_ERR "EPT: Misconfiguration.\n");
4937 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4938
4939 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4940
4941 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4942 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4943
851ba692
AK		 4944 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4945 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4946
4947 return 0;
4948}
4949
851ba692 4950static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4951{
4952 u32 cpu_based_vm_exec_control;
4953
4954 /* clear pending NMI */
4955 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4956 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4958 ++vcpu->stat.nmi_window_exits;
3842d135 4959 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4960
4961 return 1;
4962}
4963
80ced186 4964static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4965{
8b3079a5
AK		 4966 struct vcpu_vmx *vmx = to_vmx(vcpu);
4967 enum emulation_result err = EMULATE_DONE;
80ced186 4968 int ret = 1;
49e9d557
AK		 4969 u32 cpu_exec_ctrl;
4970 bool intr_window_requested;
4971
4972 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4973 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4974
4975 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4976 if (intr_window_requested
4977 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4978 return handle_interrupt_window(&vmx->vcpu);
4979
51d8b661 4980 err = emulate_instruction(vcpu, 0);
ea953ef0 4981
80ced186
MG		 4982 if (err == EMULATE_DO_MMIO) {
4983 ret = 0;
4984 goto out;
4985 }
1d5a4d9b 4986
6d77dbfc
GN		 4987 if (err != EMULATE_DONE)
4988 return 0;
ea953ef0
MG		 4989
4990 if (signal_pending(current))
80ced186 4991 goto out;
ea953ef0
MG		 4992 if (need_resched())
4993 schedule();
4994 }
4995
80ced186
MG		 4996 vmx->emulation_required = 0;
4997out:
4998 return ret;
ea953ef0
MG		 4999}
5000
4b8d54f9
ZE		 5001/*
5002 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5003 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5004 */
9fb41ba8 5005static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5006{
5007 skip_emulated_instruction(vcpu);
5008 kvm_vcpu_on_spin(vcpu);
5009
5010 return 1;
5011}
5012
59708670
SY		 5013static int handle_invalid_op(struct kvm_vcpu *vcpu)
5014{
5015 kvm_queue_exception(vcpu, UD_VECTOR);
5016 return 1;
5017}
5018
ff2f6fe9
NHE		 5019/*
5020 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5021 * We could reuse a single VMCS for all the L2 guests, but we also want the
5022 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5023 * allows keeping them loaded on the processor, and in the future will allow
5024 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5025 * every entry if they never change.
5026 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5027 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5028 *
5029 * The following functions allocate and free a vmcs02 in this pool.
5030 */
5031
5032/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5033static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5034{
5035 struct vmcs02_list *item;
5036 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5037 if (item->vmptr == vmx->nested.current_vmptr) {
5038 list_move(&item->list, &vmx->nested.vmcs02_pool);
5039 return &item->vmcs02;
5040 }
5041
5042 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5043 /* Recycle the least recently used VMCS. */
5044 item = list_entry(vmx->nested.vmcs02_pool.prev,
5045 struct vmcs02_list, list);
5046 item->vmptr = vmx->nested.current_vmptr;
5047 list_move(&item->list, &vmx->nested.vmcs02_pool);
5048 return &item->vmcs02;
5049 }
5050
5051 /* Create a new VMCS */
5052 item = (struct vmcs02_list *)
5053 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5054 if (!item)
5055 return NULL;
5056 item->vmcs02.vmcs = alloc_vmcs();
5057 if (!item->vmcs02.vmcs) {
5058 kfree(item);
5059 return NULL;
5060 }
5061 loaded_vmcs_init(&item->vmcs02);
5062 item->vmptr = vmx->nested.current_vmptr;
5063 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5064 vmx->nested.vmcs02_num++;
5065 return &item->vmcs02;
5066}
5067
5068/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5069static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5070{
5071 struct vmcs02_list *item;
5072 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5073 if (item->vmptr == vmptr) {
5074 free_loaded_vmcs(&item->vmcs02);
5075 list_del(&item->list);
5076 kfree(item);
5077 vmx->nested.vmcs02_num--;
5078 return;
5079 }
5080}
5081
5082/*
5083 * Free all VMCSs saved for this vcpu, except the one pointed by
5084 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5085 * currently used, if running L2), and vmcs01 when running L2.
5086 */
5087static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5088{
5089 struct vmcs02_list *item, *n;
5090 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5091 if (vmx->loaded_vmcs != &item->vmcs02)
5092 free_loaded_vmcs(&item->vmcs02);
5093 list_del(&item->list);
5094 kfree(item);
5095 }
5096 vmx->nested.vmcs02_num = 0;
5097
5098 if (vmx->loaded_vmcs != &vmx->vmcs01)
5099 free_loaded_vmcs(&vmx->vmcs01);
5100}
5101
ec378aee
NHE		 5102/*
5103 * Emulate the VMXON instruction.
5104 * Currently, we just remember that VMX is active, and do not save or even
5105 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5106 * do not currently need to store anything in that guest-allocated memory
5107 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5108 * argument is different from the VMXON pointer (which the spec says they do).
5109 */
5110static int handle_vmon(struct kvm_vcpu *vcpu)
5111{
5112 struct kvm_segment cs;
5113 struct vcpu_vmx *vmx = to_vmx(vcpu);
5114
5115 /* The Intel VMX Instruction Reference lists a bunch of bits that
5116 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5117 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5118 * Otherwise, we should fail with #UD. We test these now:
5119 */
5120 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5121 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5122 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5123 kvm_queue_exception(vcpu, UD_VECTOR);
5124 return 1;
5125 }
5126
5127 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5128 if (is_long_mode(vcpu) && !cs.l) {
5129 kvm_queue_exception(vcpu, UD_VECTOR);
5130 return 1;
5131 }
5132
5133 if (vmx_get_cpl(vcpu)) {
5134 kvm_inject_gp(vcpu, 0);
5135 return 1;
5136 }
5137
ff2f6fe9
NHE		 5138 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5139 vmx->nested.vmcs02_num = 0;
5140
ec378aee
NHE		 5141 vmx->nested.vmxon = true;
5142
5143 skip_emulated_instruction(vcpu);
5144 return 1;
5145}
5146
5147/*
5148 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5149 * for running VMX instructions (except VMXON, whose prerequisites are
5150 * slightly different). It also specifies what exception to inject otherwise.
5151 */
5152static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5153{
5154 struct kvm_segment cs;
5155 struct vcpu_vmx *vmx = to_vmx(vcpu);
5156
5157 if (!vmx->nested.vmxon) {
5158 kvm_queue_exception(vcpu, UD_VECTOR);
5159 return 0;
5160 }
5161
5162 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5163 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5164 (is_long_mode(vcpu) && !cs.l)) {
5165 kvm_queue_exception(vcpu, UD_VECTOR);
5166 return 0;
5167 }
5168
5169 if (vmx_get_cpl(vcpu)) {
5170 kvm_inject_gp(vcpu, 0);
5171 return 0;
5172 }
5173
5174 return 1;
5175}
5176
5177/*
5178 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5179 * just stops using VMX.
5180 */
5181static void free_nested(struct vcpu_vmx *vmx)
5182{
5183 if (!vmx->nested.vmxon)
5184 return;
5185 vmx->nested.vmxon = false;
a9d30f33
NHE		 5186 if (vmx->nested.current_vmptr != -1ull) {
5187 kunmap(vmx->nested.current_vmcs12_page);
5188 nested_release_page(vmx->nested.current_vmcs12_page);
5189 vmx->nested.current_vmptr = -1ull;
5190 vmx->nested.current_vmcs12 = NULL;
5191 }
fe3ef05c
NHE		 5192 /* Unpin physical memory we referred to in current vmcs02 */
5193 if (vmx->nested.apic_access_page) {
5194 nested_release_page(vmx->nested.apic_access_page);
5195 vmx->nested.apic_access_page = 0;
5196 }
ff2f6fe9
NHE		 5197
5198 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5199}
5200
5201/* Emulate the VMXOFF instruction */
5202static int handle_vmoff(struct kvm_vcpu *vcpu)
5203{
5204 if (!nested_vmx_check_permission(vcpu))
5205 return 1;
5206 free_nested(to_vmx(vcpu));
5207 skip_emulated_instruction(vcpu);
5208 return 1;
5209}
5210
064aea77
NHE		 5211/*
5212 * Decode the memory-address operand of a vmx instruction, as recorded on an
5213 * exit caused by such an instruction (run by a guest hypervisor).
5214 * On success, returns 0. When the operand is invalid, returns 1 and throws
5215 * #UD or #GP.
5216 */
5217static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5218 unsigned long exit_qualification,
5219 u32 vmx_instruction_info, gva_t *ret)
5220{
5221 /*
5222 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5223 * Execution", on an exit, vmx_instruction_info holds most of the
5224 * addressing components of the operand. Only the displacement part
5225 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5226 * For how an actual address is calculated from all these components,
5227 * refer to Vol. 1, "Operand Addressing".
5228 */
5229 int scaling = vmx_instruction_info & 3;
5230 int addr_size = (vmx_instruction_info >> 7) & 7;
5231 bool is_reg = vmx_instruction_info & (1u << 10);
5232 int seg_reg = (vmx_instruction_info >> 15) & 7;
5233 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5234 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5235 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5236 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5237
5238 if (is_reg) {
5239 kvm_queue_exception(vcpu, UD_VECTOR);
5240 return 1;
5241 }
5242
5243 /* Addr = segment_base + offset */
5244 /* offset = base + [index * scale] + displacement */
5245 *ret = vmx_get_segment_base(vcpu, seg_reg);
5246 if (base_is_valid)
5247 *ret += kvm_register_read(vcpu, base_reg);
5248 if (index_is_valid)
5249 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5250 *ret += exit_qualification; /* holds the displacement */
5251
5252 if (addr_size == 1) /* 32 bit */
5253 *ret &= 0xffffffff;
5254
5255 /*
5256 * TODO: throw #GP (and return 1) in various cases that the VM*
5257 * instructions require it - e.g., offset beyond segment limit,
5258 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5259 * address, and so on. Currently these are not checked.
5260 */
5261 return 0;
5262}
5263
0140caea
NHE		 5264/*
5265 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5266 * set the success or error code of an emulated VMX instruction, as specified
5267 * by Vol 2B, VMX Instruction Reference, "Conventions".
5268 */
5269static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5270{
5271 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5272 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5273 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5274}
5275
5276static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5277{
5278 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5279 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5280 X86_EFLAGS_SF | X86_EFLAGS_OF))
5281 | X86_EFLAGS_CF);
5282}
5283
5284static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5285 u32 vm_instruction_error)
5286{
5287 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5288 /*
5289 * failValid writes the error number to the current VMCS, which
5290 * can't be done there isn't a current VMCS.
5291 */
5292 nested_vmx_failInvalid(vcpu);
5293 return;
5294 }
5295 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5296 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5297 X86_EFLAGS_SF | X86_EFLAGS_OF))
5298 | X86_EFLAGS_ZF);
5299 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5300}
5301
27d6c865
NHE		 5302/* Emulate the VMCLEAR instruction */
5303static int handle_vmclear(struct kvm_vcpu *vcpu)
5304{
5305 struct vcpu_vmx *vmx = to_vmx(vcpu);
5306 gva_t gva;
5307 gpa_t vmptr;
5308 struct vmcs12 *vmcs12;
5309 struct page *page;
5310 struct x86_exception e;
5311
5312 if (!nested_vmx_check_permission(vcpu))
5313 return 1;
5314
5315 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5316 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5317 return 1;
5318
5319 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5320 sizeof(vmptr), &e)) {
5321 kvm_inject_page_fault(vcpu, &e);
5322 return 1;
5323 }
5324
5325 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5326 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5327 skip_emulated_instruction(vcpu);
5328 return 1;
5329 }
5330
5331 if (vmptr == vmx->nested.current_vmptr) {
5332 kunmap(vmx->nested.current_vmcs12_page);
5333 nested_release_page(vmx->nested.current_vmcs12_page);
5334 vmx->nested.current_vmptr = -1ull;
5335 vmx->nested.current_vmcs12 = NULL;
5336 }
5337
5338 page = nested_get_page(vcpu, vmptr);
5339 if (page == NULL) {
5340 /*
5341 * For accurate processor emulation, VMCLEAR beyond available
5342 * physical memory should do nothing at all. However, it is
5343 * possible that a nested vmx bug, not a guest hypervisor bug,
5344 * resulted in this case, so let's shut down before doing any
5345 * more damage:
5346 */
5347 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5348 return 1;
5349 }
5350 vmcs12 = kmap(page);
5351 vmcs12->launch_state = 0;
5352 kunmap(page);
5353 nested_release_page(page);
5354
5355 nested_free_vmcs02(vmx, vmptr);
5356
5357 skip_emulated_instruction(vcpu);
5358 nested_vmx_succeed(vcpu);
5359 return 1;
5360}
5361
cd232ad0
NHE		 5362static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5363
5364/* Emulate the VMLAUNCH instruction */
5365static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5366{
5367 return nested_vmx_run(vcpu, true);
5368}
5369
5370/* Emulate the VMRESUME instruction */
5371static int handle_vmresume(struct kvm_vcpu *vcpu)
5372{
5373
5374 return nested_vmx_run(vcpu, false);
5375}
5376
49f705c5
NHE		 5377enum vmcs_field_type {
5378 VMCS_FIELD_TYPE_U16 = 0,
5379 VMCS_FIELD_TYPE_U64 = 1,
5380 VMCS_FIELD_TYPE_U32 = 2,
5381 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5382};
5383
5384static inline int vmcs_field_type(unsigned long field)
5385{
5386 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5387 return VMCS_FIELD_TYPE_U32;
5388 return (field >> 13) & 0x3 ;
5389}
5390
5391static inline int vmcs_field_readonly(unsigned long field)
5392{
5393 return (((field >> 10) & 0x3) == 1);
5394}
5395
5396/*
5397 * Read a vmcs12 field. Since these can have varying lengths and we return
5398 * one type, we chose the biggest type (u64) and zero-extend the return value
5399 * to that size. Note that the caller, handle_vmread, might need to use only
5400 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5401 * 64-bit fields are to be returned).
5402 */
5403static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5404 unsigned long field, u64 *ret)
5405{
5406 short offset = vmcs_field_to_offset(field);
5407 char *p;
5408
5409 if (offset < 0)
5410 return 0;
5411
5412 p = ((char *)(get_vmcs12(vcpu))) + offset;
5413
5414 switch (vmcs_field_type(field)) {
5415 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5416 *ret = *((natural_width *)p);
5417 return 1;
5418 case VMCS_FIELD_TYPE_U16:
5419 *ret = *((u16 *)p);
5420 return 1;
5421 case VMCS_FIELD_TYPE_U32:
5422 *ret = *((u32 *)p);
5423 return 1;
5424 case VMCS_FIELD_TYPE_U64:
5425 *ret = *((u64 *)p);
5426 return 1;
5427 default:
5428 return 0; /* can never happen. */
5429 }
5430}
5431
5432/*
5433 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5434 * used before) all generate the same failure when it is missing.
5435 */
5436static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5437{
5438 struct vcpu_vmx *vmx = to_vmx(vcpu);
5439 if (vmx->nested.current_vmptr == -1ull) {
5440 nested_vmx_failInvalid(vcpu);
5441 skip_emulated_instruction(vcpu);
5442 return 0;
5443 }
5444 return 1;
5445}
5446
5447static int handle_vmread(struct kvm_vcpu *vcpu)
5448{
5449 unsigned long field;
5450 u64 field_value;
5451 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5452 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5453 gva_t gva = 0;
5454
5455 if (!nested_vmx_check_permission(vcpu) ||
5456 !nested_vmx_check_vmcs12(vcpu))
5457 return 1;
5458
5459 /* Decode instruction info and find the field to read */
5460 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5461 /* Read the field, zero-extended to a u64 field_value */
5462 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5463 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5464 skip_emulated_instruction(vcpu);
5465 return 1;
5466 }
5467 /*
5468 * Now copy part of this value to register or memory, as requested.
5469 * Note that the number of bits actually copied is 32 or 64 depending
5470 * on the guest's mode (32 or 64 bit), not on the given field's length.
5471 */
5472 if (vmx_instruction_info & (1u << 10)) {
5473 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5474 field_value);
5475 } else {
5476 if (get_vmx_mem_address(vcpu, exit_qualification,
5477 vmx_instruction_info, &gva))
5478 return 1;
5479 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5480 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5481 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5482 }
5483
5484 nested_vmx_succeed(vcpu);
5485 skip_emulated_instruction(vcpu);
5486 return 1;
5487}
5488
5489
5490static int handle_vmwrite(struct kvm_vcpu *vcpu)
5491{
5492 unsigned long field;
5493 gva_t gva;
5494 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5495 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5496 char *p;
5497 short offset;
5498 /* The value to write might be 32 or 64 bits, depending on L1's long
5499 * mode, and eventually we need to write that into a field of several
5500 * possible lengths. The code below first zero-extends the value to 64
5501 * bit (field_value), and then copies only the approriate number of
5502 * bits into the vmcs12 field.
5503 */
5504 u64 field_value = 0;
5505 struct x86_exception e;
5506
5507 if (!nested_vmx_check_permission(vcpu) ||
5508 !nested_vmx_check_vmcs12(vcpu))
5509 return 1;
5510
5511 if (vmx_instruction_info & (1u << 10))
5512 field_value = kvm_register_read(vcpu,
5513 (((vmx_instruction_info) >> 3) & 0xf));
5514 else {
5515 if (get_vmx_mem_address(vcpu, exit_qualification,
5516 vmx_instruction_info, &gva))
5517 return 1;
5518 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5519 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5520 kvm_inject_page_fault(vcpu, &e);
5521 return 1;
5522 }
5523 }
5524
5525
5526 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5527 if (vmcs_field_readonly(field)) {
5528 nested_vmx_failValid(vcpu,
5529 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5530 skip_emulated_instruction(vcpu);
5531 return 1;
5532 }
5533
5534 offset = vmcs_field_to_offset(field);
5535 if (offset < 0) {
5536 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5537 skip_emulated_instruction(vcpu);
5538 return 1;
5539 }
5540 p = ((char *) get_vmcs12(vcpu)) + offset;
5541
5542 switch (vmcs_field_type(field)) {
5543 case VMCS_FIELD_TYPE_U16:
5544 *(u16 *)p = field_value;
5545 break;
5546 case VMCS_FIELD_TYPE_U32:
5547 *(u32 *)p = field_value;
5548 break;
5549 case VMCS_FIELD_TYPE_U64:
5550 *(u64 *)p = field_value;
5551 break;
5552 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5553 *(natural_width *)p = field_value;
5554 break;
5555 default:
5556 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5557 skip_emulated_instruction(vcpu);
5558 return 1;
5559 }
5560
5561 nested_vmx_succeed(vcpu);
5562 skip_emulated_instruction(vcpu);
5563 return 1;
5564}
5565
63846663
NHE		 5566/* Emulate the VMPTRLD instruction */
5567static int handle_vmptrld(struct kvm_vcpu *vcpu)
5568{
5569 struct vcpu_vmx *vmx = to_vmx(vcpu);
5570 gva_t gva;
5571 gpa_t vmptr;
5572 struct x86_exception e;
5573
5574 if (!nested_vmx_check_permission(vcpu))
5575 return 1;
5576
5577 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5578 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5579 return 1;
5580
5581 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5582 sizeof(vmptr), &e)) {
5583 kvm_inject_page_fault(vcpu, &e);
5584 return 1;
5585 }
5586
5587 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5588 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5589 skip_emulated_instruction(vcpu);
5590 return 1;
5591 }
5592
5593 if (vmx->nested.current_vmptr != vmptr) {
5594 struct vmcs12 *new_vmcs12;
5595 struct page *page;
5596 page = nested_get_page(vcpu, vmptr);
5597 if (page == NULL) {
5598 nested_vmx_failInvalid(vcpu);
5599 skip_emulated_instruction(vcpu);
5600 return 1;
5601 }
5602 new_vmcs12 = kmap(page);
5603 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5604 kunmap(page);
5605 nested_release_page_clean(page);
5606 nested_vmx_failValid(vcpu,
5607 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5608 skip_emulated_instruction(vcpu);
5609 return 1;
5610 }
5611 if (vmx->nested.current_vmptr != -1ull) {
5612 kunmap(vmx->nested.current_vmcs12_page);
5613 nested_release_page(vmx->nested.current_vmcs12_page);
5614 }
5615
5616 vmx->nested.current_vmptr = vmptr;
5617 vmx->nested.current_vmcs12 = new_vmcs12;
5618 vmx->nested.current_vmcs12_page = page;
5619 }
5620
5621 nested_vmx_succeed(vcpu);
5622 skip_emulated_instruction(vcpu);
5623 return 1;
5624}
5625
6a4d7550
NHE		 5626/* Emulate the VMPTRST instruction */
5627static int handle_vmptrst(struct kvm_vcpu *vcpu)
5628{
5629 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5630 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5631 gva_t vmcs_gva;
5632 struct x86_exception e;
5633
5634 if (!nested_vmx_check_permission(vcpu))
5635 return 1;
5636
5637 if (get_vmx_mem_address(vcpu, exit_qualification,
5638 vmx_instruction_info, &vmcs_gva))
5639 return 1;
5640 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5641 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5642 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5643 sizeof(u64), &e)) {
5644 kvm_inject_page_fault(vcpu, &e);
5645 return 1;
5646 }
5647 nested_vmx_succeed(vcpu);
5648 skip_emulated_instruction(vcpu);
5649 return 1;
5650}
5651
6aa8b732
AK		 5652/*
5653 * The exit handlers return 1 if the exit was handled fully and guest execution
5654 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5655 * to be done to userspace and return 0.
5656 */
851ba692 5657static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5658 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5659 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5660 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5661 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5662 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5663 [EXIT_REASON_CR_ACCESS] = handle_cr,
5664 [EXIT_REASON_DR_ACCESS] = handle_dr,
5665 [EXIT_REASON_CPUID] = handle_cpuid,
5666 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5667 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5668 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5669 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5670 [EXIT_REASON_INVD] = handle_invd,
a7052897 5671 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5672 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5673 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5674 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5675 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5676 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5677 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5678 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5679 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5680 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5681 [EXIT_REASON_VMOFF] = handle_vmoff,
5682 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5683 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5684 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5685 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5686 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5687 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5688 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5689 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5690 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5691 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5692 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5693 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5694};
5695
5696static const int kvm_vmx_max_exit_handlers =
50a3485c 5697 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5698
644d711a
NHE		 5699/*
5700 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5701 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5702 * disinterest in the current event (read or write a specific MSR) by using an
5703 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5704 */
5705static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5706 struct vmcs12 *vmcs12, u32 exit_reason)
5707{
5708 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5709 gpa_t bitmap;
5710
5711 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5712 return 1;
5713
5714 /*
5715 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5716 * for the four combinations of read/write and low/high MSR numbers.
5717 * First we need to figure out which of the four to use:
5718 */
5719 bitmap = vmcs12->msr_bitmap;
5720 if (exit_reason == EXIT_REASON_MSR_WRITE)
5721 bitmap += 2048;
5722 if (msr_index >= 0xc0000000) {
5723 msr_index -= 0xc0000000;
5724 bitmap += 1024;
5725 }
5726
5727 /* Then read the msr_index'th bit from this bitmap: */
5728 if (msr_index < 1024*8) {
5729 unsigned char b;
5730 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5731 return 1 & (b >> (msr_index & 7));
5732 } else
5733 return 1; /* let L1 handle the wrong parameter */
5734}
5735
5736/*
5737 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5738 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5739 * intercept (via guest_host_mask etc.) the current event.
5740 */
5741static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5742 struct vmcs12 *vmcs12)
5743{
5744 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5745 int cr = exit_qualification & 15;
5746 int reg = (exit_qualification >> 8) & 15;
5747 unsigned long val = kvm_register_read(vcpu, reg);
5748
5749 switch ((exit_qualification >> 4) & 3) {
5750 case 0: /* mov to cr */
5751 switch (cr) {
5752 case 0:
5753 if (vmcs12->cr0_guest_host_mask &
5754 (val ^ vmcs12->cr0_read_shadow))
5755 return 1;
5756 break;
5757 case 3:
5758 if ((vmcs12->cr3_target_count >= 1 &&
5759 vmcs12->cr3_target_value0 == val) ||
5760 (vmcs12->cr3_target_count >= 2 &&
5761 vmcs12->cr3_target_value1 == val) ||
5762 (vmcs12->cr3_target_count >= 3 &&
5763 vmcs12->cr3_target_value2 == val) ||
5764 (vmcs12->cr3_target_count >= 4 &&
5765 vmcs12->cr3_target_value3 == val))
5766 return 0;
5767 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5768 return 1;
5769 break;
5770 case 4:
5771 if (vmcs12->cr4_guest_host_mask &
5772 (vmcs12->cr4_read_shadow ^ val))
5773 return 1;
5774 break;
5775 case 8:
5776 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5777 return 1;
5778 break;
5779 }
5780 break;
5781 case 2: /* clts */
5782 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5783 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5784 return 1;
5785 break;
5786 case 1: /* mov from cr */
5787 switch (cr) {
5788 case 3:
5789 if (vmcs12->cpu_based_vm_exec_control &
5790 CPU_BASED_CR3_STORE_EXITING)
5791 return 1;
5792 break;
5793 case 8:
5794 if (vmcs12->cpu_based_vm_exec_control &
5795 CPU_BASED_CR8_STORE_EXITING)
5796 return 1;
5797 break;
5798 }
5799 break;
5800 case 3: /* lmsw */
5801 /*
5802 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5803 * cr0. Other attempted changes are ignored, with no exit.
5804 */
5805 if (vmcs12->cr0_guest_host_mask & 0xe &
5806 (val ^ vmcs12->cr0_read_shadow))
5807 return 1;
5808 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5809 !(vmcs12->cr0_read_shadow & 0x1) &&
5810 (val & 0x1))
5811 return 1;
5812 break;
5813 }
5814 return 0;
5815}
5816
5817/*
5818 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5819 * should handle it ourselves in L0 (and then continue L2). Only call this
5820 * when in is_guest_mode (L2).
5821 */
5822static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5823{
5824 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5825 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5826 struct vcpu_vmx *vmx = to_vmx(vcpu);
5827 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5828
5829 if (vmx->nested.nested_run_pending)
5830 return 0;
5831
5832 if (unlikely(vmx->fail)) {
bd80158a
JK		 5833 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5834 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5835 return 1;
5836 }
5837
5838 switch (exit_reason) {
5839 case EXIT_REASON_EXCEPTION_NMI:
5840 if (!is_exception(intr_info))
5841 return 0;
5842 else if (is_page_fault(intr_info))
5843 return enable_ept;
5844 return vmcs12->exception_bitmap &
5845 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5846 case EXIT_REASON_EXTERNAL_INTERRUPT:
5847 return 0;
5848 case EXIT_REASON_TRIPLE_FAULT:
5849 return 1;
5850 case EXIT_REASON_PENDING_INTERRUPT:
5851 case EXIT_REASON_NMI_WINDOW:
5852 /*
5853 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5854 * (aka Interrupt Window Exiting) only when L1 turned it on,
5855 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5856 * Same for NMI Window Exiting.
5857 */
5858 return 1;
5859 case EXIT_REASON_TASK_SWITCH:
5860 return 1;
5861 case EXIT_REASON_CPUID:
5862 return 1;
5863 case EXIT_REASON_HLT:
5864 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5865 case EXIT_REASON_INVD:
5866 return 1;
5867 case EXIT_REASON_INVLPG:
5868 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5869 case EXIT_REASON_RDPMC:
5870 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5871 case EXIT_REASON_RDTSC:
5872 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5873 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5874 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5875 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5876 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5877 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5878 /*
5879 * VMX instructions trap unconditionally. This allows L1 to
5880 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5881 */
5882 return 1;
5883 case EXIT_REASON_CR_ACCESS:
5884 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5885 case EXIT_REASON_DR_ACCESS:
5886 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5887 case EXIT_REASON_IO_INSTRUCTION:
5888 /* TODO: support IO bitmaps */
5889 return 1;
5890 case EXIT_REASON_MSR_READ:
5891 case EXIT_REASON_MSR_WRITE:
5892 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5893 case EXIT_REASON_INVALID_STATE:
5894 return 1;
5895 case EXIT_REASON_MWAIT_INSTRUCTION:
5896 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5897 case EXIT_REASON_MONITOR_INSTRUCTION:
5898 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5899 case EXIT_REASON_PAUSE_INSTRUCTION:
5900 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5901 nested_cpu_has2(vmcs12,
5902 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5903 case EXIT_REASON_MCE_DURING_VMENTRY:
5904 return 0;
5905 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5906 return 1;
5907 case EXIT_REASON_APIC_ACCESS:
5908 return nested_cpu_has2(vmcs12,
5909 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5910 case EXIT_REASON_EPT_VIOLATION:
5911 case EXIT_REASON_EPT_MISCONFIG:
5912 return 0;
5913 case EXIT_REASON_WBINVD:
5914 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5915 case EXIT_REASON_XSETBV:
5916 return 1;
5917 default:
5918 return 1;
5919 }
5920}
5921
586f9607
AK		 5922static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5923{
5924 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5925 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5926}
5927
6aa8b732
AK		 5928/*
5929 * The guest has exited. See if we can fix it or if we need userspace
5930 * assistance.
5931 */
851ba692 5932static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5933{
29bd8a78 5934 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5935 u32 exit_reason = vmx->exit_reason;
1155f76a 5936 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5937
80ced186
MG		 5938 /* If guest state is invalid, start emulating */
5939 if (vmx->emulation_required && emulate_invalid_guest_state)
5940 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5941
b6f1250e
NHE		 5942 /*
5943 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5944 * we did not inject a still-pending event to L1 now because of
5945 * nested_run_pending, we need to re-enable this bit.
5946 */
5947 if (vmx->nested.nested_run_pending)
5948 kvm_make_request(KVM_REQ_EVENT, vcpu);
5949
509c75ea
NHE		 5950 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5951 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5952 vmx->nested.nested_run_pending = 1;
5953 else
5954 vmx->nested.nested_run_pending = 0;
5955
5956 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5957 nested_vmx_vmexit(vcpu);
5958 return 1;
5959 }
5960
5120702e
MG		 5961 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5962 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5963 vcpu->run->fail_entry.hardware_entry_failure_reason
5964 = exit_reason;
5965 return 0;
5966 }
5967
29bd8a78 5968 if (unlikely(vmx->fail)) {
851ba692
AK		 5969 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5970 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5971 = vmcs_read32(VM_INSTRUCTION_ERROR);
5972 return 0;
5973 }
6aa8b732 5974
d77c26fc 5975 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5976 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5977 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5978 exit_reason != EXIT_REASON_TASK_SWITCH))
5979 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5980 "(0x%x) and exit reason is 0x%x\n",
5981 __func__, vectoring_info, exit_reason);
3b86cd99 5982
644d711a
NHE		 5983 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5984 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5985 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5986 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5987 vmx->soft_vnmi_blocked = 0;
3b86cd99 5988 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5989 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5990 /*
5991 * This CPU don't support us in finding the end of an
5992 * NMI-blocked window if the guest runs with IRQs
5993 * disabled. So we pull the trigger after 1 s of
5994 * futile waiting, but inform the user about this.
5995 */
5996 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5997 "state on VCPU %d after 1 s timeout\n",
5998 __func__, vcpu->vcpu_id);
5999 vmx->soft_vnmi_blocked = 0;
3b86cd99 6000 }
3b86cd99
JK		 6001 }
6002
6aa8b732
AK		 6003 if (exit_reason < kvm_vmx_max_exit_handlers
6004 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6005 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6006 else {
851ba692
AK		 6007 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6008 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6009 }
6010 return 0;
6011}
6012
95ba8273 6013static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6014{
95ba8273 6015 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6016 vmcs_write32(TPR_THRESHOLD, 0);
6017 return;
6018 }
6019
95ba8273 6020 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6021}
6022
51aa01d1 6023static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6024{
00eba012
AK		 6025 u32 exit_intr_info;
6026
6027 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6028 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6029 return;
6030
c5ca8e57 6031 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6032 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6033
6034 /* Handle machine checks before interrupts are enabled */
00eba012 6035 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6036 kvm_machine_check();
6037
20f65983 6038 /* We need to handle NMIs before interrupts are enabled */
00eba012 6039 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6040 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6041 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6042 asm("int $2");
ff9d07a0
ZY		 6043 kvm_after_handle_nmi(&vmx->vcpu);
6044 }
51aa01d1 6045}
20f65983 6046
51aa01d1
AK		 6047static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6048{
c5ca8e57 6049 u32 exit_intr_info;
51aa01d1
AK		 6050 bool unblock_nmi;
6051 u8 vector;
6052 bool idtv_info_valid;
6053
6054 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6055
cf393f75 6056 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6057 if (vmx->nmi_known_unmasked)
6058 return;
c5ca8e57
AK		 6059 /*
6060 * Can't use vmx->exit_intr_info since we're not sure what
6061 * the exit reason is.
6062 */
6063 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6064 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6065 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6066 /*
7b4a25cb 6067 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6068 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6069 * a guest IRET fault.
7b4a25cb
GN		 6070 * SDM 3: 23.2.2 (September 2008)
6071 * Bit 12 is undefined in any of the following cases:
6072 * If the VM exit sets the valid bit in the IDT-vectoring
6073 * information field.
6074 * If the VM exit is due to a double fault.
cf393f75 6075 */
7b4a25cb
GN		 6076 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6077 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6078 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6079 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6080 else
6081 vmx->nmi_known_unmasked =
6082 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6083 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6084 } else if (unlikely(vmx->soft_vnmi_blocked))
6085 vmx->vnmi_blocked_time +=
6086 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6087}
6088
83422e17
AK		 6089static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6090 u32 idt_vectoring_info,
6091 int instr_len_field,
6092 int error_code_field)
51aa01d1 6093{
51aa01d1
AK		 6094 u8 vector;
6095 int type;
6096 bool idtv_info_valid;
6097
6098 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6099
37b96e98
GN		 6100 vmx->vcpu.arch.nmi_injected = false;
6101 kvm_clear_exception_queue(&vmx->vcpu);
6102 kvm_clear_interrupt_queue(&vmx->vcpu);
6103
6104 if (!idtv_info_valid)
6105 return;
6106
3842d135
AK		 6107 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6108
668f612f
AK		 6109 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6110 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6111
64a7ec06 6112 switch (type) {
37b96e98
GN		 6113 case INTR_TYPE_NMI_INTR:
6114 vmx->vcpu.arch.nmi_injected = true;
668f612f 6115 /*
7b4a25cb 6116 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6117 * Clear bit "block by NMI" before VM entry if a NMI
6118 * delivery faulted.
668f612f 6119 */
654f06fc 6120 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6121 break;
37b96e98 6122 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6123 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6124 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6125 /* fall through */
6126 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6127 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6128 u32 err = vmcs_read32(error_code_field);
37b96e98 6129 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6130 } else
6131 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6132 break;
66fd3f7f
GN		 6133 case INTR_TYPE_SOFT_INTR:
6134 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6135 vmcs_read32(instr_len_field);
66fd3f7f 6136 /* fall through */
37b96e98 6137 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6138 kvm_queue_interrupt(&vmx->vcpu, vector,
6139 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6140 break;
6141 default:
6142 break;
f7d9238f 6143 }
cf393f75
AK		 6144}
6145
83422e17
AK		 6146static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6147{
66c78ae4
NHE		 6148 if (is_guest_mode(&vmx->vcpu))
6149 return;
83422e17
AK		 6150 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6151 VM_EXIT_INSTRUCTION_LEN,
6152 IDT_VECTORING_ERROR_CODE);
6153}
6154
b463a6f7
AK		 6155static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6156{
66c78ae4
NHE		 6157 if (is_guest_mode(vcpu))
6158 return;
b463a6f7
AK		 6159 __vmx_complete_interrupts(to_vmx(vcpu),
6160 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6161 VM_ENTRY_INSTRUCTION_LEN,
6162 VM_ENTRY_EXCEPTION_ERROR_CODE);
6163
6164 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6165}
6166
d7cd9796
GN		 6167static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6168{
6169 int i, nr_msrs;
6170 struct perf_guest_switch_msr *msrs;
6171
6172 msrs = perf_guest_get_msrs(&nr_msrs);
6173
6174 if (!msrs)
6175 return;
6176
6177 for (i = 0; i < nr_msrs; i++)
6178 if (msrs[i].host == msrs[i].guest)
6179 clear_atomic_switch_msr(vmx, msrs[i].msr);
6180 else
6181 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6182 msrs[i].host);
6183}
6184
c801949d
AK		 6185#ifdef CONFIG_X86_64
6186#define R "r"
6187#define Q "q"
6188#else
6189#define R "e"
6190#define Q "l"
6191#endif
6192
a3b5ba49 6193static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6194{
a2fa3e9f 6195 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6196
66c78ae4
NHE		 6197 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6198 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6199 if (vmcs12->idt_vectoring_info_field &
6200 VECTORING_INFO_VALID_MASK) {
6201 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6202 vmcs12->idt_vectoring_info_field);
6203 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6204 vmcs12->vm_exit_instruction_len);
6205 if (vmcs12->idt_vectoring_info_field &
6206 VECTORING_INFO_DELIVER_CODE_MASK)
6207 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6208 vmcs12->idt_vectoring_error_code);
6209 }
6210 }
6211
104f226b
AK		 6212 /* Record the guest's net vcpu time for enforced NMI injections. */
6213 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6214 vmx->entry_time = ktime_get();
6215
6216 /* Don't enter VMX if guest state is invalid, let the exit handler
6217 start emulation until we arrive back to a valid state */
6218 if (vmx->emulation_required && emulate_invalid_guest_state)
6219 return;
6220
6221 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6222 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6223 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6224 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6225
6226 /* When single-stepping over STI and MOV SS, we must clear the
6227 * corresponding interruptibility bits in the guest state. Otherwise
6228 * vmentry fails as it then expects bit 14 (BS) in pending debug
6229 * exceptions being set, but that's not correct for the guest debugging
6230 * case. */
6231 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6232 vmx_set_interrupt_shadow(vcpu, 0);
6233
d7cd9796
GN		 6234 atomic_switch_perf_msrs(vmx);
6235
d462b819 6236 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6237 asm(
6aa8b732 6238 /* Store host registers */
c801949d 6239 "push %%"R"dx; push %%"R"bp;"
40712fae 6240 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6241 "push %%"R"cx \n\t"
313dbd49
AK		 6242 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6243 "je 1f \n\t"
6244 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6245 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6246 "1: \n\t"
d3edefc0
AK		 6247 /* Reload cr2 if changed */
6248 "mov %c[cr2](%0), %%"R"ax \n\t"
6249 "mov %%cr2, %%"R"dx \n\t"
6250 "cmp %%"R"ax, %%"R"dx \n\t"
6251 "je 2f \n\t"
6252 "mov %%"R"ax, %%cr2 \n\t"
6253 "2: \n\t"
6aa8b732 6254 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6255 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6256 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6257 "mov %c[rax](%0), %%"R"ax \n\t"
6258 "mov %c[rbx](%0), %%"R"bx \n\t"
6259 "mov %c[rdx](%0), %%"R"dx \n\t"
6260 "mov %c[rsi](%0), %%"R"si \n\t"
6261 "mov %c[rdi](%0), %%"R"di \n\t"
6262 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6263#ifdef CONFIG_X86_64
e08aa78a
AK		 6264 "mov %c[r8](%0), %%r8 \n\t"
6265 "mov %c[r9](%0), %%r9 \n\t"
6266 "mov %c[r10](%0), %%r10 \n\t"
6267 "mov %c[r11](%0), %%r11 \n\t"
6268 "mov %c[r12](%0), %%r12 \n\t"
6269 "mov %c[r13](%0), %%r13 \n\t"
6270 "mov %c[r14](%0), %%r14 \n\t"
6271 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6272#endif
c801949d
AK		 6273 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6274
6aa8b732 6275 /* Enter guest mode */
cd2276a7 6276 "jne .Llaunched \n\t"
4ecac3fd 6277 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6278 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6279 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6280 ".Lkvm_vmx_return: "
6aa8b732 6281 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6282 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6283 "pop %0 \n\t"
c801949d
AK		 6284 "mov %%"R"ax, %c[rax](%0) \n\t"
6285 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6286 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6287 "mov %%"R"dx, %c[rdx](%0) \n\t"
6288 "mov %%"R"si, %c[rsi](%0) \n\t"
6289 "mov %%"R"di, %c[rdi](%0) \n\t"
6290 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6291#ifdef CONFIG_X86_64
e08aa78a
AK		 6292 "mov %%r8, %c[r8](%0) \n\t"
6293 "mov %%r9, %c[r9](%0) \n\t"
6294 "mov %%r10, %c[r10](%0) \n\t"
6295 "mov %%r11, %c[r11](%0) \n\t"
6296 "mov %%r12, %c[r12](%0) \n\t"
6297 "mov %%r13, %c[r13](%0) \n\t"
6298 "mov %%r14, %c[r14](%0) \n\t"
6299 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6300#endif
c801949d
AK		 6301 "mov %%cr2, %%"R"ax \n\t"
6302 "mov %%"R"ax, %c[cr2](%0) \n\t"
6303
1c696d0e 6304 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6305 "setbe %c[fail](%0) \n\t"
6306 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6307 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6308 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6309 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6310 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6311 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6312 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6313 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6314 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6315 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6316 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6317#ifdef CONFIG_X86_64
ad312c7c
ZX		 6318 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6319 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6320 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6321 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6322 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6323 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6324 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6325 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6326#endif
40712fae
AK		 6327 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6328 [wordsize]"i"(sizeof(ulong))
c2036300 6329 : "cc", "memory"
07d6f555 6330 , R"ax", R"bx", R"di", R"si"
c2036300 6331#ifdef CONFIG_X86_64
c2036300
LV		 6332 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6333#endif
6334 );
6aa8b732 6335
6de4f3ad 6336 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6337 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6338 | (1 << VCPU_EXREG_CPL)
aff48baa 6339 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6340 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6341 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6342 vcpu->arch.regs_dirty = 0;
6343
1155f76a
AK		 6344 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6345
66c78ae4
NHE		 6346 if (is_guest_mode(vcpu)) {
6347 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6348 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6349 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6350 vmcs12->idt_vectoring_error_code =
6351 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6352 vmcs12->vm_exit_instruction_len =
6353 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6354 }
6355 }
6356
d462b819 6357 vmx->loaded_vmcs->launched = 1;
1b6269db 6358
51aa01d1 6359 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6360 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6361
6362 vmx_complete_atomic_exit(vmx);
6363 vmx_recover_nmi_blocking(vmx);
cf393f75 6364 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6365}
6366
c801949d
AK		 6367#undef R
6368#undef Q
6369
6aa8b732
AK		 6370static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6371{
fb3f0f51
RR		 6372 struct vcpu_vmx *vmx = to_vmx(vcpu);
6373
cdbecfc3 6374 free_vpid(vmx);
ec378aee 6375 free_nested(vmx);
d462b819 6376 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6377 kfree(vmx->guest_msrs);
6378 kvm_vcpu_uninit(vcpu);
a4770347 6379 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6380}
6381
fb3f0f51 6382static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6383{
fb3f0f51 6384 int err;
c16f862d 6385 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6386 int cpu;
6aa8b732 6387
a2fa3e9f 6388 if (!vmx)
fb3f0f51
RR		 6389 return ERR_PTR(-ENOMEM);
6390
2384d2b3
SY		 6391 allocate_vpid(vmx);
6392
fb3f0f51
RR		 6393 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6394 if (err)
6395 goto free_vcpu;
965b58a5 6396
a2fa3e9f 6397 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6398 err = -ENOMEM;
fb3f0f51 6399 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6400 goto uninit_vcpu;
6401 }
965b58a5 6402
d462b819
NHE		 6403 vmx->loaded_vmcs = &vmx->vmcs01;
6404 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6405 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6406 goto free_msrs;
d462b819
NHE		 6407 if (!vmm_exclusive)
6408 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6409 loaded_vmcs_init(vmx->loaded_vmcs);
6410 if (!vmm_exclusive)
6411 kvm_cpu_vmxoff();
a2fa3e9f 6412
15ad7146
AK		 6413 cpu = get_cpu();
6414 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6415 vmx->vcpu.cpu = cpu;
8b9cf98c 6416 err = vmx_vcpu_setup(vmx);
fb3f0f51 6417 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6418 put_cpu();
fb3f0f51
RR		 6419 if (err)
6420 goto free_vmcs;
5e4a0b3c 6421 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6422 err = alloc_apic_access_page(kvm);
6423 if (err)
5e4a0b3c 6424 goto free_vmcs;
fb3f0f51 6425
b927a3ce
SY		 6426 if (enable_ept) {
6427 if (!kvm->arch.ept_identity_map_addr)
6428 kvm->arch.ept_identity_map_addr =
6429 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6430 err = -ENOMEM;
b7ebfb05
SY		 6431 if (alloc_identity_pagetable(kvm) != 0)
6432 goto free_vmcs;
93ea5388
GN		 6433 if (!init_rmode_identity_map(kvm))
6434 goto free_vmcs;
b927a3ce 6435 }
b7ebfb05 6436
a9d30f33
NHE		 6437 vmx->nested.current_vmptr = -1ull;
6438 vmx->nested.current_vmcs12 = NULL;
6439
fb3f0f51
RR		 6440 return &vmx->vcpu;
6441
6442free_vmcs:
5f3fbc34 6443 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6444free_msrs:
fb3f0f51
RR		 6445 kfree(vmx->guest_msrs);
6446uninit_vcpu:
6447 kvm_vcpu_uninit(&vmx->vcpu);
6448free_vcpu:
cdbecfc3 6449 free_vpid(vmx);
a4770347 6450 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6451 return ERR_PTR(err);
6aa8b732
AK		 6452}
6453
002c7f7c
YS		 6454static void __init vmx_check_processor_compat(void *rtn)
6455{
6456 struct vmcs_config vmcs_conf;
6457
6458 *(int *)rtn = 0;
6459 if (setup_vmcs_config(&vmcs_conf) < 0)
6460 *(int *)rtn = -EIO;
6461 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6462 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6463 smp_processor_id());
6464 *(int *)rtn = -EIO;
6465 }
6466}
6467
67253af5
SY		 6468static int get_ept_level(void)
6469{
6470 return VMX_EPT_DEFAULT_GAW + 1;
6471}
6472
4b12f0de 6473static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6474{
4b12f0de
SY		 6475 u64 ret;
6476
522c68c4
SY		 6477 /* For VT-d and EPT combination
6478 * 1. MMIO: always map as UC
6479 * 2. EPT with VT-d:
6480 * a. VT-d without snooping control feature: can't guarantee the
6481 * result, try to trust guest.
6482 * b. VT-d with snooping control feature: snooping control feature of
6483 * VT-d engine can guarantee the cache correctness. Just set it
6484 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6485 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6486 * consistent with host MTRR
6487 */
4b12f0de
SY		 6488 if (is_mmio)
6489 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6490 else if (vcpu->kvm->arch.iommu_domain &&
6491 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6492 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6493 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6494 else
522c68c4 6495 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6496 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6497
6498 return ret;
64d4d521
SY		 6499}
6500
17cc3935 6501static int vmx_get_lpage_level(void)
344f414f 6502{
878403b7
SY		 6503 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6504 return PT_DIRECTORY_LEVEL;
6505 else
6506 /* For shadow and EPT supported 1GB page */
6507 return PT_PDPE_LEVEL;
344f414f
JR		 6508}
6509
0e851880
SY		 6510static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6511{
4e47c7a6
SY		 6512 struct kvm_cpuid_entry2 *best;
6513 struct vcpu_vmx *vmx = to_vmx(vcpu);
6514 u32 exec_control;
6515
6516 vmx->rdtscp_enabled = false;
6517 if (vmx_rdtscp_supported()) {
6518 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6519 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6520 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6521 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6522 vmx->rdtscp_enabled = true;
6523 else {
6524 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6525 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6526 exec_control);
6527 }
6528 }
6529 }
0e851880
SY		 6530}
6531
d4330ef2
JR		 6532static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6533{
7b8050f5
NHE		 6534 if (func == 1 && nested)
6535 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6536}
6537
fe3ef05c
NHE		 6538/*
6539 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6540 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6541 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6542 * guest in a way that will both be appropriate to L1's requests, and our
6543 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6544 * function also has additional necessary side-effects, like setting various
6545 * vcpu->arch fields.
6546 */
6547static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6548{
6549 struct vcpu_vmx *vmx = to_vmx(vcpu);
6550 u32 exec_control;
6551
6552 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6553 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6554 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6555 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6556 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6557 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6558 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6559 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6560 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6561 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6562 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6563 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6564 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6565 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6566 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6567 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6568 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6569 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6570 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6571 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6572 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6573 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6574 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6575 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6576 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6577 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6578 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6579 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6580 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6581 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6582 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6583 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6584 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6585 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6586 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6587 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6588
6589 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6590 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6591 vmcs12->vm_entry_intr_info_field);
6592 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6593 vmcs12->vm_entry_exception_error_code);
6594 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6595 vmcs12->vm_entry_instruction_len);
6596 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6597 vmcs12->guest_interruptibility_info);
6598 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6599 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6600 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6601 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6602 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6603 vmcs12->guest_pending_dbg_exceptions);
6604 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6605 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6606
6607 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6608
6609 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6610 (vmcs_config.pin_based_exec_ctrl |
6611 vmcs12->pin_based_vm_exec_control));
6612
6613 /*
6614 * Whether page-faults are trapped is determined by a combination of
6615 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6616 * If enable_ept, L0 doesn't care about page faults and we should
6617 * set all of these to L1's desires. However, if !enable_ept, L0 does
6618 * care about (at least some) page faults, and because it is not easy
6619 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6620 * to exit on each and every L2 page fault. This is done by setting
6621 * MASK=MATCH=0 and (see below) EB.PF=1.
6622 * Note that below we don't need special code to set EB.PF beyond the
6623 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6624 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6625 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6626 *
6627 * A problem with this approach (when !enable_ept) is that L1 may be
6628 * injected with more page faults than it asked for. This could have
6629 * caused problems, but in practice existing hypervisors don't care.
6630 * To fix this, we will need to emulate the PFEC checking (on the L1
6631 * page tables), using walk_addr(), when injecting PFs to L1.
6632 */
6633 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6634 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6635 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6636 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6637
6638 if (cpu_has_secondary_exec_ctrls()) {
6639 u32 exec_control = vmx_secondary_exec_control(vmx);
6640 if (!vmx->rdtscp_enabled)
6641 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6642 /* Take the following fields only from vmcs12 */
6643 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6644 if (nested_cpu_has(vmcs12,
6645 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6646 exec_control |= vmcs12->secondary_vm_exec_control;
6647
6648 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6649 /*
6650 * Translate L1 physical address to host physical
6651 * address for vmcs02. Keep the page pinned, so this
6652 * physical address remains valid. We keep a reference
6653 * to it so we can release it later.
6654 */
6655 if (vmx->nested.apic_access_page) /* shouldn't happen */
6656 nested_release_page(vmx->nested.apic_access_page);
6657 vmx->nested.apic_access_page =
6658 nested_get_page(vcpu, vmcs12->apic_access_addr);
6659 /*
6660 * If translation failed, no matter: This feature asks
6661 * to exit when accessing the given address, and if it
6662 * can never be accessed, this feature won't do
6663 * anything anyway.
6664 */
6665 if (!vmx->nested.apic_access_page)
6666 exec_control &=
6667 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6668 else
6669 vmcs_write64(APIC_ACCESS_ADDR,
6670 page_to_phys(vmx->nested.apic_access_page));
6671 }
6672
6673 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6674 }
6675
6676
6677 /*
6678 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6679 * Some constant fields are set here by vmx_set_constant_host_state().
6680 * Other fields are different per CPU, and will be set later when
6681 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6682 */
6683 vmx_set_constant_host_state();
6684
6685 /*
6686 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6687 * entry, but only if the current (host) sp changed from the value
6688 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6689 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6690 * here we just force the write to happen on entry.
6691 */
6692 vmx->host_rsp = 0;
6693
6694 exec_control = vmx_exec_control(vmx); /* L0's desires */
6695 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6696 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6697 exec_control &= ~CPU_BASED_TPR_SHADOW;
6698 exec_control |= vmcs12->cpu_based_vm_exec_control;
6699 /*
6700 * Merging of IO and MSR bitmaps not currently supported.
6701 * Rather, exit every time.
6702 */
6703 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6704 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6705 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6706
6707 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6708
6709 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6710 * bitwise-or of what L1 wants to trap for L2, and what we want to
6711 * trap. Note that CR0.TS also needs updating - we do this later.
6712 */
6713 update_exception_bitmap(vcpu);
6714 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6715 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6716
6717 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6718 vmcs_write32(VM_EXIT_CONTROLS,
6719 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6720 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6721 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6722
6723 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6724 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6725 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6726 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6727
6728
6729 set_cr4_guest_host_mask(vmx);
6730
27fc51b2
NHE		 6731 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6732 vmcs_write64(TSC_OFFSET,
6733 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6734 else
6735 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6736
6737 if (enable_vpid) {
6738 /*
6739 * Trivially support vpid by letting L2s share their parent
6740 * L1's vpid. TODO: move to a more elaborate solution, giving
6741 * each L2 its own vpid and exposing the vpid feature to L1.
6742 */
6743 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6744 vmx_flush_tlb(vcpu);
6745 }
6746
6747 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6748 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6749 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6750 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6751 else
6752 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6753 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6754 vmx_set_efer(vcpu, vcpu->arch.efer);
6755
6756 /*
6757 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6758 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6759 * The CR0_READ_SHADOW is what L2 should have expected to read given
6760 * the specifications by L1; It's not enough to take
6761 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6762 * have more bits than L1 expected.
6763 */
6764 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6765 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6766
6767 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6768 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6769
6770 /* shadow page tables on either EPT or shadow page tables */
6771 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6772 kvm_mmu_reset_context(vcpu);
6773
6774 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6775 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6776}
6777
cd232ad0
NHE		 6778/*
6779 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6780 * for running an L2 nested guest.
6781 */
6782static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6783{
6784 struct vmcs12 *vmcs12;
6785 struct vcpu_vmx *vmx = to_vmx(vcpu);
6786 int cpu;
6787 struct loaded_vmcs *vmcs02;
6788
6789 if (!nested_vmx_check_permission(vcpu) ||
6790 !nested_vmx_check_vmcs12(vcpu))
6791 return 1;
6792
6793 skip_emulated_instruction(vcpu);
6794 vmcs12 = get_vmcs12(vcpu);
6795
7c177938
NHE		 6796 /*
6797 * The nested entry process starts with enforcing various prerequisites
6798 * on vmcs12 as required by the Intel SDM, and act appropriately when
6799 * they fail: As the SDM explains, some conditions should cause the
6800 * instruction to fail, while others will cause the instruction to seem
6801 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6802 * To speed up the normal (success) code path, we should avoid checking
6803 * for misconfigurations which will anyway be caught by the processor
6804 * when using the merged vmcs02.
6805 */
6806 if (vmcs12->launch_state == launch) {
6807 nested_vmx_failValid(vcpu,
6808 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6809 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6810 return 1;
6811 }
6812
6813 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6814 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6815 /*TODO: Also verify bits beyond physical address width are 0*/
6816 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6817 return 1;
6818 }
6819
6820 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6821 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6822 /*TODO: Also verify bits beyond physical address width are 0*/
6823 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6824 return 1;
6825 }
6826
6827 if (vmcs12->vm_entry_msr_load_count > 0 ||
6828 vmcs12->vm_exit_msr_load_count > 0 ||
6829 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6830 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6831 __func__);
7c177938
NHE		 6832 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6833 return 1;
6834 }
6835
6836 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6837 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6838 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6839 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6840 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6841 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6842 !vmx_control_verify(vmcs12->vm_exit_controls,
6843 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6844 !vmx_control_verify(vmcs12->vm_entry_controls,
6845 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6846 {
6847 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6848 return 1;
6849 }
6850
6851 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6852 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6853 nested_vmx_failValid(vcpu,
6854 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6855 return 1;
6856 }
6857
6858 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6859 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6860 nested_vmx_entry_failure(vcpu, vmcs12,
6861 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6862 return 1;
6863 }
6864 if (vmcs12->vmcs_link_pointer != -1ull) {
6865 nested_vmx_entry_failure(vcpu, vmcs12,
6866 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6867 return 1;
6868 }
6869
6870 /*
6871 * We're finally done with prerequisite checking, and can start with
6872 * the nested entry.
6873 */
6874
cd232ad0
NHE		 6875 vmcs02 = nested_get_current_vmcs02(vmx);
6876 if (!vmcs02)
6877 return -ENOMEM;
6878
6879 enter_guest_mode(vcpu);
6880
6881 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6882
6883 cpu = get_cpu();
6884 vmx->loaded_vmcs = vmcs02;
6885 vmx_vcpu_put(vcpu);
6886 vmx_vcpu_load(vcpu, cpu);
6887 vcpu->cpu = cpu;
6888 put_cpu();
6889
6890 vmcs12->launch_state = 1;
6891
6892 prepare_vmcs02(vcpu, vmcs12);
6893
6894 /*
6895 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6896 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6897 * returned as far as L1 is concerned. It will only return (and set
6898 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6899 */
6900 return 1;
6901}
6902
4704d0be
NHE		 6903/*
6904 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6905 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6906 * This function returns the new value we should put in vmcs12.guest_cr0.
6907 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6908 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6909 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6910 * didn't trap the bit, because if L1 did, so would L0).
6911 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6912 * been modified by L2, and L1 knows it. So just leave the old value of
6913 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6914 * isn't relevant, because if L0 traps this bit it can set it to anything.
6915 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6916 * changed these bits, and therefore they need to be updated, but L0
6917 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6918 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6919 */
6920static inline unsigned long
6921vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6922{
6923 return
6924 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6925 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6926 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6927 vcpu->arch.cr0_guest_owned_bits));
6928}
6929
6930static inline unsigned long
6931vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6932{
6933 return
6934 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6935 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6936 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6937 vcpu->arch.cr4_guest_owned_bits));
6938}
6939
6940/*
6941 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6942 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6943 * and this function updates it to reflect the changes to the guest state while
6944 * L2 was running (and perhaps made some exits which were handled directly by L0
6945 * without going back to L1), and to reflect the exit reason.
6946 * Note that we do not have to copy here all VMCS fields, just those that
6947 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6948 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6949 * which already writes to vmcs12 directly.
6950 */
6951void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6952{
6953 /* update guest state fields: */
6954 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6955 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6956
6957 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6958 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6959 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6960 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6961
6962 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6963 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6964 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6965 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6966 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6967 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6968 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6969 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6970 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6971 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6972 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6973 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6974 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6975 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6976 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6977 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6978 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6979 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6980 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6981 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6982 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6983 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6984 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6985 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6986 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6987 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6988 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6989 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6990 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6991 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6992 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6993 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6994 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6995 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6996 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6997 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6998
6999 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7000 vmcs12->guest_interruptibility_info =
7001 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7002 vmcs12->guest_pending_dbg_exceptions =
7003 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7004
7005 /* TODO: These cannot have changed unless we have MSR bitmaps and
7006 * the relevant bit asks not to trap the change */
7007 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7008 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7009 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7010 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7011 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7012 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7013
7014 /* update exit information fields: */
7015
7016 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7017 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7018
7019 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7020 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7021 vmcs12->idt_vectoring_info_field =
7022 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7023 vmcs12->idt_vectoring_error_code =
7024 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7025 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7026 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7027
7028 /* clear vm-entry fields which are to be cleared on exit */
7029 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7030 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7031}
7032
7033/*
7034 * A part of what we need to when the nested L2 guest exits and we want to
7035 * run its L1 parent, is to reset L1's guest state to the host state specified
7036 * in vmcs12.
7037 * This function is to be called not only on normal nested exit, but also on
7038 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7039 * Failures During or After Loading Guest State").
7040 * This function should be called when the active VMCS is L1's (vmcs01).
7041 */
7042void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7043{
7044 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7045 vcpu->arch.efer = vmcs12->host_ia32_efer;
7046 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7047 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7048 else
7049 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7050 vmx_set_efer(vcpu, vcpu->arch.efer);
7051
7052 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7053 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7054 /*
7055 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7056 * actually changed, because it depends on the current state of
7057 * fpu_active (which may have changed).
7058 * Note that vmx_set_cr0 refers to efer set above.
7059 */
7060 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7061 /*
7062 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7063 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7064 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7065 */
7066 update_exception_bitmap(vcpu);
7067 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7068 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7069
7070 /*
7071 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7072 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7073 */
7074 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7075 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7076
7077 /* shadow page tables on either EPT or shadow page tables */
7078 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7079 kvm_mmu_reset_context(vcpu);
7080
7081 if (enable_vpid) {
7082 /*
7083 * Trivially support vpid by letting L2s share their parent
7084 * L1's vpid. TODO: move to a more elaborate solution, giving
7085 * each L2 its own vpid and exposing the vpid feature to L1.
7086 */
7087 vmx_flush_tlb(vcpu);
7088 }
7089
7090
7091 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7092 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7093 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7094 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7095 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7096 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7097 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7098 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7099 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7100 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7101 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7102 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7103 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7104 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7105 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7106
7107 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7108 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7109 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7110 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7111 vmcs12->host_ia32_perf_global_ctrl);
7112}
7113
7114/*
7115 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7116 * and modify vmcs12 to make it see what it would expect to see there if
7117 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7118 */
7119static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7120{
7121 struct vcpu_vmx *vmx = to_vmx(vcpu);
7122 int cpu;
7123 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7124
7125 leave_guest_mode(vcpu);
7126 prepare_vmcs12(vcpu, vmcs12);
7127
7128 cpu = get_cpu();
7129 vmx->loaded_vmcs = &vmx->vmcs01;
7130 vmx_vcpu_put(vcpu);
7131 vmx_vcpu_load(vcpu, cpu);
7132 vcpu->cpu = cpu;
7133 put_cpu();
7134
7135 /* if no vmcs02 cache requested, remove the one we used */
7136 if (VMCS02_POOL_SIZE == 0)
7137 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7138
7139 load_vmcs12_host_state(vcpu, vmcs12);
7140
27fc51b2 7141 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7142 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7143
7144 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7145 vmx->host_rsp = 0;
7146
7147 /* Unpin physical memory we referred to in vmcs02 */
7148 if (vmx->nested.apic_access_page) {
7149 nested_release_page(vmx->nested.apic_access_page);
7150 vmx->nested.apic_access_page = 0;
7151 }
7152
7153 /*
7154 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7155 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7156 * success or failure flag accordingly.
7157 */
7158 if (unlikely(vmx->fail)) {
7159 vmx->fail = 0;
7160 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7161 } else
7162 nested_vmx_succeed(vcpu);
7163}
7164
7c177938
NHE		 7165/*
7166 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7167 * 23.7 "VM-entry failures during or after loading guest state" (this also
7168 * lists the acceptable exit-reason and exit-qualification parameters).
7169 * It should only be called before L2 actually succeeded to run, and when
7170 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7171 */
7172static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7173 struct vmcs12 *vmcs12,
7174 u32 reason, unsigned long qualification)
7175{
7176 load_vmcs12_host_state(vcpu, vmcs12);
7177 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7178 vmcs12->exit_qualification = qualification;
7179 nested_vmx_succeed(vcpu);
7180}
7181
8a76d7f2
JR		 7182static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7183 struct x86_instruction_info *info,
7184 enum x86_intercept_stage stage)
7185{
7186 return X86EMUL_CONTINUE;
7187}
7188
cbdd1bea 7189static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7190 .cpu_has_kvm_support = cpu_has_kvm_support,
7191 .disabled_by_bios = vmx_disabled_by_bios,
7192 .hardware_setup = hardware_setup,
7193 .hardware_unsetup = hardware_unsetup,
002c7f7c 7194 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7195 .hardware_enable = hardware_enable,
7196 .hardware_disable = hardware_disable,
04547156 7197 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7198
7199 .vcpu_create = vmx_create_vcpu,
7200 .vcpu_free = vmx_free_vcpu,
04d2cc77 7201 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7202
04d2cc77 7203 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7204 .vcpu_load = vmx_vcpu_load,
7205 .vcpu_put = vmx_vcpu_put,
7206
7207 .set_guest_debug = set_guest_debug,
7208 .get_msr = vmx_get_msr,
7209 .set_msr = vmx_set_msr,
7210 .get_segment_base = vmx_get_segment_base,
7211 .get_segment = vmx_get_segment,
7212 .set_segment = vmx_set_segment,
2e4d2653 7213 .get_cpl = vmx_get_cpl,
6aa8b732 7214 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7215 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7216 .decache_cr3 = vmx_decache_cr3,
25c4c276 7217 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7218 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7219 .set_cr3 = vmx_set_cr3,
7220 .set_cr4 = vmx_set_cr4,
6aa8b732 7221 .set_efer = vmx_set_efer,
6aa8b732
AK		 7222 .get_idt = vmx_get_idt,
7223 .set_idt = vmx_set_idt,
7224 .get_gdt = vmx_get_gdt,
7225 .set_gdt = vmx_set_gdt,
020df079 7226 .set_dr7 = vmx_set_dr7,
5fdbf976 7227 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7228 .get_rflags = vmx_get_rflags,
7229 .set_rflags = vmx_set_rflags,
ebcbab4c 7230 .fpu_activate = vmx_fpu_activate,
02daab21 7231 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7232
7233 .tlb_flush = vmx_flush_tlb,
6aa8b732 7234
6aa8b732 7235 .run = vmx_vcpu_run,
6062d012 7236 .handle_exit = vmx_handle_exit,
6aa8b732 7237 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7238 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7239 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7240 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7241 .set_irq = vmx_inject_irq,
95ba8273 7242 .set_nmi = vmx_inject_nmi,
298101da 7243 .queue_exception = vmx_queue_exception,
b463a6f7 7244 .cancel_injection = vmx_cancel_injection,
78646121 7245 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7246 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7247 .get_nmi_mask = vmx_get_nmi_mask,
7248 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7249 .enable_nmi_window = enable_nmi_window,
7250 .enable_irq_window = enable_irq_window,
7251 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7252
cbc94022 7253 .set_tss_addr = vmx_set_tss_addr,
67253af5 7254 .get_tdp_level = get_ept_level,
4b12f0de 7255 .get_mt_mask = vmx_get_mt_mask,
229456fc 7256
586f9607 7257 .get_exit_info = vmx_get_exit_info,
586f9607 7258
17cc3935 7259 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7260
7261 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7262
7263 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7264
7265 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7266
7267 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7268
4051b188 7269 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7270 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7271 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7272 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7273 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7274
7275 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7276
7277 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7278};
7279
7280static int __init vmx_init(void)
7281{
26bb0981
AK		 7282 int r, i;
7283
7284 rdmsrl_safe(MSR_EFER, &host_efer);
7285
7286 for (i = 0; i < NR_VMX_MSR; ++i)
7287 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7288
3e7c73e9 7289 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7290 if (!vmx_io_bitmap_a)
7291 return -ENOMEM;
7292
3e7c73e9 7293 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7294 if (!vmx_io_bitmap_b) {
7295 r = -ENOMEM;
7296 goto out;
7297 }
7298
5897297b
AK		 7299 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7300 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7301 r = -ENOMEM;
7302 goto out1;
7303 }
7304
5897297b
AK		 7305 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7306 if (!vmx_msr_bitmap_longmode) {
7307 r = -ENOMEM;
7308 goto out2;
7309 }
7310
fdef3ad1
HQ		 7311 /*
7312 * Allow direct access to the PC debug port (it is often used for I/O
7313 * delays, but the vmexits simply slow things down).
7314 */
3e7c73e9
AK		 7315 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7316 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7317
3e7c73e9 7318 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7319
5897297b
AK		 7320 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7321 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7322
2384d2b3
SY		 7323 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7324
0ee75bea
AK		 7325 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7326 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7327 if (r)
5897297b 7328 goto out3;
25c5f225 7329
5897297b
AK		 7330 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7331 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7332 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7333 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7334 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7335 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7336
089d034e 7337 if (enable_ept) {
3f6d8c8a
XH		 7338 kvm_mmu_set_mask_ptes(0ull,
7339 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7340 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7341 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7342 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7343 kvm_enable_tdp();
7344 } else
7345 kvm_disable_tdp();
1439442c 7346
fdef3ad1
HQ		 7347 return 0;
7348
5897297b
AK		 7349out3:
7350 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7351out2:
5897297b 7352 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7353out1:
3e7c73e9 7354 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7355out:
3e7c73e9 7356 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7357 return r;
6aa8b732
AK		 7358}
7359
7360static void __exit vmx_exit(void)
7361{
5897297b
AK		 7362 free_page((unsigned long)vmx_msr_bitmap_legacy);
7363 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7364 free_page((unsigned long)vmx_io_bitmap_b);
7365 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7366
cb498ea2 7367 kvm_exit();
6aa8b732
AK		 7368}
7369
7370module_init(vmx_init)
7371module_exit(vmx_exit)
Linux kernel - Deliverables
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