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KVM: MMU: make kvm_mmu_available_pages robust against n_used_mmu_pages > n_max_mmu_pages
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
257090f7 87static bool __read_mostly enable_apicv_reg_vid;
83d4c286 88
801d3424
NHE		 89/*
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
93 */
476bc001 94static bool __read_mostly nested = 0;
801d3424
NHE		 95module_param(nested, bool, S_IRUGO);
96
5037878e
GN		 97#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 99#define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 101#define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
104
cdc0e244
AK		 105#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
107
78ac8b47
AK		 108#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
109
4b8d54f9
ZE		 110/*
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 114 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
120 */
00c25bce 121#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 122#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
124module_param(ple_gap, int, S_IRUGO);
125
126static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
127module_param(ple_window, int, S_IRUGO);
128
83287ea4
AK		 129extern const ulong vmx_return;
130
8bf00a52 131#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 132#define VMCS02_POOL_SIZE 1
61d2ef2c 133
a2fa3e9f
GH		 134struct vmcs {
135 u32 revision_id;
136 u32 abort;
137 char data[0];
138};
139
d462b819
NHE		 140/*
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
144 */
145struct loaded_vmcs {
146 struct vmcs *vmcs;
147 int cpu;
148 int launched;
149 struct list_head loaded_vmcss_on_cpu_link;
150};
151
26bb0981
AK		 152struct shared_msr_entry {
153 unsigned index;
154 u64 data;
d5696725 155 u64 mask;
26bb0981
AK		 156};
157
a9d30f33
NHE		 158/*
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 */
22bd0358 171typedef u64 natural_width;
a9d30f33
NHE		 172struct __packed vmcs12 {
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
175 */
176 u32 revision_id;
177 u32 abort;
22bd0358 178
27d6c865
NHE		 179 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding[7]; /* room for future expansion */
181
22bd0358
NHE		 182 u64 io_bitmap_a;
183 u64 io_bitmap_b;
184 u64 msr_bitmap;
185 u64 vm_exit_msr_store_addr;
186 u64 vm_exit_msr_load_addr;
187 u64 vm_entry_msr_load_addr;
188 u64 tsc_offset;
189 u64 virtual_apic_page_addr;
190 u64 apic_access_addr;
191 u64 ept_pointer;
192 u64 guest_physical_address;
193 u64 vmcs_link_pointer;
194 u64 guest_ia32_debugctl;
195 u64 guest_ia32_pat;
196 u64 guest_ia32_efer;
197 u64 guest_ia32_perf_global_ctrl;
198 u64 guest_pdptr0;
199 u64 guest_pdptr1;
200 u64 guest_pdptr2;
201 u64 guest_pdptr3;
202 u64 host_ia32_pat;
203 u64 host_ia32_efer;
204 u64 host_ia32_perf_global_ctrl;
205 u64 padding64[8]; /* room for future expansion */
206 /*
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
211 */
212 natural_width cr0_guest_host_mask;
213 natural_width cr4_guest_host_mask;
214 natural_width cr0_read_shadow;
215 natural_width cr4_read_shadow;
216 natural_width cr3_target_value0;
217 natural_width cr3_target_value1;
218 natural_width cr3_target_value2;
219 natural_width cr3_target_value3;
220 natural_width exit_qualification;
221 natural_width guest_linear_address;
222 natural_width guest_cr0;
223 natural_width guest_cr3;
224 natural_width guest_cr4;
225 natural_width guest_es_base;
226 natural_width guest_cs_base;
227 natural_width guest_ss_base;
228 natural_width guest_ds_base;
229 natural_width guest_fs_base;
230 natural_width guest_gs_base;
231 natural_width guest_ldtr_base;
232 natural_width guest_tr_base;
233 natural_width guest_gdtr_base;
234 natural_width guest_idtr_base;
235 natural_width guest_dr7;
236 natural_width guest_rsp;
237 natural_width guest_rip;
238 natural_width guest_rflags;
239 natural_width guest_pending_dbg_exceptions;
240 natural_width guest_sysenter_esp;
241 natural_width guest_sysenter_eip;
242 natural_width host_cr0;
243 natural_width host_cr3;
244 natural_width host_cr4;
245 natural_width host_fs_base;
246 natural_width host_gs_base;
247 natural_width host_tr_base;
248 natural_width host_gdtr_base;
249 natural_width host_idtr_base;
250 natural_width host_ia32_sysenter_esp;
251 natural_width host_ia32_sysenter_eip;
252 natural_width host_rsp;
253 natural_width host_rip;
254 natural_width paddingl[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control;
256 u32 cpu_based_vm_exec_control;
257 u32 exception_bitmap;
258 u32 page_fault_error_code_mask;
259 u32 page_fault_error_code_match;
260 u32 cr3_target_count;
261 u32 vm_exit_controls;
262 u32 vm_exit_msr_store_count;
263 u32 vm_exit_msr_load_count;
264 u32 vm_entry_controls;
265 u32 vm_entry_msr_load_count;
266 u32 vm_entry_intr_info_field;
267 u32 vm_entry_exception_error_code;
268 u32 vm_entry_instruction_len;
269 u32 tpr_threshold;
270 u32 secondary_vm_exec_control;
271 u32 vm_instruction_error;
272 u32 vm_exit_reason;
273 u32 vm_exit_intr_info;
274 u32 vm_exit_intr_error_code;
275 u32 idt_vectoring_info_field;
276 u32 idt_vectoring_error_code;
277 u32 vm_exit_instruction_len;
278 u32 vmx_instruction_info;
279 u32 guest_es_limit;
280 u32 guest_cs_limit;
281 u32 guest_ss_limit;
282 u32 guest_ds_limit;
283 u32 guest_fs_limit;
284 u32 guest_gs_limit;
285 u32 guest_ldtr_limit;
286 u32 guest_tr_limit;
287 u32 guest_gdtr_limit;
288 u32 guest_idtr_limit;
289 u32 guest_es_ar_bytes;
290 u32 guest_cs_ar_bytes;
291 u32 guest_ss_ar_bytes;
292 u32 guest_ds_ar_bytes;
293 u32 guest_fs_ar_bytes;
294 u32 guest_gs_ar_bytes;
295 u32 guest_ldtr_ar_bytes;
296 u32 guest_tr_ar_bytes;
297 u32 guest_interruptibility_info;
298 u32 guest_activity_state;
299 u32 guest_sysenter_cs;
300 u32 host_ia32_sysenter_cs;
301 u32 padding32[8]; /* room for future expansion */
302 u16 virtual_processor_id;
303 u16 guest_es_selector;
304 u16 guest_cs_selector;
305 u16 guest_ss_selector;
306 u16 guest_ds_selector;
307 u16 guest_fs_selector;
308 u16 guest_gs_selector;
309 u16 guest_ldtr_selector;
310 u16 guest_tr_selector;
311 u16 host_es_selector;
312 u16 host_cs_selector;
313 u16 host_ss_selector;
314 u16 host_ds_selector;
315 u16 host_fs_selector;
316 u16 host_gs_selector;
317 u16 host_tr_selector;
a9d30f33
NHE		 318};
319
320/*
321 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
322 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
323 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 */
325#define VMCS12_REVISION 0x11e57ed0
326
327/*
328 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
329 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
330 * current implementation, 4K are reserved to avoid future complications.
331 */
332#define VMCS12_SIZE 0x1000
333
ff2f6fe9
NHE		 334/* Used to remember the last vmcs02 used for some recently used vmcs12s */
335struct vmcs02_list {
336 struct list_head list;
337 gpa_t vmptr;
338 struct loaded_vmcs vmcs02;
339};
340
ec378aee
NHE		 341/*
342 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
343 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
344 */
345struct nested_vmx {
346 /* Has the level1 guest done vmxon? */
347 bool vmxon;
a9d30f33
NHE		 348
349 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 gpa_t current_vmptr;
351 /* The host-usable pointer to the above */
352 struct page *current_vmcs12_page;
353 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 354
355 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
356 struct list_head vmcs02_pool;
357 int vmcs02_num;
fe3ef05c 358 u64 vmcs01_tsc_offset;
644d711a
NHE		 359 /* L2 must run next, and mustn't decide to exit to L1. */
360 bool nested_run_pending;
fe3ef05c
NHE		 361 /*
362 * Guest pages referred to in vmcs02 with host-physical pointers, so
363 * we must keep them pinned while L2 runs.
364 */
365 struct page *apic_access_page;
ec378aee
NHE		 366};
367
a2fa3e9f 368struct vcpu_vmx {
fb3f0f51 369 struct kvm_vcpu vcpu;
313dbd49 370 unsigned long host_rsp;
29bd8a78 371 u8 fail;
69c73028 372 u8 cpl;
9d58b931 373 bool nmi_known_unmasked;
51aa01d1 374 u32 exit_intr_info;
1155f76a 375 u32 idt_vectoring_info;
6de12732 376 ulong rflags;
26bb0981 377 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 378 int nmsrs;
379 int save_nmsrs;
a2fa3e9f 380#ifdef CONFIG_X86_64
44ea2b17
AK		 381 u64 msr_host_kernel_gs_base;
382 u64 msr_guest_kernel_gs_base;
a2fa3e9f 383#endif
d462b819
NHE		 384 /*
385 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
386 * non-nested (L1) guest, it always points to vmcs01. For a nested
387 * guest (L2), it points to a different VMCS.
388 */
389 struct loaded_vmcs vmcs01;
390 struct loaded_vmcs *loaded_vmcs;
391 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 392 struct msr_autoload {
393 unsigned nr;
394 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
395 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
396 } msr_autoload;
a2fa3e9f
GH		 397 struct {
398 int loaded;
399 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 400#ifdef CONFIG_X86_64
401 u16 ds_sel, es_sel;
402#endif
152d3f2f
LV		 403 int gs_ldt_reload_needed;
404 int fs_reload_needed;
d77c26fc 405 } host_state;
9c8cba37 406 struct {
7ffd92c5 407 int vm86_active;
78ac8b47 408 ulong save_rflags;
f5f7b2fe
AK		 409 struct kvm_segment segs[8];
410 } rmode;
411 struct {
412 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 413 struct kvm_save_segment {
414 u16 selector;
415 unsigned long base;
416 u32 limit;
417 u32 ar;
f5f7b2fe 418 } seg[8];
2fb92db1 419 } segment_cache;
2384d2b3 420 int vpid;
04fa4d32 421 bool emulation_required;
3b86cd99
JK		 422
423 /* Support for vnmi-less CPUs */
424 int soft_vnmi_blocked;
425 ktime_t entry_time;
426 s64 vnmi_blocked_time;
a0861c02 427 u32 exit_reason;
4e47c7a6
SY		 428
429 bool rdtscp_enabled;
ec378aee
NHE		 430
431 /* Support for a guest hypervisor (nested VMX) */
432 struct nested_vmx nested;
a2fa3e9f
GH		 433};
434
2fb92db1
AK		 435enum segment_cache_field {
436 SEG_FIELD_SEL = 0,
437 SEG_FIELD_BASE = 1,
438 SEG_FIELD_LIMIT = 2,
439 SEG_FIELD_AR = 3,
440
441 SEG_FIELD_NR = 4
442};
443
a2fa3e9f
GH		 444static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
445{
fb3f0f51 446 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 447}
448
22bd0358
NHE		 449#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
450#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
451#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
452 [number##_HIGH] = VMCS12_OFFSET(name)+4
453
772e0318 454static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 455 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
456 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
457 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
458 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
459 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
460 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
461 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
462 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
463 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
464 FIELD(HOST_ES_SELECTOR, host_es_selector),
465 FIELD(HOST_CS_SELECTOR, host_cs_selector),
466 FIELD(HOST_SS_SELECTOR, host_ss_selector),
467 FIELD(HOST_DS_SELECTOR, host_ds_selector),
468 FIELD(HOST_FS_SELECTOR, host_fs_selector),
469 FIELD(HOST_GS_SELECTOR, host_gs_selector),
470 FIELD(HOST_TR_SELECTOR, host_tr_selector),
471 FIELD64(IO_BITMAP_A, io_bitmap_a),
472 FIELD64(IO_BITMAP_B, io_bitmap_b),
473 FIELD64(MSR_BITMAP, msr_bitmap),
474 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
475 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
476 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
477 FIELD64(TSC_OFFSET, tsc_offset),
478 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
479 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
480 FIELD64(EPT_POINTER, ept_pointer),
481 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
482 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
483 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
484 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
485 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
486 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
487 FIELD64(GUEST_PDPTR0, guest_pdptr0),
488 FIELD64(GUEST_PDPTR1, guest_pdptr1),
489 FIELD64(GUEST_PDPTR2, guest_pdptr2),
490 FIELD64(GUEST_PDPTR3, guest_pdptr3),
491 FIELD64(HOST_IA32_PAT, host_ia32_pat),
492 FIELD64(HOST_IA32_EFER, host_ia32_efer),
493 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
494 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
495 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
496 FIELD(EXCEPTION_BITMAP, exception_bitmap),
497 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
498 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
499 FIELD(CR3_TARGET_COUNT, cr3_target_count),
500 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
501 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
502 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
503 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
504 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
505 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
506 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
507 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
508 FIELD(TPR_THRESHOLD, tpr_threshold),
509 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
510 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
511 FIELD(VM_EXIT_REASON, vm_exit_reason),
512 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
513 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
514 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
515 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
516 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
517 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
518 FIELD(GUEST_ES_LIMIT, guest_es_limit),
519 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
520 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
521 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
522 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
523 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
524 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
525 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
526 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
527 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
528 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
529 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
530 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
531 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
532 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
533 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
534 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
535 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
536 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
537 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
538 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
539 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
540 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
541 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
542 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
543 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
544 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
545 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
546 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
547 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
548 FIELD(EXIT_QUALIFICATION, exit_qualification),
549 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
550 FIELD(GUEST_CR0, guest_cr0),
551 FIELD(GUEST_CR3, guest_cr3),
552 FIELD(GUEST_CR4, guest_cr4),
553 FIELD(GUEST_ES_BASE, guest_es_base),
554 FIELD(GUEST_CS_BASE, guest_cs_base),
555 FIELD(GUEST_SS_BASE, guest_ss_base),
556 FIELD(GUEST_DS_BASE, guest_ds_base),
557 FIELD(GUEST_FS_BASE, guest_fs_base),
558 FIELD(GUEST_GS_BASE, guest_gs_base),
559 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
560 FIELD(GUEST_TR_BASE, guest_tr_base),
561 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
562 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
563 FIELD(GUEST_DR7, guest_dr7),
564 FIELD(GUEST_RSP, guest_rsp),
565 FIELD(GUEST_RIP, guest_rip),
566 FIELD(GUEST_RFLAGS, guest_rflags),
567 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
568 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
569 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
570 FIELD(HOST_CR0, host_cr0),
571 FIELD(HOST_CR3, host_cr3),
572 FIELD(HOST_CR4, host_cr4),
573 FIELD(HOST_FS_BASE, host_fs_base),
574 FIELD(HOST_GS_BASE, host_gs_base),
575 FIELD(HOST_TR_BASE, host_tr_base),
576 FIELD(HOST_GDTR_BASE, host_gdtr_base),
577 FIELD(HOST_IDTR_BASE, host_idtr_base),
578 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
579 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
580 FIELD(HOST_RSP, host_rsp),
581 FIELD(HOST_RIP, host_rip),
582};
583static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
584
585static inline short vmcs_field_to_offset(unsigned long field)
586{
587 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
588 return -1;
589 return vmcs_field_to_offset_table[field];
590}
591
a9d30f33
NHE		 592static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
593{
594 return to_vmx(vcpu)->nested.current_vmcs12;
595}
596
597static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
598{
599 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 600 if (is_error_page(page))
a9d30f33 601 return NULL;
32cad84f 602
a9d30f33
NHE		 603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
d99e4152
GN		 625static bool guest_state_valid(struct kvm_vcpu *vcpu);
626static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 627
6aa8b732
AK		 628static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 630/*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 635static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 636
3e7c73e9
AK		 637static unsigned long *vmx_io_bitmap_a;
638static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 639static unsigned long *vmx_msr_bitmap_legacy;
640static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 641static unsigned long *vmx_msr_bitmap_legacy_x2apic;
642static unsigned long *vmx_msr_bitmap_longmode_x2apic;
fdef3ad1 643
110312c8 644static bool cpu_has_load_ia32_efer;
8bf00a52 645static bool cpu_has_load_perf_global_ctrl;
110312c8 646
2384d2b3
SY		 647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
1c3d14fe 650static struct vmcs_config {
6aa8b732
AK		 651 int size;
652 int order;
653 u32 revision_id;
1c3d14fe
YS		 654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
f78e0e2e 656 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
6aa8b732 660
efff9e53 661static struct vmx_capability {
d56f546d
SY		 662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
6aa8b732
AK		 666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
772e0318 674static const struct kvm_vmx_segment_field {
6aa8b732
AK		 675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
26bb0981
AK		 690static u64 host_efer;
691
6de4f3ad
AK		 692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
4d56c8a7 694/*
8c06585d 695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 696 * away by decrementing the array size.
697 */
6aa8b732 698static const u32 vmx_msr_index[] = {
05b3e0c2 699#ifdef CONFIG_X86_64
44ea2b17 700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 701#endif
8c06585d 702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 703};
9d8f549d 704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 705
31299944 706static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 711}
712
31299944 713static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 718}
719
31299944 720static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 725}
726
31299944 727static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
31299944 733static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
31299944 740static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 743}
744
31299944 745static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 746{
04547156 747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 748}
749
31299944 750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 751{
04547156 752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 753}
754
31299944 755static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 756{
04547156
SY		 757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 759}
760
774ead3a 761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 762{
04547156
SY		 763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
8d14695f
YZ		 767static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
768{
769 return vmcs_config.cpu_based_2nd_exec_ctrl &
770 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
771}
772
83d4c286
YZ		 773static inline bool cpu_has_vmx_apic_register_virt(void)
774{
775 return vmcs_config.cpu_based_2nd_exec_ctrl &
776 SECONDARY_EXEC_APIC_REGISTER_VIRT;
777}
778
c7c9c56c
YZ		 779static inline bool cpu_has_vmx_virtual_intr_delivery(void)
780{
781 return vmcs_config.cpu_based_2nd_exec_ctrl &
782 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
783}
784
04547156
SY		 785static inline bool cpu_has_vmx_flexpriority(void)
786{
787 return cpu_has_vmx_tpr_shadow() &&
788 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 789}
790
e799794e
MT		 791static inline bool cpu_has_vmx_ept_execute_only(void)
792{
31299944 793 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 794}
795
796static inline bool cpu_has_vmx_eptp_uncacheable(void)
797{
31299944 798 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 799}
800
801static inline bool cpu_has_vmx_eptp_writeback(void)
802{
31299944 803 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 804}
805
806static inline bool cpu_has_vmx_ept_2m_page(void)
807{
31299944 808 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 809}
810
878403b7
SY		 811static inline bool cpu_has_vmx_ept_1g_page(void)
812{
31299944 813 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 814}
815
4bc9b982
SY		 816static inline bool cpu_has_vmx_ept_4levels(void)
817{
818 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
819}
820
83c3a331
XH		 821static inline bool cpu_has_vmx_ept_ad_bits(void)
822{
823 return vmx_capability.ept & VMX_EPT_AD_BIT;
824}
825
31299944 826static inline bool cpu_has_vmx_invept_context(void)
d56f546d 827{
31299944 828 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 829}
830
31299944 831static inline bool cpu_has_vmx_invept_global(void)
d56f546d 832{
31299944 833 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 834}
835
518c8aee
GJ		 836static inline bool cpu_has_vmx_invvpid_single(void)
837{
838 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
839}
840
b9d762fa
GJ		 841static inline bool cpu_has_vmx_invvpid_global(void)
842{
843 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
844}
845
31299944 846static inline bool cpu_has_vmx_ept(void)
d56f546d 847{
04547156
SY		 848 return vmcs_config.cpu_based_2nd_exec_ctrl &
849 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 853{
854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_UNRESTRICTED_GUEST;
856}
857
31299944 858static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
862}
863
31299944 864static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 865{
6d3e435e 866 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 867}
868
31299944 869static inline bool cpu_has_vmx_vpid(void)
2384d2b3 870{
04547156
SY		 871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 873}
874
31299944 875static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 876{
877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_RDTSCP;
879}
880
ad756a16
MJ		 881static inline bool cpu_has_vmx_invpcid(void)
882{
883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_ENABLE_INVPCID;
885}
886
31299944 887static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 888{
889 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
890}
891
f5f48ee1
SY		 892static inline bool cpu_has_vmx_wbinvd_exit(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_WBINVD_EXITING;
896}
897
04547156
SY		 898static inline bool report_flexpriority(void)
899{
900 return flexpriority_enabled;
901}
902
fe3ef05c
NHE		 903static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
904{
905 return vmcs12->cpu_based_vm_exec_control & bit;
906}
907
908static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
909{
910 return (vmcs12->cpu_based_vm_exec_control &
911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
912 (vmcs12->secondary_vm_exec_control & bit);
913}
914
644d711a
NHE		 915static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
916 struct kvm_vcpu *vcpu)
917{
918 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
919}
920
921static inline bool is_exception(u32 intr_info)
922{
923 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
924 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
925}
926
927static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 928static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
929 struct vmcs12 *vmcs12,
930 u32 reason, unsigned long qualification);
931
8b9cf98c 932static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 933{
934 int i;
935
a2fa3e9f 936 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 937 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 938 return i;
939 return -1;
940}
941
2384d2b3
SY		 942static inline void __invvpid(int ext, u16 vpid, gva_t gva)
943{
944 struct {
945 u64 vpid : 16;
946 u64 rsvd : 48;
947 u64 gva;
948 } operand = { vpid, 0, gva };
949
4ecac3fd 950 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 951 /* CF==1 or ZF==1 --> rc = -1 */
952 "; ja 1f ; ud2 ; 1:"
953 : : "a"(&operand), "c"(ext) : "cc", "memory");
954}
955
1439442c
SY		 956static inline void __invept(int ext, u64 eptp, gpa_t gpa)
957{
958 struct {
959 u64 eptp, gpa;
960 } operand = {eptp, gpa};
961
4ecac3fd 962 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 963 /* CF==1 or ZF==1 --> rc = -1 */
964 "; ja 1f ; ud2 ; 1:\n"
965 : : "a" (&operand), "c" (ext) : "cc", "memory");
966}
967
26bb0981 968static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 969{
970 int i;
971
8b9cf98c 972 i = __find_msr_index(vmx, msr);
a75beee6 973 if (i >= 0)
a2fa3e9f 974 return &vmx->guest_msrs[i];
8b6d44c7 975 return NULL;
7725f0ba
AK		 976}
977
6aa8b732
AK		 978static void vmcs_clear(struct vmcs *vmcs)
979{
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
4ecac3fd 983 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 985 : "cc", "memory");
986 if (error)
987 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
988 vmcs, phys_addr);
989}
990
d462b819
NHE		 991static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
992{
993 vmcs_clear(loaded_vmcs->vmcs);
994 loaded_vmcs->cpu = -1;
995 loaded_vmcs->launched = 0;
996}
997
7725b894
DX		 998static void vmcs_load(struct vmcs *vmcs)
999{
1000 u64 phys_addr = __pa(vmcs);
1001 u8 error;
1002
1003 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1004 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1005 : "cc", "memory");
1006 if (error)
2844d849 1007 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1008 vmcs, phys_addr);
1009}
1010
8f536b76
ZY		 1011#ifdef CONFIG_KEXEC
1012/*
1013 * This bitmap is used to indicate whether the vmclear
1014 * operation is enabled on all cpus. All disabled by
1015 * default.
1016 */
1017static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1018
1019static inline void crash_enable_local_vmclear(int cpu)
1020{
1021 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1022}
1023
1024static inline void crash_disable_local_vmclear(int cpu)
1025{
1026 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027}
1028
1029static inline int crash_local_vmclear_enabled(int cpu)
1030{
1031 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032}
1033
1034static void crash_vmclear_local_loaded_vmcss(void)
1035{
1036 int cpu = raw_smp_processor_id();
1037 struct loaded_vmcs *v;
1038
1039 if (!crash_local_vmclear_enabled(cpu))
1040 return;
1041
1042 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1043 loaded_vmcss_on_cpu_link)
1044 vmcs_clear(v->vmcs);
1045}
1046#else
1047static inline void crash_enable_local_vmclear(int cpu) { }
1048static inline void crash_disable_local_vmclear(int cpu) { }
1049#endif /* CONFIG_KEXEC */
1050
d462b819 1051static void __loaded_vmcs_clear(void *arg)
6aa8b732 1052{
d462b819 1053 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1054 int cpu = raw_smp_processor_id();
6aa8b732 1055
d462b819
NHE		 1056 if (loaded_vmcs->cpu != cpu)
1057 return; /* vcpu migration can race with cpu offline */
1058 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1059 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1060 crash_disable_local_vmclear(cpu);
d462b819 1061 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1062
1063 /*
1064 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065 * is before setting loaded_vmcs->vcpu to -1 which is done in
1066 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067 * then adds the vmcs into percpu list before it is deleted.
1068 */
1069 smp_wmb();
1070
d462b819 1071 loaded_vmcs_init(loaded_vmcs);
8f536b76 1072 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1073}
1074
d462b819 1075static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1076{
e6c7d321
XG		 1077 int cpu = loaded_vmcs->cpu;
1078
1079 if (cpu != -1)
1080 smp_call_function_single(cpu,
1081 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1082}
1083
1760dd49 1084static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1085{
1086 if (vmx->vpid == 0)
1087 return;
1088
518c8aee
GJ		 1089 if (cpu_has_vmx_invvpid_single())
1090 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1091}
1092
b9d762fa
GJ		 1093static inline void vpid_sync_vcpu_global(void)
1094{
1095 if (cpu_has_vmx_invvpid_global())
1096 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1097}
1098
1099static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1100{
1101 if (cpu_has_vmx_invvpid_single())
1760dd49 1102 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1103 else
1104 vpid_sync_vcpu_global();
1105}
1106
1439442c
SY		 1107static inline void ept_sync_global(void)
1108{
1109 if (cpu_has_vmx_invept_global())
1110 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1111}
1112
1113static inline void ept_sync_context(u64 eptp)
1114{
089d034e 1115 if (enable_ept) {
1439442c
SY		 1116 if (cpu_has_vmx_invept_context())
1117 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1118 else
1119 ept_sync_global();
1120 }
1121}
1122
96304217 1123static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1124{
5e520e62 1125 unsigned long value;
6aa8b732 1126
5e520e62
AK		 1127 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1128 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1129 return value;
1130}
1131
96304217 1132static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1133{
1134 return vmcs_readl(field);
1135}
1136
96304217 1137static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1138{
1139 return vmcs_readl(field);
1140}
1141
96304217 1142static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1143{
05b3e0c2 1144#ifdef CONFIG_X86_64
6aa8b732
AK		 1145 return vmcs_readl(field);
1146#else
1147 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1148#endif
1149}
1150
e52de1b8
AK		 1151static noinline void vmwrite_error(unsigned long field, unsigned long value)
1152{
1153 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1154 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1155 dump_stack();
1156}
1157
6aa8b732
AK		 1158static void vmcs_writel(unsigned long field, unsigned long value)
1159{
1160 u8 error;
1161
4ecac3fd 1162 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1163 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1164 if (unlikely(error))
1165 vmwrite_error(field, value);
6aa8b732
AK		 1166}
1167
1168static void vmcs_write16(unsigned long field, u16 value)
1169{
1170 vmcs_writel(field, value);
1171}
1172
1173static void vmcs_write32(unsigned long field, u32 value)
1174{
1175 vmcs_writel(field, value);
1176}
1177
1178static void vmcs_write64(unsigned long field, u64 value)
1179{
6aa8b732 1180 vmcs_writel(field, value);
7682f2d0 1181#ifndef CONFIG_X86_64
6aa8b732
AK		 1182 asm volatile ("");
1183 vmcs_writel(field+1, value >> 32);
1184#endif
1185}
1186
2ab455cc
AL		 1187static void vmcs_clear_bits(unsigned long field, u32 mask)
1188{
1189 vmcs_writel(field, vmcs_readl(field) & ~mask);
1190}
1191
1192static void vmcs_set_bits(unsigned long field, u32 mask)
1193{
1194 vmcs_writel(field, vmcs_readl(field) | mask);
1195}
1196
2fb92db1
AK		 1197static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1198{
1199 vmx->segment_cache.bitmask = 0;
1200}
1201
1202static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1203 unsigned field)
1204{
1205 bool ret;
1206 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1207
1208 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1209 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1210 vmx->segment_cache.bitmask = 0;
1211 }
1212 ret = vmx->segment_cache.bitmask & mask;
1213 vmx->segment_cache.bitmask |= mask;
1214 return ret;
1215}
1216
1217static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u16 *p = &vmx->segment_cache.seg[seg].selector;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1222 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1223 return *p;
1224}
1225
1226static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 ulong *p = &vmx->segment_cache.seg[seg].base;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1231 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1232 return *p;
1233}
1234
1235static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1236{
1237 u32 *p = &vmx->segment_cache.seg[seg].limit;
1238
1239 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1240 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1241 return *p;
1242}
1243
1244static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1245{
1246 u32 *p = &vmx->segment_cache.seg[seg].ar;
1247
1248 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1249 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1250 return *p;
1251}
1252
abd3f2d6
AK		 1253static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1254{
1255 u32 eb;
1256
fd7373cc
JK		 1257 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1258 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1259 if ((vcpu->guest_debug &
1260 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1261 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1262 eb |= 1u << BP_VECTOR;
7ffd92c5 1263 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1264 eb = ~0;
089d034e 1265 if (enable_ept)
1439442c 1266 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1267 if (vcpu->fpu_active)
1268 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1269
1270 /* When we are running a nested L2 guest and L1 specified for it a
1271 * certain exception bitmap, we must trap the same exceptions and pass
1272 * them to L1. When running L2, we will only handle the exceptions
1273 * specified above if L1 did not want them.
1274 */
1275 if (is_guest_mode(vcpu))
1276 eb |= get_vmcs12(vcpu)->exception_bitmap;
1277
abd3f2d6
AK		 1278 vmcs_write32(EXCEPTION_BITMAP, eb);
1279}
1280
8bf00a52
GN		 1281static void clear_atomic_switch_msr_special(unsigned long entry,
1282 unsigned long exit)
1283{
1284 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1285 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1286}
1287
61d2ef2c
AK		 1288static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1289{
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
8bf00a52
GN		 1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER);
1298 return;
1299 }
1300 break;
1301 case MSR_CORE_PERF_GLOBAL_CTRL:
1302 if (cpu_has_load_perf_global_ctrl) {
1303 clear_atomic_switch_msr_special(
1304 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1305 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1306 return;
1307 }
1308 break;
110312c8
AK		 1309 }
1310
61d2ef2c
AK		 1311 for (i = 0; i < m->nr; ++i)
1312 if (m->guest[i].index == msr)
1313 break;
1314
1315 if (i == m->nr)
1316 return;
1317 --m->nr;
1318 m->guest[i] = m->guest[m->nr];
1319 m->host[i] = m->host[m->nr];
1320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1321 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1322}
1323
8bf00a52
GN		 1324static void add_atomic_switch_msr_special(unsigned long entry,
1325 unsigned long exit, unsigned long guest_val_vmcs,
1326 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1327{
1328 vmcs_write64(guest_val_vmcs, guest_val);
1329 vmcs_write64(host_val_vmcs, host_val);
1330 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1331 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1332}
1333
61d2ef2c
AK		 1334static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1335 u64 guest_val, u64 host_val)
1336{
1337 unsigned i;
1338 struct msr_autoload *m = &vmx->msr_autoload;
1339
8bf00a52
GN		 1340 switch (msr) {
1341 case MSR_EFER:
1342 if (cpu_has_load_ia32_efer) {
1343 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1344 VM_EXIT_LOAD_IA32_EFER,
1345 GUEST_IA32_EFER,
1346 HOST_IA32_EFER,
1347 guest_val, host_val);
1348 return;
1349 }
1350 break;
1351 case MSR_CORE_PERF_GLOBAL_CTRL:
1352 if (cpu_has_load_perf_global_ctrl) {
1353 add_atomic_switch_msr_special(
1354 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1356 GUEST_IA32_PERF_GLOBAL_CTRL,
1357 HOST_IA32_PERF_GLOBAL_CTRL,
1358 guest_val, host_val);
1359 return;
1360 }
1361 break;
110312c8
AK		 1362 }
1363
61d2ef2c
AK		 1364 for (i = 0; i < m->nr; ++i)
1365 if (m->guest[i].index == msr)
1366 break;
1367
e7fc6f93
GN		 1368 if (i == NR_AUTOLOAD_MSRS) {
1369 printk_once(KERN_WARNING"Not enough mst switch entries. "
1370 "Can't add msr %x\n", msr);
1371 return;
1372 } else if (i == m->nr) {
61d2ef2c
AK		 1373 ++m->nr;
1374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1376 }
1377
1378 m->guest[i].index = msr;
1379 m->guest[i].value = guest_val;
1380 m->host[i].index = msr;
1381 m->host[i].value = host_val;
1382}
1383
33ed6329
AK		 1384static void reload_tss(void)
1385{
33ed6329
AK		 1386 /*
1387 * VT restores TR but not its size. Useless.
1388 */
d359192f 1389 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1390 struct desc_struct *descs;
33ed6329 1391
d359192f 1392 descs = (void *)gdt->address;
33ed6329
AK		 1393 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1394 load_TR_desc();
33ed6329
AK		 1395}
1396
92c0d900 1397static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1398{
3a34a881 1399 u64 guest_efer;
51c6cf66
AK		 1400 u64 ignore_bits;
1401
f6801dff 1402 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1403
51c6cf66 1404 /*
0fa06071 1405 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1406 * outside long mode
1407 */
1408 ignore_bits = EFER_NX | EFER_SCE;
1409#ifdef CONFIG_X86_64
1410 ignore_bits |= EFER_LMA | EFER_LME;
1411 /* SCE is meaningful only in long mode on Intel */
1412 if (guest_efer & EFER_LMA)
1413 ignore_bits &= ~(u64)EFER_SCE;
1414#endif
51c6cf66
AK		 1415 guest_efer &= ~ignore_bits;
1416 guest_efer |= host_efer & ignore_bits;
26bb0981 1417 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1418 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1419
1420 clear_atomic_switch_msr(vmx, MSR_EFER);
1421 /* On ept, can't emulate nx, and must switch nx atomically */
1422 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1423 guest_efer = vmx->vcpu.arch.efer;
1424 if (!(guest_efer & EFER_LMA))
1425 guest_efer &= ~EFER_LME;
1426 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1427 return false;
1428 }
1429
26bb0981 1430 return true;
51c6cf66
AK		 1431}
1432
2d49ec72
GN		 1433static unsigned long segment_base(u16 selector)
1434{
d359192f 1435 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1436 struct desc_struct *d;
1437 unsigned long table_base;
1438 unsigned long v;
1439
1440 if (!(selector & ~3))
1441 return 0;
1442
d359192f 1443 table_base = gdt->address;
2d49ec72
GN		 1444
1445 if (selector & 4) { /* from ldt */
1446 u16 ldt_selector = kvm_read_ldt();
1447
1448 if (!(ldt_selector & ~3))
1449 return 0;
1450
1451 table_base = segment_base(ldt_selector);
1452 }
1453 d = (struct desc_struct *)(table_base + (selector & ~7));
1454 v = get_desc_base(d);
1455#ifdef CONFIG_X86_64
1456 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1457 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1458#endif
1459 return v;
1460}
1461
1462static inline unsigned long kvm_read_tr_base(void)
1463{
1464 u16 tr;
1465 asm("str %0" : "=g"(tr));
1466 return segment_base(tr);
1467}
1468
04d2cc77 1469static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1470{
04d2cc77 1471 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1472 int i;
04d2cc77 1473
a2fa3e9f 1474 if (vmx->host_state.loaded)
33ed6329
AK		 1475 return;
1476
a2fa3e9f 1477 vmx->host_state.loaded = 1;
33ed6329
AK		 1478 /*
1479 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1480 * allow segment selectors with cpl > 0 or ti == 1.
1481 */
d6e88aec 1482 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1483 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1484 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1485 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1486 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1487 vmx->host_state.fs_reload_needed = 0;
1488 } else {
33ed6329 1489 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1490 vmx->host_state.fs_reload_needed = 1;
33ed6329 1491 }
9581d442 1492 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1493 if (!(vmx->host_state.gs_sel & 7))
1494 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1495 else {
1496 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1497 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1498 }
1499
b2da15ac
AK		 1500#ifdef CONFIG_X86_64
1501 savesegment(ds, vmx->host_state.ds_sel);
1502 savesegment(es, vmx->host_state.es_sel);
1503#endif
1504
33ed6329
AK		 1505#ifdef CONFIG_X86_64
1506 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1507 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1508#else
a2fa3e9f
GH		 1509 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1510 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1511#endif
707c0874
AK		 1512
1513#ifdef CONFIG_X86_64
c8770e7b
AK		 1514 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1515 if (is_long_mode(&vmx->vcpu))
44ea2b17 1516 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1517#endif
26bb0981
AK		 1518 for (i = 0; i < vmx->save_nmsrs; ++i)
1519 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1520 vmx->guest_msrs[i].data,
1521 vmx->guest_msrs[i].mask);
33ed6329
AK		 1522}
1523
a9b21b62 1524static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1525{
a2fa3e9f 1526 if (!vmx->host_state.loaded)
33ed6329
AK		 1527 return;
1528
e1beb1d3 1529 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1530 vmx->host_state.loaded = 0;
c8770e7b
AK		 1531#ifdef CONFIG_X86_64
1532 if (is_long_mode(&vmx->vcpu))
1533 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1534#endif
152d3f2f 1535 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1536 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1537#ifdef CONFIG_X86_64
9581d442 1538 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1539#else
1540 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1541#endif
33ed6329 1542 }
0a77fe4c
AK		 1543 if (vmx->host_state.fs_reload_needed)
1544 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1545#ifdef CONFIG_X86_64
1546 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1547 loadsegment(ds, vmx->host_state.ds_sel);
1548 loadsegment(es, vmx->host_state.es_sel);
1549 }
b2da15ac 1550#endif
152d3f2f 1551 reload_tss();
44ea2b17 1552#ifdef CONFIG_X86_64
c8770e7b 1553 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1554#endif
b1a74bf8
SS		 1555 /*
1556 * If the FPU is not active (through the host task or
1557 * the guest vcpu), then restore the cr0.TS bit.
1558 */
1559 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1560 stts();
3444d7da 1561 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1562}
1563
a9b21b62
AK		 1564static void vmx_load_host_state(struct vcpu_vmx *vmx)
1565{
1566 preempt_disable();
1567 __vmx_load_host_state(vmx);
1568 preempt_enable();
1569}
1570
6aa8b732
AK		 1571/*
1572 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573 * vcpu mutex is already taken.
1574 */
15ad7146 1575static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1576{
a2fa3e9f 1577 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1578 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1579
4610c9cc
DX		 1580 if (!vmm_exclusive)
1581 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1582 else if (vmx->loaded_vmcs->cpu != cpu)
1583 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1584
d462b819
NHE		 1585 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1586 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1587 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1588 }
1589
d462b819 1590 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1591 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1592 unsigned long sysenter_esp;
1593
a8eeb04a 1594 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1595 local_irq_disable();
8f536b76 1596 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1597
1598 /*
1599 * Read loaded_vmcs->cpu should be before fetching
1600 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601 * See the comments in __loaded_vmcs_clear().
1602 */
1603 smp_rmb();
1604
d462b819
NHE		 1605 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1606 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1607 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1608 local_irq_enable();
1609
6aa8b732
AK		 1610 /*
1611 * Linux uses per-cpu TSS and GDT, so set these when switching
1612 * processors.
1613 */
d6e88aec 1614 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1615 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1616
1617 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1618 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1619 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1620 }
6aa8b732
AK		 1621}
1622
1623static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1624{
a9b21b62 1625 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1626 if (!vmm_exclusive) {
d462b819
NHE		 1627 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1628 vcpu->cpu = -1;
4610c9cc
DX		 1629 kvm_cpu_vmxoff();
1630 }
6aa8b732
AK		 1631}
1632
5fd86fcf
AK		 1633static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1634{
81231c69
AK		 1635 ulong cr0;
1636
5fd86fcf
AK		 1637 if (vcpu->fpu_active)
1638 return;
1639 vcpu->fpu_active = 1;
81231c69
AK		 1640 cr0 = vmcs_readl(GUEST_CR0);
1641 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1642 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1643 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1644 update_exception_bitmap(vcpu);
edcafe3c 1645 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1646 if (is_guest_mode(vcpu))
1647 vcpu->arch.cr0_guest_owned_bits &=
1648 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1649 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1650}
1651
edcafe3c
AK		 1652static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1653
fe3ef05c
NHE		 1654/*
1655 * Return the cr0 value that a nested guest would read. This is a combination
1656 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657 * its hypervisor (cr0_read_shadow).
1658 */
1659static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1660{
1661 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1662 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1663}
1664static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1665{
1666 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1667 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1668}
1669
5fd86fcf
AK		 1670static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1671{
36cf24e0
NHE		 1672 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673 * set this *before* calling this function.
1674 */
edcafe3c 1675 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1676 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1677 update_exception_bitmap(vcpu);
edcafe3c
AK		 1678 vcpu->arch.cr0_guest_owned_bits = 0;
1679 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1680 if (is_guest_mode(vcpu)) {
1681 /*
1682 * L1's specified read shadow might not contain the TS bit,
1683 * so now that we turned on shadowing of this bit, we need to
1684 * set this bit of the shadow. Like in nested_vmx_run we need
1685 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686 * up-to-date here because we just decached cr0.TS (and we'll
1687 * only update vmcs12->guest_cr0 on nested exit).
1688 */
1689 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1691 (vcpu->arch.cr0 & X86_CR0_TS);
1692 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1693 } else
1694 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1695}
1696
6aa8b732
AK		 1697static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1698{
78ac8b47 1699 unsigned long rflags, save_rflags;
345dcaa8 1700
6de12732
AK		 1701 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1702 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1703 rflags = vmcs_readl(GUEST_RFLAGS);
1704 if (to_vmx(vcpu)->rmode.vm86_active) {
1705 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1707 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1708 }
1709 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1710 }
6de12732 1711 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1712}
1713
1714static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1715{
6de12732
AK		 1716 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1717 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1718 if (to_vmx(vcpu)->rmode.vm86_active) {
1719 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1720 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1721 }
6aa8b732
AK		 1722 vmcs_writel(GUEST_RFLAGS, rflags);
1723}
1724
2809f5d2
GC		 1725static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1726{
1727 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1728 int ret = 0;
1729
1730 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1731 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1732 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1733 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1734
1735 return ret & mask;
1736}
1737
1738static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1739{
1740 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1741 u32 interruptibility = interruptibility_old;
1742
1743 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1744
48005f64 1745 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1746 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1747 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1748 interruptibility |= GUEST_INTR_STATE_STI;
1749
1750 if ((interruptibility != interruptibility_old))
1751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1752}
1753
6aa8b732
AK		 1754static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1755{
1756 unsigned long rip;
6aa8b732 1757
5fdbf976 1758 rip = kvm_rip_read(vcpu);
6aa8b732 1759 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1760 kvm_rip_write(vcpu, rip);
6aa8b732 1761
2809f5d2
GC		 1762 /* skipping an emulated instruction also counts */
1763 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1764}
1765
0b6ac343
NHE		 1766/*
1767 * KVM wants to inject page-faults which it got to the guest. This function
1768 * checks whether in a nested guest, we need to inject them to L1 or L2.
1769 * This function assumes it is called with the exit reason in vmcs02 being
1770 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1771 * is running).
1772 */
1773static int nested_pf_handled(struct kvm_vcpu *vcpu)
1774{
1775 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1776
1777 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1778 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1779 return 0;
1780
1781 nested_vmx_vmexit(vcpu);
1782 return 1;
1783}
1784
298101da 1785static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1786 bool has_error_code, u32 error_code,
1787 bool reinject)
298101da 1788{
77ab6db0 1789 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1790 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1791
0b6ac343
NHE		 1792 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1793 nested_pf_handled(vcpu))
1794 return;
1795
8ab2d2e2 1796 if (has_error_code) {
77ab6db0 1797 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1798 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1799 }
77ab6db0 1800
7ffd92c5 1801 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1802 int inc_eip = 0;
1803 if (kvm_exception_is_soft(nr))
1804 inc_eip = vcpu->arch.event_exit_inst_len;
1805 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1806 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1807 return;
1808 }
1809
66fd3f7f
GN		 1810 if (kvm_exception_is_soft(nr)) {
1811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1812 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1813 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1814 } else
1815 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1816
1817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1818}
1819
4e47c7a6
SY		 1820static bool vmx_rdtscp_supported(void)
1821{
1822 return cpu_has_vmx_rdtscp();
1823}
1824
ad756a16
MJ		 1825static bool vmx_invpcid_supported(void)
1826{
1827 return cpu_has_vmx_invpcid() && enable_ept;
1828}
1829
a75beee6
ED		 1830/*
1831 * Swap MSR entry in host/guest MSR entry array.
1832 */
8b9cf98c 1833static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1834{
26bb0981 1835 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1836
1837 tmp = vmx->guest_msrs[to];
1838 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1839 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1840}
1841
8d14695f
YZ		 1842static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1843{
1844 unsigned long *msr_bitmap;
1845
1846 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1847 if (is_long_mode(vcpu))
1848 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1849 else
1850 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1851 } else {
1852 if (is_long_mode(vcpu))
1853 msr_bitmap = vmx_msr_bitmap_longmode;
1854 else
1855 msr_bitmap = vmx_msr_bitmap_legacy;
1856 }
1857
1858 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1859}
1860
e38aea3e
AK		 1861/*
1862 * Set up the vmcs to automatically save and restore system
1863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1864 * mode, as fiddling with msrs is very expensive.
1865 */
8b9cf98c 1866static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1867{
26bb0981 1868 int save_nmsrs, index;
e38aea3e 1869
a75beee6
ED		 1870 save_nmsrs = 0;
1871#ifdef CONFIG_X86_64
8b9cf98c 1872 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1873 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1874 if (index >= 0)
8b9cf98c
RR		 1875 move_msr_up(vmx, index, save_nmsrs++);
1876 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1877 if (index >= 0)
8b9cf98c
RR		 1878 move_msr_up(vmx, index, save_nmsrs++);
1879 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1880 if (index >= 0)
8b9cf98c 1881 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1882 index = __find_msr_index(vmx, MSR_TSC_AUX);
1883 if (index >= 0 && vmx->rdtscp_enabled)
1884 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1885 /*
8c06585d 1886 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1887 * if efer.sce is enabled.
1888 */
8c06585d 1889 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1890 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1891 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1892 }
1893#endif
92c0d900
AK		 1894 index = __find_msr_index(vmx, MSR_EFER);
1895 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1896 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1897
26bb0981 1898 vmx->save_nmsrs = save_nmsrs;
5897297b 1899
8d14695f
YZ		 1900 if (cpu_has_vmx_msr_bitmap())
1901 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1902}
1903
6aa8b732
AK		 1904/*
1905 * reads and returns guest's timestamp counter "register"
1906 * guest_tsc = host_tsc + tsc_offset -- 21.3
1907 */
1908static u64 guest_read_tsc(void)
1909{
1910 u64 host_tsc, tsc_offset;
1911
1912 rdtscll(host_tsc);
1913 tsc_offset = vmcs_read64(TSC_OFFSET);
1914 return host_tsc + tsc_offset;
1915}
1916
d5c1785d
NHE		 1917/*
1918 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919 * counter, even if a nested guest (L2) is currently running.
1920 */
886b470c 1921u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1922{
886b470c 1923 u64 tsc_offset;
d5c1785d 1924
d5c1785d
NHE		 1925 tsc_offset = is_guest_mode(vcpu) ?
1926 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1927 vmcs_read64(TSC_OFFSET);
1928 return host_tsc + tsc_offset;
1929}
1930
4051b188 1931/*
cc578287
ZA		 1932 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1933 * software catchup for faster rates on slower CPUs.
4051b188 1934 */
cc578287 1935static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1936{
cc578287
ZA		 1937 if (!scale)
1938 return;
1939
1940 if (user_tsc_khz > tsc_khz) {
1941 vcpu->arch.tsc_catchup = 1;
1942 vcpu->arch.tsc_always_catchup = 1;
1943 } else
1944 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1945}
1946
ba904635
WA		 1947static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1948{
1949 return vmcs_read64(TSC_OFFSET);
1950}
1951
6aa8b732 1952/*
99e3e30a 1953 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1954 */
99e3e30a 1955static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1956{
27fc51b2 1957 if (is_guest_mode(vcpu)) {
7991825b 1958 /*
27fc51b2
NHE		 1959 * We're here if L1 chose not to trap WRMSR to TSC. According
1960 * to the spec, this should set L1's TSC; The offset that L1
1961 * set for L2 remains unchanged, and still needs to be added
1962 * to the newly set TSC to get L2's TSC.
7991825b 1963 */
27fc51b2
NHE		 1964 struct vmcs12 *vmcs12;
1965 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1966 /* recalculate vmcs02.TSC_OFFSET: */
1967 vmcs12 = get_vmcs12(vcpu);
1968 vmcs_write64(TSC_OFFSET, offset +
1969 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1970 vmcs12->tsc_offset : 0));
1971 } else {
1972 vmcs_write64(TSC_OFFSET, offset);
1973 }
6aa8b732
AK		 1974}
1975
f1e2b260 1976static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1977{
1978 u64 offset = vmcs_read64(TSC_OFFSET);
1979 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1980 if (is_guest_mode(vcpu)) {
1981 /* Even when running L2, the adjustment needs to apply to L1 */
1982 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1983 }
e48672fa
ZA		 1984}
1985
857e4099
JR		 1986static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1987{
1988 return target_tsc - native_read_tsc();
1989}
1990
801d3424
NHE		 1991static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1992{
1993 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1994 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1995}
1996
1997/*
1998 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000 * all guests if the "nested" module option is off, and can also be disabled
2001 * for a single guest by disabling its VMX cpuid bit.
2002 */
2003static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2004{
2005 return nested && guest_cpuid_has_vmx(vcpu);
2006}
2007
b87a51ae
NHE		 2008/*
2009 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010 * returned for the various VMX controls MSRs when nested VMX is enabled.
2011 * The same values should also be used to verify that vmcs12 control fields are
2012 * valid during nested entry from L1 to L2.
2013 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015 * bit in the high half is on if the corresponding bit in the control field
2016 * may be on. See also vmx_control_verify().
2017 * TODO: allow these variables to be modified (downgraded) by module options
2018 * or other means.
2019 */
2020static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2021static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2022static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2023static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2024static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2025static __init void nested_vmx_setup_ctls_msrs(void)
2026{
2027 /*
2028 * Note that as a general rule, the high half of the MSRs (bits in
2029 * the control fields which may be 1) should be initialized by the
2030 * intersection of the underlying hardware's MSR (i.e., features which
2031 * can be supported) and the list of features we want to expose -
2032 * because they are known to be properly supported in our code.
2033 * Also, usually, the low half of the MSRs (bits which must be 1) can
2034 * be set to 0, meaning that L1 may turn off any of these bits. The
2035 * reason is that if one of these bits is necessary, it will appear
2036 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037 * fields of vmcs01 and vmcs02, will turn these bits off - and
2038 * nested_vmx_exit_handled() will not pass related exits to L1.
2039 * These rules have exceptions below.
2040 */
2041
2042 /* pin-based controls */
2043 /*
2044 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2045 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2046 */
2047 nested_vmx_pinbased_ctls_low = 0x16 ;
2048 nested_vmx_pinbased_ctls_high = 0x16 |
2049 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2050 PIN_BASED_VIRTUAL_NMIS;
2051
33fb20c3
JK		 2052 /*
2053 * Exit controls
2054 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2055 * 17 must be 1.
2056 */
2057 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2058 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2059#ifdef CONFIG_X86_64
2060 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2061#else
2062 nested_vmx_exit_ctls_high = 0;
2063#endif
33fb20c3 2064 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2065
2066 /* entry controls */
2067 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2068 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2069 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2070 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2071 nested_vmx_entry_ctls_high &=
2072 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2073 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2074
2075 /* cpu-based controls */
2076 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2077 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2078 nested_vmx_procbased_ctls_low = 0;
2079 nested_vmx_procbased_ctls_high &=
2080 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2081 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2082 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2083 CPU_BASED_CR3_STORE_EXITING |
2084#ifdef CONFIG_X86_64
2085 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2086#endif
2087 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2088 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2089 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2090 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2091 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2092 /*
2093 * We can allow some features even when not supported by the
2094 * hardware. For example, L1 can specify an MSR bitmap - and we
2095 * can use it to avoid exits to L1 - even when L0 runs L2
2096 * without MSR bitmaps.
2097 */
2098 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2099
2100 /* secondary cpu-based controls */
2101 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2102 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2103 nested_vmx_secondary_ctls_low = 0;
2104 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2106 SECONDARY_EXEC_WBINVD_EXITING;
b87a51ae
NHE		 2107}
2108
2109static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2110{
2111 /*
2112 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2113 */
2114 return ((control & high) | low) == control;
2115}
2116
2117static inline u64 vmx_control_msr(u32 low, u32 high)
2118{
2119 return low | ((u64)high << 32);
2120}
2121
2122/*
2123 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2124 * also let it use VMX-specific MSRs.
2125 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2126 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2127 * like all other MSRs).
2128 */
2129static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2130{
2131 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2132 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2133 /*
2134 * According to the spec, processors which do not support VMX
2135 * should throw a #GP(0) when VMX capability MSRs are read.
2136 */
2137 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2138 return 1;
2139 }
2140
2141 switch (msr_index) {
2142 case MSR_IA32_FEATURE_CONTROL:
2143 *pdata = 0;
2144 break;
2145 case MSR_IA32_VMX_BASIC:
2146 /*
2147 * This MSR reports some information about VMX support. We
2148 * should return information about the VMX we emulate for the
2149 * guest, and the VMCS structure we give it - not about the
2150 * VMX support of the underlying hardware.
2151 */
2152 *pdata = VMCS12_REVISION |
2153 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2154 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2155 break;
2156 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2157 case MSR_IA32_VMX_PINBASED_CTLS:
2158 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2159 nested_vmx_pinbased_ctls_high);
2160 break;
2161 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2162 case MSR_IA32_VMX_PROCBASED_CTLS:
2163 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2164 nested_vmx_procbased_ctls_high);
2165 break;
2166 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2167 case MSR_IA32_VMX_EXIT_CTLS:
2168 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2169 nested_vmx_exit_ctls_high);
2170 break;
2171 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2172 case MSR_IA32_VMX_ENTRY_CTLS:
2173 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2174 nested_vmx_entry_ctls_high);
2175 break;
2176 case MSR_IA32_VMX_MISC:
2177 *pdata = 0;
2178 break;
2179 /*
2180 * These MSRs specify bits which the guest must keep fixed (on or off)
2181 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2182 * We picked the standard core2 setting.
2183 */
2184#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2185#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2186 case MSR_IA32_VMX_CR0_FIXED0:
2187 *pdata = VMXON_CR0_ALWAYSON;
2188 break;
2189 case MSR_IA32_VMX_CR0_FIXED1:
2190 *pdata = -1ULL;
2191 break;
2192 case MSR_IA32_VMX_CR4_FIXED0:
2193 *pdata = VMXON_CR4_ALWAYSON;
2194 break;
2195 case MSR_IA32_VMX_CR4_FIXED1:
2196 *pdata = -1ULL;
2197 break;
2198 case MSR_IA32_VMX_VMCS_ENUM:
2199 *pdata = 0x1f;
2200 break;
2201 case MSR_IA32_VMX_PROCBASED_CTLS2:
2202 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2203 nested_vmx_secondary_ctls_high);
2204 break;
2205 case MSR_IA32_VMX_EPT_VPID_CAP:
2206 /* Currently, no nested ept or nested vpid */
2207 *pdata = 0;
2208 break;
2209 default:
2210 return 0;
2211 }
2212
2213 return 1;
2214}
2215
2216static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2217{
2218 if (!nested_vmx_allowed(vcpu))
2219 return 0;
2220
2221 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2222 /* TODO: the right thing. */
2223 return 1;
2224 /*
2225 * No need to treat VMX capability MSRs specially: If we don't handle
2226 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2227 */
2228 return 0;
2229}
2230
6aa8b732
AK		 2231/*
2232 * Reads an msr value (of 'msr_index') into 'pdata'.
2233 * Returns 0 on success, non-0 otherwise.
2234 * Assumes vcpu_load() was already called.
2235 */
2236static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2237{
2238 u64 data;
26bb0981 2239 struct shared_msr_entry *msr;
6aa8b732
AK		 2240
2241 if (!pdata) {
2242 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2243 return -EINVAL;
2244 }
2245
2246 switch (msr_index) {
05b3e0c2 2247#ifdef CONFIG_X86_64
6aa8b732
AK		 2248 case MSR_FS_BASE:
2249 data = vmcs_readl(GUEST_FS_BASE);
2250 break;
2251 case MSR_GS_BASE:
2252 data = vmcs_readl(GUEST_GS_BASE);
2253 break;
44ea2b17
AK		 2254 case MSR_KERNEL_GS_BASE:
2255 vmx_load_host_state(to_vmx(vcpu));
2256 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2257 break;
26bb0981 2258#endif
6aa8b732 2259 case MSR_EFER:
3bab1f5d 2260 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2261 case MSR_IA32_TSC:
6aa8b732
AK		 2262 data = guest_read_tsc();
2263 break;
2264 case MSR_IA32_SYSENTER_CS:
2265 data = vmcs_read32(GUEST_SYSENTER_CS);
2266 break;
2267 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2268 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2269 break;
2270 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2271 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2272 break;
4e47c7a6
SY		 2273 case MSR_TSC_AUX:
2274 if (!to_vmx(vcpu)->rdtscp_enabled)
2275 return 1;
2276 /* Otherwise falls through */
6aa8b732 2277 default:
b87a51ae
NHE		 2278 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2279 return 0;
8b9cf98c 2280 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2281 if (msr) {
2282 data = msr->data;
2283 break;
6aa8b732 2284 }
3bab1f5d 2285 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2286 }
2287
2288 *pdata = data;
2289 return 0;
2290}
2291
2292/*
2293 * Writes msr value into into the appropriate "register".
2294 * Returns 0 on success, non-0 otherwise.
2295 * Assumes vcpu_load() was already called.
2296 */
8fe8ab46 2297static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2298{
a2fa3e9f 2299 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2300 struct shared_msr_entry *msr;
2cc51560 2301 int ret = 0;
8fe8ab46
WA		 2302 u32 msr_index = msr_info->index;
2303 u64 data = msr_info->data;
2cc51560 2304
6aa8b732 2305 switch (msr_index) {
3bab1f5d 2306 case MSR_EFER:
8fe8ab46 2307 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2308 break;
16175a79 2309#ifdef CONFIG_X86_64
6aa8b732 2310 case MSR_FS_BASE:
2fb92db1 2311 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2312 vmcs_writel(GUEST_FS_BASE, data);
2313 break;
2314 case MSR_GS_BASE:
2fb92db1 2315 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2316 vmcs_writel(GUEST_GS_BASE, data);
2317 break;
44ea2b17
AK		 2318 case MSR_KERNEL_GS_BASE:
2319 vmx_load_host_state(vmx);
2320 vmx->msr_guest_kernel_gs_base = data;
2321 break;
6aa8b732
AK		 2322#endif
2323 case MSR_IA32_SYSENTER_CS:
2324 vmcs_write32(GUEST_SYSENTER_CS, data);
2325 break;
2326 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2327 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2328 break;
2329 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2330 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2331 break;
af24a4e4 2332 case MSR_IA32_TSC:
8fe8ab46 2333 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2334 break;
468d472f
SY		 2335 case MSR_IA32_CR_PAT:
2336 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2337 vmcs_write64(GUEST_IA32_PAT, data);
2338 vcpu->arch.pat = data;
2339 break;
2340 }
8fe8ab46 2341 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2342 break;
ba904635
WA		 2343 case MSR_IA32_TSC_ADJUST:
2344 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2345 break;
2346 case MSR_TSC_AUX:
2347 if (!vmx->rdtscp_enabled)
2348 return 1;
2349 /* Check reserved bit, higher 32 bits should be zero */
2350 if ((data >> 32) != 0)
2351 return 1;
2352 /* Otherwise falls through */
6aa8b732 2353 default:
b87a51ae
NHE		 2354 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2355 break;
8b9cf98c 2356 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2357 if (msr) {
2358 msr->data = data;
2225fd56
AK		 2359 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2360 preempt_disable();
9ee73970
AK		 2361 kvm_set_shared_msr(msr->index, msr->data,
2362 msr->mask);
2225fd56
AK		 2363 preempt_enable();
2364 }
3bab1f5d 2365 break;
6aa8b732 2366 }
8fe8ab46 2367 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2368 }
2369
2cc51560 2370 return ret;
6aa8b732
AK		 2371}
2372
5fdbf976 2373static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2374{
5fdbf976
MT		 2375 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2376 switch (reg) {
2377 case VCPU_REGS_RSP:
2378 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2379 break;
2380 case VCPU_REGS_RIP:
2381 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2382 break;
6de4f3ad
AK		 2383 case VCPU_EXREG_PDPTR:
2384 if (enable_ept)
2385 ept_save_pdptrs(vcpu);
2386 break;
5fdbf976
MT		 2387 default:
2388 break;
2389 }
6aa8b732
AK		 2390}
2391
6aa8b732
AK		 2392static __init int cpu_has_kvm_support(void)
2393{
6210e37b 2394 return cpu_has_vmx();
6aa8b732
AK		 2395}
2396
2397static __init int vmx_disabled_by_bios(void)
2398{
2399 u64 msr;
2400
2401 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2402 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2403 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2404 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2405 && tboot_enabled())
2406 return 1;
23f3e991 2407 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2408 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2409 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2410 && !tboot_enabled()) {
2411 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2412 "activate TXT before enabling KVM\n");
cafd6659 2413 return 1;
f9335afe 2414 }
23f3e991
JC		 2415 /* launched w/o TXT and VMX disabled */
2416 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2417 && !tboot_enabled())
2418 return 1;
cafd6659
SW		 2419 }
2420
2421 return 0;
6aa8b732
AK		 2422}
2423
7725b894
DX		 2424static void kvm_cpu_vmxon(u64 addr)
2425{
2426 asm volatile (ASM_VMX_VMXON_RAX
2427 : : "a"(&addr), "m"(addr)
2428 : "memory", "cc");
2429}
2430
10474ae8 2431static int hardware_enable(void *garbage)
6aa8b732
AK		 2432{
2433 int cpu = raw_smp_processor_id();
2434 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2435 u64 old, test_bits;
6aa8b732 2436
10474ae8
AG		 2437 if (read_cr4() & X86_CR4_VMXE)
2438 return -EBUSY;
2439
d462b819 2440 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2441
2442 /*
2443 * Now we can enable the vmclear operation in kdump
2444 * since the loaded_vmcss_on_cpu list on this cpu
2445 * has been initialized.
2446 *
2447 * Though the cpu is not in VMX operation now, there
2448 * is no problem to enable the vmclear operation
2449 * for the loaded_vmcss_on_cpu list is empty!
2450 */
2451 crash_enable_local_vmclear(cpu);
2452
6aa8b732 2453 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2454
2455 test_bits = FEATURE_CONTROL_LOCKED;
2456 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2457 if (tboot_enabled())
2458 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2459
2460 if ((old & test_bits) != test_bits) {
6aa8b732 2461 /* enable and lock */
cafd6659
SW		 2462 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2463 }
66aee91a 2464 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2465
4610c9cc
DX		 2466 if (vmm_exclusive) {
2467 kvm_cpu_vmxon(phys_addr);
2468 ept_sync_global();
2469 }
10474ae8 2470
3444d7da
AK		 2471 store_gdt(&__get_cpu_var(host_gdt));
2472
10474ae8 2473 return 0;
6aa8b732
AK		 2474}
2475
d462b819 2476static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2477{
2478 int cpu = raw_smp_processor_id();
d462b819 2479 struct loaded_vmcs *v, *n;
543e4243 2480
d462b819
NHE		 2481 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2482 loaded_vmcss_on_cpu_link)
2483 __loaded_vmcs_clear(v);
543e4243
AK		 2484}
2485
710ff4a8
EH		 2486
2487/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2488 * tricks.
2489 */
2490static void kvm_cpu_vmxoff(void)
6aa8b732 2491{
4ecac3fd 2492 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2493}
2494
710ff4a8
EH		 2495static void hardware_disable(void *garbage)
2496{
4610c9cc 2497 if (vmm_exclusive) {
d462b819 2498 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2499 kvm_cpu_vmxoff();
2500 }
7725b894 2501 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2502}
2503
1c3d14fe 2504static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2505 u32 msr, u32 *result)
1c3d14fe
YS		 2506{
2507 u32 vmx_msr_low, vmx_msr_high;
2508 u32 ctl = ctl_min | ctl_opt;
2509
2510 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2511
2512 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2513 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2514
2515 /* Ensure minimum (required) set of control bits are supported. */
2516 if (ctl_min & ~ctl)
002c7f7c 2517 return -EIO;
1c3d14fe
YS		 2518
2519 *result = ctl;
2520 return 0;
2521}
2522
110312c8
AK		 2523static __init bool allow_1_setting(u32 msr, u32 ctl)
2524{
2525 u32 vmx_msr_low, vmx_msr_high;
2526
2527 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2528 return vmx_msr_high & ctl;
2529}
2530
002c7f7c 2531static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2532{
2533 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2534 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2535 u32 _pin_based_exec_control = 0;
2536 u32 _cpu_based_exec_control = 0;
f78e0e2e 2537 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2538 u32 _vmexit_control = 0;
2539 u32 _vmentry_control = 0;
2540
2541 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2542 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2543 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2544 &_pin_based_exec_control) < 0)
002c7f7c 2545 return -EIO;
1c3d14fe 2546
10166744 2547 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2548#ifdef CONFIG_X86_64
2549 CPU_BASED_CR8_LOAD_EXITING |
2550 CPU_BASED_CR8_STORE_EXITING |
2551#endif
d56f546d
SY		 2552 CPU_BASED_CR3_LOAD_EXITING |
2553 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2554 CPU_BASED_USE_IO_BITMAPS |
2555 CPU_BASED_MOV_DR_EXITING |
a7052897 2556 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2557 CPU_BASED_MWAIT_EXITING |
2558 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2559 CPU_BASED_INVLPG_EXITING |
2560 CPU_BASED_RDPMC_EXITING;
443381a8 2561
f78e0e2e 2562 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2563 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2564 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2565 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2566 &_cpu_based_exec_control) < 0)
002c7f7c 2567 return -EIO;
6e5d865c
YS		 2568#ifdef CONFIG_X86_64
2569 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2570 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2571 ~CPU_BASED_CR8_STORE_EXITING;
2572#endif
f78e0e2e 2573 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2574 min2 = 0;
2575 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2576 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2577 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2578 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2579 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2580 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2581 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2582 SECONDARY_EXEC_RDTSCP |
83d4c286 2583 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c
YZ		 2584 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2585 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
d56f546d
SY		 2586 if (adjust_vmx_controls(min2, opt2,
2587 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2588 &_cpu_based_2nd_exec_control) < 0)
2589 return -EIO;
2590 }
2591#ifndef CONFIG_X86_64
2592 if (!(_cpu_based_2nd_exec_control &
2593 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2594 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2595#endif
83d4c286
YZ		 2596
2597 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2598 _cpu_based_2nd_exec_control &= ~(
8d14695f 2599 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2600 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2601 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2602
d56f546d 2603 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2604 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2605 enabled */
5fff7d27
GN		 2606 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2607 CPU_BASED_CR3_STORE_EXITING |
2608 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2609 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2610 vmx_capability.ept, vmx_capability.vpid);
2611 }
1c3d14fe
YS		 2612
2613 min = 0;
2614#ifdef CONFIG_X86_64
2615 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2616#endif
468d472f 2617 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2618 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2619 &_vmexit_control) < 0)
002c7f7c 2620 return -EIO;
1c3d14fe 2621
468d472f
SY		 2622 min = 0;
2623 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2624 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2625 &_vmentry_control) < 0)
002c7f7c 2626 return -EIO;
6aa8b732 2627
c68876fd 2628 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2629
2630 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2631 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2632 return -EIO;
1c3d14fe
YS		 2633
2634#ifdef CONFIG_X86_64
2635 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2636 if (vmx_msr_high & (1u<<16))
002c7f7c 2637 return -EIO;
1c3d14fe
YS		 2638#endif
2639
2640 /* Require Write-Back (WB) memory type for VMCS accesses. */
2641 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2642 return -EIO;
1c3d14fe 2643
002c7f7c
YS		 2644 vmcs_conf->size = vmx_msr_high & 0x1fff;
2645 vmcs_conf->order = get_order(vmcs_config.size);
2646 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2647
002c7f7c
YS		 2648 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2649 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2650 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2651 vmcs_conf->vmexit_ctrl = _vmexit_control;
2652 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2653
110312c8
AK		 2654 cpu_has_load_ia32_efer =
2655 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2656 VM_ENTRY_LOAD_IA32_EFER)
2657 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2658 VM_EXIT_LOAD_IA32_EFER);
2659
8bf00a52
GN		 2660 cpu_has_load_perf_global_ctrl =
2661 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2662 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2663 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2664 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2665
2666 /*
2667 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2668 * but due to arrata below it can't be used. Workaround is to use
2669 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2670 *
2671 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2672 *
2673 * AAK155 (model 26)
2674 * AAP115 (model 30)
2675 * AAT100 (model 37)
2676 * BC86,AAY89,BD102 (model 44)
2677 * BA97 (model 46)
2678 *
2679 */
2680 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2681 switch (boot_cpu_data.x86_model) {
2682 case 26:
2683 case 30:
2684 case 37:
2685 case 44:
2686 case 46:
2687 cpu_has_load_perf_global_ctrl = false;
2688 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2689 "does not work properly. Using workaround\n");
2690 break;
2691 default:
2692 break;
2693 }
2694 }
2695
1c3d14fe 2696 return 0;
c68876fd 2697}
6aa8b732
AK		 2698
2699static struct vmcs *alloc_vmcs_cpu(int cpu)
2700{
2701 int node = cpu_to_node(cpu);
2702 struct page *pages;
2703 struct vmcs *vmcs;
2704
6484eb3e 2705 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2706 if (!pages)
2707 return NULL;
2708 vmcs = page_address(pages);
1c3d14fe
YS		 2709 memset(vmcs, 0, vmcs_config.size);
2710 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2711 return vmcs;
2712}
2713
2714static struct vmcs *alloc_vmcs(void)
2715{
d3b2c338 2716 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2717}
2718
2719static void free_vmcs(struct vmcs *vmcs)
2720{
1c3d14fe 2721 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2722}
2723
d462b819
NHE		 2724/*
2725 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2726 */
2727static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2728{
2729 if (!loaded_vmcs->vmcs)
2730 return;
2731 loaded_vmcs_clear(loaded_vmcs);
2732 free_vmcs(loaded_vmcs->vmcs);
2733 loaded_vmcs->vmcs = NULL;
2734}
2735
39959588 2736static void free_kvm_area(void)
6aa8b732
AK		 2737{
2738 int cpu;
2739
3230bb47 2740 for_each_possible_cpu(cpu) {
6aa8b732 2741 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2742 per_cpu(vmxarea, cpu) = NULL;
2743 }
6aa8b732
AK		 2744}
2745
6aa8b732
AK		 2746static __init int alloc_kvm_area(void)
2747{
2748 int cpu;
2749
3230bb47 2750 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2751 struct vmcs *vmcs;
2752
2753 vmcs = alloc_vmcs_cpu(cpu);
2754 if (!vmcs) {
2755 free_kvm_area();
2756 return -ENOMEM;
2757 }
2758
2759 per_cpu(vmxarea, cpu) = vmcs;
2760 }
2761 return 0;
2762}
2763
2764static __init int hardware_setup(void)
2765{
002c7f7c
YS		 2766 if (setup_vmcs_config(&vmcs_config) < 0)
2767 return -EIO;
50a37eb4
JR		 2768
2769 if (boot_cpu_has(X86_FEATURE_NX))
2770 kvm_enable_efer_bits(EFER_NX);
2771
93ba03c2
SY		 2772 if (!cpu_has_vmx_vpid())
2773 enable_vpid = 0;
2774
4bc9b982
SY		 2775 if (!cpu_has_vmx_ept() ||
2776 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2777 enable_ept = 0;
3a624e29 2778 enable_unrestricted_guest = 0;
83c3a331 2779 enable_ept_ad_bits = 0;
3a624e29
NK		 2780 }
2781
83c3a331
XH		 2782 if (!cpu_has_vmx_ept_ad_bits())
2783 enable_ept_ad_bits = 0;
2784
3a624e29
NK		 2785 if (!cpu_has_vmx_unrestricted_guest())
2786 enable_unrestricted_guest = 0;
93ba03c2
SY		 2787
2788 if (!cpu_has_vmx_flexpriority())
2789 flexpriority_enabled = 0;
2790
95ba8273
GN		 2791 if (!cpu_has_vmx_tpr_shadow())
2792 kvm_x86_ops->update_cr8_intercept = NULL;
2793
54dee993
MT		 2794 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2795 kvm_disable_largepages();
2796
4b8d54f9
ZE		 2797 if (!cpu_has_vmx_ple())
2798 ple_gap = 0;
2799
c7c9c56c
YZ		 2800 if (!cpu_has_vmx_apic_register_virt() ||
2801 !cpu_has_vmx_virtual_intr_delivery())
2802 enable_apicv_reg_vid = 0;
2803
2804 if (enable_apicv_reg_vid)
2805 kvm_x86_ops->update_cr8_intercept = NULL;
2806 else
2807 kvm_x86_ops->hwapic_irr_update = NULL;
83d4c286 2808
b87a51ae
NHE		 2809 if (nested)
2810 nested_vmx_setup_ctls_msrs();
2811
6aa8b732
AK		 2812 return alloc_kvm_area();
2813}
2814
2815static __exit void hardware_unsetup(void)
2816{
2817 free_kvm_area();
2818}
2819
14168786
GN		 2820static bool emulation_required(struct kvm_vcpu *vcpu)
2821{
2822 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2823}
2824
91b0aa2c 2825static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2826 struct kvm_segment *save)
6aa8b732 2827{
d99e4152
GN		 2828 if (!emulate_invalid_guest_state) {
2829 /*
2830 * CS and SS RPL should be equal during guest entry according
2831 * to VMX spec, but in reality it is not always so. Since vcpu
2832 * is in the middle of the transition from real mode to
2833 * protected mode it is safe to assume that RPL 0 is a good
2834 * default value.
2835 */
2836 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2837 save->selector &= ~SELECTOR_RPL_MASK;
2838 save->dpl = save->selector & SELECTOR_RPL_MASK;
2839 save->s = 1;
6aa8b732 2840 }
d99e4152 2841 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2842}
2843
2844static void enter_pmode(struct kvm_vcpu *vcpu)
2845{
2846 unsigned long flags;
a89a8fb9 2847 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2848
d99e4152
GN		 2849 /*
2850 * Update real mode segment cache. It may be not up-to-date if sement
2851 * register was written while vcpu was in a guest mode.
2852 */
2853 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2859
7ffd92c5 2860 vmx->rmode.vm86_active = 0;
6aa8b732 2861
2fb92db1
AK		 2862 vmx_segment_cache_clear(vmx);
2863
f5f7b2fe 2864 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2865
2866 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2867 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2868 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2869 vmcs_writel(GUEST_RFLAGS, flags);
2870
66aee91a
RR		 2871 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2872 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2873
2874 update_exception_bitmap(vcpu);
2875
91b0aa2c
GN		 2876 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2877 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2878 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2879 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2880 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2881 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 2882
2883 /* CPL is always 0 when CPU enters protected mode */
2884 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2885 vmx->cpl = 0;
6aa8b732
AK		 2886}
2887
d77c26fc 2888static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2889{
bfc6d222 2890 if (!kvm->arch.tss_addr) {
bc6678a3 2891 struct kvm_memslots *slots;
28a37544 2892 struct kvm_memory_slot *slot;
bc6678a3
MT		 2893 gfn_t base_gfn;
2894
90d83dc3 2895 slots = kvm_memslots(kvm);
28a37544
XG		 2896 slot = id_to_memslot(slots, 0);
2897 base_gfn = slot->base_gfn + slot->npages - 3;
2898
cbc94022
IE		 2899 return base_gfn << PAGE_SHIFT;
2900 }
bfc6d222 2901 return kvm->arch.tss_addr;
6aa8b732
AK		 2902}
2903
f5f7b2fe 2904static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2905{
772e0318 2906 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2907 struct kvm_segment var = *save;
2908
2909 var.dpl = 0x3;
2910 if (seg == VCPU_SREG_CS)
2911 var.type = 0x3;
2912
2913 if (!emulate_invalid_guest_state) {
2914 var.selector = var.base >> 4;
2915 var.base = var.base & 0xffff0;
2916 var.limit = 0xffff;
2917 var.g = 0;
2918 var.db = 0;
2919 var.present = 1;
2920 var.s = 1;
2921 var.l = 0;
2922 var.unusable = 0;
2923 var.type = 0x3;
2924 var.avl = 0;
2925 if (save->base & 0xf)
2926 printk_once(KERN_WARNING "kvm: segment base is not "
2927 "paragraph aligned when entering "
2928 "protected mode (seg=%d)", seg);
2929 }
6aa8b732 2930
d99e4152
GN		 2931 vmcs_write16(sf->selector, var.selector);
2932 vmcs_write32(sf->base, var.base);
2933 vmcs_write32(sf->limit, var.limit);
2934 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2935}
2936
2937static void enter_rmode(struct kvm_vcpu *vcpu)
2938{
2939 unsigned long flags;
a89a8fb9 2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2941
f5f7b2fe
AK		 2942 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2943 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2948 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2949
7ffd92c5 2950 vmx->rmode.vm86_active = 1;
6aa8b732 2951
776e58ea
GN		 2952 /*
2953 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2954 * vcpu. Call it here with phys address pointing 16M below 4G.
2955 */
2956 if (!vcpu->kvm->arch.tss_addr) {
2957 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2958 "called before entering vcpu\n");
2959 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2960 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2961 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2962 }
2963
2fb92db1
AK		 2964 vmx_segment_cache_clear(vmx);
2965
6aa8b732 2966 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2967 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2968 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2969
2970 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2971 vmx->rmode.save_rflags = flags;
6aa8b732 2972
053de044 2973 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2974
2975 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2976 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2977 update_exception_bitmap(vcpu);
2978
d99e4152
GN		 2979 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2980 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2981 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2982 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2983 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2984 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2985
8668a3c4 2986 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2987}
2988
401d10de
AS		 2989static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2990{
2991 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2992 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2993
2994 if (!msr)
2995 return;
401d10de 2996
44ea2b17
AK		 2997 /*
2998 * Force kernel_gs_base reloading before EFER changes, as control
2999 * of this msr depends on is_long_mode().
3000 */
3001 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3002 vcpu->arch.efer = efer;
401d10de
AS		 3003 if (efer & EFER_LMA) {
3004 vmcs_write32(VM_ENTRY_CONTROLS,
3005 vmcs_read32(VM_ENTRY_CONTROLS) |
3006 VM_ENTRY_IA32E_MODE);
3007 msr->data = efer;
3008 } else {
3009 vmcs_write32(VM_ENTRY_CONTROLS,
3010 vmcs_read32(VM_ENTRY_CONTROLS) &
3011 ~VM_ENTRY_IA32E_MODE);
3012
3013 msr->data = efer & ~EFER_LME;
3014 }
3015 setup_msrs(vmx);
3016}
3017
05b3e0c2 3018#ifdef CONFIG_X86_64
6aa8b732
AK		 3019
3020static void enter_lmode(struct kvm_vcpu *vcpu)
3021{
3022 u32 guest_tr_ar;
3023
2fb92db1
AK		 3024 vmx_segment_cache_clear(to_vmx(vcpu));
3025
6aa8b732
AK		 3026 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3027 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3028 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3029 __func__);
6aa8b732
AK		 3030 vmcs_write32(GUEST_TR_AR_BYTES,
3031 (guest_tr_ar & ~AR_TYPE_MASK)
3032 | AR_TYPE_BUSY_64_TSS);
3033 }
da38f438 3034 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3035}
3036
3037static void exit_lmode(struct kvm_vcpu *vcpu)
3038{
6aa8b732
AK		 3039 vmcs_write32(VM_ENTRY_CONTROLS,
3040 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3041 & ~VM_ENTRY_IA32E_MODE);
da38f438 3042 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3043}
3044
3045#endif
3046
2384d2b3
SY		 3047static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3048{
b9d762fa 3049 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3050 if (enable_ept) {
3051 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3052 return;
4e1096d2 3053 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3054 }
2384d2b3
SY		 3055}
3056
e8467fda
AK		 3057static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3058{
3059 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3060
3061 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3062 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3063}
3064
aff48baa
AK		 3065static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3066{
3067 if (enable_ept && is_paging(vcpu))
3068 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3069 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3070}
3071
25c4c276 3072static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3073{
fc78f519
AK		 3074 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3075
3076 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3077 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3078}
3079
1439442c
SY		 3080static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3081{
6de4f3ad
AK		 3082 if (!test_bit(VCPU_EXREG_PDPTR,
3083 (unsigned long *)&vcpu->arch.regs_dirty))
3084 return;
3085
1439442c 3086 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3087 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3088 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3089 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3090 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3091 }
3092}
3093
8f5d549f
AK		 3094static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3095{
3096 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3097 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3098 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3099 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3100 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3101 }
6de4f3ad
AK		 3102
3103 __set_bit(VCPU_EXREG_PDPTR,
3104 (unsigned long *)&vcpu->arch.regs_avail);
3105 __set_bit(VCPU_EXREG_PDPTR,
3106 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3107}
3108
5e1746d6 3109static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3110
3111static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3112 unsigned long cr0,
3113 struct kvm_vcpu *vcpu)
3114{
5233dd51
MT		 3115 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3116 vmx_decache_cr3(vcpu);
1439442c
SY		 3117 if (!(cr0 & X86_CR0_PG)) {
3118 /* From paging/starting to nonpaging */
3119 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3120 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3121 (CPU_BASED_CR3_LOAD_EXITING |
3122 CPU_BASED_CR3_STORE_EXITING));
3123 vcpu->arch.cr0 = cr0;
fc78f519 3124 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3125 } else if (!is_paging(vcpu)) {
3126 /* From nonpaging to paging */
3127 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3128 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3129 ~(CPU_BASED_CR3_LOAD_EXITING |
3130 CPU_BASED_CR3_STORE_EXITING));
3131 vcpu->arch.cr0 = cr0;
fc78f519 3132 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3133 }
95eb84a7
SY		 3134
3135 if (!(cr0 & X86_CR0_WP))
3136 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3137}
3138
6aa8b732
AK		 3139static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3140{
7ffd92c5 3141 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3142 unsigned long hw_cr0;
3143
5037878e 3144 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3145 if (enable_unrestricted_guest)
5037878e 3146 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3147 else {
5037878e 3148 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3149
218e763f
GN		 3150 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3151 enter_pmode(vcpu);
6aa8b732 3152
218e763f
GN		 3153 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3154 enter_rmode(vcpu);
3155 }
6aa8b732 3156
05b3e0c2 3157#ifdef CONFIG_X86_64
f6801dff 3158 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3159 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3160 enter_lmode(vcpu);
707d92fa 3161 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3162 exit_lmode(vcpu);
3163 }
3164#endif
3165
089d034e 3166 if (enable_ept)
1439442c
SY		 3167 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3168
02daab21 3169 if (!vcpu->fpu_active)
81231c69 3170 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3171
6aa8b732 3172 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3173 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3174 vcpu->arch.cr0 = cr0;
14168786
GN		 3175
3176 /* depends on vcpu->arch.cr0 to be set to a new value */
3177 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3178}
3179
1439442c
SY		 3180static u64 construct_eptp(unsigned long root_hpa)
3181{
3182 u64 eptp;
3183
3184 /* TODO write the value reading from MSR */
3185 eptp = VMX_EPT_DEFAULT_MT |
3186 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3187 if (enable_ept_ad_bits)
3188 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3189 eptp |= (root_hpa & PAGE_MASK);
3190
3191 return eptp;
3192}
3193
6aa8b732
AK		 3194static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3195{
1439442c
SY		 3196 unsigned long guest_cr3;
3197 u64 eptp;
3198
3199 guest_cr3 = cr3;
089d034e 3200 if (enable_ept) {
1439442c
SY		 3201 eptp = construct_eptp(cr3);
3202 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3203 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3204 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3205 ept_load_pdptrs(vcpu);
1439442c
SY		 3206 }
3207
2384d2b3 3208 vmx_flush_tlb(vcpu);
1439442c 3209 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3210}
3211
5e1746d6 3212static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3213{
7ffd92c5 3214 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3215 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3216
5e1746d6
NHE		 3217 if (cr4 & X86_CR4_VMXE) {
3218 /*
3219 * To use VMXON (and later other VMX instructions), a guest
3220 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3221 * So basically the check on whether to allow nested VMX
3222 * is here.
3223 */
3224 if (!nested_vmx_allowed(vcpu))
3225 return 1;
1a0d74e6
JK		 3226 }
3227 if (to_vmx(vcpu)->nested.vmxon &&
3228 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3229 return 1;
3230
ad312c7c 3231 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3232 if (enable_ept) {
3233 if (!is_paging(vcpu)) {
3234 hw_cr4 &= ~X86_CR4_PAE;
3235 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3236 /*
3237 * SMEP is disabled if CPU is in non-paging mode in
3238 * hardware. However KVM always uses paging mode to
3239 * emulate guest non-paging mode with TDP.
3240 * To emulate this behavior, SMEP needs to be manually
3241 * disabled when guest switches to non-paging mode.
3242 */
3243 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3244 } else if (!(cr4 & X86_CR4_PAE)) {
3245 hw_cr4 &= ~X86_CR4_PAE;
3246 }
3247 }
1439442c
SY		 3248
3249 vmcs_writel(CR4_READ_SHADOW, cr4);
3250 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3251 return 0;
6aa8b732
AK		 3252}
3253
6aa8b732
AK		 3254static void vmx_get_segment(struct kvm_vcpu *vcpu,
3255 struct kvm_segment *var, int seg)
3256{
a9179499 3257 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3258 u32 ar;
3259
c6ad1153 3260 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3261 *var = vmx->rmode.segs[seg];
a9179499 3262 if (seg == VCPU_SREG_TR
2fb92db1 3263 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3264 return;
1390a28b
AK		 3265 var->base = vmx_read_guest_seg_base(vmx, seg);
3266 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3267 return;
a9179499 3268 }
2fb92db1
AK		 3269 var->base = vmx_read_guest_seg_base(vmx, seg);
3270 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3271 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3272 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3273 var->type = ar & 15;
3274 var->s = (ar >> 4) & 1;
3275 var->dpl = (ar >> 5) & 3;
3276 var->present = (ar >> 7) & 1;
3277 var->avl = (ar >> 12) & 1;
3278 var->l = (ar >> 13) & 1;
3279 var->db = (ar >> 14) & 1;
3280 var->g = (ar >> 15) & 1;
3281 var->unusable = (ar >> 16) & 1;
3282}
3283
a9179499
AK		 3284static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3285{
a9179499
AK		 3286 struct kvm_segment s;
3287
3288 if (to_vmx(vcpu)->rmode.vm86_active) {
3289 vmx_get_segment(vcpu, &s, seg);
3290 return s.base;
3291 }
2fb92db1 3292 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3293}
3294
b09408d0 3295static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3296{
b09408d0
MT		 3297 struct vcpu_vmx *vmx = to_vmx(vcpu);
3298
3eeb3288 3299 if (!is_protmode(vcpu))
2e4d2653
IE		 3300 return 0;
3301
f4c63e5d
AK		 3302 if (!is_long_mode(vcpu)
3303 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3304 return 3;
3305
69c73028
AK		 3306 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3307 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3308 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3309 }
d881e6f6
AK		 3310
3311 return vmx->cpl;
69c73028
AK		 3312}
3313
3314
653e3108 3315static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3316{
6aa8b732
AK		 3317 u32 ar;
3318
f0495f9b 3319 if (var->unusable || !var->present)
6aa8b732
AK		 3320 ar = 1 << 16;
3321 else {
3322 ar = var->type & 15;
3323 ar |= (var->s & 1) << 4;
3324 ar |= (var->dpl & 3) << 5;
3325 ar |= (var->present & 1) << 7;
3326 ar |= (var->avl & 1) << 12;
3327 ar |= (var->l & 1) << 13;
3328 ar |= (var->db & 1) << 14;
3329 ar |= (var->g & 1) << 15;
3330 }
653e3108
AK		 3331
3332 return ar;
3333}
3334
3335static void vmx_set_segment(struct kvm_vcpu *vcpu,
3336 struct kvm_segment *var, int seg)
3337{
7ffd92c5 3338 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3339 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3340
2fb92db1 3341 vmx_segment_cache_clear(vmx);
2f143240
GN		 3342 if (seg == VCPU_SREG_CS)
3343 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3344
1ecd50a9
GN		 3345 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3346 vmx->rmode.segs[seg] = *var;
3347 if (seg == VCPU_SREG_TR)
3348 vmcs_write16(sf->selector, var->selector);
3349 else if (var->s)
3350 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3351 goto out;
653e3108 3352 }
1ecd50a9 3353
653e3108
AK		 3354 vmcs_writel(sf->base, var->base);
3355 vmcs_write32(sf->limit, var->limit);
3356 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3357
3358 /*
3359 * Fix the "Accessed" bit in AR field of segment registers for older
3360 * qemu binaries.
3361 * IA32 arch specifies that at the time of processor reset the
3362 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3363 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3364 * state vmexit when "unrestricted guest" mode is turned on.
3365 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3366 * tree. Newer qemu binaries with that qemu fix would not need this
3367 * kvm hack.
3368 */
3369 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3370 var->type |= 0x1; /* Accessed */
3a624e29 3371
f924d66d 3372 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3373
3374out:
14168786 3375 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3376}
3377
6aa8b732
AK		 3378static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3379{
2fb92db1 3380 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3381
3382 *db = (ar >> 14) & 1;
3383 *l = (ar >> 13) & 1;
3384}
3385
89a27f4d 3386static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3387{
89a27f4d
GN		 3388 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3389 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3390}
3391
89a27f4d 3392static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3393{
89a27f4d
GN		 3394 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3395 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3396}
3397
89a27f4d 3398static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3399{
89a27f4d
GN		 3400 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3401 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3402}
3403
89a27f4d 3404static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3405{
89a27f4d
GN		 3406 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3407 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3408}
3409
648dfaa7
MG		 3410static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3411{
3412 struct kvm_segment var;
3413 u32 ar;
3414
3415 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3416 var.dpl = 0x3;
0647f4aa
GN		 3417 if (seg == VCPU_SREG_CS)
3418 var.type = 0x3;
648dfaa7
MG		 3419 ar = vmx_segment_access_rights(&var);
3420
3421 if (var.base != (var.selector << 4))
3422 return false;
89efbed0 3423 if (var.limit != 0xffff)
648dfaa7 3424 return false;
07f42f5f 3425 if (ar != 0xf3)
648dfaa7
MG		 3426 return false;
3427
3428 return true;
3429}
3430
3431static bool code_segment_valid(struct kvm_vcpu *vcpu)
3432{
3433 struct kvm_segment cs;
3434 unsigned int cs_rpl;
3435
3436 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3437 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3438
1872a3f4
AK		 3439 if (cs.unusable)
3440 return false;
648dfaa7
MG		 3441 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3442 return false;
3443 if (!cs.s)
3444 return false;
1872a3f4 3445 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3446 if (cs.dpl > cs_rpl)
3447 return false;
1872a3f4 3448 } else {
648dfaa7
MG		 3449 if (cs.dpl != cs_rpl)
3450 return false;
3451 }
3452 if (!cs.present)
3453 return false;
3454
3455 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3456 return true;
3457}
3458
3459static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3460{
3461 struct kvm_segment ss;
3462 unsigned int ss_rpl;
3463
3464 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3465 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3466
1872a3f4
AK		 3467 if (ss.unusable)
3468 return true;
3469 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3470 return false;
3471 if (!ss.s)
3472 return false;
3473 if (ss.dpl != ss_rpl) /* DPL != RPL */
3474 return false;
3475 if (!ss.present)
3476 return false;
3477
3478 return true;
3479}
3480
3481static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3482{
3483 struct kvm_segment var;
3484 unsigned int rpl;
3485
3486 vmx_get_segment(vcpu, &var, seg);
3487 rpl = var.selector & SELECTOR_RPL_MASK;
3488
1872a3f4
AK		 3489 if (var.unusable)
3490 return true;
648dfaa7
MG		 3491 if (!var.s)
3492 return false;
3493 if (!var.present)
3494 return false;
3495 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3496 if (var.dpl < rpl) /* DPL < RPL */
3497 return false;
3498 }
3499
3500 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3501 * rights flags
3502 */
3503 return true;
3504}
3505
3506static bool tr_valid(struct kvm_vcpu *vcpu)
3507{
3508 struct kvm_segment tr;
3509
3510 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3511
1872a3f4
AK		 3512 if (tr.unusable)
3513 return false;
648dfaa7
MG		 3514 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3515 return false;
1872a3f4 3516 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3517 return false;
3518 if (!tr.present)
3519 return false;
3520
3521 return true;
3522}
3523
3524static bool ldtr_valid(struct kvm_vcpu *vcpu)
3525{
3526 struct kvm_segment ldtr;
3527
3528 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3529
1872a3f4
AK		 3530 if (ldtr.unusable)
3531 return true;
648dfaa7
MG		 3532 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3533 return false;
3534 if (ldtr.type != 2)
3535 return false;
3536 if (!ldtr.present)
3537 return false;
3538
3539 return true;
3540}
3541
3542static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3543{
3544 struct kvm_segment cs, ss;
3545
3546 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3547 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3548
3549 return ((cs.selector & SELECTOR_RPL_MASK) ==
3550 (ss.selector & SELECTOR_RPL_MASK));
3551}
3552
3553/*
3554 * Check if guest state is valid. Returns true if valid, false if
3555 * not.
3556 * We assume that registers are always usable
3557 */
3558static bool guest_state_valid(struct kvm_vcpu *vcpu)
3559{
c5e97c80
GN		 3560 if (enable_unrestricted_guest)
3561 return true;
3562
648dfaa7 3563 /* real mode guest state checks */
3eeb3288 3564 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3565 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3566 return false;
3567 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3568 return false;
3569 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3570 return false;
3571 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3572 return false;
3573 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3574 return false;
3575 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3576 return false;
3577 } else {
3578 /* protected mode guest state checks */
3579 if (!cs_ss_rpl_check(vcpu))
3580 return false;
3581 if (!code_segment_valid(vcpu))
3582 return false;
3583 if (!stack_segment_valid(vcpu))
3584 return false;
3585 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3586 return false;
3587 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3588 return false;
3589 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3590 return false;
3591 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3592 return false;
3593 if (!tr_valid(vcpu))
3594 return false;
3595 if (!ldtr_valid(vcpu))
3596 return false;
3597 }
3598 /* TODO:
3599 * - Add checks on RIP
3600 * - Add checks on RFLAGS
3601 */
3602
3603 return true;
3604}
3605
d77c26fc 3606static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3607{
40dcaa9f 3608 gfn_t fn;
195aefde 3609 u16 data = 0;
40dcaa9f 3610 int r, idx, ret = 0;
6aa8b732 3611
40dcaa9f
XG		 3612 idx = srcu_read_lock(&kvm->srcu);
3613 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3614 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3615 if (r < 0)
10589a46 3616 goto out;
195aefde 3617 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3618 r = kvm_write_guest_page(kvm, fn++, &data,
3619 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3620 if (r < 0)
10589a46 3621 goto out;
195aefde
IE		 3622 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3623 if (r < 0)
10589a46 3624 goto out;
195aefde
IE		 3625 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3626 if (r < 0)
10589a46 3627 goto out;
195aefde 3628 data = ~0;
10589a46
MT		 3629 r = kvm_write_guest_page(kvm, fn, &data,
3630 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3631 sizeof(u8));
195aefde 3632 if (r < 0)
10589a46
MT		 3633 goto out;
3634
3635 ret = 1;
3636out:
40dcaa9f 3637 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3638 return ret;
6aa8b732
AK		 3639}
3640
b7ebfb05
SY		 3641static int init_rmode_identity_map(struct kvm *kvm)
3642{
40dcaa9f 3643 int i, idx, r, ret;
b7ebfb05
SY		 3644 pfn_t identity_map_pfn;
3645 u32 tmp;
3646
089d034e 3647 if (!enable_ept)
b7ebfb05
SY		 3648 return 1;
3649 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3650 printk(KERN_ERR "EPT: identity-mapping pagetable "
3651 "haven't been allocated!\n");
3652 return 0;
3653 }
3654 if (likely(kvm->arch.ept_identity_pagetable_done))
3655 return 1;
3656 ret = 0;
b927a3ce 3657 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3658 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3659 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3660 if (r < 0)
3661 goto out;
3662 /* Set up identity-mapping pagetable for EPT in real mode */
3663 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3664 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3665 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3666 r = kvm_write_guest_page(kvm, identity_map_pfn,
3667 &tmp, i * sizeof(tmp), sizeof(tmp));
3668 if (r < 0)
3669 goto out;
3670 }
3671 kvm->arch.ept_identity_pagetable_done = true;
3672 ret = 1;
3673out:
40dcaa9f 3674 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3675 return ret;
3676}
3677
6aa8b732
AK		 3678static void seg_setup(int seg)
3679{
772e0318 3680 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3681 unsigned int ar;
6aa8b732
AK		 3682
3683 vmcs_write16(sf->selector, 0);
3684 vmcs_writel(sf->base, 0);
3685 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3686 ar = 0x93;
3687 if (seg == VCPU_SREG_CS)
3688 ar |= 0x08; /* code segment */
3a624e29
NK		 3689
3690 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3691}
3692
f78e0e2e
SY		 3693static int alloc_apic_access_page(struct kvm *kvm)
3694{
4484141a 3695 struct page *page;
f78e0e2e
SY		 3696 struct kvm_userspace_memory_region kvm_userspace_mem;
3697 int r = 0;
3698
79fac95e 3699 mutex_lock(&kvm->slots_lock);
bfc6d222 3700 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3701 goto out;
3702 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3703 kvm_userspace_mem.flags = 0;
3704 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3705 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3706 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3707 if (r)
3708 goto out;
72dc67a6 3709
4484141a
XG		 3710 page = gfn_to_page(kvm, 0xfee00);
3711 if (is_error_page(page)) {
3712 r = -EFAULT;
3713 goto out;
3714 }
3715
3716 kvm->arch.apic_access_page = page;
f78e0e2e 3717out:
79fac95e 3718 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3719 return r;
3720}
3721
b7ebfb05
SY		 3722static int alloc_identity_pagetable(struct kvm *kvm)
3723{
4484141a 3724 struct page *page;
b7ebfb05
SY		 3725 struct kvm_userspace_memory_region kvm_userspace_mem;
3726 int r = 0;
3727
79fac95e 3728 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3729 if (kvm->arch.ept_identity_pagetable)
3730 goto out;
3731 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3732 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3733 kvm_userspace_mem.guest_phys_addr =
3734 kvm->arch.ept_identity_map_addr;
b7ebfb05 3735 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3736 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3737 if (r)
3738 goto out;
3739
4484141a
XG		 3740 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3741 if (is_error_page(page)) {
3742 r = -EFAULT;
3743 goto out;
3744 }
3745
3746 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3747out:
79fac95e 3748 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3749 return r;
3750}
3751
2384d2b3
SY		 3752static void allocate_vpid(struct vcpu_vmx *vmx)
3753{
3754 int vpid;
3755
3756 vmx->vpid = 0;
919818ab 3757 if (!enable_vpid)
2384d2b3
SY		 3758 return;
3759 spin_lock(&vmx_vpid_lock);
3760 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3761 if (vpid < VMX_NR_VPIDS) {
3762 vmx->vpid = vpid;
3763 __set_bit(vpid, vmx_vpid_bitmap);
3764 }
3765 spin_unlock(&vmx_vpid_lock);
3766}
3767
cdbecfc3
LJ		 3768static void free_vpid(struct vcpu_vmx *vmx)
3769{
3770 if (!enable_vpid)
3771 return;
3772 spin_lock(&vmx_vpid_lock);
3773 if (vmx->vpid != 0)
3774 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3775 spin_unlock(&vmx_vpid_lock);
3776}
3777
8d14695f
YZ		 3778#define MSR_TYPE_R 1
3779#define MSR_TYPE_W 2
3780static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3781 u32 msr, int type)
25c5f225 3782{
3e7c73e9 3783 int f = sizeof(unsigned long);
25c5f225
SY		 3784
3785 if (!cpu_has_vmx_msr_bitmap())
3786 return;
3787
3788 /*
3789 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3790 * have the write-low and read-high bitmap offsets the wrong way round.
3791 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3792 */
25c5f225 3793 if (msr <= 0x1fff) {
8d14695f
YZ		 3794 if (type & MSR_TYPE_R)
3795 /* read-low */
3796 __clear_bit(msr, msr_bitmap + 0x000 / f);
3797
3798 if (type & MSR_TYPE_W)
3799 /* write-low */
3800 __clear_bit(msr, msr_bitmap + 0x800 / f);
3801
25c5f225
SY		 3802 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3803 msr &= 0x1fff;
8d14695f
YZ		 3804 if (type & MSR_TYPE_R)
3805 /* read-high */
3806 __clear_bit(msr, msr_bitmap + 0x400 / f);
3807
3808 if (type & MSR_TYPE_W)
3809 /* write-high */
3810 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3811
3812 }
3813}
3814
3815static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3816 u32 msr, int type)
3817{
3818 int f = sizeof(unsigned long);
3819
3820 if (!cpu_has_vmx_msr_bitmap())
3821 return;
3822
3823 /*
3824 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3825 * have the write-low and read-high bitmap offsets the wrong way round.
3826 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3827 */
3828 if (msr <= 0x1fff) {
3829 if (type & MSR_TYPE_R)
3830 /* read-low */
3831 __set_bit(msr, msr_bitmap + 0x000 / f);
3832
3833 if (type & MSR_TYPE_W)
3834 /* write-low */
3835 __set_bit(msr, msr_bitmap + 0x800 / f);
3836
3837 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3838 msr &= 0x1fff;
3839 if (type & MSR_TYPE_R)
3840 /* read-high */
3841 __set_bit(msr, msr_bitmap + 0x400 / f);
3842
3843 if (type & MSR_TYPE_W)
3844 /* write-high */
3845 __set_bit(msr, msr_bitmap + 0xc00 / f);
3846
25c5f225 3847 }
25c5f225
SY		 3848}
3849
5897297b
AK		 3850static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3851{
3852 if (!longmode_only)
8d14695f
YZ		 3853 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3854 msr, MSR_TYPE_R | MSR_TYPE_W);
3855 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3856 msr, MSR_TYPE_R | MSR_TYPE_W);
3857}
3858
3859static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3860{
3861 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3862 msr, MSR_TYPE_R);
3863 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3864 msr, MSR_TYPE_R);
3865}
3866
3867static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3868{
3869 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3870 msr, MSR_TYPE_R);
3871 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3872 msr, MSR_TYPE_R);
3873}
3874
3875static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3876{
3877 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3878 msr, MSR_TYPE_W);
3879 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3880 msr, MSR_TYPE_W);
5897297b
AK		 3881}
3882
a3a8ff8e
NHE		 3883/*
3884 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3885 * will not change in the lifetime of the guest.
3886 * Note that host-state that does change is set elsewhere. E.g., host-state
3887 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3888 */
3889static void vmx_set_constant_host_state(void)
3890{
3891 u32 low32, high32;
3892 unsigned long tmpl;
3893 struct desc_ptr dt;
3894
b1a74bf8 3895 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3896 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3897 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3898
3899 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3900#ifdef CONFIG_X86_64
3901 /*
3902 * Load null selectors, so we can avoid reloading them in
3903 * __vmx_load_host_state(), in case userspace uses the null selectors
3904 * too (the expected case).
3905 */
3906 vmcs_write16(HOST_DS_SELECTOR, 0);
3907 vmcs_write16(HOST_ES_SELECTOR, 0);
3908#else
a3a8ff8e
NHE		 3909 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3910 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3911#endif
a3a8ff8e
NHE		 3912 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3913 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3914
3915 native_store_idt(&dt);
3916 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3917
83287ea4 3918 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3919
3920 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3921 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3922 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3923 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3924
3925 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3926 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3927 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3928 }
3929}
3930
bf8179a0
NHE		 3931static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3932{
3933 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3934 if (enable_ept)
3935 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3936 if (is_guest_mode(&vmx->vcpu))
3937 vmx->vcpu.arch.cr4_guest_owned_bits &=
3938 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3939 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3940}
3941
3942static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3943{
3944 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3945 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3946 exec_control &= ~CPU_BASED_TPR_SHADOW;
3947#ifdef CONFIG_X86_64
3948 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3949 CPU_BASED_CR8_LOAD_EXITING;
3950#endif
3951 }
3952 if (!enable_ept)
3953 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3954 CPU_BASED_CR3_LOAD_EXITING |
3955 CPU_BASED_INVLPG_EXITING;
3956 return exec_control;
3957}
3958
c7c9c56c
YZ		 3959static int vmx_vm_has_apicv(struct kvm *kvm)
3960{
3961 return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3962}
3963
bf8179a0
NHE		 3964static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3965{
3966 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3967 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3968 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3969 if (vmx->vpid == 0)
3970 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3971 if (!enable_ept) {
3972 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3973 enable_unrestricted_guest = 0;
ad756a16
MJ		 3974 /* Enable INVPCID for non-ept guests may cause performance regression. */
3975 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3976 }
3977 if (!enable_unrestricted_guest)
3978 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3979 if (!ple_gap)
3980 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 3981 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3982 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3983 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3984 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
bf8179a0
NHE		 3985 return exec_control;
3986}
3987
ce88decf
XG		 3988static void ept_set_mmio_spte_mask(void)
3989{
3990 /*
3991 * EPT Misconfigurations can be generated if the value of bits 2:0
3992 * of an EPT paging-structure entry is 110b (write/execute).
3993 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3994 * spte.
3995 */
3996 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3997}
3998
6aa8b732
AK		 3999/*
4000 * Sets up the vmcs for emulated real mode.
4001 */
8b9cf98c 4002static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4003{
2e4ce7f5 4004#ifdef CONFIG_X86_64
6aa8b732 4005 unsigned long a;
2e4ce7f5 4006#endif
6aa8b732 4007 int i;
6aa8b732 4008
6aa8b732 4009 /* I/O */
3e7c73e9
AK		 4010 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4011 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4012
25c5f225 4013 if (cpu_has_vmx_msr_bitmap())
5897297b 4014 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4015
6aa8b732
AK		 4016 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4017
6aa8b732 4018 /* Control */
1c3d14fe
YS		 4019 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4020 vmcs_config.pin_based_exec_ctrl);
6e5d865c 4021
bf8179a0 4022 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4023
83ff3b9d 4024 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4025 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4026 vmx_secondary_exec_control(vmx));
83ff3b9d 4027 }
f78e0e2e 4028
c7c9c56c
YZ		 4029 if (enable_apicv_reg_vid) {
4030 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4031 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4032 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4033 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4034
4035 vmcs_write16(GUEST_INTR_STATUS, 0);
4036 }
4037
4b8d54f9
ZE		 4038 if (ple_gap) {
4039 vmcs_write32(PLE_GAP, ple_gap);
4040 vmcs_write32(PLE_WINDOW, ple_window);
4041 }
4042
c3707958
XG		 4043 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4044 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4045 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4046
9581d442
AK		 4047 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4048 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 4049 vmx_set_constant_host_state();
05b3e0c2 4050#ifdef CONFIG_X86_64
6aa8b732
AK		 4051 rdmsrl(MSR_FS_BASE, a);
4052 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4053 rdmsrl(MSR_GS_BASE, a);
4054 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4055#else
4056 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4057 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4058#endif
4059
2cc51560
ED		 4060 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4061 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4062 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4063 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4064 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4065
468d472f 4066 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4067 u32 msr_low, msr_high;
4068 u64 host_pat;
468d472f
SY		 4069 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4070 host_pat = msr_low | ((u64) msr_high << 32);
4071 /* Write the default value follow host pat */
4072 vmcs_write64(GUEST_IA32_PAT, host_pat);
4073 /* Keep arch.pat sync with GUEST_IA32_PAT */
4074 vmx->vcpu.arch.pat = host_pat;
4075 }
4076
6aa8b732
AK		 4077 for (i = 0; i < NR_VMX_MSR; ++i) {
4078 u32 index = vmx_msr_index[i];
4079 u32 data_low, data_high;
a2fa3e9f 4080 int j = vmx->nmsrs;
6aa8b732
AK		 4081
4082 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4083 continue;
432bd6cb
AK		 4084 if (wrmsr_safe(index, data_low, data_high) < 0)
4085 continue;
26bb0981
AK		 4086 vmx->guest_msrs[j].index = i;
4087 vmx->guest_msrs[j].data = 0;
d5696725 4088 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4089 ++vmx->nmsrs;
6aa8b732 4090 }
6aa8b732 4091
1c3d14fe 4092 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4093
4094 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4095 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4096
e00c8cf2 4097 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4098 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4099
4100 return 0;
4101}
4102
57f252f2 4103static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4104{
4105 struct vcpu_vmx *vmx = to_vmx(vcpu);
4106 u64 msr;
e00c8cf2 4107
7ffd92c5 4108 vmx->rmode.vm86_active = 0;
e00c8cf2 4109
3b86cd99
JK		 4110 vmx->soft_vnmi_blocked = 0;
4111
ad312c7c 4112 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4113 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4114 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4115 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4116 msr |= MSR_IA32_APICBASE_BSP;
4117 kvm_set_apic_base(&vmx->vcpu, msr);
4118
2fb92db1
AK		 4119 vmx_segment_cache_clear(vmx);
4120
5706be0d 4121 seg_setup(VCPU_SREG_CS);
d54d07b2 4122 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2 4123 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
d54d07b2 4124 else {
ad312c7c
ZX		 4125 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4126 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 4127 }
e00c8cf2
AK		 4128
4129 seg_setup(VCPU_SREG_DS);
4130 seg_setup(VCPU_SREG_ES);
4131 seg_setup(VCPU_SREG_FS);
4132 seg_setup(VCPU_SREG_GS);
4133 seg_setup(VCPU_SREG_SS);
4134
4135 vmcs_write16(GUEST_TR_SELECTOR, 0);
4136 vmcs_writel(GUEST_TR_BASE, 0);
4137 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4138 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4139
4140 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4141 vmcs_writel(GUEST_LDTR_BASE, 0);
4142 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4143 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4144
4145 vmcs_write32(GUEST_SYSENTER_CS, 0);
4146 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4147 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4148
4149 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 4150 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 4151 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4152 else
5fdbf976 4153 kvm_rip_write(vcpu, 0);
e00c8cf2 4154
e00c8cf2
AK		 4155 vmcs_writel(GUEST_GDTR_BASE, 0);
4156 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4157
4158 vmcs_writel(GUEST_IDTR_BASE, 0);
4159 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4160
443381a8 4161 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4162 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4163 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4164
e00c8cf2
AK		 4165 /* Special registers */
4166 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4167
4168 setup_msrs(vmx);
4169
6aa8b732
AK		 4170 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4171
f78e0e2e
SY		 4172 if (cpu_has_vmx_tpr_shadow()) {
4173 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4174 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4175 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4176 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4177 vmcs_write32(TPR_THRESHOLD, 0);
4178 }
4179
4180 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4181 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4182 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4183
2384d2b3
SY		 4184 if (vmx->vpid != 0)
4185 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4186
fa40052c 4187 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4188 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4189 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4190 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4191 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4192 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4193 vmx_fpu_activate(&vmx->vcpu);
4194 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4195
b9d762fa 4196 vpid_sync_context(vmx);
6aa8b732
AK		 4197}
4198
b6f1250e
NHE		 4199/*
4200 * In nested virtualization, check if L1 asked to exit on external interrupts.
4201 * For most existing hypervisors, this will always return true.
4202 */
4203static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4204{
4205 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4206 PIN_BASED_EXT_INTR_MASK;
4207}
4208
3b86cd99
JK		 4209static void enable_irq_window(struct kvm_vcpu *vcpu)
4210{
4211 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4212 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4213 /*
4214 * We get here if vmx_interrupt_allowed() said we can't
4215 * inject to L1 now because L2 must run. Ask L2 to exit
4216 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4217 */
d6185f20 4218 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4219 return;
d6185f20 4220 }
3b86cd99
JK		 4221
4222 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4223 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4224 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4225}
4226
4227static void enable_nmi_window(struct kvm_vcpu *vcpu)
4228{
4229 u32 cpu_based_vm_exec_control;
4230
4231 if (!cpu_has_virtual_nmis()) {
4232 enable_irq_window(vcpu);
4233 return;
4234 }
4235
30bd0c4c
AK		 4236 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4237 enable_irq_window(vcpu);
4238 return;
4239 }
3b86cd99
JK		 4240 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4241 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4242 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4243}
4244
66fd3f7f 4245static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4246{
9c8cba37 4247 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4248 uint32_t intr;
4249 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4250
229456fc 4251 trace_kvm_inj_virq(irq);
2714d1d3 4252
fa89a817 4253 ++vcpu->stat.irq_injections;
7ffd92c5 4254 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4255 int inc_eip = 0;
4256 if (vcpu->arch.interrupt.soft)
4257 inc_eip = vcpu->arch.event_exit_inst_len;
4258 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4259 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4260 return;
4261 }
66fd3f7f
GN		 4262 intr = irq | INTR_INFO_VALID_MASK;
4263 if (vcpu->arch.interrupt.soft) {
4264 intr |= INTR_TYPE_SOFT_INTR;
4265 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4266 vmx->vcpu.arch.event_exit_inst_len);
4267 } else
4268 intr |= INTR_TYPE_EXT_INTR;
4269 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4270}
4271
f08864b4
SY		 4272static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4273{
66a5a347
JK		 4274 struct vcpu_vmx *vmx = to_vmx(vcpu);
4275
0b6ac343
NHE		 4276 if (is_guest_mode(vcpu))
4277 return;
4278
3b86cd99
JK		 4279 if (!cpu_has_virtual_nmis()) {
4280 /*
4281 * Tracking the NMI-blocked state in software is built upon
4282 * finding the next open IRQ window. This, in turn, depends on
4283 * well-behaving guests: They have to keep IRQs disabled at
4284 * least as long as the NMI handler runs. Otherwise we may
4285 * cause NMI nesting, maybe breaking the guest. But as this is
4286 * highly unlikely, we can live with the residual risk.
4287 */
4288 vmx->soft_vnmi_blocked = 1;
4289 vmx->vnmi_blocked_time = 0;
4290 }
4291
487b391d 4292 ++vcpu->stat.nmi_injections;
9d58b931 4293 vmx->nmi_known_unmasked = false;
7ffd92c5 4294 if (vmx->rmode.vm86_active) {
71f9833b 4295 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4296 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4297 return;
4298 }
f08864b4
SY		 4299 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4300 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4301}
4302
c4282df9 4303static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4304{
3b86cd99 4305 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4306 return 0;
33f089ca 4307
c4282df9 4308 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4309 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4310 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4311}
4312
3cfc3092
JK		 4313static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4314{
4315 if (!cpu_has_virtual_nmis())
4316 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4317 if (to_vmx(vcpu)->nmi_known_unmasked)
4318 return false;
c332c83a 4319 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4320}
4321
4322static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4323{
4324 struct vcpu_vmx *vmx = to_vmx(vcpu);
4325
4326 if (!cpu_has_virtual_nmis()) {
4327 if (vmx->soft_vnmi_blocked != masked) {
4328 vmx->soft_vnmi_blocked = masked;
4329 vmx->vnmi_blocked_time = 0;
4330 }
4331 } else {
9d58b931 4332 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4333 if (masked)
4334 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4335 GUEST_INTR_STATE_NMI);
4336 else
4337 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4338 GUEST_INTR_STATE_NMI);
4339 }
4340}
4341
78646121
GN		 4342static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4343{
b6f1250e 4344 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4345 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4346 if (to_vmx(vcpu)->nested.nested_run_pending ||
4347 (vmcs12->idt_vectoring_info_field &
4348 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4349 return 0;
4350 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4351 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4352 vmcs12->vm_exit_intr_info = 0;
4353 /* fall through to normal code, but now in L1, not L2 */
4354 }
4355
c4282df9
GN		 4356 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4357 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4358 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4359}
4360
cbc94022
IE		 4361static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4362{
4363 int ret;
4364 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4365 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4366 .guest_phys_addr = addr,
4367 .memory_size = PAGE_SIZE * 3,
4368 .flags = 0,
4369 };
4370
47ae31e2 4371 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4372 if (ret)
4373 return ret;
bfc6d222 4374 kvm->arch.tss_addr = addr;
93ea5388
GN		 4375 if (!init_rmode_tss(kvm))
4376 return -ENOMEM;
4377
cbc94022
IE		 4378 return 0;
4379}
4380
0ca1b4f4 4381static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4382{
77ab6db0 4383 switch (vec) {
77ab6db0 4384 case BP_VECTOR:
c573cd22
JK		 4385 /*
4386 * Update instruction length as we may reinject the exception
4387 * from user space while in guest debugging mode.
4388 */
4389 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4390 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4391 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4392 return false;
4393 /* fall through */
4394 case DB_VECTOR:
4395 if (vcpu->guest_debug &
4396 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4397 return false;
d0bfb940
JK		 4398 /* fall through */
4399 case DE_VECTOR:
77ab6db0
JK		 4400 case OF_VECTOR:
4401 case BR_VECTOR:
4402 case UD_VECTOR:
4403 case DF_VECTOR:
4404 case SS_VECTOR:
4405 case GP_VECTOR:
4406 case MF_VECTOR:
0ca1b4f4
GN		 4407 return true;
4408 break;
77ab6db0 4409 }
0ca1b4f4
GN		 4410 return false;
4411}
4412
4413static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4414 int vec, u32 err_code)
4415{
4416 /*
4417 * Instruction with address size override prefix opcode 0x67
4418 * Cause the #SS fault with 0 error code in VM86 mode.
4419 */
4420 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4421 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4422 if (vcpu->arch.halt_request) {
4423 vcpu->arch.halt_request = 0;
4424 return kvm_emulate_halt(vcpu);
4425 }
4426 return 1;
4427 }
4428 return 0;
4429 }
4430
4431 /*
4432 * Forward all other exceptions that are valid in real mode.
4433 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4434 * the required debugging infrastructure rework.
4435 */
4436 kvm_queue_exception(vcpu, vec);
4437 return 1;
6aa8b732
AK		 4438}
4439
a0861c02
AK		 4440/*
4441 * Trigger machine check on the host. We assume all the MSRs are already set up
4442 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4443 * We pass a fake environment to the machine check handler because we want
4444 * the guest to be always treated like user space, no matter what context
4445 * it used internally.
4446 */
4447static void kvm_machine_check(void)
4448{
4449#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4450 struct pt_regs regs = {
4451 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4452 .flags = X86_EFLAGS_IF,
4453 };
4454
4455 do_machine_check(&regs, 0);
4456#endif
4457}
4458
851ba692 4459static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4460{
4461 /* already handled by vcpu_run */
4462 return 1;
4463}
4464
851ba692 4465static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4466{
1155f76a 4467 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4468 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4469 u32 intr_info, ex_no, error_code;
42dbaa5a 4470 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4471 u32 vect_info;
4472 enum emulation_result er;
4473
1155f76a 4474 vect_info = vmx->idt_vectoring_info;
88786475 4475 intr_info = vmx->exit_intr_info;
6aa8b732 4476
a0861c02 4477 if (is_machine_check(intr_info))
851ba692 4478 return handle_machine_check(vcpu);
a0861c02 4479
e4a41889 4480 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4481 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4482
4483 if (is_no_device(intr_info)) {
5fd86fcf 4484 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4485 return 1;
4486 }
4487
7aa81cc0 4488 if (is_invalid_opcode(intr_info)) {
51d8b661 4489 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4490 if (er != EMULATE_DONE)
7ee5d940 4491 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4492 return 1;
4493 }
4494
6aa8b732 4495 error_code = 0;
2e11384c 4496 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4497 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4498
4499 /*
4500 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4501 * MMIO, it is better to report an internal error.
4502 * See the comments in vmx_handle_exit.
4503 */
4504 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4505 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4506 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4507 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4508 vcpu->run->internal.ndata = 2;
4509 vcpu->run->internal.data[0] = vect_info;
4510 vcpu->run->internal.data[1] = intr_info;
4511 return 0;
4512 }
4513
6aa8b732 4514 if (is_page_fault(intr_info)) {
1439442c 4515 /* EPT won't cause page fault directly */
cf3ace79 4516 BUG_ON(enable_ept);
6aa8b732 4517 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4518 trace_kvm_page_fault(cr2, error_code);
4519
3298b75c 4520 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4521 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4522 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4523 }
4524
d0bfb940 4525 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4526
4527 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4528 return handle_rmode_exception(vcpu, ex_no, error_code);
4529
42dbaa5a
JK		 4530 switch (ex_no) {
4531 case DB_VECTOR:
4532 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4533 if (!(vcpu->guest_debug &
4534 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4535 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4536 kvm_queue_exception(vcpu, DB_VECTOR);
4537 return 1;
4538 }
4539 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4540 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4541 /* fall through */
4542 case BP_VECTOR:
c573cd22
JK		 4543 /*
4544 * Update instruction length as we may reinject #BP from
4545 * user space while in guest debugging mode. Reading it for
4546 * #DB as well causes no harm, it is not used in that case.
4547 */
4548 vmx->vcpu.arch.event_exit_inst_len =
4549 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4550 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4551 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4552 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4553 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4554 break;
4555 default:
d0bfb940
JK		 4556 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4557 kvm_run->ex.exception = ex_no;
4558 kvm_run->ex.error_code = error_code;
42dbaa5a 4559 break;
6aa8b732 4560 }
6aa8b732
AK		 4561 return 0;
4562}
4563
851ba692 4564static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4565{
1165f5fe 4566 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4567 return 1;
4568}
4569
851ba692 4570static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4571{
851ba692 4572 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4573 return 0;
4574}
6aa8b732 4575
851ba692 4576static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4577{
bfdaab09 4578 unsigned long exit_qualification;
34c33d16 4579 int size, in, string;
039576c0 4580 unsigned port;
6aa8b732 4581
bfdaab09 4582 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4583 string = (exit_qualification & 16) != 0;
cf8f70bf 4584 in = (exit_qualification & 8) != 0;
e70669ab 4585
cf8f70bf 4586 ++vcpu->stat.io_exits;
e70669ab 4587
cf8f70bf 4588 if (string || in)
51d8b661 4589 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4590
cf8f70bf
GN		 4591 port = exit_qualification >> 16;
4592 size = (exit_qualification & 7) + 1;
e93f36bc 4593 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4594
4595 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4596}
4597
102d8325
IM		 4598static void
4599vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4600{
4601 /*
4602 * Patch in the VMCALL instruction:
4603 */
4604 hypercall[0] = 0x0f;
4605 hypercall[1] = 0x01;
4606 hypercall[2] = 0xc1;
102d8325
IM		 4607}
4608
0fa06071 4609/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4610static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4611{
eeadf9e7 4612 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4613 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4614 unsigned long orig_val = val;
4615
eeadf9e7
NHE		 4616 /*
4617 * We get here when L2 changed cr0 in a way that did not change
4618 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4619 * but did change L0 shadowed bits. So we first calculate the
4620 * effective cr0 value that L1 would like to write into the
4621 * hardware. It consists of the L2-owned bits from the new
4622 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4623 */
1a0d74e6
JK		 4624 val = (val & ~vmcs12->cr0_guest_host_mask) |
4625 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4626
4627 /* TODO: will have to take unrestricted guest mode into
4628 * account */
4629 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4630 return 1;
1a0d74e6
JK		 4631
4632 if (kvm_set_cr0(vcpu, val))
4633 return 1;
4634 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4635 return 0;
1a0d74e6
JK		 4636 } else {
4637 if (to_vmx(vcpu)->nested.vmxon &&
4638 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4639 return 1;
eeadf9e7 4640 return kvm_set_cr0(vcpu, val);
1a0d74e6 4641 }
eeadf9e7
NHE		 4642}
4643
4644static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4645{
4646 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4647 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4648 unsigned long orig_val = val;
4649
4650 /* analogously to handle_set_cr0 */
4651 val = (val & ~vmcs12->cr4_guest_host_mask) |
4652 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4653 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4654 return 1;
1a0d74e6 4655 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4656 return 0;
4657 } else
4658 return kvm_set_cr4(vcpu, val);
4659}
4660
4661/* called to set cr0 as approriate for clts instruction exit. */
4662static void handle_clts(struct kvm_vcpu *vcpu)
4663{
4664 if (is_guest_mode(vcpu)) {
4665 /*
4666 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4667 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4668 * just pretend it's off (also in arch.cr0 for fpu_activate).
4669 */
4670 vmcs_writel(CR0_READ_SHADOW,
4671 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4672 vcpu->arch.cr0 &= ~X86_CR0_TS;
4673 } else
4674 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4675}
4676
851ba692 4677static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4678{
229456fc 4679 unsigned long exit_qualification, val;
6aa8b732
AK		 4680 int cr;
4681 int reg;
49a9b07e 4682 int err;
6aa8b732 4683
bfdaab09 4684 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4685 cr = exit_qualification & 15;
4686 reg = (exit_qualification >> 8) & 15;
4687 switch ((exit_qualification >> 4) & 3) {
4688 case 0: /* mov to cr */
229456fc
MT		 4689 val = kvm_register_read(vcpu, reg);
4690 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4691 switch (cr) {
4692 case 0:
eeadf9e7 4693 err = handle_set_cr0(vcpu, val);
db8fcefa 4694 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4695 return 1;
4696 case 3:
2390218b 4697 err = kvm_set_cr3(vcpu, val);
db8fcefa 4698 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4699 return 1;
4700 case 4:
eeadf9e7 4701 err = handle_set_cr4(vcpu, val);
db8fcefa 4702 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4703 return 1;
0a5fff19
GN		 4704 case 8: {
4705 u8 cr8_prev = kvm_get_cr8(vcpu);
4706 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4707 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4708 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4709 if (irqchip_in_kernel(vcpu->kvm))
4710 return 1;
4711 if (cr8_prev <= cr8)
4712 return 1;
851ba692 4713 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4714 return 0;
4715 }
4b8073e4 4716 }
6aa8b732 4717 break;
25c4c276 4718 case 2: /* clts */
eeadf9e7 4719 handle_clts(vcpu);
4d4ec087 4720 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4721 skip_emulated_instruction(vcpu);
6b52d186 4722 vmx_fpu_activate(vcpu);
25c4c276 4723 return 1;
6aa8b732
AK		 4724 case 1: /*mov from cr*/
4725 switch (cr) {
4726 case 3:
9f8fe504
AK		 4727 val = kvm_read_cr3(vcpu);
4728 kvm_register_write(vcpu, reg, val);
4729 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4730 skip_emulated_instruction(vcpu);
4731 return 1;
4732 case 8:
229456fc
MT		 4733 val = kvm_get_cr8(vcpu);
4734 kvm_register_write(vcpu, reg, val);
4735 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4736 skip_emulated_instruction(vcpu);
4737 return 1;
4738 }
4739 break;
4740 case 3: /* lmsw */
a1f83a74 4741 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4742 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4743 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4744
4745 skip_emulated_instruction(vcpu);
4746 return 1;
4747 default:
4748 break;
4749 }
851ba692 4750 vcpu->run->exit_reason = 0;
a737f256 4751 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4752 (int)(exit_qualification >> 4) & 3, cr);
4753 return 0;
4754}
4755
851ba692 4756static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4757{
bfdaab09 4758 unsigned long exit_qualification;
6aa8b732
AK		 4759 int dr, reg;
4760
f2483415 4761 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4762 if (!kvm_require_cpl(vcpu, 0))
4763 return 1;
42dbaa5a
JK		 4764 dr = vmcs_readl(GUEST_DR7);
4765 if (dr & DR7_GD) {
4766 /*
4767 * As the vm-exit takes precedence over the debug trap, we
4768 * need to emulate the latter, either for the host or the
4769 * guest debugging itself.
4770 */
4771 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4772 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4773 vcpu->run->debug.arch.dr7 = dr;
4774 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4775 vmcs_readl(GUEST_CS_BASE) +
4776 vmcs_readl(GUEST_RIP);
851ba692
AK		 4777 vcpu->run->debug.arch.exception = DB_VECTOR;
4778 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4779 return 0;
4780 } else {
4781 vcpu->arch.dr7 &= ~DR7_GD;
4782 vcpu->arch.dr6 |= DR6_BD;
4783 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4784 kvm_queue_exception(vcpu, DB_VECTOR);
4785 return 1;
4786 }
4787 }
4788
bfdaab09 4789 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4790 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4791 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4792 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4793 unsigned long val;
4794 if (!kvm_get_dr(vcpu, dr, &val))
4795 kvm_register_write(vcpu, reg, val);
4796 } else
4797 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4798 skip_emulated_instruction(vcpu);
4799 return 1;
4800}
4801
020df079
GN		 4802static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4803{
4804 vmcs_writel(GUEST_DR7, val);
4805}
4806
851ba692 4807static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4808{
06465c5a
AK		 4809 kvm_emulate_cpuid(vcpu);
4810 return 1;
6aa8b732
AK		 4811}
4812
851ba692 4813static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4814{
ad312c7c 4815 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4816 u64 data;
4817
4818 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4819 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4820 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4821 return 1;
4822 }
4823
229456fc 4824 trace_kvm_msr_read(ecx, data);
2714d1d3 4825
6aa8b732 4826 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4827 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4828 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4829 skip_emulated_instruction(vcpu);
4830 return 1;
4831}
4832
851ba692 4833static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4834{
8fe8ab46 4835 struct msr_data msr;
ad312c7c
ZX		 4836 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4837 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4838 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4839
8fe8ab46
WA		 4840 msr.data = data;
4841 msr.index = ecx;
4842 msr.host_initiated = false;
4843 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4844 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4845 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4846 return 1;
4847 }
4848
59200273 4849 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4850 skip_emulated_instruction(vcpu);
4851 return 1;
4852}
4853
851ba692 4854static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4855{
3842d135 4856 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4857 return 1;
4858}
4859
851ba692 4860static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4861{
85f455f7
ED		 4862 u32 cpu_based_vm_exec_control;
4863
4864 /* clear pending irq */
4865 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4866 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4867 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4868
3842d135
AK		 4869 kvm_make_request(KVM_REQ_EVENT, vcpu);
4870
a26bf12a 4871 ++vcpu->stat.irq_window_exits;
2714d1d3 4872
c1150d8c
DL		 4873 /*
4874 * If the user space waits to inject interrupts, exit as soon as
4875 * possible
4876 */
8061823a 4877 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4878 vcpu->run->request_interrupt_window &&
8061823a 4879 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4880 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4881 return 0;
4882 }
6aa8b732
AK		 4883 return 1;
4884}
4885
851ba692 4886static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4887{
4888 skip_emulated_instruction(vcpu);
d3bef15f 4889 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4890}
4891
851ba692 4892static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4893{
510043da 4894 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4895 kvm_emulate_hypercall(vcpu);
4896 return 1;
c21415e8
IM		 4897}
4898
ec25d5e6
GN		 4899static int handle_invd(struct kvm_vcpu *vcpu)
4900{
51d8b661 4901 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4902}
4903
851ba692 4904static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4905{
f9c617f6 4906 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4907
4908 kvm_mmu_invlpg(vcpu, exit_qualification);
4909 skip_emulated_instruction(vcpu);
4910 return 1;
4911}
4912
fee84b07
AK		 4913static int handle_rdpmc(struct kvm_vcpu *vcpu)
4914{
4915 int err;
4916
4917 err = kvm_rdpmc(vcpu);
4918 kvm_complete_insn_gp(vcpu, err);
4919
4920 return 1;
4921}
4922
851ba692 4923static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4924{
4925 skip_emulated_instruction(vcpu);
f5f48ee1 4926 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4927 return 1;
4928}
4929
2acf923e
DC		 4930static int handle_xsetbv(struct kvm_vcpu *vcpu)
4931{
4932 u64 new_bv = kvm_read_edx_eax(vcpu);
4933 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4934
4935 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4936 skip_emulated_instruction(vcpu);
4937 return 1;
4938}
4939
851ba692 4940static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4941{
58fbbf26
KT		 4942 if (likely(fasteoi)) {
4943 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4944 int access_type, offset;
4945
4946 access_type = exit_qualification & APIC_ACCESS_TYPE;
4947 offset = exit_qualification & APIC_ACCESS_OFFSET;
4948 /*
4949 * Sane guest uses MOV to write EOI, with written value
4950 * not cared. So make a short-circuit here by avoiding
4951 * heavy instruction emulation.
4952 */
4953 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4954 (offset == APIC_EOI)) {
4955 kvm_lapic_set_eoi(vcpu);
4956 skip_emulated_instruction(vcpu);
4957 return 1;
4958 }
4959 }
51d8b661 4960 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4961}
4962
c7c9c56c
YZ		 4963static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4964{
4965 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4966 int vector = exit_qualification & 0xff;
4967
4968 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4969 kvm_apic_set_eoi_accelerated(vcpu, vector);
4970 return 1;
4971}
4972
83d4c286
YZ		 4973static int handle_apic_write(struct kvm_vcpu *vcpu)
4974{
4975 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4976 u32 offset = exit_qualification & 0xfff;
4977
4978 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4979 kvm_apic_write_nodecode(vcpu, offset);
4980 return 1;
4981}
4982
851ba692 4983static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4984{
60637aac 4985 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4986 unsigned long exit_qualification;
e269fb21
JK		 4987 bool has_error_code = false;
4988 u32 error_code = 0;
37817f29 4989 u16 tss_selector;
7f3d35fd 4990 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4991
4992 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4993 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4994 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4995
4996 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4997
4998 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4999 if (reason == TASK_SWITCH_GATE && idt_v) {
5000 switch (type) {
5001 case INTR_TYPE_NMI_INTR:
5002 vcpu->arch.nmi_injected = false;
654f06fc 5003 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5004 break;
5005 case INTR_TYPE_EXT_INTR:
66fd3f7f 5006 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5007 kvm_clear_interrupt_queue(vcpu);
5008 break;
5009 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5010 if (vmx->idt_vectoring_info &
5011 VECTORING_INFO_DELIVER_CODE_MASK) {
5012 has_error_code = true;
5013 error_code =
5014 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5015 }
5016 /* fall through */
64a7ec06
GN		 5017 case INTR_TYPE_SOFT_EXCEPTION:
5018 kvm_clear_exception_queue(vcpu);
5019 break;
5020 default:
5021 break;
5022 }
60637aac 5023 }
37817f29
IE		 5024 tss_selector = exit_qualification;
5025
64a7ec06
GN		 5026 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5027 type != INTR_TYPE_EXT_INTR &&
5028 type != INTR_TYPE_NMI_INTR))
5029 skip_emulated_instruction(vcpu);
5030
7f3d35fd
KW		 5031 if (kvm_task_switch(vcpu, tss_selector,
5032 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5033 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5034 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5035 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5036 vcpu->run->internal.ndata = 0;
42dbaa5a 5037 return 0;
acb54517 5038 }
42dbaa5a
JK		 5039
5040 /* clear all local breakpoint enable flags */
5041 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5042
5043 /*
5044 * TODO: What about debug traps on tss switch?
5045 * Are we supposed to inject them and update dr6?
5046 */
5047
5048 return 1;
37817f29
IE		 5049}
5050
851ba692 5051static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5052{
f9c617f6 5053 unsigned long exit_qualification;
1439442c 5054 gpa_t gpa;
4f5982a5 5055 u32 error_code;
1439442c 5056 int gla_validity;
1439442c 5057
f9c617f6 5058 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5059
1439442c
SY		 5060 gla_validity = (exit_qualification >> 7) & 0x3;
5061 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5062 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5063 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5064 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5065 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5066 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5067 (long unsigned int)exit_qualification);
851ba692
AK		 5068 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5069 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5070 return 0;
1439442c
SY		 5071 }
5072
5073 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5074 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5075
5076 /* It is a write fault? */
5077 error_code = exit_qualification & (1U << 1);
5078 /* ept page table is present? */
5079 error_code |= (exit_qualification >> 3) & 0x1;
5080
5081 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5082}
5083
68f89400
MT		 5084static u64 ept_rsvd_mask(u64 spte, int level)
5085{
5086 int i;
5087 u64 mask = 0;
5088
5089 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5090 mask |= (1ULL << i);
5091
5092 if (level > 2)
5093 /* bits 7:3 reserved */
5094 mask |= 0xf8;
5095 else if (level == 2) {
5096 if (spte & (1ULL << 7))
5097 /* 2MB ref, bits 20:12 reserved */
5098 mask |= 0x1ff000;
5099 else
5100 /* bits 6:3 reserved */
5101 mask |= 0x78;
5102 }
5103
5104 return mask;
5105}
5106
5107static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5108 int level)
5109{
5110 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5111
5112 /* 010b (write-only) */
5113 WARN_ON((spte & 0x7) == 0x2);
5114
5115 /* 110b (write/execute) */
5116 WARN_ON((spte & 0x7) == 0x6);
5117
5118 /* 100b (execute-only) and value not supported by logical processor */
5119 if (!cpu_has_vmx_ept_execute_only())
5120 WARN_ON((spte & 0x7) == 0x4);
5121
5122 /* not 000b */
5123 if ((spte & 0x7)) {
5124 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5125
5126 if (rsvd_bits != 0) {
5127 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5128 __func__, rsvd_bits);
5129 WARN_ON(1);
5130 }
5131
5132 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5133 u64 ept_mem_type = (spte & 0x38) >> 3;
5134
5135 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5136 ept_mem_type == 7) {
5137 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5138 __func__, ept_mem_type);
5139 WARN_ON(1);
5140 }
5141 }
5142 }
5143}
5144
851ba692 5145static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5146{
5147 u64 sptes[4];
ce88decf 5148 int nr_sptes, i, ret;
68f89400
MT		 5149 gpa_t gpa;
5150
5151 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5152
ce88decf
XG		 5153 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5154 if (likely(ret == 1))
5155 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5156 EMULATE_DONE;
5157 if (unlikely(!ret))
5158 return 1;
5159
5160 /* It is the real ept misconfig */
68f89400
MT		 5161 printk(KERN_ERR "EPT: Misconfiguration.\n");
5162 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5163
5164 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5165
5166 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5167 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5168
851ba692
AK		 5169 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5170 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5171
5172 return 0;
5173}
5174
851ba692 5175static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5176{
5177 u32 cpu_based_vm_exec_control;
5178
5179 /* clear pending NMI */
5180 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5181 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5182 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5183 ++vcpu->stat.nmi_window_exits;
3842d135 5184 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5185
5186 return 1;
5187}
5188
80ced186 5189static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5190{
8b3079a5
AK		 5191 struct vcpu_vmx *vmx = to_vmx(vcpu);
5192 enum emulation_result err = EMULATE_DONE;
80ced186 5193 int ret = 1;
49e9d557
AK		 5194 u32 cpu_exec_ctrl;
5195 bool intr_window_requested;
b8405c18 5196 unsigned count = 130;
49e9d557
AK		 5197
5198 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5199 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5200
b8405c18 5201 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5202 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5203 return handle_interrupt_window(&vmx->vcpu);
5204
de87dcdd
AK		 5205 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5206 return 1;
5207
51d8b661 5208 err = emulate_instruction(vcpu, 0);
ea953ef0 5209
80ced186
MG		 5210 if (err == EMULATE_DO_MMIO) {
5211 ret = 0;
5212 goto out;
5213 }
1d5a4d9b 5214
de5f70e0
AK		 5215 if (err != EMULATE_DONE) {
5216 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5217 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5218 vcpu->run->internal.ndata = 0;
6d77dbfc 5219 return 0;
de5f70e0 5220 }
ea953ef0
MG		 5221
5222 if (signal_pending(current))
80ced186 5223 goto out;
ea953ef0
MG		 5224 if (need_resched())
5225 schedule();
5226 }
5227
14168786 5228 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5229out:
5230 return ret;
ea953ef0
MG		 5231}
5232
4b8d54f9
ZE		 5233/*
5234 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5235 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5236 */
9fb41ba8 5237static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5238{
5239 skip_emulated_instruction(vcpu);
5240 kvm_vcpu_on_spin(vcpu);
5241
5242 return 1;
5243}
5244
59708670
SY		 5245static int handle_invalid_op(struct kvm_vcpu *vcpu)
5246{
5247 kvm_queue_exception(vcpu, UD_VECTOR);
5248 return 1;
5249}
5250
ff2f6fe9
NHE		 5251/*
5252 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5253 * We could reuse a single VMCS for all the L2 guests, but we also want the
5254 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5255 * allows keeping them loaded on the processor, and in the future will allow
5256 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5257 * every entry if they never change.
5258 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5259 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5260 *
5261 * The following functions allocate and free a vmcs02 in this pool.
5262 */
5263
5264/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5265static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5266{
5267 struct vmcs02_list *item;
5268 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5269 if (item->vmptr == vmx->nested.current_vmptr) {
5270 list_move(&item->list, &vmx->nested.vmcs02_pool);
5271 return &item->vmcs02;
5272 }
5273
5274 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5275 /* Recycle the least recently used VMCS. */
5276 item = list_entry(vmx->nested.vmcs02_pool.prev,
5277 struct vmcs02_list, list);
5278 item->vmptr = vmx->nested.current_vmptr;
5279 list_move(&item->list, &vmx->nested.vmcs02_pool);
5280 return &item->vmcs02;
5281 }
5282
5283 /* Create a new VMCS */
0fa24ce3 5284 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5285 if (!item)
5286 return NULL;
5287 item->vmcs02.vmcs = alloc_vmcs();
5288 if (!item->vmcs02.vmcs) {
5289 kfree(item);
5290 return NULL;
5291 }
5292 loaded_vmcs_init(&item->vmcs02);
5293 item->vmptr = vmx->nested.current_vmptr;
5294 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5295 vmx->nested.vmcs02_num++;
5296 return &item->vmcs02;
5297}
5298
5299/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5300static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5301{
5302 struct vmcs02_list *item;
5303 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5304 if (item->vmptr == vmptr) {
5305 free_loaded_vmcs(&item->vmcs02);
5306 list_del(&item->list);
5307 kfree(item);
5308 vmx->nested.vmcs02_num--;
5309 return;
5310 }
5311}
5312
5313/*
5314 * Free all VMCSs saved for this vcpu, except the one pointed by
5315 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5316 * currently used, if running L2), and vmcs01 when running L2.
5317 */
5318static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5319{
5320 struct vmcs02_list *item, *n;
5321 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5322 if (vmx->loaded_vmcs != &item->vmcs02)
5323 free_loaded_vmcs(&item->vmcs02);
5324 list_del(&item->list);
5325 kfree(item);
5326 }
5327 vmx->nested.vmcs02_num = 0;
5328
5329 if (vmx->loaded_vmcs != &vmx->vmcs01)
5330 free_loaded_vmcs(&vmx->vmcs01);
5331}
5332
ec378aee
NHE		 5333/*
5334 * Emulate the VMXON instruction.
5335 * Currently, we just remember that VMX is active, and do not save or even
5336 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5337 * do not currently need to store anything in that guest-allocated memory
5338 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5339 * argument is different from the VMXON pointer (which the spec says they do).
5340 */
5341static int handle_vmon(struct kvm_vcpu *vcpu)
5342{
5343 struct kvm_segment cs;
5344 struct vcpu_vmx *vmx = to_vmx(vcpu);
5345
5346 /* The Intel VMX Instruction Reference lists a bunch of bits that
5347 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5348 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5349 * Otherwise, we should fail with #UD. We test these now:
5350 */
5351 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5352 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5353 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5354 kvm_queue_exception(vcpu, UD_VECTOR);
5355 return 1;
5356 }
5357
5358 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5359 if (is_long_mode(vcpu) && !cs.l) {
5360 kvm_queue_exception(vcpu, UD_VECTOR);
5361 return 1;
5362 }
5363
5364 if (vmx_get_cpl(vcpu)) {
5365 kvm_inject_gp(vcpu, 0);
5366 return 1;
5367 }
5368
ff2f6fe9
NHE		 5369 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5370 vmx->nested.vmcs02_num = 0;
5371
ec378aee
NHE		 5372 vmx->nested.vmxon = true;
5373
5374 skip_emulated_instruction(vcpu);
5375 return 1;
5376}
5377
5378/*
5379 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5380 * for running VMX instructions (except VMXON, whose prerequisites are
5381 * slightly different). It also specifies what exception to inject otherwise.
5382 */
5383static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5384{
5385 struct kvm_segment cs;
5386 struct vcpu_vmx *vmx = to_vmx(vcpu);
5387
5388 if (!vmx->nested.vmxon) {
5389 kvm_queue_exception(vcpu, UD_VECTOR);
5390 return 0;
5391 }
5392
5393 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5394 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5395 (is_long_mode(vcpu) && !cs.l)) {
5396 kvm_queue_exception(vcpu, UD_VECTOR);
5397 return 0;
5398 }
5399
5400 if (vmx_get_cpl(vcpu)) {
5401 kvm_inject_gp(vcpu, 0);
5402 return 0;
5403 }
5404
5405 return 1;
5406}
5407
5408/*
5409 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5410 * just stops using VMX.
5411 */
5412static void free_nested(struct vcpu_vmx *vmx)
5413{
5414 if (!vmx->nested.vmxon)
5415 return;
5416 vmx->nested.vmxon = false;
a9d30f33
NHE		 5417 if (vmx->nested.current_vmptr != -1ull) {
5418 kunmap(vmx->nested.current_vmcs12_page);
5419 nested_release_page(vmx->nested.current_vmcs12_page);
5420 vmx->nested.current_vmptr = -1ull;
5421 vmx->nested.current_vmcs12 = NULL;
5422 }
fe3ef05c
NHE		 5423 /* Unpin physical memory we referred to in current vmcs02 */
5424 if (vmx->nested.apic_access_page) {
5425 nested_release_page(vmx->nested.apic_access_page);
5426 vmx->nested.apic_access_page = 0;
5427 }
ff2f6fe9
NHE		 5428
5429 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5430}
5431
5432/* Emulate the VMXOFF instruction */
5433static int handle_vmoff(struct kvm_vcpu *vcpu)
5434{
5435 if (!nested_vmx_check_permission(vcpu))
5436 return 1;
5437 free_nested(to_vmx(vcpu));
5438 skip_emulated_instruction(vcpu);
5439 return 1;
5440}
5441
064aea77
NHE		 5442/*
5443 * Decode the memory-address operand of a vmx instruction, as recorded on an
5444 * exit caused by such an instruction (run by a guest hypervisor).
5445 * On success, returns 0. When the operand is invalid, returns 1 and throws
5446 * #UD or #GP.
5447 */
5448static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5449 unsigned long exit_qualification,
5450 u32 vmx_instruction_info, gva_t *ret)
5451{
5452 /*
5453 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5454 * Execution", on an exit, vmx_instruction_info holds most of the
5455 * addressing components of the operand. Only the displacement part
5456 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5457 * For how an actual address is calculated from all these components,
5458 * refer to Vol. 1, "Operand Addressing".
5459 */
5460 int scaling = vmx_instruction_info & 3;
5461 int addr_size = (vmx_instruction_info >> 7) & 7;
5462 bool is_reg = vmx_instruction_info & (1u << 10);
5463 int seg_reg = (vmx_instruction_info >> 15) & 7;
5464 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5465 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5466 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5467 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5468
5469 if (is_reg) {
5470 kvm_queue_exception(vcpu, UD_VECTOR);
5471 return 1;
5472 }
5473
5474 /* Addr = segment_base + offset */
5475 /* offset = base + [index * scale] + displacement */
5476 *ret = vmx_get_segment_base(vcpu, seg_reg);
5477 if (base_is_valid)
5478 *ret += kvm_register_read(vcpu, base_reg);
5479 if (index_is_valid)
5480 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5481 *ret += exit_qualification; /* holds the displacement */
5482
5483 if (addr_size == 1) /* 32 bit */
5484 *ret &= 0xffffffff;
5485
5486 /*
5487 * TODO: throw #GP (and return 1) in various cases that the VM*
5488 * instructions require it - e.g., offset beyond segment limit,
5489 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5490 * address, and so on. Currently these are not checked.
5491 */
5492 return 0;
5493}
5494
0140caea
NHE		 5495/*
5496 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5497 * set the success or error code of an emulated VMX instruction, as specified
5498 * by Vol 2B, VMX Instruction Reference, "Conventions".
5499 */
5500static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5501{
5502 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5503 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5504 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5505}
5506
5507static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5508{
5509 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5510 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5511 X86_EFLAGS_SF | X86_EFLAGS_OF))
5512 | X86_EFLAGS_CF);
5513}
5514
5515static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5516 u32 vm_instruction_error)
5517{
5518 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5519 /*
5520 * failValid writes the error number to the current VMCS, which
5521 * can't be done there isn't a current VMCS.
5522 */
5523 nested_vmx_failInvalid(vcpu);
5524 return;
5525 }
5526 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5527 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5528 X86_EFLAGS_SF | X86_EFLAGS_OF))
5529 | X86_EFLAGS_ZF);
5530 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5531}
5532
27d6c865
NHE		 5533/* Emulate the VMCLEAR instruction */
5534static int handle_vmclear(struct kvm_vcpu *vcpu)
5535{
5536 struct vcpu_vmx *vmx = to_vmx(vcpu);
5537 gva_t gva;
5538 gpa_t vmptr;
5539 struct vmcs12 *vmcs12;
5540 struct page *page;
5541 struct x86_exception e;
5542
5543 if (!nested_vmx_check_permission(vcpu))
5544 return 1;
5545
5546 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5547 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5548 return 1;
5549
5550 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5551 sizeof(vmptr), &e)) {
5552 kvm_inject_page_fault(vcpu, &e);
5553 return 1;
5554 }
5555
5556 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5557 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5558 skip_emulated_instruction(vcpu);
5559 return 1;
5560 }
5561
5562 if (vmptr == vmx->nested.current_vmptr) {
5563 kunmap(vmx->nested.current_vmcs12_page);
5564 nested_release_page(vmx->nested.current_vmcs12_page);
5565 vmx->nested.current_vmptr = -1ull;
5566 vmx->nested.current_vmcs12 = NULL;
5567 }
5568
5569 page = nested_get_page(vcpu, vmptr);
5570 if (page == NULL) {
5571 /*
5572 * For accurate processor emulation, VMCLEAR beyond available
5573 * physical memory should do nothing at all. However, it is
5574 * possible that a nested vmx bug, not a guest hypervisor bug,
5575 * resulted in this case, so let's shut down before doing any
5576 * more damage:
5577 */
5578 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5579 return 1;
5580 }
5581 vmcs12 = kmap(page);
5582 vmcs12->launch_state = 0;
5583 kunmap(page);
5584 nested_release_page(page);
5585
5586 nested_free_vmcs02(vmx, vmptr);
5587
5588 skip_emulated_instruction(vcpu);
5589 nested_vmx_succeed(vcpu);
5590 return 1;
5591}
5592
cd232ad0
NHE		 5593static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5594
5595/* Emulate the VMLAUNCH instruction */
5596static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5597{
5598 return nested_vmx_run(vcpu, true);
5599}
5600
5601/* Emulate the VMRESUME instruction */
5602static int handle_vmresume(struct kvm_vcpu *vcpu)
5603{
5604
5605 return nested_vmx_run(vcpu, false);
5606}
5607
49f705c5
NHE		 5608enum vmcs_field_type {
5609 VMCS_FIELD_TYPE_U16 = 0,
5610 VMCS_FIELD_TYPE_U64 = 1,
5611 VMCS_FIELD_TYPE_U32 = 2,
5612 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5613};
5614
5615static inline int vmcs_field_type(unsigned long field)
5616{
5617 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5618 return VMCS_FIELD_TYPE_U32;
5619 return (field >> 13) & 0x3 ;
5620}
5621
5622static inline int vmcs_field_readonly(unsigned long field)
5623{
5624 return (((field >> 10) & 0x3) == 1);
5625}
5626
5627/*
5628 * Read a vmcs12 field. Since these can have varying lengths and we return
5629 * one type, we chose the biggest type (u64) and zero-extend the return value
5630 * to that size. Note that the caller, handle_vmread, might need to use only
5631 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5632 * 64-bit fields are to be returned).
5633 */
5634static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5635 unsigned long field, u64 *ret)
5636{
5637 short offset = vmcs_field_to_offset(field);
5638 char *p;
5639
5640 if (offset < 0)
5641 return 0;
5642
5643 p = ((char *)(get_vmcs12(vcpu))) + offset;
5644
5645 switch (vmcs_field_type(field)) {
5646 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5647 *ret = *((natural_width *)p);
5648 return 1;
5649 case VMCS_FIELD_TYPE_U16:
5650 *ret = *((u16 *)p);
5651 return 1;
5652 case VMCS_FIELD_TYPE_U32:
5653 *ret = *((u32 *)p);
5654 return 1;
5655 case VMCS_FIELD_TYPE_U64:
5656 *ret = *((u64 *)p);
5657 return 1;
5658 default:
5659 return 0; /* can never happen. */
5660 }
5661}
5662
5663/*
5664 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5665 * used before) all generate the same failure when it is missing.
5666 */
5667static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5668{
5669 struct vcpu_vmx *vmx = to_vmx(vcpu);
5670 if (vmx->nested.current_vmptr == -1ull) {
5671 nested_vmx_failInvalid(vcpu);
5672 skip_emulated_instruction(vcpu);
5673 return 0;
5674 }
5675 return 1;
5676}
5677
5678static int handle_vmread(struct kvm_vcpu *vcpu)
5679{
5680 unsigned long field;
5681 u64 field_value;
5682 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5683 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5684 gva_t gva = 0;
5685
5686 if (!nested_vmx_check_permission(vcpu) ||
5687 !nested_vmx_check_vmcs12(vcpu))
5688 return 1;
5689
5690 /* Decode instruction info and find the field to read */
5691 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5692 /* Read the field, zero-extended to a u64 field_value */
5693 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5694 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5695 skip_emulated_instruction(vcpu);
5696 return 1;
5697 }
5698 /*
5699 * Now copy part of this value to register or memory, as requested.
5700 * Note that the number of bits actually copied is 32 or 64 depending
5701 * on the guest's mode (32 or 64 bit), not on the given field's length.
5702 */
5703 if (vmx_instruction_info & (1u << 10)) {
5704 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5705 field_value);
5706 } else {
5707 if (get_vmx_mem_address(vcpu, exit_qualification,
5708 vmx_instruction_info, &gva))
5709 return 1;
5710 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5711 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5712 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5713 }
5714
5715 nested_vmx_succeed(vcpu);
5716 skip_emulated_instruction(vcpu);
5717 return 1;
5718}
5719
5720
5721static int handle_vmwrite(struct kvm_vcpu *vcpu)
5722{
5723 unsigned long field;
5724 gva_t gva;
5725 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5726 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5727 char *p;
5728 short offset;
5729 /* The value to write might be 32 or 64 bits, depending on L1's long
5730 * mode, and eventually we need to write that into a field of several
5731 * possible lengths. The code below first zero-extends the value to 64
5732 * bit (field_value), and then copies only the approriate number of
5733 * bits into the vmcs12 field.
5734 */
5735 u64 field_value = 0;
5736 struct x86_exception e;
5737
5738 if (!nested_vmx_check_permission(vcpu) ||
5739 !nested_vmx_check_vmcs12(vcpu))
5740 return 1;
5741
5742 if (vmx_instruction_info & (1u << 10))
5743 field_value = kvm_register_read(vcpu,
5744 (((vmx_instruction_info) >> 3) & 0xf));
5745 else {
5746 if (get_vmx_mem_address(vcpu, exit_qualification,
5747 vmx_instruction_info, &gva))
5748 return 1;
5749 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5750 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5751 kvm_inject_page_fault(vcpu, &e);
5752 return 1;
5753 }
5754 }
5755
5756
5757 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5758 if (vmcs_field_readonly(field)) {
5759 nested_vmx_failValid(vcpu,
5760 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5761 skip_emulated_instruction(vcpu);
5762 return 1;
5763 }
5764
5765 offset = vmcs_field_to_offset(field);
5766 if (offset < 0) {
5767 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5768 skip_emulated_instruction(vcpu);
5769 return 1;
5770 }
5771 p = ((char *) get_vmcs12(vcpu)) + offset;
5772
5773 switch (vmcs_field_type(field)) {
5774 case VMCS_FIELD_TYPE_U16:
5775 *(u16 *)p = field_value;
5776 break;
5777 case VMCS_FIELD_TYPE_U32:
5778 *(u32 *)p = field_value;
5779 break;
5780 case VMCS_FIELD_TYPE_U64:
5781 *(u64 *)p = field_value;
5782 break;
5783 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5784 *(natural_width *)p = field_value;
5785 break;
5786 default:
5787 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5788 skip_emulated_instruction(vcpu);
5789 return 1;
5790 }
5791
5792 nested_vmx_succeed(vcpu);
5793 skip_emulated_instruction(vcpu);
5794 return 1;
5795}
5796
63846663
NHE		 5797/* Emulate the VMPTRLD instruction */
5798static int handle_vmptrld(struct kvm_vcpu *vcpu)
5799{
5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 gva_t gva;
5802 gpa_t vmptr;
5803 struct x86_exception e;
5804
5805 if (!nested_vmx_check_permission(vcpu))
5806 return 1;
5807
5808 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5809 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5810 return 1;
5811
5812 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5813 sizeof(vmptr), &e)) {
5814 kvm_inject_page_fault(vcpu, &e);
5815 return 1;
5816 }
5817
5818 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5819 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5820 skip_emulated_instruction(vcpu);
5821 return 1;
5822 }
5823
5824 if (vmx->nested.current_vmptr != vmptr) {
5825 struct vmcs12 *new_vmcs12;
5826 struct page *page;
5827 page = nested_get_page(vcpu, vmptr);
5828 if (page == NULL) {
5829 nested_vmx_failInvalid(vcpu);
5830 skip_emulated_instruction(vcpu);
5831 return 1;
5832 }
5833 new_vmcs12 = kmap(page);
5834 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5835 kunmap(page);
5836 nested_release_page_clean(page);
5837 nested_vmx_failValid(vcpu,
5838 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5839 skip_emulated_instruction(vcpu);
5840 return 1;
5841 }
5842 if (vmx->nested.current_vmptr != -1ull) {
5843 kunmap(vmx->nested.current_vmcs12_page);
5844 nested_release_page(vmx->nested.current_vmcs12_page);
5845 }
5846
5847 vmx->nested.current_vmptr = vmptr;
5848 vmx->nested.current_vmcs12 = new_vmcs12;
5849 vmx->nested.current_vmcs12_page = page;
5850 }
5851
5852 nested_vmx_succeed(vcpu);
5853 skip_emulated_instruction(vcpu);
5854 return 1;
5855}
5856
6a4d7550
NHE		 5857/* Emulate the VMPTRST instruction */
5858static int handle_vmptrst(struct kvm_vcpu *vcpu)
5859{
5860 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5861 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5862 gva_t vmcs_gva;
5863 struct x86_exception e;
5864
5865 if (!nested_vmx_check_permission(vcpu))
5866 return 1;
5867
5868 if (get_vmx_mem_address(vcpu, exit_qualification,
5869 vmx_instruction_info, &vmcs_gva))
5870 return 1;
5871 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5872 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5873 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5874 sizeof(u64), &e)) {
5875 kvm_inject_page_fault(vcpu, &e);
5876 return 1;
5877 }
5878 nested_vmx_succeed(vcpu);
5879 skip_emulated_instruction(vcpu);
5880 return 1;
5881}
5882
6aa8b732
AK		 5883/*
5884 * The exit handlers return 1 if the exit was handled fully and guest execution
5885 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5886 * to be done to userspace and return 0.
5887 */
772e0318 5888static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5889 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5890 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5891 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5892 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5893 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5894 [EXIT_REASON_CR_ACCESS] = handle_cr,
5895 [EXIT_REASON_DR_ACCESS] = handle_dr,
5896 [EXIT_REASON_CPUID] = handle_cpuid,
5897 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5898 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5899 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5900 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5901 [EXIT_REASON_INVD] = handle_invd,
a7052897 5902 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5903 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5904 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5905 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5906 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5907 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5908 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5909 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5910 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5911 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5912 [EXIT_REASON_VMOFF] = handle_vmoff,
5913 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5914 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5915 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 5916 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 5917 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 5918 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5919 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5920 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5921 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5922 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5923 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5924 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5925 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5926 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5927};
5928
5929static const int kvm_vmx_max_exit_handlers =
50a3485c 5930 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5931
908a7bdd
JK		 5932static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5933 struct vmcs12 *vmcs12)
5934{
5935 unsigned long exit_qualification;
5936 gpa_t bitmap, last_bitmap;
5937 unsigned int port;
5938 int size;
5939 u8 b;
5940
5941 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5942 return 1;
5943
5944 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5945 return 0;
5946
5947 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5948
5949 port = exit_qualification >> 16;
5950 size = (exit_qualification & 7) + 1;
5951
5952 last_bitmap = (gpa_t)-1;
5953 b = -1;
5954
5955 while (size > 0) {
5956 if (port < 0x8000)
5957 bitmap = vmcs12->io_bitmap_a;
5958 else if (port < 0x10000)
5959 bitmap = vmcs12->io_bitmap_b;
5960 else
5961 return 1;
5962 bitmap += (port & 0x7fff) / 8;
5963
5964 if (last_bitmap != bitmap)
5965 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5966 return 1;
5967 if (b & (1 << (port & 7)))
5968 return 1;
5969
5970 port++;
5971 size--;
5972 last_bitmap = bitmap;
5973 }
5974
5975 return 0;
5976}
5977
644d711a
NHE		 5978/*
5979 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5980 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5981 * disinterest in the current event (read or write a specific MSR) by using an
5982 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5983 */
5984static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5985 struct vmcs12 *vmcs12, u32 exit_reason)
5986{
5987 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5988 gpa_t bitmap;
5989
cbd29cb6 5990 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 5991 return 1;
5992
5993 /*
5994 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5995 * for the four combinations of read/write and low/high MSR numbers.
5996 * First we need to figure out which of the four to use:
5997 */
5998 bitmap = vmcs12->msr_bitmap;
5999 if (exit_reason == EXIT_REASON_MSR_WRITE)
6000 bitmap += 2048;
6001 if (msr_index >= 0xc0000000) {
6002 msr_index -= 0xc0000000;
6003 bitmap += 1024;
6004 }
6005
6006 /* Then read the msr_index'th bit from this bitmap: */
6007 if (msr_index < 1024*8) {
6008 unsigned char b;
bd31a7f5
JK		 6009 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6010 return 1;
644d711a
NHE		 6011 return 1 & (b >> (msr_index & 7));
6012 } else
6013 return 1; /* let L1 handle the wrong parameter */
6014}
6015
6016/*
6017 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6018 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6019 * intercept (via guest_host_mask etc.) the current event.
6020 */
6021static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6022 struct vmcs12 *vmcs12)
6023{
6024 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6025 int cr = exit_qualification & 15;
6026 int reg = (exit_qualification >> 8) & 15;
6027 unsigned long val = kvm_register_read(vcpu, reg);
6028
6029 switch ((exit_qualification >> 4) & 3) {
6030 case 0: /* mov to cr */
6031 switch (cr) {
6032 case 0:
6033 if (vmcs12->cr0_guest_host_mask &
6034 (val ^ vmcs12->cr0_read_shadow))
6035 return 1;
6036 break;
6037 case 3:
6038 if ((vmcs12->cr3_target_count >= 1 &&
6039 vmcs12->cr3_target_value0 == val) ||
6040 (vmcs12->cr3_target_count >= 2 &&
6041 vmcs12->cr3_target_value1 == val) ||
6042 (vmcs12->cr3_target_count >= 3 &&
6043 vmcs12->cr3_target_value2 == val) ||
6044 (vmcs12->cr3_target_count >= 4 &&
6045 vmcs12->cr3_target_value3 == val))
6046 return 0;
6047 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6048 return 1;
6049 break;
6050 case 4:
6051 if (vmcs12->cr4_guest_host_mask &
6052 (vmcs12->cr4_read_shadow ^ val))
6053 return 1;
6054 break;
6055 case 8:
6056 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6057 return 1;
6058 break;
6059 }
6060 break;
6061 case 2: /* clts */
6062 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6063 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6064 return 1;
6065 break;
6066 case 1: /* mov from cr */
6067 switch (cr) {
6068 case 3:
6069 if (vmcs12->cpu_based_vm_exec_control &
6070 CPU_BASED_CR3_STORE_EXITING)
6071 return 1;
6072 break;
6073 case 8:
6074 if (vmcs12->cpu_based_vm_exec_control &
6075 CPU_BASED_CR8_STORE_EXITING)
6076 return 1;
6077 break;
6078 }
6079 break;
6080 case 3: /* lmsw */
6081 /*
6082 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6083 * cr0. Other attempted changes are ignored, with no exit.
6084 */
6085 if (vmcs12->cr0_guest_host_mask & 0xe &
6086 (val ^ vmcs12->cr0_read_shadow))
6087 return 1;
6088 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6089 !(vmcs12->cr0_read_shadow & 0x1) &&
6090 (val & 0x1))
6091 return 1;
6092 break;
6093 }
6094 return 0;
6095}
6096
6097/*
6098 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6099 * should handle it ourselves in L0 (and then continue L2). Only call this
6100 * when in is_guest_mode (L2).
6101 */
6102static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6103{
644d711a
NHE		 6104 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6105 struct vcpu_vmx *vmx = to_vmx(vcpu);
6106 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6107 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6108
6109 if (vmx->nested.nested_run_pending)
6110 return 0;
6111
6112 if (unlikely(vmx->fail)) {
bd80158a
JK		 6113 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6114 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6115 return 1;
6116 }
6117
6118 switch (exit_reason) {
6119 case EXIT_REASON_EXCEPTION_NMI:
6120 if (!is_exception(intr_info))
6121 return 0;
6122 else if (is_page_fault(intr_info))
6123 return enable_ept;
6124 return vmcs12->exception_bitmap &
6125 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6126 case EXIT_REASON_EXTERNAL_INTERRUPT:
6127 return 0;
6128 case EXIT_REASON_TRIPLE_FAULT:
6129 return 1;
6130 case EXIT_REASON_PENDING_INTERRUPT:
6131 case EXIT_REASON_NMI_WINDOW:
6132 /*
6133 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6134 * (aka Interrupt Window Exiting) only when L1 turned it on,
6135 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6136 * Same for NMI Window Exiting.
6137 */
6138 return 1;
6139 case EXIT_REASON_TASK_SWITCH:
6140 return 1;
6141 case EXIT_REASON_CPUID:
6142 return 1;
6143 case EXIT_REASON_HLT:
6144 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6145 case EXIT_REASON_INVD:
6146 return 1;
6147 case EXIT_REASON_INVLPG:
6148 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6149 case EXIT_REASON_RDPMC:
6150 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6151 case EXIT_REASON_RDTSC:
6152 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6153 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6154 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6155 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6156 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6157 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6158 /*
6159 * VMX instructions trap unconditionally. This allows L1 to
6160 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6161 */
6162 return 1;
6163 case EXIT_REASON_CR_ACCESS:
6164 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6165 case EXIT_REASON_DR_ACCESS:
6166 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6167 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6168 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6169 case EXIT_REASON_MSR_READ:
6170 case EXIT_REASON_MSR_WRITE:
6171 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6172 case EXIT_REASON_INVALID_STATE:
6173 return 1;
6174 case EXIT_REASON_MWAIT_INSTRUCTION:
6175 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6176 case EXIT_REASON_MONITOR_INSTRUCTION:
6177 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6178 case EXIT_REASON_PAUSE_INSTRUCTION:
6179 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6180 nested_cpu_has2(vmcs12,
6181 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6182 case EXIT_REASON_MCE_DURING_VMENTRY:
6183 return 0;
6184 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6185 return 1;
6186 case EXIT_REASON_APIC_ACCESS:
6187 return nested_cpu_has2(vmcs12,
6188 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6189 case EXIT_REASON_EPT_VIOLATION:
6190 case EXIT_REASON_EPT_MISCONFIG:
6191 return 0;
6192 case EXIT_REASON_WBINVD:
6193 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6194 case EXIT_REASON_XSETBV:
6195 return 1;
6196 default:
6197 return 1;
6198 }
6199}
6200
586f9607
AK		 6201static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6202{
6203 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6204 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6205}
6206
6aa8b732
AK		 6207/*
6208 * The guest has exited. See if we can fix it or if we need userspace
6209 * assistance.
6210 */
851ba692 6211static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6212{
29bd8a78 6213 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6214 u32 exit_reason = vmx->exit_reason;
1155f76a 6215 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6216
80ced186 6217 /* If guest state is invalid, start emulating */
14168786 6218 if (vmx->emulation_required)
80ced186 6219 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6220
b6f1250e
NHE		 6221 /*
6222 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6223 * we did not inject a still-pending event to L1 now because of
6224 * nested_run_pending, we need to re-enable this bit.
6225 */
6226 if (vmx->nested.nested_run_pending)
6227 kvm_make_request(KVM_REQ_EVENT, vcpu);
6228
509c75ea
NHE		 6229 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6230 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6231 vmx->nested.nested_run_pending = 1;
6232 else
6233 vmx->nested.nested_run_pending = 0;
6234
6235 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6236 nested_vmx_vmexit(vcpu);
6237 return 1;
6238 }
6239
5120702e
MG		 6240 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6241 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6242 vcpu->run->fail_entry.hardware_entry_failure_reason
6243 = exit_reason;
6244 return 0;
6245 }
6246
29bd8a78 6247 if (unlikely(vmx->fail)) {
851ba692
AK		 6248 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6249 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6250 = vmcs_read32(VM_INSTRUCTION_ERROR);
6251 return 0;
6252 }
6aa8b732 6253
b9bf6882
XG		 6254 /*
6255 * Note:
6256 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6257 * delivery event since it indicates guest is accessing MMIO.
6258 * The vm-exit can be triggered again after return to guest that
6259 * will cause infinite loop.
6260 */
d77c26fc 6261 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6262 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6263 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6264 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6265 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6266 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6267 vcpu->run->internal.ndata = 2;
6268 vcpu->run->internal.data[0] = vectoring_info;
6269 vcpu->run->internal.data[1] = exit_reason;
6270 return 0;
6271 }
3b86cd99 6272
644d711a
NHE		 6273 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6274 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6275 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6276 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6277 vmx->soft_vnmi_blocked = 0;
3b86cd99 6278 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6279 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6280 /*
6281 * This CPU don't support us in finding the end of an
6282 * NMI-blocked window if the guest runs with IRQs
6283 * disabled. So we pull the trigger after 1 s of
6284 * futile waiting, but inform the user about this.
6285 */
6286 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6287 "state on VCPU %d after 1 s timeout\n",
6288 __func__, vcpu->vcpu_id);
6289 vmx->soft_vnmi_blocked = 0;
3b86cd99 6290 }
3b86cd99
JK		 6291 }
6292
6aa8b732
AK		 6293 if (exit_reason < kvm_vmx_max_exit_handlers
6294 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6295 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6296 else {
851ba692
AK		 6297 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6298 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6299 }
6300 return 0;
6301}
6302
95ba8273 6303static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6304{
95ba8273 6305 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6306 vmcs_write32(TPR_THRESHOLD, 0);
6307 return;
6308 }
6309
95ba8273 6310 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6311}
6312
8d14695f
YZ		 6313static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6314{
6315 u32 sec_exec_control;
6316
6317 /*
6318 * There is not point to enable virtualize x2apic without enable
6319 * apicv
6320 */
c7c9c56c
YZ		 6321 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6322 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6323 return;
6324
6325 if (!vm_need_tpr_shadow(vcpu->kvm))
6326 return;
6327
6328 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6329
6330 if (set) {
6331 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6332 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6333 } else {
6334 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6335 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6336 }
6337 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6338
6339 vmx_set_msr_bitmap(vcpu);
6340}
6341
c7c9c56c
YZ		 6342static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6343{
6344 u16 status;
6345 u8 old;
6346
6347 if (!vmx_vm_has_apicv(kvm))
6348 return;
6349
6350 if (isr == -1)
6351 isr = 0;
6352
6353 status = vmcs_read16(GUEST_INTR_STATUS);
6354 old = status >> 8;
6355 if (isr != old) {
6356 status &= 0xff;
6357 status |= isr << 8;
6358 vmcs_write16(GUEST_INTR_STATUS, status);
6359 }
6360}
6361
6362static void vmx_set_rvi(int vector)
6363{
6364 u16 status;
6365 u8 old;
6366
6367 status = vmcs_read16(GUEST_INTR_STATUS);
6368 old = (u8)status & 0xff;
6369 if ((u8)vector != old) {
6370 status &= ~0xff;
6371 status |= (u8)vector;
6372 vmcs_write16(GUEST_INTR_STATUS, status);
6373 }
6374}
6375
6376static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6377{
6378 if (max_irr == -1)
6379 return;
6380
6381 vmx_set_rvi(max_irr);
6382}
6383
6384static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6385{
6386 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6387 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6388 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6389 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6390}
6391
51aa01d1 6392static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6393{
00eba012
AK		 6394 u32 exit_intr_info;
6395
6396 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6397 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6398 return;
6399
c5ca8e57 6400 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6401 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6402
6403 /* Handle machine checks before interrupts are enabled */
00eba012 6404 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6405 kvm_machine_check();
6406
20f65983 6407 /* We need to handle NMIs before interrupts are enabled */
00eba012 6408 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6409 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6410 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6411 asm("int $2");
ff9d07a0
ZY		 6412 kvm_after_handle_nmi(&vmx->vcpu);
6413 }
51aa01d1 6414}
20f65983 6415
51aa01d1
AK		 6416static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6417{
c5ca8e57 6418 u32 exit_intr_info;
51aa01d1
AK		 6419 bool unblock_nmi;
6420 u8 vector;
6421 bool idtv_info_valid;
6422
6423 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6424
cf393f75 6425 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6426 if (vmx->nmi_known_unmasked)
6427 return;
c5ca8e57
AK		 6428 /*
6429 * Can't use vmx->exit_intr_info since we're not sure what
6430 * the exit reason is.
6431 */
6432 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6433 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6434 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6435 /*
7b4a25cb 6436 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6437 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6438 * a guest IRET fault.
7b4a25cb
GN		 6439 * SDM 3: 23.2.2 (September 2008)
6440 * Bit 12 is undefined in any of the following cases:
6441 * If the VM exit sets the valid bit in the IDT-vectoring
6442 * information field.
6443 * If the VM exit is due to a double fault.
cf393f75 6444 */
7b4a25cb
GN		 6445 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6446 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6447 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6448 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6449 else
6450 vmx->nmi_known_unmasked =
6451 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6452 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6453 } else if (unlikely(vmx->soft_vnmi_blocked))
6454 vmx->vnmi_blocked_time +=
6455 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6456}
6457
3ab66e8a 6458static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6459 u32 idt_vectoring_info,
6460 int instr_len_field,
6461 int error_code_field)
51aa01d1 6462{
51aa01d1
AK		 6463 u8 vector;
6464 int type;
6465 bool idtv_info_valid;
6466
6467 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6468
3ab66e8a
JK		 6469 vcpu->arch.nmi_injected = false;
6470 kvm_clear_exception_queue(vcpu);
6471 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6472
6473 if (!idtv_info_valid)
6474 return;
6475
3ab66e8a 6476 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6477
668f612f
AK		 6478 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6479 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6480
64a7ec06 6481 switch (type) {
37b96e98 6482 case INTR_TYPE_NMI_INTR:
3ab66e8a 6483 vcpu->arch.nmi_injected = true;
668f612f 6484 /*
7b4a25cb 6485 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6486 * Clear bit "block by NMI" before VM entry if a NMI
6487 * delivery faulted.
668f612f 6488 */
3ab66e8a 6489 vmx_set_nmi_mask(vcpu, false);
37b96e98 6490 break;
37b96e98 6491 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6492 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6493 /* fall through */
6494 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6495 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6496 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6497 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6498 } else
3ab66e8a 6499 kvm_queue_exception(vcpu, vector);
37b96e98 6500 break;
66fd3f7f 6501 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6502 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6503 /* fall through */
37b96e98 6504 case INTR_TYPE_EXT_INTR:
3ab66e8a 6505 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6506 break;
6507 default:
6508 break;
f7d9238f 6509 }
cf393f75
AK		 6510}
6511
83422e17
AK		 6512static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6513{
66c78ae4
NHE		 6514 if (is_guest_mode(&vmx->vcpu))
6515 return;
3ab66e8a 6516 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6517 VM_EXIT_INSTRUCTION_LEN,
6518 IDT_VECTORING_ERROR_CODE);
6519}
6520
b463a6f7
AK		 6521static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6522{
66c78ae4
NHE		 6523 if (is_guest_mode(vcpu))
6524 return;
3ab66e8a 6525 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6526 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6527 VM_ENTRY_INSTRUCTION_LEN,
6528 VM_ENTRY_EXCEPTION_ERROR_CODE);
6529
6530 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6531}
6532
d7cd9796
GN		 6533static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6534{
6535 int i, nr_msrs;
6536 struct perf_guest_switch_msr *msrs;
6537
6538 msrs = perf_guest_get_msrs(&nr_msrs);
6539
6540 if (!msrs)
6541 return;
6542
6543 for (i = 0; i < nr_msrs; i++)
6544 if (msrs[i].host == msrs[i].guest)
6545 clear_atomic_switch_msr(vmx, msrs[i].msr);
6546 else
6547 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6548 msrs[i].host);
6549}
6550
a3b5ba49 6551static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6552{
a2fa3e9f 6553 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6554 unsigned long debugctlmsr;
104f226b 6555
66c78ae4
NHE		 6556 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6557 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6558 if (vmcs12->idt_vectoring_info_field &
6559 VECTORING_INFO_VALID_MASK) {
6560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6561 vmcs12->idt_vectoring_info_field);
6562 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6563 vmcs12->vm_exit_instruction_len);
6564 if (vmcs12->idt_vectoring_info_field &
6565 VECTORING_INFO_DELIVER_CODE_MASK)
6566 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6567 vmcs12->idt_vectoring_error_code);
6568 }
6569 }
6570
104f226b
AK		 6571 /* Record the guest's net vcpu time for enforced NMI injections. */
6572 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6573 vmx->entry_time = ktime_get();
6574
6575 /* Don't enter VMX if guest state is invalid, let the exit handler
6576 start emulation until we arrive back to a valid state */
14168786 6577 if (vmx->emulation_required)
104f226b
AK		 6578 return;
6579
6580 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6581 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6582 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6583 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6584
6585 /* When single-stepping over STI and MOV SS, we must clear the
6586 * corresponding interruptibility bits in the guest state. Otherwise
6587 * vmentry fails as it then expects bit 14 (BS) in pending debug
6588 * exceptions being set, but that's not correct for the guest debugging
6589 * case. */
6590 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6591 vmx_set_interrupt_shadow(vcpu, 0);
6592
d7cd9796 6593 atomic_switch_perf_msrs(vmx);
2a7921b7 6594 debugctlmsr = get_debugctlmsr();
d7cd9796 6595
d462b819 6596 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6597 asm(
6aa8b732 6598 /* Store host registers */
b188c81f
AK		 6599 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6600 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6601 "push %%" _ASM_CX " \n\t"
6602 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6603 "je 1f \n\t"
b188c81f 6604 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6605 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6606 "1: \n\t"
d3edefc0 6607 /* Reload cr2 if changed */
b188c81f
AK		 6608 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6609 "mov %%cr2, %%" _ASM_DX " \n\t"
6610 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6611 "je 2f \n\t"
b188c81f 6612 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6613 "2: \n\t"
6aa8b732 6614 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6615 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6616 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6617 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6618 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6619 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6620 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6621 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6622 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6623#ifdef CONFIG_X86_64
e08aa78a
AK		 6624 "mov %c[r8](%0), %%r8 \n\t"
6625 "mov %c[r9](%0), %%r9 \n\t"
6626 "mov %c[r10](%0), %%r10 \n\t"
6627 "mov %c[r11](%0), %%r11 \n\t"
6628 "mov %c[r12](%0), %%r12 \n\t"
6629 "mov %c[r13](%0), %%r13 \n\t"
6630 "mov %c[r14](%0), %%r14 \n\t"
6631 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6632#endif
b188c81f 6633 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6634
6aa8b732 6635 /* Enter guest mode */
83287ea4 6636 "jne 1f \n\t"
4ecac3fd 6637 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6638 "jmp 2f \n\t"
6639 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6640 "2: "
6aa8b732 6641 /* Save guest registers, load host registers, keep flags */
b188c81f 6642 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6643 "pop %0 \n\t"
b188c81f
AK		 6644 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6645 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6646 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6647 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6648 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6649 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6650 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6651#ifdef CONFIG_X86_64
e08aa78a
AK		 6652 "mov %%r8, %c[r8](%0) \n\t"
6653 "mov %%r9, %c[r9](%0) \n\t"
6654 "mov %%r10, %c[r10](%0) \n\t"
6655 "mov %%r11, %c[r11](%0) \n\t"
6656 "mov %%r12, %c[r12](%0) \n\t"
6657 "mov %%r13, %c[r13](%0) \n\t"
6658 "mov %%r14, %c[r14](%0) \n\t"
6659 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6660#endif
b188c81f
AK		 6661 "mov %%cr2, %%" _ASM_AX " \n\t"
6662 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6663
b188c81f 6664 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6665 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6666 ".pushsection .rodata \n\t"
6667 ".global vmx_return \n\t"
6668 "vmx_return: " _ASM_PTR " 2b \n\t"
6669 ".popsection"
e08aa78a 6670 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6671 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6672 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6673 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6674 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6675 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6676 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6677 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6678 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6679 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6680 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6681#ifdef CONFIG_X86_64
ad312c7c
ZX		 6682 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6683 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6684 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6685 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6686 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6687 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6688 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6689 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6690#endif
40712fae
AK		 6691 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6692 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6693 : "cc", "memory"
6694#ifdef CONFIG_X86_64
b188c81f 6695 , "rax", "rbx", "rdi", "rsi"
c2036300 6696 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6697#else
6698 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6699#endif
6700 );
6aa8b732 6701
2a7921b7
GN		 6702 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6703 if (debugctlmsr)
6704 update_debugctlmsr(debugctlmsr);
6705
aa67f609
AK		 6706#ifndef CONFIG_X86_64
6707 /*
6708 * The sysexit path does not restore ds/es, so we must set them to
6709 * a reasonable value ourselves.
6710 *
6711 * We can't defer this to vmx_load_host_state() since that function
6712 * may be executed in interrupt context, which saves and restore segments
6713 * around it, nullifying its effect.
6714 */
6715 loadsegment(ds, __USER_DS);
6716 loadsegment(es, __USER_DS);
6717#endif
6718
6de4f3ad 6719 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6720 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6721 | (1 << VCPU_EXREG_CPL)
aff48baa 6722 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6723 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6724 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6725 vcpu->arch.regs_dirty = 0;
6726
1155f76a
AK		 6727 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6728
66c78ae4
NHE		 6729 if (is_guest_mode(vcpu)) {
6730 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6731 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6732 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6733 vmcs12->idt_vectoring_error_code =
6734 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6735 vmcs12->vm_exit_instruction_len =
6736 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6737 }
6738 }
6739
d462b819 6740 vmx->loaded_vmcs->launched = 1;
1b6269db 6741
51aa01d1 6742 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6743 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6744
6745 vmx_complete_atomic_exit(vmx);
6746 vmx_recover_nmi_blocking(vmx);
cf393f75 6747 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6748}
6749
6aa8b732
AK		 6750static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6751{
fb3f0f51
RR		 6752 struct vcpu_vmx *vmx = to_vmx(vcpu);
6753
cdbecfc3 6754 free_vpid(vmx);
ec378aee 6755 free_nested(vmx);
d462b819 6756 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6757 kfree(vmx->guest_msrs);
6758 kvm_vcpu_uninit(vcpu);
a4770347 6759 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6760}
6761
fb3f0f51 6762static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6763{
fb3f0f51 6764 int err;
c16f862d 6765 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6766 int cpu;
6aa8b732 6767
a2fa3e9f 6768 if (!vmx)
fb3f0f51
RR		 6769 return ERR_PTR(-ENOMEM);
6770
2384d2b3
SY		 6771 allocate_vpid(vmx);
6772
fb3f0f51
RR		 6773 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6774 if (err)
6775 goto free_vcpu;
965b58a5 6776
a2fa3e9f 6777 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6778 err = -ENOMEM;
fb3f0f51 6779 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6780 goto uninit_vcpu;
6781 }
965b58a5 6782
d462b819
NHE		 6783 vmx->loaded_vmcs = &vmx->vmcs01;
6784 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6785 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6786 goto free_msrs;
d462b819
NHE		 6787 if (!vmm_exclusive)
6788 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6789 loaded_vmcs_init(vmx->loaded_vmcs);
6790 if (!vmm_exclusive)
6791 kvm_cpu_vmxoff();
a2fa3e9f 6792
15ad7146
AK		 6793 cpu = get_cpu();
6794 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6795 vmx->vcpu.cpu = cpu;
8b9cf98c 6796 err = vmx_vcpu_setup(vmx);
fb3f0f51 6797 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6798 put_cpu();
fb3f0f51
RR		 6799 if (err)
6800 goto free_vmcs;
5e4a0b3c 6801 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6802 err = alloc_apic_access_page(kvm);
6803 if (err)
5e4a0b3c 6804 goto free_vmcs;
fb3f0f51 6805
b927a3ce
SY		 6806 if (enable_ept) {
6807 if (!kvm->arch.ept_identity_map_addr)
6808 kvm->arch.ept_identity_map_addr =
6809 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6810 err = -ENOMEM;
b7ebfb05
SY		 6811 if (alloc_identity_pagetable(kvm) != 0)
6812 goto free_vmcs;
93ea5388
GN		 6813 if (!init_rmode_identity_map(kvm))
6814 goto free_vmcs;
b927a3ce 6815 }
b7ebfb05 6816
a9d30f33
NHE		 6817 vmx->nested.current_vmptr = -1ull;
6818 vmx->nested.current_vmcs12 = NULL;
6819
fb3f0f51
RR		 6820 return &vmx->vcpu;
6821
6822free_vmcs:
5f3fbc34 6823 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6824free_msrs:
fb3f0f51
RR		 6825 kfree(vmx->guest_msrs);
6826uninit_vcpu:
6827 kvm_vcpu_uninit(&vmx->vcpu);
6828free_vcpu:
cdbecfc3 6829 free_vpid(vmx);
a4770347 6830 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6831 return ERR_PTR(err);
6aa8b732
AK		 6832}
6833
002c7f7c
YS		 6834static void __init vmx_check_processor_compat(void *rtn)
6835{
6836 struct vmcs_config vmcs_conf;
6837
6838 *(int *)rtn = 0;
6839 if (setup_vmcs_config(&vmcs_conf) < 0)
6840 *(int *)rtn = -EIO;
6841 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6842 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6843 smp_processor_id());
6844 *(int *)rtn = -EIO;
6845 }
6846}
6847
67253af5
SY		 6848static int get_ept_level(void)
6849{
6850 return VMX_EPT_DEFAULT_GAW + 1;
6851}
6852
4b12f0de 6853static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6854{
4b12f0de
SY		 6855 u64 ret;
6856
522c68c4
SY		 6857 /* For VT-d and EPT combination
6858 * 1. MMIO: always map as UC
6859 * 2. EPT with VT-d:
6860 * a. VT-d without snooping control feature: can't guarantee the
6861 * result, try to trust guest.
6862 * b. VT-d with snooping control feature: snooping control feature of
6863 * VT-d engine can guarantee the cache correctness. Just set it
6864 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6865 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6866 * consistent with host MTRR
6867 */
4b12f0de
SY		 6868 if (is_mmio)
6869 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6870 else if (vcpu->kvm->arch.iommu_domain &&
6871 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6872 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6873 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6874 else
522c68c4 6875 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6876 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6877
6878 return ret;
64d4d521
SY		 6879}
6880
17cc3935 6881static int vmx_get_lpage_level(void)
344f414f 6882{
878403b7
SY		 6883 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6884 return PT_DIRECTORY_LEVEL;
6885 else
6886 /* For shadow and EPT supported 1GB page */
6887 return PT_PDPE_LEVEL;
344f414f
JR		 6888}
6889
0e851880
SY		 6890static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6891{
4e47c7a6
SY		 6892 struct kvm_cpuid_entry2 *best;
6893 struct vcpu_vmx *vmx = to_vmx(vcpu);
6894 u32 exec_control;
6895
6896 vmx->rdtscp_enabled = false;
6897 if (vmx_rdtscp_supported()) {
6898 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6899 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6900 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6901 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6902 vmx->rdtscp_enabled = true;
6903 else {
6904 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6905 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6906 exec_control);
6907 }
6908 }
6909 }
ad756a16 6910
ad756a16
MJ		 6911 /* Exposing INVPCID only when PCID is exposed */
6912 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6913 if (vmx_invpcid_supported() &&
4f977045 6914 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6915 guest_cpuid_has_pcid(vcpu)) {
29282fde 6916 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6917 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6918 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6919 exec_control);
6920 } else {
29282fde
TI		 6921 if (cpu_has_secondary_exec_ctrls()) {
6922 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6923 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6924 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6925 exec_control);
6926 }
ad756a16 6927 if (best)
4f977045 6928 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6929 }
0e851880
SY		 6930}
6931
d4330ef2
JR		 6932static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6933{
7b8050f5
NHE		 6934 if (func == 1 && nested)
6935 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6936}
6937
fe3ef05c
NHE		 6938/*
6939 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6940 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6941 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6942 * guest in a way that will both be appropriate to L1's requests, and our
6943 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6944 * function also has additional necessary side-effects, like setting various
6945 * vcpu->arch fields.
6946 */
6947static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6948{
6949 struct vcpu_vmx *vmx = to_vmx(vcpu);
6950 u32 exec_control;
6951
6952 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6953 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6954 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6955 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6956 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6957 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6958 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6959 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6960 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6961 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6962 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6963 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6964 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6965 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6966 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6967 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6968 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6969 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6970 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6971 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6972 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6973 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6974 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6975 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6976 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6977 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6978 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6979 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6980 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6981 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6982 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6983 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6984 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6985 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6986 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6987 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6988
6989 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6990 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6991 vmcs12->vm_entry_intr_info_field);
6992 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6993 vmcs12->vm_entry_exception_error_code);
6994 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6995 vmcs12->vm_entry_instruction_len);
6996 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6997 vmcs12->guest_interruptibility_info);
6998 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6999 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7000 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7001 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7002 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7003 vmcs12->guest_pending_dbg_exceptions);
7004 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7005 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7006
7007 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7008
7009 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7010 (vmcs_config.pin_based_exec_ctrl |
7011 vmcs12->pin_based_vm_exec_control));
7012
7013 /*
7014 * Whether page-faults are trapped is determined by a combination of
7015 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7016 * If enable_ept, L0 doesn't care about page faults and we should
7017 * set all of these to L1's desires. However, if !enable_ept, L0 does
7018 * care about (at least some) page faults, and because it is not easy
7019 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7020 * to exit on each and every L2 page fault. This is done by setting
7021 * MASK=MATCH=0 and (see below) EB.PF=1.
7022 * Note that below we don't need special code to set EB.PF beyond the
7023 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7024 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7025 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7026 *
7027 * A problem with this approach (when !enable_ept) is that L1 may be
7028 * injected with more page faults than it asked for. This could have
7029 * caused problems, but in practice existing hypervisors don't care.
7030 * To fix this, we will need to emulate the PFEC checking (on the L1
7031 * page tables), using walk_addr(), when injecting PFs to L1.
7032 */
7033 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7034 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7035 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7036 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7037
7038 if (cpu_has_secondary_exec_ctrls()) {
7039 u32 exec_control = vmx_secondary_exec_control(vmx);
7040 if (!vmx->rdtscp_enabled)
7041 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7042 /* Take the following fields only from vmcs12 */
7043 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7044 if (nested_cpu_has(vmcs12,
7045 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7046 exec_control |= vmcs12->secondary_vm_exec_control;
7047
7048 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7049 /*
7050 * Translate L1 physical address to host physical
7051 * address for vmcs02. Keep the page pinned, so this
7052 * physical address remains valid. We keep a reference
7053 * to it so we can release it later.
7054 */
7055 if (vmx->nested.apic_access_page) /* shouldn't happen */
7056 nested_release_page(vmx->nested.apic_access_page);
7057 vmx->nested.apic_access_page =
7058 nested_get_page(vcpu, vmcs12->apic_access_addr);
7059 /*
7060 * If translation failed, no matter: This feature asks
7061 * to exit when accessing the given address, and if it
7062 * can never be accessed, this feature won't do
7063 * anything anyway.
7064 */
7065 if (!vmx->nested.apic_access_page)
7066 exec_control &=
7067 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7068 else
7069 vmcs_write64(APIC_ACCESS_ADDR,
7070 page_to_phys(vmx->nested.apic_access_page));
7071 }
7072
7073 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7074 }
7075
7076
7077 /*
7078 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7079 * Some constant fields are set here by vmx_set_constant_host_state().
7080 * Other fields are different per CPU, and will be set later when
7081 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7082 */
7083 vmx_set_constant_host_state();
7084
7085 /*
7086 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7087 * entry, but only if the current (host) sp changed from the value
7088 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7089 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7090 * here we just force the write to happen on entry.
7091 */
7092 vmx->host_rsp = 0;
7093
7094 exec_control = vmx_exec_control(vmx); /* L0's desires */
7095 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7096 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7097 exec_control &= ~CPU_BASED_TPR_SHADOW;
7098 exec_control |= vmcs12->cpu_based_vm_exec_control;
7099 /*
7100 * Merging of IO and MSR bitmaps not currently supported.
7101 * Rather, exit every time.
7102 */
7103 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7104 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7105 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7106
7107 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7108
7109 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7110 * bitwise-or of what L1 wants to trap for L2, and what we want to
7111 * trap. Note that CR0.TS also needs updating - we do this later.
7112 */
7113 update_exception_bitmap(vcpu);
7114 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7115 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7116
7117 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7118 vmcs_write32(VM_EXIT_CONTROLS,
7119 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7120 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7121 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7122
7123 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7124 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7125 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7126 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7127
7128
7129 set_cr4_guest_host_mask(vmx);
7130
27fc51b2
NHE		 7131 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7132 vmcs_write64(TSC_OFFSET,
7133 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7134 else
7135 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7136
7137 if (enable_vpid) {
7138 /*
7139 * Trivially support vpid by letting L2s share their parent
7140 * L1's vpid. TODO: move to a more elaborate solution, giving
7141 * each L2 its own vpid and exposing the vpid feature to L1.
7142 */
7143 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7144 vmx_flush_tlb(vcpu);
7145 }
7146
7147 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7148 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7149 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7150 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7151 else
7152 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7153 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7154 vmx_set_efer(vcpu, vcpu->arch.efer);
7155
7156 /*
7157 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7158 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7159 * The CR0_READ_SHADOW is what L2 should have expected to read given
7160 * the specifications by L1; It's not enough to take
7161 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7162 * have more bits than L1 expected.
7163 */
7164 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7165 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7166
7167 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7168 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7169
7170 /* shadow page tables on either EPT or shadow page tables */
7171 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7172 kvm_mmu_reset_context(vcpu);
7173
7174 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7175 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7176}
7177
cd232ad0
NHE		 7178/*
7179 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7180 * for running an L2 nested guest.
7181 */
7182static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7183{
7184 struct vmcs12 *vmcs12;
7185 struct vcpu_vmx *vmx = to_vmx(vcpu);
7186 int cpu;
7187 struct loaded_vmcs *vmcs02;
7188
7189 if (!nested_vmx_check_permission(vcpu) ||
7190 !nested_vmx_check_vmcs12(vcpu))
7191 return 1;
7192
7193 skip_emulated_instruction(vcpu);
7194 vmcs12 = get_vmcs12(vcpu);
7195
7c177938
NHE		 7196 /*
7197 * The nested entry process starts with enforcing various prerequisites
7198 * on vmcs12 as required by the Intel SDM, and act appropriately when
7199 * they fail: As the SDM explains, some conditions should cause the
7200 * instruction to fail, while others will cause the instruction to seem
7201 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7202 * To speed up the normal (success) code path, we should avoid checking
7203 * for misconfigurations which will anyway be caught by the processor
7204 * when using the merged vmcs02.
7205 */
7206 if (vmcs12->launch_state == launch) {
7207 nested_vmx_failValid(vcpu,
7208 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7209 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7210 return 1;
7211 }
7212
7213 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7214 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7215 /*TODO: Also verify bits beyond physical address width are 0*/
7216 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7217 return 1;
7218 }
7219
7220 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7221 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7222 /*TODO: Also verify bits beyond physical address width are 0*/
7223 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7224 return 1;
7225 }
7226
7227 if (vmcs12->vm_entry_msr_load_count > 0 ||
7228 vmcs12->vm_exit_msr_load_count > 0 ||
7229 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7230 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7231 __func__);
7c177938
NHE		 7232 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7233 return 1;
7234 }
7235
7236 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7237 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7238 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7239 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7240 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7241 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7242 !vmx_control_verify(vmcs12->vm_exit_controls,
7243 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7244 !vmx_control_verify(vmcs12->vm_entry_controls,
7245 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7246 {
7247 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7248 return 1;
7249 }
7250
7251 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7252 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7253 nested_vmx_failValid(vcpu,
7254 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7255 return 1;
7256 }
7257
7258 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7259 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7260 nested_vmx_entry_failure(vcpu, vmcs12,
7261 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7262 return 1;
7263 }
7264 if (vmcs12->vmcs_link_pointer != -1ull) {
7265 nested_vmx_entry_failure(vcpu, vmcs12,
7266 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7267 return 1;
7268 }
7269
7270 /*
7271 * We're finally done with prerequisite checking, and can start with
7272 * the nested entry.
7273 */
7274
cd232ad0
NHE		 7275 vmcs02 = nested_get_current_vmcs02(vmx);
7276 if (!vmcs02)
7277 return -ENOMEM;
7278
7279 enter_guest_mode(vcpu);
7280
7281 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7282
7283 cpu = get_cpu();
7284 vmx->loaded_vmcs = vmcs02;
7285 vmx_vcpu_put(vcpu);
7286 vmx_vcpu_load(vcpu, cpu);
7287 vcpu->cpu = cpu;
7288 put_cpu();
7289
36c3cc42
JK		 7290 vmx_segment_cache_clear(vmx);
7291
cd232ad0
NHE		 7292 vmcs12->launch_state = 1;
7293
7294 prepare_vmcs02(vcpu, vmcs12);
7295
7296 /*
7297 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7298 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7299 * returned as far as L1 is concerned. It will only return (and set
7300 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7301 */
7302 return 1;
7303}
7304
4704d0be
NHE		 7305/*
7306 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7307 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7308 * This function returns the new value we should put in vmcs12.guest_cr0.
7309 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7310 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7311 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7312 * didn't trap the bit, because if L1 did, so would L0).
7313 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7314 * been modified by L2, and L1 knows it. So just leave the old value of
7315 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7316 * isn't relevant, because if L0 traps this bit it can set it to anything.
7317 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7318 * changed these bits, and therefore they need to be updated, but L0
7319 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7320 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7321 */
7322static inline unsigned long
7323vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7324{
7325 return
7326 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7327 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7328 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7329 vcpu->arch.cr0_guest_owned_bits));
7330}
7331
7332static inline unsigned long
7333vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7334{
7335 return
7336 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7337 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7338 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7339 vcpu->arch.cr4_guest_owned_bits));
7340}
7341
7342/*
7343 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7344 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7345 * and this function updates it to reflect the changes to the guest state while
7346 * L2 was running (and perhaps made some exits which were handled directly by L0
7347 * without going back to L1), and to reflect the exit reason.
7348 * Note that we do not have to copy here all VMCS fields, just those that
7349 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7350 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7351 * which already writes to vmcs12 directly.
7352 */
733568f9 7353static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7354{
7355 /* update guest state fields: */
7356 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7357 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7358
7359 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7360 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7361 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7362 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7363
7364 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7365 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7366 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7367 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7368 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7369 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7370 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7371 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7372 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7373 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7374 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7375 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7376 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7377 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7378 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7379 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7380 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7381 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7382 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7383 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7384 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7385 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7386 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7387 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7388 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7389 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7390 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7391 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7392 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7393 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7394 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7395 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7396 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7397 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7398 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7399 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7400
7401 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7402 vmcs12->guest_interruptibility_info =
7403 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7404 vmcs12->guest_pending_dbg_exceptions =
7405 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7406
7407 /* TODO: These cannot have changed unless we have MSR bitmaps and
7408 * the relevant bit asks not to trap the change */
7409 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7410 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7411 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7412 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7413 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7414 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7415
7416 /* update exit information fields: */
7417
957c897e 7418 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7419 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7420
7421 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7422 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
44ceb9d6 7423 vmcs12->idt_vectoring_info_field = to_vmx(vcpu)->idt_vectoring_info;
4704d0be
NHE		 7424 vmcs12->idt_vectoring_error_code =
7425 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7426 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7427 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7428
7429 /* clear vm-entry fields which are to be cleared on exit */
7430 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7431 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7432}
7433
7434/*
7435 * A part of what we need to when the nested L2 guest exits and we want to
7436 * run its L1 parent, is to reset L1's guest state to the host state specified
7437 * in vmcs12.
7438 * This function is to be called not only on normal nested exit, but also on
7439 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7440 * Failures During or After Loading Guest State").
7441 * This function should be called when the active VMCS is L1's (vmcs01).
7442 */
733568f9
JK		 7443static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7444 struct vmcs12 *vmcs12)
4704d0be
NHE		 7445{
7446 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7447 vcpu->arch.efer = vmcs12->host_ia32_efer;
7448 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7449 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7450 else
7451 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7452 vmx_set_efer(vcpu, vcpu->arch.efer);
7453
7454 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7455 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7456 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7457 /*
7458 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7459 * actually changed, because it depends on the current state of
7460 * fpu_active (which may have changed).
7461 * Note that vmx_set_cr0 refers to efer set above.
7462 */
7463 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7464 /*
7465 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7466 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7467 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7468 */
7469 update_exception_bitmap(vcpu);
7470 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7471 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7472
7473 /*
7474 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7475 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7476 */
7477 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7478 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7479
7480 /* shadow page tables on either EPT or shadow page tables */
7481 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7482 kvm_mmu_reset_context(vcpu);
7483
7484 if (enable_vpid) {
7485 /*
7486 * Trivially support vpid by letting L2s share their parent
7487 * L1's vpid. TODO: move to a more elaborate solution, giving
7488 * each L2 its own vpid and exposing the vpid feature to L1.
7489 */
7490 vmx_flush_tlb(vcpu);
7491 }
7492
7493
7494 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7495 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7496 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7497 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7498 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7499 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7500 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7501 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7502 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7503 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7504 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7505 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7506 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7507 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7508 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7509
7510 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7511 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7512 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7513 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7514 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7515
7516 kvm_set_dr(vcpu, 7, 0x400);
7517 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7518}
7519
7520/*
7521 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7522 * and modify vmcs12 to make it see what it would expect to see there if
7523 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7524 */
7525static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7526{
7527 struct vcpu_vmx *vmx = to_vmx(vcpu);
7528 int cpu;
7529 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7530
7531 leave_guest_mode(vcpu);
7532 prepare_vmcs12(vcpu, vmcs12);
7533
7534 cpu = get_cpu();
7535 vmx->loaded_vmcs = &vmx->vmcs01;
7536 vmx_vcpu_put(vcpu);
7537 vmx_vcpu_load(vcpu, cpu);
7538 vcpu->cpu = cpu;
7539 put_cpu();
7540
36c3cc42
JK		 7541 vmx_segment_cache_clear(vmx);
7542
4704d0be
NHE		 7543 /* if no vmcs02 cache requested, remove the one we used */
7544 if (VMCS02_POOL_SIZE == 0)
7545 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7546
7547 load_vmcs12_host_state(vcpu, vmcs12);
7548
27fc51b2 7549 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7550 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7551
7552 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7553 vmx->host_rsp = 0;
7554
7555 /* Unpin physical memory we referred to in vmcs02 */
7556 if (vmx->nested.apic_access_page) {
7557 nested_release_page(vmx->nested.apic_access_page);
7558 vmx->nested.apic_access_page = 0;
7559 }
7560
7561 /*
7562 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7563 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7564 * success or failure flag accordingly.
7565 */
7566 if (unlikely(vmx->fail)) {
7567 vmx->fail = 0;
7568 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7569 } else
7570 nested_vmx_succeed(vcpu);
7571}
7572
7c177938
NHE		 7573/*
7574 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7575 * 23.7 "VM-entry failures during or after loading guest state" (this also
7576 * lists the acceptable exit-reason and exit-qualification parameters).
7577 * It should only be called before L2 actually succeeded to run, and when
7578 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7579 */
7580static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7581 struct vmcs12 *vmcs12,
7582 u32 reason, unsigned long qualification)
7583{
7584 load_vmcs12_host_state(vcpu, vmcs12);
7585 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7586 vmcs12->exit_qualification = qualification;
7587 nested_vmx_succeed(vcpu);
7588}
7589
8a76d7f2
JR		 7590static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7591 struct x86_instruction_info *info,
7592 enum x86_intercept_stage stage)
7593{
7594 return X86EMUL_CONTINUE;
7595}
7596
cbdd1bea 7597static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7598 .cpu_has_kvm_support = cpu_has_kvm_support,
7599 .disabled_by_bios = vmx_disabled_by_bios,
7600 .hardware_setup = hardware_setup,
7601 .hardware_unsetup = hardware_unsetup,
002c7f7c 7602 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7603 .hardware_enable = hardware_enable,
7604 .hardware_disable = hardware_disable,
04547156 7605 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7606
7607 .vcpu_create = vmx_create_vcpu,
7608 .vcpu_free = vmx_free_vcpu,
04d2cc77 7609 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7610
04d2cc77 7611 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7612 .vcpu_load = vmx_vcpu_load,
7613 .vcpu_put = vmx_vcpu_put,
7614
c8639010 7615 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7616 .get_msr = vmx_get_msr,
7617 .set_msr = vmx_set_msr,
7618 .get_segment_base = vmx_get_segment_base,
7619 .get_segment = vmx_get_segment,
7620 .set_segment = vmx_set_segment,
2e4d2653 7621 .get_cpl = vmx_get_cpl,
6aa8b732 7622 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7623 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7624 .decache_cr3 = vmx_decache_cr3,
25c4c276 7625 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7626 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7627 .set_cr3 = vmx_set_cr3,
7628 .set_cr4 = vmx_set_cr4,
6aa8b732 7629 .set_efer = vmx_set_efer,
6aa8b732
AK		 7630 .get_idt = vmx_get_idt,
7631 .set_idt = vmx_set_idt,
7632 .get_gdt = vmx_get_gdt,
7633 .set_gdt = vmx_set_gdt,
020df079 7634 .set_dr7 = vmx_set_dr7,
5fdbf976 7635 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7636 .get_rflags = vmx_get_rflags,
7637 .set_rflags = vmx_set_rflags,
ebcbab4c 7638 .fpu_activate = vmx_fpu_activate,
02daab21 7639 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7640
7641 .tlb_flush = vmx_flush_tlb,
6aa8b732 7642
6aa8b732 7643 .run = vmx_vcpu_run,
6062d012 7644 .handle_exit = vmx_handle_exit,
6aa8b732 7645 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7646 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7647 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7648 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7649 .set_irq = vmx_inject_irq,
95ba8273 7650 .set_nmi = vmx_inject_nmi,
298101da 7651 .queue_exception = vmx_queue_exception,
b463a6f7 7652 .cancel_injection = vmx_cancel_injection,
78646121 7653 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7654 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7655 .get_nmi_mask = vmx_get_nmi_mask,
7656 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7657 .enable_nmi_window = enable_nmi_window,
7658 .enable_irq_window = enable_irq_window,
7659 .update_cr8_intercept = update_cr8_intercept,
8d14695f 7660 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 7661 .vm_has_apicv = vmx_vm_has_apicv,
7662 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7663 .hwapic_irr_update = vmx_hwapic_irr_update,
7664 .hwapic_isr_update = vmx_hwapic_isr_update,
95ba8273 7665
cbc94022 7666 .set_tss_addr = vmx_set_tss_addr,
67253af5 7667 .get_tdp_level = get_ept_level,
4b12f0de 7668 .get_mt_mask = vmx_get_mt_mask,
229456fc 7669
586f9607 7670 .get_exit_info = vmx_get_exit_info,
586f9607 7671
17cc3935 7672 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7673
7674 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7675
7676 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7677 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7678
7679 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7680
7681 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7682
4051b188 7683 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7684 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7685 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7686 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7687 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7688 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7689
7690 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7691
7692 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7693};
7694
7695static int __init vmx_init(void)
7696{
8d14695f 7697 int r, i, msr;
26bb0981
AK		 7698
7699 rdmsrl_safe(MSR_EFER, &host_efer);
7700
7701 for (i = 0; i < NR_VMX_MSR; ++i)
7702 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7703
3e7c73e9 7704 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7705 if (!vmx_io_bitmap_a)
7706 return -ENOMEM;
7707
2106a548
GC		 7708 r = -ENOMEM;
7709
3e7c73e9 7710 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7711 if (!vmx_io_bitmap_b)
fdef3ad1 7712 goto out;
fdef3ad1 7713
5897297b 7714 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7715 if (!vmx_msr_bitmap_legacy)
25c5f225 7716 goto out1;
2106a548 7717
8d14695f
YZ		 7718 vmx_msr_bitmap_legacy_x2apic =
7719 (unsigned long *)__get_free_page(GFP_KERNEL);
7720 if (!vmx_msr_bitmap_legacy_x2apic)
7721 goto out2;
25c5f225 7722
5897297b 7723 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7724 if (!vmx_msr_bitmap_longmode)
8d14695f 7725 goto out3;
2106a548 7726
8d14695f
YZ		 7727 vmx_msr_bitmap_longmode_x2apic =
7728 (unsigned long *)__get_free_page(GFP_KERNEL);
7729 if (!vmx_msr_bitmap_longmode_x2apic)
7730 goto out4;
5897297b 7731
fdef3ad1
HQ		 7732 /*
7733 * Allow direct access to the PC debug port (it is often used for I/O
7734 * delays, but the vmexits simply slow things down).
7735 */
3e7c73e9
AK		 7736 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7737 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7738
3e7c73e9 7739 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7740
5897297b
AK		 7741 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7742 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7743
2384d2b3
SY		 7744 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7745
0ee75bea
AK		 7746 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7747 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7748 if (r)
5897297b 7749 goto out3;
25c5f225 7750
8f536b76
ZY		 7751#ifdef CONFIG_KEXEC
7752 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7753 crash_vmclear_local_loaded_vmcss);
7754#endif
7755
5897297b
AK		 7756 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7757 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7758 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7759 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7760 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7761 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 7762 memcpy(vmx_msr_bitmap_legacy_x2apic,
7763 vmx_msr_bitmap_legacy, PAGE_SIZE);
7764 memcpy(vmx_msr_bitmap_longmode_x2apic,
7765 vmx_msr_bitmap_longmode, PAGE_SIZE);
7766
c7c9c56c 7767 if (enable_apicv_reg_vid) {
8d14695f
YZ		 7768 for (msr = 0x800; msr <= 0x8ff; msr++)
7769 vmx_disable_intercept_msr_read_x2apic(msr);
7770
7771 /* According SDM, in x2apic mode, the whole id reg is used.
7772 * But in KVM, it only use the highest eight bits. Need to
7773 * intercept it */
7774 vmx_enable_intercept_msr_read_x2apic(0x802);
7775 /* TMCCT */
7776 vmx_enable_intercept_msr_read_x2apic(0x839);
7777 /* TPR */
7778 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 7779 /* EOI */
7780 vmx_disable_intercept_msr_write_x2apic(0x80b);
7781 /* SELF-IPI */
7782 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 7783 }
fdef3ad1 7784
089d034e 7785 if (enable_ept) {
3f6d8c8a
XH		 7786 kvm_mmu_set_mask_ptes(0ull,
7787 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7788 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7789 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7790 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7791 kvm_enable_tdp();
7792 } else
7793 kvm_disable_tdp();
1439442c 7794
fdef3ad1
HQ		 7795 return 0;
7796
8d14695f 7797out4:
5897297b 7798 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 7799out3:
7800 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 7801out2:
5897297b 7802 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7803out1:
3e7c73e9 7804 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7805out:
3e7c73e9 7806 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7807 return r;
6aa8b732
AK		 7808}
7809
7810static void __exit vmx_exit(void)
7811{
8d14695f
YZ		 7812 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7813 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 7814 free_page((unsigned long)vmx_msr_bitmap_legacy);
7815 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7816 free_page((unsigned long)vmx_io_bitmap_b);
7817 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7818
8f536b76
ZY		 7819#ifdef CONFIG_KEXEC
7820 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7821 synchronize_rcu();
7822#endif
7823
cb498ea2 7824 kvm_exit();
6aa8b732
AK		 7825}
7826
7827module_init(vmx_init)
7828module_exit(vmx_exit)
Linux kernel - Deliverables
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