projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: use linux/uaccess.h instead of asm/uaccess.h
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
6aa8b732 40
229456fc
MT		 41#include "trace.h"
42
4ecac3fd
AK		 43#define __ex(x) __kvm_handle_fault_on_reboot(x)
44
6aa8b732
AK		 45MODULE_AUTHOR("Qumranet");
46MODULE_LICENSE("GPL");
47
4462d21a 48static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 49module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 50
4462d21a 51static int __read_mostly enable_vpid = 1;
736caefe 52module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 53
4462d21a 54static int __read_mostly flexpriority_enabled = 1;
736caefe 55module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 56
4462d21a 57static int __read_mostly enable_ept = 1;
736caefe 58module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 59
3a624e29
NK		 60static int __read_mostly enable_unrestricted_guest = 1;
61module_param_named(unrestricted_guest,
62 enable_unrestricted_guest, bool, S_IRUGO);
63
4462d21a 64static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 65module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 66
b923e62e
DX		 67static int __read_mostly vmm_exclusive = 1;
68module_param(vmm_exclusive, bool, S_IRUGO);
69
cdc0e244
AK		 70#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
71 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
72#define KVM_GUEST_CR0_MASK \
73 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
74#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 75 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 76#define KVM_VM_CR0_ALWAYS_ON \
77 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 78#define KVM_CR4_GUEST_OWNED_BITS \
79 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
80 | X86_CR4_OSXMMEXCPT)
81
cdc0e244
AK		 82#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
83#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
84
78ac8b47
AK		 85#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
86
4b8d54f9
ZE		 87/*
88 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
89 * ple_gap: upper bound on the amount of time between two successive
90 * executions of PAUSE in a loop. Also indicate if ple enabled.
91 * According to test, this time is usually small than 41 cycles.
92 * ple_window: upper bound on the amount of time a guest is allowed to execute
93 * in a PAUSE loop. Tests indicate that most spinlocks are held for
94 * less than 2^12 cycles
95 * Time is measured based on a counter that runs at the same rate as the TSC,
96 * refer SDM volume 3b section 21.6.13 & 22.1.3.
97 */
98#define KVM_VMX_DEFAULT_PLE_GAP 41
99#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
100static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
101module_param(ple_gap, int, S_IRUGO);
102
103static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
104module_param(ple_window, int, S_IRUGO);
105
61d2ef2c
AK		 106#define NR_AUTOLOAD_MSRS 1
107
a2fa3e9f
GH		 108struct vmcs {
109 u32 revision_id;
110 u32 abort;
111 char data[0];
112};
113
26bb0981
AK		 114struct shared_msr_entry {
115 unsigned index;
116 u64 data;
d5696725 117 u64 mask;
26bb0981
AK		 118};
119
a2fa3e9f 120struct vcpu_vmx {
fb3f0f51 121 struct kvm_vcpu vcpu;
543e4243 122 struct list_head local_vcpus_link;
313dbd49 123 unsigned long host_rsp;
a2fa3e9f 124 int launched;
29bd8a78 125 u8 fail;
1155f76a 126 u32 idt_vectoring_info;
26bb0981 127 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 128 int nmsrs;
129 int save_nmsrs;
a2fa3e9f 130#ifdef CONFIG_X86_64
44ea2b17
AK		 131 u64 msr_host_kernel_gs_base;
132 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 133#endif
134 struct vmcs *vmcs;
61d2ef2c
AK		 135 struct msr_autoload {
136 unsigned nr;
137 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
138 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
139 } msr_autoload;
a2fa3e9f
GH		 140 struct {
141 int loaded;
142 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 143 int gs_ldt_reload_needed;
144 int fs_reload_needed;
d77c26fc 145 } host_state;
9c8cba37 146 struct {
7ffd92c5 147 int vm86_active;
78ac8b47 148 ulong save_rflags;
7ffd92c5
AK		 149 struct kvm_save_segment {
150 u16 selector;
151 unsigned long base;
152 u32 limit;
153 u32 ar;
154 } tr, es, ds, fs, gs;
9c8cba37
AK		 155 struct {
156 bool pending;
157 u8 vector;
158 unsigned rip;
159 } irq;
160 } rmode;
2384d2b3 161 int vpid;
04fa4d32 162 bool emulation_required;
3b86cd99
JK		 163
164 /* Support for vnmi-less CPUs */
165 int soft_vnmi_blocked;
166 ktime_t entry_time;
167 s64 vnmi_blocked_time;
a0861c02 168 u32 exit_reason;
4e47c7a6
SY		 169
170 bool rdtscp_enabled;
a2fa3e9f
GH		 171};
172
173static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 176}
177
b7ebfb05 178static int init_rmode(struct kvm *kvm);
4e1096d2 179static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 180static void kvm_cpu_vmxon(u64 addr);
181static void kvm_cpu_vmxoff(void);
75880a01 182
6aa8b732
AK		 183static DEFINE_PER_CPU(struct vmcs *, vmxarea);
184static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 185static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 186
3e7c73e9
AK		 187static unsigned long *vmx_io_bitmap_a;
188static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 189static unsigned long *vmx_msr_bitmap_legacy;
190static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 191
2384d2b3
SY		 192static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
193static DEFINE_SPINLOCK(vmx_vpid_lock);
194
1c3d14fe 195static struct vmcs_config {
6aa8b732
AK		 196 int size;
197 int order;
198 u32 revision_id;
1c3d14fe
YS		 199 u32 pin_based_exec_ctrl;
200 u32 cpu_based_exec_ctrl;
f78e0e2e 201 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 202 u32 vmexit_ctrl;
203 u32 vmentry_ctrl;
204} vmcs_config;
6aa8b732 205
efff9e53 206static struct vmx_capability {
d56f546d
SY		 207 u32 ept;
208 u32 vpid;
209} vmx_capability;
210
6aa8b732
AK		 211#define VMX_SEGMENT_FIELD(seg) \
212 [VCPU_SREG_##seg] = { \
213 .selector = GUEST_##seg##_SELECTOR, \
214 .base = GUEST_##seg##_BASE, \
215 .limit = GUEST_##seg##_LIMIT, \
216 .ar_bytes = GUEST_##seg##_AR_BYTES, \
217 }
218
219static struct kvm_vmx_segment_field {
220 unsigned selector;
221 unsigned base;
222 unsigned limit;
223 unsigned ar_bytes;
224} kvm_vmx_segment_fields[] = {
225 VMX_SEGMENT_FIELD(CS),
226 VMX_SEGMENT_FIELD(DS),
227 VMX_SEGMENT_FIELD(ES),
228 VMX_SEGMENT_FIELD(FS),
229 VMX_SEGMENT_FIELD(GS),
230 VMX_SEGMENT_FIELD(SS),
231 VMX_SEGMENT_FIELD(TR),
232 VMX_SEGMENT_FIELD(LDTR),
233};
234
26bb0981
AK		 235static u64 host_efer;
236
6de4f3ad
AK		 237static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
238
4d56c8a7
AK		 239/*
240 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
241 * away by decrementing the array size.
242 */
6aa8b732 243static const u32 vmx_msr_index[] = {
05b3e0c2 244#ifdef CONFIG_X86_64
44ea2b17 245 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 246#endif
4e47c7a6 247 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 248};
9d8f549d 249#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 250
31299944 251static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 256}
257
31299944 258static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
261 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 262 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 263}
264
31299944 265static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 266{
267 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
268 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 269 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 270}
271
31299944 272static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 273{
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
275 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
276}
277
31299944 278static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 279{
280 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
281 INTR_INFO_VALID_MASK)) ==
282 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
283}
284
31299944 285static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 286{
04547156 287 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 288}
289
31299944 290static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 291{
04547156 292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 293}
294
31299944 295static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 296{
04547156 297 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 298}
299
31299944 300static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 301{
04547156
SY		 302 return vmcs_config.cpu_based_exec_ctrl &
303 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 304}
305
774ead3a 306static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 307{
04547156
SY		 308 return vmcs_config.cpu_based_2nd_exec_ctrl &
309 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
310}
311
312static inline bool cpu_has_vmx_flexpriority(void)
313{
314 return cpu_has_vmx_tpr_shadow() &&
315 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 316}
317
e799794e
MT		 318static inline bool cpu_has_vmx_ept_execute_only(void)
319{
31299944 320 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 321}
322
323static inline bool cpu_has_vmx_eptp_uncacheable(void)
324{
31299944 325 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 326}
327
328static inline bool cpu_has_vmx_eptp_writeback(void)
329{
31299944 330 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 331}
332
333static inline bool cpu_has_vmx_ept_2m_page(void)
334{
31299944 335 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 336}
337
878403b7
SY		 338static inline bool cpu_has_vmx_ept_1g_page(void)
339{
31299944 340 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 341}
342
4bc9b982
SY		 343static inline bool cpu_has_vmx_ept_4levels(void)
344{
345 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
346}
347
31299944 348static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 349{
31299944 350 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 351}
352
31299944 353static inline bool cpu_has_vmx_invept_context(void)
d56f546d 354{
31299944 355 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_invept_global(void)
d56f546d 359{
31299944 360 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 361}
362
31299944 363static inline bool cpu_has_vmx_ept(void)
d56f546d 364{
04547156
SY		 365 return vmcs_config.cpu_based_2nd_exec_ctrl &
366 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 367}
368
31299944 369static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 370{
371 return vmcs_config.cpu_based_2nd_exec_ctrl &
372 SECONDARY_EXEC_UNRESTRICTED_GUEST;
373}
374
31299944 375static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 376{
377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
379}
380
31299944 381static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 382{
6d3e435e 383 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 384}
385
31299944 386static inline bool cpu_has_vmx_vpid(void)
2384d2b3 387{
04547156
SY		 388 return vmcs_config.cpu_based_2nd_exec_ctrl &
389 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 390}
391
31299944 392static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 393{
394 return vmcs_config.cpu_based_2nd_exec_ctrl &
395 SECONDARY_EXEC_RDTSCP;
396}
397
31299944 398static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 399{
400 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
401}
402
04547156
SY		 403static inline bool report_flexpriority(void)
404{
405 return flexpriority_enabled;
406}
407
8b9cf98c 408static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 409{
410 int i;
411
a2fa3e9f 412 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 413 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 414 return i;
415 return -1;
416}
417
2384d2b3
SY		 418static inline void __invvpid(int ext, u16 vpid, gva_t gva)
419{
420 struct {
421 u64 vpid : 16;
422 u64 rsvd : 48;
423 u64 gva;
424 } operand = { vpid, 0, gva };
425
4ecac3fd 426 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 427 /* CF==1 or ZF==1 --> rc = -1 */
428 "; ja 1f ; ud2 ; 1:"
429 : : "a"(&operand), "c"(ext) : "cc", "memory");
430}
431
1439442c
SY		 432static inline void __invept(int ext, u64 eptp, gpa_t gpa)
433{
434 struct {
435 u64 eptp, gpa;
436 } operand = {eptp, gpa};
437
4ecac3fd 438 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 439 /* CF==1 or ZF==1 --> rc = -1 */
440 "; ja 1f ; ud2 ; 1:\n"
441 : : "a" (&operand), "c" (ext) : "cc", "memory");
442}
443
26bb0981 444static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 445{
446 int i;
447
8b9cf98c 448 i = __find_msr_index(vmx, msr);
a75beee6 449 if (i >= 0)
a2fa3e9f 450 return &vmx->guest_msrs[i];
8b6d44c7 451 return NULL;
7725f0ba
AK		 452}
453
6aa8b732
AK		 454static void vmcs_clear(struct vmcs *vmcs)
455{
456 u64 phys_addr = __pa(vmcs);
457 u8 error;
458
4ecac3fd 459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 460 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
461 : "cc", "memory");
462 if (error)
463 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
464 vmcs, phys_addr);
465}
466
7725b894
DX		 467static void vmcs_load(struct vmcs *vmcs)
468{
469 u64 phys_addr = __pa(vmcs);
470 u8 error;
471
472 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
473 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
474 : "cc", "memory");
475 if (error)
476 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
477 vmcs, phys_addr);
478}
479
6aa8b732
AK		 480static void __vcpu_clear(void *arg)
481{
8b9cf98c 482 struct vcpu_vmx *vmx = arg;
d3b2c338 483 int cpu = raw_smp_processor_id();
6aa8b732 484
8b9cf98c 485 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 486 vmcs_clear(vmx->vmcs);
487 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 488 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 489 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 490 list_del(&vmx->local_vcpus_link);
491 vmx->vcpu.cpu = -1;
492 vmx->launched = 0;
6aa8b732
AK		 493}
494
8b9cf98c 495static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 496{
eae5ecb5
AK		 497 if (vmx->vcpu.cpu == -1)
498 return;
8691e5a8 499 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 500}
501
2384d2b3
SY		 502static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
503{
504 if (vmx->vpid == 0)
505 return;
506
507 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
508}
509
1439442c
SY		 510static inline void ept_sync_global(void)
511{
512 if (cpu_has_vmx_invept_global())
513 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
514}
515
516static inline void ept_sync_context(u64 eptp)
517{
089d034e 518 if (enable_ept) {
1439442c
SY		 519 if (cpu_has_vmx_invept_context())
520 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
521 else
522 ept_sync_global();
523 }
524}
525
526static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
527{
089d034e 528 if (enable_ept) {
1439442c
SY		 529 if (cpu_has_vmx_invept_individual_addr())
530 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
531 eptp, gpa);
532 else
533 ept_sync_context(eptp);
534 }
535}
536
6aa8b732
AK		 537static unsigned long vmcs_readl(unsigned long field)
538{
539 unsigned long value;
540
4ecac3fd 541 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 542 : "=a"(value) : "d"(field) : "cc");
543 return value;
544}
545
546static u16 vmcs_read16(unsigned long field)
547{
548 return vmcs_readl(field);
549}
550
551static u32 vmcs_read32(unsigned long field)
552{
553 return vmcs_readl(field);
554}
555
556static u64 vmcs_read64(unsigned long field)
557{
05b3e0c2 558#ifdef CONFIG_X86_64
6aa8b732
AK		 559 return vmcs_readl(field);
560#else
561 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
562#endif
563}
564
e52de1b8
AK		 565static noinline void vmwrite_error(unsigned long field, unsigned long value)
566{
567 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
568 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
569 dump_stack();
570}
571
6aa8b732
AK		 572static void vmcs_writel(unsigned long field, unsigned long value)
573{
574 u8 error;
575
4ecac3fd 576 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 577 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 578 if (unlikely(error))
579 vmwrite_error(field, value);
6aa8b732
AK		 580}
581
582static void vmcs_write16(unsigned long field, u16 value)
583{
584 vmcs_writel(field, value);
585}
586
587static void vmcs_write32(unsigned long field, u32 value)
588{
589 vmcs_writel(field, value);
590}
591
592static void vmcs_write64(unsigned long field, u64 value)
593{
6aa8b732 594 vmcs_writel(field, value);
7682f2d0 595#ifndef CONFIG_X86_64
6aa8b732
AK		 596 asm volatile ("");
597 vmcs_writel(field+1, value >> 32);
598#endif
599}
600
2ab455cc
AL		 601static void vmcs_clear_bits(unsigned long field, u32 mask)
602{
603 vmcs_writel(field, vmcs_readl(field) & ~mask);
604}
605
606static void vmcs_set_bits(unsigned long field, u32 mask)
607{
608 vmcs_writel(field, vmcs_readl(field) | mask);
609}
610
abd3f2d6
AK		 611static void update_exception_bitmap(struct kvm_vcpu *vcpu)
612{
613 u32 eb;
614
fd7373cc
JK		 615 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
616 (1u << NM_VECTOR) | (1u << DB_VECTOR);
617 if ((vcpu->guest_debug &
618 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
619 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
620 eb |= 1u << BP_VECTOR;
7ffd92c5 621 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 622 eb = ~0;
089d034e 623 if (enable_ept)
1439442c 624 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 625 if (vcpu->fpu_active)
626 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 627 vmcs_write32(EXCEPTION_BITMAP, eb);
628}
629
61d2ef2c
AK		 630static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
631{
632 unsigned i;
633 struct msr_autoload *m = &vmx->msr_autoload;
634
635 for (i = 0; i < m->nr; ++i)
636 if (m->guest[i].index == msr)
637 break;
638
639 if (i == m->nr)
640 return;
641 --m->nr;
642 m->guest[i] = m->guest[m->nr];
643 m->host[i] = m->host[m->nr];
644 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
645 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
646}
647
648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
649 u64 guest_val, u64 host_val)
650{
651 unsigned i;
652 struct msr_autoload *m = &vmx->msr_autoload;
653
654 for (i = 0; i < m->nr; ++i)
655 if (m->guest[i].index == msr)
656 break;
657
658 if (i == m->nr) {
659 ++m->nr;
660 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
661 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
662 }
663
664 m->guest[i].index = msr;
665 m->guest[i].value = guest_val;
666 m->host[i].index = msr;
667 m->host[i].value = host_val;
668}
669
33ed6329
AK		 670static void reload_tss(void)
671{
33ed6329
AK		 672 /*
673 * VT restores TR but not its size. Useless.
674 */
89a27f4d 675 struct desc_ptr gdt;
a5f61300 676 struct desc_struct *descs;
33ed6329 677
d6ab1ed4 678 native_store_gdt(&gdt);
89a27f4d 679 descs = (void *)gdt.address;
33ed6329
AK		 680 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
681 load_TR_desc();
33ed6329
AK		 682}
683
92c0d900 684static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 685{
3a34a881 686 u64 guest_efer;
51c6cf66
AK		 687 u64 ignore_bits;
688
f6801dff 689 guest_efer = vmx->vcpu.arch.efer;
3a34a881 690
51c6cf66
AK		 691 /*
692 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
693 * outside long mode
694 */
695 ignore_bits = EFER_NX | EFER_SCE;
696#ifdef CONFIG_X86_64
697 ignore_bits |= EFER_LMA | EFER_LME;
698 /* SCE is meaningful only in long mode on Intel */
699 if (guest_efer & EFER_LMA)
700 ignore_bits &= ~(u64)EFER_SCE;
701#endif
51c6cf66
AK		 702 guest_efer &= ~ignore_bits;
703 guest_efer |= host_efer & ignore_bits;
26bb0981 704 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 705 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 706
707 clear_atomic_switch_msr(vmx, MSR_EFER);
708 /* On ept, can't emulate nx, and must switch nx atomically */
709 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
710 guest_efer = vmx->vcpu.arch.efer;
711 if (!(guest_efer & EFER_LMA))
712 guest_efer &= ~EFER_LME;
713 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
714 return false;
715 }
716
26bb0981 717 return true;
51c6cf66
AK		 718}
719
2d49ec72
GN		 720static unsigned long segment_base(u16 selector)
721{
722 struct desc_ptr gdt;
723 struct desc_struct *d;
724 unsigned long table_base;
725 unsigned long v;
726
727 if (!(selector & ~3))
728 return 0;
729
730 native_store_gdt(&gdt);
731 table_base = gdt.address;
732
733 if (selector & 4) { /* from ldt */
734 u16 ldt_selector = kvm_read_ldt();
735
736 if (!(ldt_selector & ~3))
737 return 0;
738
739 table_base = segment_base(ldt_selector);
740 }
741 d = (struct desc_struct *)(table_base + (selector & ~7));
742 v = get_desc_base(d);
743#ifdef CONFIG_X86_64
744 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
745 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
746#endif
747 return v;
748}
749
750static inline unsigned long kvm_read_tr_base(void)
751{
752 u16 tr;
753 asm("str %0" : "=g"(tr));
754 return segment_base(tr);
755}
756
04d2cc77 757static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 758{
04d2cc77 759 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 760 int i;
04d2cc77 761
a2fa3e9f 762 if (vmx->host_state.loaded)
33ed6329
AK		 763 return;
764
a2fa3e9f 765 vmx->host_state.loaded = 1;
33ed6329
AK		 766 /*
767 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
768 * allow segment selectors with cpl > 0 or ti == 1.
769 */
d6e88aec 770 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 771 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 772 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 773 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 774 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 775 vmx->host_state.fs_reload_needed = 0;
776 } else {
33ed6329 777 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 778 vmx->host_state.fs_reload_needed = 1;
33ed6329 779 }
d6e88aec 780 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 781 if (!(vmx->host_state.gs_sel & 7))
782 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 783 else {
784 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 785 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 786 }
787
788#ifdef CONFIG_X86_64
789 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
790 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
791#else
a2fa3e9f
GH		 792 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
793 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 794#endif
707c0874
AK		 795
796#ifdef CONFIG_X86_64
44ea2b17
AK		 797 if (is_long_mode(&vmx->vcpu)) {
798 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
799 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
800 }
707c0874 801#endif
26bb0981
AK		 802 for (i = 0; i < vmx->save_nmsrs; ++i)
803 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 804 vmx->guest_msrs[i].data,
805 vmx->guest_msrs[i].mask);
33ed6329
AK		 806}
807
a9b21b62 808static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 809{
15ad7146 810 unsigned long flags;
33ed6329 811
a2fa3e9f 812 if (!vmx->host_state.loaded)
33ed6329
AK		 813 return;
814
e1beb1d3 815 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 816 vmx->host_state.loaded = 0;
152d3f2f 817 if (vmx->host_state.fs_reload_needed)
d6e88aec 818 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 819 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 820 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 821 /*
822 * If we have to reload gs, we must take care to
823 * preserve our gs base.
824 */
15ad7146 825 local_irq_save(flags);
d6e88aec 826 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 827#ifdef CONFIG_X86_64
828 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
829#endif
15ad7146 830 local_irq_restore(flags);
33ed6329 831 }
152d3f2f 832 reload_tss();
44ea2b17
AK		 833#ifdef CONFIG_X86_64
834 if (is_long_mode(&vmx->vcpu)) {
835 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
836 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
837 }
838#endif
1c11e713
AK		 839 if (current_thread_info()->status & TS_USEDFPU)
840 clts();
33ed6329
AK		 841}
842
a9b21b62
AK		 843static void vmx_load_host_state(struct vcpu_vmx *vmx)
844{
845 preempt_disable();
846 __vmx_load_host_state(vmx);
847 preempt_enable();
848}
849
6aa8b732
AK		 850/*
851 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
852 * vcpu mutex is already taken.
853 */
15ad7146 854static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 855{
a2fa3e9f 856 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 857 u64 tsc_this, delta, new_offset;
4610c9cc 858 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 859
4610c9cc
DX		 860 if (!vmm_exclusive)
861 kvm_cpu_vmxon(phys_addr);
862 else if (vcpu->cpu != cpu)
8b9cf98c 863 vcpu_clear(vmx);
6aa8b732 864
a2fa3e9f 865 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 866 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 867 vmcs_load(vmx->vmcs);
6aa8b732
AK		 868 }
869
870 if (vcpu->cpu != cpu) {
89a27f4d 871 struct desc_ptr dt;
6aa8b732
AK		 872 unsigned long sysenter_esp;
873
92fe13be
DX		 874 kvm_migrate_timers(vcpu);
875 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
876 local_irq_disable();
877 list_add(&vmx->local_vcpus_link,
878 &per_cpu(vcpus_on_cpu, cpu));
879 local_irq_enable();
880
6aa8b732
AK		 881 vcpu->cpu = cpu;
882 /*
883 * Linux uses per-cpu TSS and GDT, so set these when switching
884 * processors.
885 */
d6e88aec 886 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 887 native_store_gdt(&dt);
89a27f4d 888 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 889
890 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
891 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 892
893 /*
894 * Make sure the time stamp counter is monotonous.
895 */
896 rdtscll(tsc_this);
019960ae
AK		 897 if (tsc_this < vcpu->arch.host_tsc) {
898 delta = vcpu->arch.host_tsc - tsc_this;
899 new_offset = vmcs_read64(TSC_OFFSET) + delta;
900 vmcs_write64(TSC_OFFSET, new_offset);
901 }
6aa8b732 902 }
6aa8b732
AK		 903}
904
905static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
906{
a9b21b62 907 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 908 if (!vmm_exclusive) {
b923e62e 909 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 910 kvm_cpu_vmxoff();
911 }
6aa8b732
AK		 912}
913
5fd86fcf
AK		 914static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
915{
81231c69
AK		 916 ulong cr0;
917
5fd86fcf
AK		 918 if (vcpu->fpu_active)
919 return;
920 vcpu->fpu_active = 1;
81231c69
AK		 921 cr0 = vmcs_readl(GUEST_CR0);
922 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
923 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
924 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 925 update_exception_bitmap(vcpu);
edcafe3c
AK		 926 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
927 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 928}
929
edcafe3c
AK		 930static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
931
5fd86fcf
AK		 932static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
933{
edcafe3c 934 vmx_decache_cr0_guest_bits(vcpu);
81231c69 935 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 936 update_exception_bitmap(vcpu);
edcafe3c
AK		 937 vcpu->arch.cr0_guest_owned_bits = 0;
938 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
939 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 940}
941
6aa8b732
AK		 942static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
943{
78ac8b47 944 unsigned long rflags, save_rflags;
345dcaa8
AK		 945
946 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 947 if (to_vmx(vcpu)->rmode.vm86_active) {
948 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
949 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
950 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
951 }
345dcaa8 952 return rflags;
6aa8b732
AK		 953}
954
955static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
956{
78ac8b47
AK		 957 if (to_vmx(vcpu)->rmode.vm86_active) {
958 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 959 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 960 }
6aa8b732
AK		 961 vmcs_writel(GUEST_RFLAGS, rflags);
962}
963
2809f5d2
GC		 964static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
965{
966 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
967 int ret = 0;
968
969 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 970 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 971 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 972 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 973
974 return ret & mask;
975}
976
977static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
978{
979 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
980 u32 interruptibility = interruptibility_old;
981
982 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
983
48005f64 984 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 985 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 986 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 987 interruptibility |= GUEST_INTR_STATE_STI;
988
989 if ((interruptibility != interruptibility_old))
990 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
991}
992
6aa8b732
AK		 993static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
994{
995 unsigned long rip;
6aa8b732 996
5fdbf976 997 rip = kvm_rip_read(vcpu);
6aa8b732 998 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 999 kvm_rip_write(vcpu, rip);
6aa8b732 1000
2809f5d2
GC		 1001 /* skipping an emulated instruction also counts */
1002 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1003}
1004
298101da 1005static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1006 bool has_error_code, u32 error_code,
1007 bool reinject)
298101da 1008{
77ab6db0 1009 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1010 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1011
8ab2d2e2 1012 if (has_error_code) {
77ab6db0 1013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1015 }
77ab6db0 1016
7ffd92c5 1017 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1018 vmx->rmode.irq.pending = true;
1019 vmx->rmode.irq.vector = nr;
1020 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1021 if (kvm_exception_is_soft(nr))
1022 vmx->rmode.irq.rip +=
1023 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1024 intr_info |= INTR_TYPE_SOFT_INTR;
1025 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1026 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1027 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1028 return;
1029 }
1030
66fd3f7f
GN		 1031 if (kvm_exception_is_soft(nr)) {
1032 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1033 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1034 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1035 } else
1036 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1037
1038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1039}
1040
4e47c7a6
SY		 1041static bool vmx_rdtscp_supported(void)
1042{
1043 return cpu_has_vmx_rdtscp();
1044}
1045
a75beee6
ED		 1046/*
1047 * Swap MSR entry in host/guest MSR entry array.
1048 */
8b9cf98c 1049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1050{
26bb0981 1051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1052
1053 tmp = vmx->guest_msrs[to];
1054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1056}
1057
e38aea3e
AK		 1058/*
1059 * Set up the vmcs to automatically save and restore system
1060 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1061 * mode, as fiddling with msrs is very expensive.
1062 */
8b9cf98c 1063static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1064{
26bb0981 1065 int save_nmsrs, index;
5897297b 1066 unsigned long *msr_bitmap;
e38aea3e 1067
33f9c505 1068 vmx_load_host_state(vmx);
a75beee6
ED		 1069 save_nmsrs = 0;
1070#ifdef CONFIG_X86_64
8b9cf98c 1071 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1072 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1073 if (index >= 0)
8b9cf98c
RR		 1074 move_msr_up(vmx, index, save_nmsrs++);
1075 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1076 if (index >= 0)
8b9cf98c
RR		 1077 move_msr_up(vmx, index, save_nmsrs++);
1078 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1079 if (index >= 0)
8b9cf98c 1080 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1081 index = __find_msr_index(vmx, MSR_TSC_AUX);
1082 if (index >= 0 && vmx->rdtscp_enabled)
1083 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1084 /*
1085 * MSR_K6_STAR is only needed on long mode guests, and only
1086 * if efer.sce is enabled.
1087 */
8b9cf98c 1088 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1089 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1090 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1091 }
1092#endif
92c0d900
AK		 1093 index = __find_msr_index(vmx, MSR_EFER);
1094 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1095 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1096
26bb0981 1097 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1098
1099 if (cpu_has_vmx_msr_bitmap()) {
1100 if (is_long_mode(&vmx->vcpu))
1101 msr_bitmap = vmx_msr_bitmap_longmode;
1102 else
1103 msr_bitmap = vmx_msr_bitmap_legacy;
1104
1105 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1106 }
e38aea3e
AK		 1107}
1108
6aa8b732
AK		 1109/*
1110 * reads and returns guest's timestamp counter "register"
1111 * guest_tsc = host_tsc + tsc_offset -- 21.3
1112 */
1113static u64 guest_read_tsc(void)
1114{
1115 u64 host_tsc, tsc_offset;
1116
1117 rdtscll(host_tsc);
1118 tsc_offset = vmcs_read64(TSC_OFFSET);
1119 return host_tsc + tsc_offset;
1120}
1121
1122/*
1123 * writes 'guest_tsc' into guest's timestamp counter "register"
1124 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1125 */
53f658b3 1126static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1127{
6aa8b732
AK		 1128 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1129}
1130
6aa8b732
AK		 1131/*
1132 * Reads an msr value (of 'msr_index') into 'pdata'.
1133 * Returns 0 on success, non-0 otherwise.
1134 * Assumes vcpu_load() was already called.
1135 */
1136static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1137{
1138 u64 data;
26bb0981 1139 struct shared_msr_entry *msr;
6aa8b732
AK		 1140
1141 if (!pdata) {
1142 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1143 return -EINVAL;
1144 }
1145
1146 switch (msr_index) {
05b3e0c2 1147#ifdef CONFIG_X86_64
6aa8b732
AK		 1148 case MSR_FS_BASE:
1149 data = vmcs_readl(GUEST_FS_BASE);
1150 break;
1151 case MSR_GS_BASE:
1152 data = vmcs_readl(GUEST_GS_BASE);
1153 break;
44ea2b17
AK		 1154 case MSR_KERNEL_GS_BASE:
1155 vmx_load_host_state(to_vmx(vcpu));
1156 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1157 break;
26bb0981 1158#endif
6aa8b732 1159 case MSR_EFER:
3bab1f5d 1160 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1161 case MSR_IA32_TSC:
6aa8b732
AK		 1162 data = guest_read_tsc();
1163 break;
1164 case MSR_IA32_SYSENTER_CS:
1165 data = vmcs_read32(GUEST_SYSENTER_CS);
1166 break;
1167 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1168 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1169 break;
1170 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1171 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1172 break;
4e47c7a6
SY		 1173 case MSR_TSC_AUX:
1174 if (!to_vmx(vcpu)->rdtscp_enabled)
1175 return 1;
1176 /* Otherwise falls through */
6aa8b732 1177 default:
26bb0981 1178 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1179 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1180 if (msr) {
542423b0 1181 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1182 data = msr->data;
1183 break;
6aa8b732 1184 }
3bab1f5d 1185 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1186 }
1187
1188 *pdata = data;
1189 return 0;
1190}
1191
1192/*
1193 * Writes msr value into into the appropriate "register".
1194 * Returns 0 on success, non-0 otherwise.
1195 * Assumes vcpu_load() was already called.
1196 */
1197static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1198{
a2fa3e9f 1199 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1200 struct shared_msr_entry *msr;
53f658b3 1201 u64 host_tsc;
2cc51560
ED		 1202 int ret = 0;
1203
6aa8b732 1204 switch (msr_index) {
3bab1f5d 1205 case MSR_EFER:
a9b21b62 1206 vmx_load_host_state(vmx);
2cc51560 1207 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1208 break;
16175a79 1209#ifdef CONFIG_X86_64
6aa8b732
AK		 1210 case MSR_FS_BASE:
1211 vmcs_writel(GUEST_FS_BASE, data);
1212 break;
1213 case MSR_GS_BASE:
1214 vmcs_writel(GUEST_GS_BASE, data);
1215 break;
44ea2b17
AK		 1216 case MSR_KERNEL_GS_BASE:
1217 vmx_load_host_state(vmx);
1218 vmx->msr_guest_kernel_gs_base = data;
1219 break;
6aa8b732
AK		 1220#endif
1221 case MSR_IA32_SYSENTER_CS:
1222 vmcs_write32(GUEST_SYSENTER_CS, data);
1223 break;
1224 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1225 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1226 break;
1227 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1228 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1229 break;
af24a4e4 1230 case MSR_IA32_TSC:
53f658b3
MT		 1231 rdtscll(host_tsc);
1232 guest_write_tsc(data, host_tsc);
6aa8b732 1233 break;
468d472f
SY		 1234 case MSR_IA32_CR_PAT:
1235 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1236 vmcs_write64(GUEST_IA32_PAT, data);
1237 vcpu->arch.pat = data;
1238 break;
1239 }
4e47c7a6
SY		 1240 ret = kvm_set_msr_common(vcpu, msr_index, data);
1241 break;
1242 case MSR_TSC_AUX:
1243 if (!vmx->rdtscp_enabled)
1244 return 1;
1245 /* Check reserved bit, higher 32 bits should be zero */
1246 if ((data >> 32) != 0)
1247 return 1;
1248 /* Otherwise falls through */
6aa8b732 1249 default:
8b9cf98c 1250 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1251 if (msr) {
542423b0 1252 vmx_load_host_state(vmx);
3bab1f5d
AK		 1253 msr->data = data;
1254 break;
6aa8b732 1255 }
2cc51560 1256 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1257 }
1258
2cc51560 1259 return ret;
6aa8b732
AK		 1260}
1261
5fdbf976 1262static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1263{
5fdbf976
MT		 1264 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1265 switch (reg) {
1266 case VCPU_REGS_RSP:
1267 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1268 break;
1269 case VCPU_REGS_RIP:
1270 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1271 break;
6de4f3ad
AK		 1272 case VCPU_EXREG_PDPTR:
1273 if (enable_ept)
1274 ept_save_pdptrs(vcpu);
1275 break;
5fdbf976
MT		 1276 default:
1277 break;
1278 }
6aa8b732
AK		 1279}
1280
355be0b9 1281static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1282{
ae675ef0
JK		 1283 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1284 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1285 else
1286 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1287
abd3f2d6 1288 update_exception_bitmap(vcpu);
6aa8b732
AK		 1289}
1290
1291static __init int cpu_has_kvm_support(void)
1292{
6210e37b 1293 return cpu_has_vmx();
6aa8b732
AK		 1294}
1295
1296static __init int vmx_disabled_by_bios(void)
1297{
1298 u64 msr;
1299
1300 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1301 if (msr & FEATURE_CONTROL_LOCKED) {
1302 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1303 && tboot_enabled())
1304 return 1;
1305 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1306 && !tboot_enabled())
1307 return 1;
1308 }
1309
1310 return 0;
62b3ffb8 1311 /* locked but not enabled */
6aa8b732
AK		 1312}
1313
7725b894
DX		 1314static void kvm_cpu_vmxon(u64 addr)
1315{
1316 asm volatile (ASM_VMX_VMXON_RAX
1317 : : "a"(&addr), "m"(addr)
1318 : "memory", "cc");
1319}
1320
10474ae8 1321static int hardware_enable(void *garbage)
6aa8b732
AK		 1322{
1323 int cpu = raw_smp_processor_id();
1324 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1325 u64 old, test_bits;
6aa8b732 1326
10474ae8
AG		 1327 if (read_cr4() & X86_CR4_VMXE)
1328 return -EBUSY;
1329
543e4243 1330 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1331 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1332
1333 test_bits = FEATURE_CONTROL_LOCKED;
1334 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1335 if (tboot_enabled())
1336 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1337
1338 if ((old & test_bits) != test_bits) {
6aa8b732 1339 /* enable and lock */
cafd6659
SW		 1340 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1341 }
66aee91a 1342 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1343
4610c9cc
DX		 1344 if (vmm_exclusive) {
1345 kvm_cpu_vmxon(phys_addr);
1346 ept_sync_global();
1347 }
10474ae8
AG		 1348
1349 return 0;
6aa8b732
AK		 1350}
1351
543e4243
AK		 1352static void vmclear_local_vcpus(void)
1353{
1354 int cpu = raw_smp_processor_id();
1355 struct vcpu_vmx *vmx, *n;
1356
1357 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1358 local_vcpus_link)
1359 __vcpu_clear(vmx);
1360}
1361
710ff4a8
EH		 1362
1363/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1364 * tricks.
1365 */
1366static void kvm_cpu_vmxoff(void)
6aa8b732 1367{
4ecac3fd 1368 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1369}
1370
710ff4a8
EH		 1371static void hardware_disable(void *garbage)
1372{
4610c9cc
DX		 1373 if (vmm_exclusive) {
1374 vmclear_local_vcpus();
1375 kvm_cpu_vmxoff();
1376 }
7725b894 1377 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1378}
1379
1c3d14fe 1380static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1381 u32 msr, u32 *result)
1c3d14fe
YS		 1382{
1383 u32 vmx_msr_low, vmx_msr_high;
1384 u32 ctl = ctl_min | ctl_opt;
1385
1386 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1387
1388 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1389 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1390
1391 /* Ensure minimum (required) set of control bits are supported. */
1392 if (ctl_min & ~ctl)
002c7f7c 1393 return -EIO;
1c3d14fe
YS		 1394
1395 *result = ctl;
1396 return 0;
1397}
1398
002c7f7c 1399static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1400{
1401 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1402 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1403 u32 _pin_based_exec_control = 0;
1404 u32 _cpu_based_exec_control = 0;
f78e0e2e 1405 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1406 u32 _vmexit_control = 0;
1407 u32 _vmentry_control = 0;
1408
1409 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1410 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1411 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1412 &_pin_based_exec_control) < 0)
002c7f7c 1413 return -EIO;
1c3d14fe
YS		 1414
1415 min = CPU_BASED_HLT_EXITING |
1416#ifdef CONFIG_X86_64
1417 CPU_BASED_CR8_LOAD_EXITING |
1418 CPU_BASED_CR8_STORE_EXITING |
1419#endif
d56f546d
SY		 1420 CPU_BASED_CR3_LOAD_EXITING |
1421 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1422 CPU_BASED_USE_IO_BITMAPS |
1423 CPU_BASED_MOV_DR_EXITING |
a7052897 1424 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1425 CPU_BASED_MWAIT_EXITING |
1426 CPU_BASED_MONITOR_EXITING |
a7052897 1427 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1428 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1429 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1430 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1431 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1432 &_cpu_based_exec_control) < 0)
002c7f7c 1433 return -EIO;
6e5d865c
YS		 1434#ifdef CONFIG_X86_64
1435 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1436 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1437 ~CPU_BASED_CR8_STORE_EXITING;
1438#endif
f78e0e2e 1439 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1440 min2 = 0;
1441 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1442 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1443 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1444 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1445 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1446 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1447 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1448 if (adjust_vmx_controls(min2, opt2,
1449 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1450 &_cpu_based_2nd_exec_control) < 0)
1451 return -EIO;
1452 }
1453#ifndef CONFIG_X86_64
1454 if (!(_cpu_based_2nd_exec_control &
1455 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1456 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1457#endif
d56f546d 1458 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1459 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1460 enabled */
5fff7d27
GN		 1461 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1462 CPU_BASED_CR3_STORE_EXITING |
1463 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1464 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1465 vmx_capability.ept, vmx_capability.vpid);
1466 }
1c3d14fe
YS		 1467
1468 min = 0;
1469#ifdef CONFIG_X86_64
1470 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1471#endif
468d472f 1472 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1473 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1474 &_vmexit_control) < 0)
002c7f7c 1475 return -EIO;
1c3d14fe 1476
468d472f
SY		 1477 min = 0;
1478 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1479 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1480 &_vmentry_control) < 0)
002c7f7c 1481 return -EIO;
6aa8b732 1482
c68876fd 1483 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1484
1485 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1486 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1487 return -EIO;
1c3d14fe
YS		 1488
1489#ifdef CONFIG_X86_64
1490 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1491 if (vmx_msr_high & (1u<<16))
002c7f7c 1492 return -EIO;
1c3d14fe
YS		 1493#endif
1494
1495 /* Require Write-Back (WB) memory type for VMCS accesses. */
1496 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1497 return -EIO;
1c3d14fe 1498
002c7f7c
YS		 1499 vmcs_conf->size = vmx_msr_high & 0x1fff;
1500 vmcs_conf->order = get_order(vmcs_config.size);
1501 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1502
002c7f7c
YS		 1503 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1504 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1505 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1506 vmcs_conf->vmexit_ctrl = _vmexit_control;
1507 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1508
1509 return 0;
c68876fd 1510}
6aa8b732
AK		 1511
1512static struct vmcs *alloc_vmcs_cpu(int cpu)
1513{
1514 int node = cpu_to_node(cpu);
1515 struct page *pages;
1516 struct vmcs *vmcs;
1517
6484eb3e 1518 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1519 if (!pages)
1520 return NULL;
1521 vmcs = page_address(pages);
1c3d14fe
YS		 1522 memset(vmcs, 0, vmcs_config.size);
1523 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1524 return vmcs;
1525}
1526
1527static struct vmcs *alloc_vmcs(void)
1528{
d3b2c338 1529 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1530}
1531
1532static void free_vmcs(struct vmcs *vmcs)
1533{
1c3d14fe 1534 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1535}
1536
39959588 1537static void free_kvm_area(void)
6aa8b732
AK		 1538{
1539 int cpu;
1540
3230bb47 1541 for_each_possible_cpu(cpu) {
6aa8b732 1542 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1543 per_cpu(vmxarea, cpu) = NULL;
1544 }
6aa8b732
AK		 1545}
1546
6aa8b732
AK		 1547static __init int alloc_kvm_area(void)
1548{
1549 int cpu;
1550
3230bb47 1551 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1552 struct vmcs *vmcs;
1553
1554 vmcs = alloc_vmcs_cpu(cpu);
1555 if (!vmcs) {
1556 free_kvm_area();
1557 return -ENOMEM;
1558 }
1559
1560 per_cpu(vmxarea, cpu) = vmcs;
1561 }
1562 return 0;
1563}
1564
1565static __init int hardware_setup(void)
1566{
002c7f7c
YS		 1567 if (setup_vmcs_config(&vmcs_config) < 0)
1568 return -EIO;
50a37eb4
JR		 1569
1570 if (boot_cpu_has(X86_FEATURE_NX))
1571 kvm_enable_efer_bits(EFER_NX);
1572
93ba03c2
SY		 1573 if (!cpu_has_vmx_vpid())
1574 enable_vpid = 0;
1575
4bc9b982
SY		 1576 if (!cpu_has_vmx_ept() ||
1577 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1578 enable_ept = 0;
3a624e29
NK		 1579 enable_unrestricted_guest = 0;
1580 }
1581
1582 if (!cpu_has_vmx_unrestricted_guest())
1583 enable_unrestricted_guest = 0;
93ba03c2
SY		 1584
1585 if (!cpu_has_vmx_flexpriority())
1586 flexpriority_enabled = 0;
1587
95ba8273
GN		 1588 if (!cpu_has_vmx_tpr_shadow())
1589 kvm_x86_ops->update_cr8_intercept = NULL;
1590
54dee993
MT		 1591 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1592 kvm_disable_largepages();
1593
4b8d54f9
ZE		 1594 if (!cpu_has_vmx_ple())
1595 ple_gap = 0;
1596
6aa8b732
AK		 1597 return alloc_kvm_area();
1598}
1599
1600static __exit void hardware_unsetup(void)
1601{
1602 free_kvm_area();
1603}
1604
6aa8b732
AK		 1605static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1606{
1607 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1608
6af11b9e 1609 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1610 vmcs_write16(sf->selector, save->selector);
1611 vmcs_writel(sf->base, save->base);
1612 vmcs_write32(sf->limit, save->limit);
1613 vmcs_write32(sf->ar_bytes, save->ar);
1614 } else {
1615 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1616 << AR_DPL_SHIFT;
1617 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1618 }
1619}
1620
1621static void enter_pmode(struct kvm_vcpu *vcpu)
1622{
1623 unsigned long flags;
a89a8fb9 1624 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1625
a89a8fb9 1626 vmx->emulation_required = 1;
7ffd92c5 1627 vmx->rmode.vm86_active = 0;
6aa8b732 1628
7ffd92c5
AK		 1629 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1630 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1631 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1632
1633 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1634 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1635 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1636 vmcs_writel(GUEST_RFLAGS, flags);
1637
66aee91a
RR		 1638 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1639 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1640
1641 update_exception_bitmap(vcpu);
1642
a89a8fb9
MG		 1643 if (emulate_invalid_guest_state)
1644 return;
1645
7ffd92c5
AK		 1646 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1647 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1648 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1649 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1650
1651 vmcs_write16(GUEST_SS_SELECTOR, 0);
1652 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1653
1654 vmcs_write16(GUEST_CS_SELECTOR,
1655 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1656 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1657}
1658
d77c26fc 1659static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1660{
bfc6d222 1661 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1662 struct kvm_memslots *slots;
1663 gfn_t base_gfn;
1664
90d83dc3 1665 slots = kvm_memslots(kvm);
bc6678a3 1666 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1667 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1668 return base_gfn << PAGE_SHIFT;
1669 }
bfc6d222 1670 return kvm->arch.tss_addr;
6aa8b732
AK		 1671}
1672
1673static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1674{
1675 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1676
1677 save->selector = vmcs_read16(sf->selector);
1678 save->base = vmcs_readl(sf->base);
1679 save->limit = vmcs_read32(sf->limit);
1680 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1681 vmcs_write16(sf->selector, save->base >> 4);
1682 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1683 vmcs_write32(sf->limit, 0xffff);
1684 vmcs_write32(sf->ar_bytes, 0xf3);
1685}
1686
1687static void enter_rmode(struct kvm_vcpu *vcpu)
1688{
1689 unsigned long flags;
a89a8fb9 1690 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1691
3a624e29
NK		 1692 if (enable_unrestricted_guest)
1693 return;
1694
a89a8fb9 1695 vmx->emulation_required = 1;
7ffd92c5 1696 vmx->rmode.vm86_active = 1;
6aa8b732 1697
7ffd92c5 1698 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1699 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1700
7ffd92c5 1701 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1702 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1703
7ffd92c5 1704 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1705 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1706
1707 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1708 vmx->rmode.save_rflags = flags;
6aa8b732 1709
053de044 1710 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1711
1712 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1713 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1714 update_exception_bitmap(vcpu);
1715
a89a8fb9
MG		 1716 if (emulate_invalid_guest_state)
1717 goto continue_rmode;
1718
6aa8b732
AK		 1719 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1720 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1721 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1722
1723 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1724 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1725 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1726 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1727 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1728
7ffd92c5
AK		 1729 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1730 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1731 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1732 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1733
a89a8fb9 1734continue_rmode:
8668a3c4 1735 kvm_mmu_reset_context(vcpu);
b7ebfb05 1736 init_rmode(vcpu->kvm);
6aa8b732
AK		 1737}
1738
401d10de
AS		 1739static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1740{
1741 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1742 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1743
1744 if (!msr)
1745 return;
401d10de 1746
44ea2b17
AK		 1747 /*
1748 * Force kernel_gs_base reloading before EFER changes, as control
1749 * of this msr depends on is_long_mode().
1750 */
1751 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1752 vcpu->arch.efer = efer;
401d10de
AS		 1753 if (efer & EFER_LMA) {
1754 vmcs_write32(VM_ENTRY_CONTROLS,
1755 vmcs_read32(VM_ENTRY_CONTROLS) |
1756 VM_ENTRY_IA32E_MODE);
1757 msr->data = efer;
1758 } else {
1759 vmcs_write32(VM_ENTRY_CONTROLS,
1760 vmcs_read32(VM_ENTRY_CONTROLS) &
1761 ~VM_ENTRY_IA32E_MODE);
1762
1763 msr->data = efer & ~EFER_LME;
1764 }
1765 setup_msrs(vmx);
1766}
1767
05b3e0c2 1768#ifdef CONFIG_X86_64
6aa8b732
AK		 1769
1770static void enter_lmode(struct kvm_vcpu *vcpu)
1771{
1772 u32 guest_tr_ar;
1773
1774 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1775 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1776 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1777 __func__);
6aa8b732
AK		 1778 vmcs_write32(GUEST_TR_AR_BYTES,
1779 (guest_tr_ar & ~AR_TYPE_MASK)
1780 | AR_TYPE_BUSY_64_TSS);
1781 }
da38f438 1782 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1783}
1784
1785static void exit_lmode(struct kvm_vcpu *vcpu)
1786{
6aa8b732
AK		 1787 vmcs_write32(VM_ENTRY_CONTROLS,
1788 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1789 & ~VM_ENTRY_IA32E_MODE);
da38f438 1790 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1791}
1792
1793#endif
1794
2384d2b3
SY		 1795static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1796{
1797 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1798 if (enable_ept)
4e1096d2 1799 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1800}
1801
e8467fda
AK		 1802static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1803{
1804 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1805
1806 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1807 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1808}
1809
25c4c276 1810static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1811{
fc78f519
AK		 1812 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1813
1814 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1815 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1816}
1817
1439442c
SY		 1818static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1819{
6de4f3ad
AK		 1820 if (!test_bit(VCPU_EXREG_PDPTR,
1821 (unsigned long *)&vcpu->arch.regs_dirty))
1822 return;
1823
1439442c 1824 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1825 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1826 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1827 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1828 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1829 }
1830}
1831
8f5d549f
AK		 1832static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1833{
1834 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1835 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1836 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1837 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1838 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1839 }
6de4f3ad
AK		 1840
1841 __set_bit(VCPU_EXREG_PDPTR,
1842 (unsigned long *)&vcpu->arch.regs_avail);
1843 __set_bit(VCPU_EXREG_PDPTR,
1844 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1845}
1846
1439442c
SY		 1847static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1848
1849static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1850 unsigned long cr0,
1851 struct kvm_vcpu *vcpu)
1852{
1853 if (!(cr0 & X86_CR0_PG)) {
1854 /* From paging/starting to nonpaging */
1855 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1856 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1857 (CPU_BASED_CR3_LOAD_EXITING |
1858 CPU_BASED_CR3_STORE_EXITING));
1859 vcpu->arch.cr0 = cr0;
fc78f519 1860 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1861 } else if (!is_paging(vcpu)) {
1862 /* From nonpaging to paging */
1863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1864 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1865 ~(CPU_BASED_CR3_LOAD_EXITING |
1866 CPU_BASED_CR3_STORE_EXITING));
1867 vcpu->arch.cr0 = cr0;
fc78f519 1868 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1869 }
95eb84a7
SY		 1870
1871 if (!(cr0 & X86_CR0_WP))
1872 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1873}
1874
6aa8b732
AK		 1875static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1876{
7ffd92c5 1877 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1878 unsigned long hw_cr0;
1879
1880 if (enable_unrestricted_guest)
1881 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1882 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1883 else
1884 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1885
7ffd92c5 1886 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1887 enter_pmode(vcpu);
1888
7ffd92c5 1889 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1890 enter_rmode(vcpu);
1891
05b3e0c2 1892#ifdef CONFIG_X86_64
f6801dff 1893 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1894 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1895 enter_lmode(vcpu);
707d92fa 1896 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1897 exit_lmode(vcpu);
1898 }
1899#endif
1900
089d034e 1901 if (enable_ept)
1439442c
SY		 1902 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1903
02daab21 1904 if (!vcpu->fpu_active)
81231c69 1905 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1906
6aa8b732 1907 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1908 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1909 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1910}
1911
1439442c
SY		 1912static u64 construct_eptp(unsigned long root_hpa)
1913{
1914 u64 eptp;
1915
1916 /* TODO write the value reading from MSR */
1917 eptp = VMX_EPT_DEFAULT_MT |
1918 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1919 eptp |= (root_hpa & PAGE_MASK);
1920
1921 return eptp;
1922}
1923
6aa8b732
AK		 1924static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1925{
1439442c
SY		 1926 unsigned long guest_cr3;
1927 u64 eptp;
1928
1929 guest_cr3 = cr3;
089d034e 1930 if (enable_ept) {
1439442c
SY		 1931 eptp = construct_eptp(cr3);
1932 vmcs_write64(EPT_POINTER, eptp);
1439442c 1933 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1934 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1935 ept_load_pdptrs(vcpu);
1439442c
SY		 1936 }
1937
2384d2b3 1938 vmx_flush_tlb(vcpu);
1439442c 1939 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1940}
1941
1942static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1943{
7ffd92c5 1944 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1945 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1946
ad312c7c 1947 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1948 if (enable_ept) {
1949 if (!is_paging(vcpu)) {
1950 hw_cr4 &= ~X86_CR4_PAE;
1951 hw_cr4 |= X86_CR4_PSE;
1952 } else if (!(cr4 & X86_CR4_PAE)) {
1953 hw_cr4 &= ~X86_CR4_PAE;
1954 }
1955 }
1439442c
SY		 1956
1957 vmcs_writel(CR4_READ_SHADOW, cr4);
1958 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1959}
1960
6aa8b732
AK		 1961static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1962{
1963 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1964
1965 return vmcs_readl(sf->base);
1966}
1967
1968static void vmx_get_segment(struct kvm_vcpu *vcpu,
1969 struct kvm_segment *var, int seg)
1970{
1971 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1972 u32 ar;
1973
1974 var->base = vmcs_readl(sf->base);
1975 var->limit = vmcs_read32(sf->limit);
1976 var->selector = vmcs_read16(sf->selector);
1977 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1978 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1979 ar = 0;
1980 var->type = ar & 15;
1981 var->s = (ar >> 4) & 1;
1982 var->dpl = (ar >> 5) & 3;
1983 var->present = (ar >> 7) & 1;
1984 var->avl = (ar >> 12) & 1;
1985 var->l = (ar >> 13) & 1;
1986 var->db = (ar >> 14) & 1;
1987 var->g = (ar >> 15) & 1;
1988 var->unusable = (ar >> 16) & 1;
1989}
1990
2e4d2653
IE		 1991static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1992{
3eeb3288 1993 if (!is_protmode(vcpu))
2e4d2653
IE		 1994 return 0;
1995
1996 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1997 return 3;
1998
eab4b8aa 1999 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2000}
2001
653e3108 2002static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2003{
6aa8b732
AK		 2004 u32 ar;
2005
653e3108 2006 if (var->unusable)
6aa8b732
AK		 2007 ar = 1 << 16;
2008 else {
2009 ar = var->type & 15;
2010 ar |= (var->s & 1) << 4;
2011 ar |= (var->dpl & 3) << 5;
2012 ar |= (var->present & 1) << 7;
2013 ar |= (var->avl & 1) << 12;
2014 ar |= (var->l & 1) << 13;
2015 ar |= (var->db & 1) << 14;
2016 ar |= (var->g & 1) << 15;
2017 }
f7fbf1fd
UL		 2018 if (ar == 0) /* a 0 value means unusable */
2019 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2020
2021 return ar;
2022}
2023
2024static void vmx_set_segment(struct kvm_vcpu *vcpu,
2025 struct kvm_segment *var, int seg)
2026{
7ffd92c5 2027 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2028 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2029 u32 ar;
2030
7ffd92c5
AK		 2031 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2032 vmx->rmode.tr.selector = var->selector;
2033 vmx->rmode.tr.base = var->base;
2034 vmx->rmode.tr.limit = var->limit;
2035 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2036 return;
2037 }
2038 vmcs_writel(sf->base, var->base);
2039 vmcs_write32(sf->limit, var->limit);
2040 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2041 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2042 /*
2043 * Hack real-mode segments into vm86 compatibility.
2044 */
2045 if (var->base == 0xffff0000 && var->selector == 0xf000)
2046 vmcs_writel(sf->base, 0xf0000);
2047 ar = 0xf3;
2048 } else
2049 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2050
2051 /*
2052 * Fix the "Accessed" bit in AR field of segment registers for older
2053 * qemu binaries.
2054 * IA32 arch specifies that at the time of processor reset the
2055 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2056 * is setting it to 0 in the usedland code. This causes invalid guest
2057 * state vmexit when "unrestricted guest" mode is turned on.
2058 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2059 * tree. Newer qemu binaries with that qemu fix would not need this
2060 * kvm hack.
2061 */
2062 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2063 ar |= 0x1; /* Accessed */
2064
6aa8b732
AK		 2065 vmcs_write32(sf->ar_bytes, ar);
2066}
2067
6aa8b732
AK		 2068static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2069{
2070 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2071
2072 *db = (ar >> 14) & 1;
2073 *l = (ar >> 13) & 1;
2074}
2075
89a27f4d 2076static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2077{
89a27f4d
GN		 2078 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2079 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2080}
2081
89a27f4d 2082static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2083{
89a27f4d
GN		 2084 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2085 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2086}
2087
89a27f4d 2088static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2089{
89a27f4d
GN		 2090 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2091 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2092}
2093
89a27f4d 2094static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2095{
89a27f4d
GN		 2096 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2097 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2098}
2099
648dfaa7
MG		 2100static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2101{
2102 struct kvm_segment var;
2103 u32 ar;
2104
2105 vmx_get_segment(vcpu, &var, seg);
2106 ar = vmx_segment_access_rights(&var);
2107
2108 if (var.base != (var.selector << 4))
2109 return false;
2110 if (var.limit != 0xffff)
2111 return false;
2112 if (ar != 0xf3)
2113 return false;
2114
2115 return true;
2116}
2117
2118static bool code_segment_valid(struct kvm_vcpu *vcpu)
2119{
2120 struct kvm_segment cs;
2121 unsigned int cs_rpl;
2122
2123 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2124 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2125
1872a3f4
AK		 2126 if (cs.unusable)
2127 return false;
648dfaa7
MG		 2128 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2129 return false;
2130 if (!cs.s)
2131 return false;
1872a3f4 2132 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2133 if (cs.dpl > cs_rpl)
2134 return false;
1872a3f4 2135 } else {
648dfaa7
MG		 2136 if (cs.dpl != cs_rpl)
2137 return false;
2138 }
2139 if (!cs.present)
2140 return false;
2141
2142 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2143 return true;
2144}
2145
2146static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2147{
2148 struct kvm_segment ss;
2149 unsigned int ss_rpl;
2150
2151 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2152 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2153
1872a3f4
AK		 2154 if (ss.unusable)
2155 return true;
2156 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2157 return false;
2158 if (!ss.s)
2159 return false;
2160 if (ss.dpl != ss_rpl) /* DPL != RPL */
2161 return false;
2162 if (!ss.present)
2163 return false;
2164
2165 return true;
2166}
2167
2168static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2169{
2170 struct kvm_segment var;
2171 unsigned int rpl;
2172
2173 vmx_get_segment(vcpu, &var, seg);
2174 rpl = var.selector & SELECTOR_RPL_MASK;
2175
1872a3f4
AK		 2176 if (var.unusable)
2177 return true;
648dfaa7
MG		 2178 if (!var.s)
2179 return false;
2180 if (!var.present)
2181 return false;
2182 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2183 if (var.dpl < rpl) /* DPL < RPL */
2184 return false;
2185 }
2186
2187 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2188 * rights flags
2189 */
2190 return true;
2191}
2192
2193static bool tr_valid(struct kvm_vcpu *vcpu)
2194{
2195 struct kvm_segment tr;
2196
2197 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2198
1872a3f4
AK		 2199 if (tr.unusable)
2200 return false;
648dfaa7
MG		 2201 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2202 return false;
1872a3f4 2203 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2204 return false;
2205 if (!tr.present)
2206 return false;
2207
2208 return true;
2209}
2210
2211static bool ldtr_valid(struct kvm_vcpu *vcpu)
2212{
2213 struct kvm_segment ldtr;
2214
2215 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2216
1872a3f4
AK		 2217 if (ldtr.unusable)
2218 return true;
648dfaa7
MG		 2219 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2220 return false;
2221 if (ldtr.type != 2)
2222 return false;
2223 if (!ldtr.present)
2224 return false;
2225
2226 return true;
2227}
2228
2229static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2230{
2231 struct kvm_segment cs, ss;
2232
2233 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2234 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2235
2236 return ((cs.selector & SELECTOR_RPL_MASK) ==
2237 (ss.selector & SELECTOR_RPL_MASK));
2238}
2239
2240/*
2241 * Check if guest state is valid. Returns true if valid, false if
2242 * not.
2243 * We assume that registers are always usable
2244 */
2245static bool guest_state_valid(struct kvm_vcpu *vcpu)
2246{
2247 /* real mode guest state checks */
3eeb3288 2248 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2249 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2250 return false;
2251 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2252 return false;
2253 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2254 return false;
2255 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2256 return false;
2257 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2258 return false;
2259 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2260 return false;
2261 } else {
2262 /* protected mode guest state checks */
2263 if (!cs_ss_rpl_check(vcpu))
2264 return false;
2265 if (!code_segment_valid(vcpu))
2266 return false;
2267 if (!stack_segment_valid(vcpu))
2268 return false;
2269 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2270 return false;
2271 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2272 return false;
2273 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2274 return false;
2275 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2276 return false;
2277 if (!tr_valid(vcpu))
2278 return false;
2279 if (!ldtr_valid(vcpu))
2280 return false;
2281 }
2282 /* TODO:
2283 * - Add checks on RIP
2284 * - Add checks on RFLAGS
2285 */
2286
2287 return true;
2288}
2289
d77c26fc 2290static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2291{
6aa8b732 2292 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2293 u16 data = 0;
10589a46 2294 int ret = 0;
195aefde 2295 int r;
6aa8b732 2296
195aefde
IE		 2297 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2298 if (r < 0)
10589a46 2299 goto out;
195aefde 2300 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2301 r = kvm_write_guest_page(kvm, fn++, &data,
2302 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2303 if (r < 0)
10589a46 2304 goto out;
195aefde
IE		 2305 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2306 if (r < 0)
10589a46 2307 goto out;
195aefde
IE		 2308 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2309 if (r < 0)
10589a46 2310 goto out;
195aefde 2311 data = ~0;
10589a46
MT		 2312 r = kvm_write_guest_page(kvm, fn, &data,
2313 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2314 sizeof(u8));
195aefde 2315 if (r < 0)
10589a46
MT		 2316 goto out;
2317
2318 ret = 1;
2319out:
10589a46 2320 return ret;
6aa8b732
AK		 2321}
2322
b7ebfb05
SY		 2323static int init_rmode_identity_map(struct kvm *kvm)
2324{
2325 int i, r, ret;
2326 pfn_t identity_map_pfn;
2327 u32 tmp;
2328
089d034e 2329 if (!enable_ept)
b7ebfb05
SY		 2330 return 1;
2331 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2332 printk(KERN_ERR "EPT: identity-mapping pagetable "
2333 "haven't been allocated!\n");
2334 return 0;
2335 }
2336 if (likely(kvm->arch.ept_identity_pagetable_done))
2337 return 1;
2338 ret = 0;
b927a3ce 2339 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2340 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2341 if (r < 0)
2342 goto out;
2343 /* Set up identity-mapping pagetable for EPT in real mode */
2344 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2345 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2346 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2347 r = kvm_write_guest_page(kvm, identity_map_pfn,
2348 &tmp, i * sizeof(tmp), sizeof(tmp));
2349 if (r < 0)
2350 goto out;
2351 }
2352 kvm->arch.ept_identity_pagetable_done = true;
2353 ret = 1;
2354out:
2355 return ret;
2356}
2357
6aa8b732
AK		 2358static void seg_setup(int seg)
2359{
2360 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2361 unsigned int ar;
6aa8b732
AK		 2362
2363 vmcs_write16(sf->selector, 0);
2364 vmcs_writel(sf->base, 0);
2365 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2366 if (enable_unrestricted_guest) {
2367 ar = 0x93;
2368 if (seg == VCPU_SREG_CS)
2369 ar |= 0x08; /* code segment */
2370 } else
2371 ar = 0xf3;
2372
2373 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2374}
2375
f78e0e2e
SY		 2376static int alloc_apic_access_page(struct kvm *kvm)
2377{
2378 struct kvm_userspace_memory_region kvm_userspace_mem;
2379 int r = 0;
2380
79fac95e 2381 mutex_lock(&kvm->slots_lock);
bfc6d222 2382 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2383 goto out;
2384 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2385 kvm_userspace_mem.flags = 0;
2386 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2387 kvm_userspace_mem.memory_size = PAGE_SIZE;
2388 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2389 if (r)
2390 goto out;
72dc67a6 2391
bfc6d222 2392 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2393out:
79fac95e 2394 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2395 return r;
2396}
2397
b7ebfb05
SY		 2398static int alloc_identity_pagetable(struct kvm *kvm)
2399{
2400 struct kvm_userspace_memory_region kvm_userspace_mem;
2401 int r = 0;
2402
79fac95e 2403 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2404 if (kvm->arch.ept_identity_pagetable)
2405 goto out;
2406 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2407 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2408 kvm_userspace_mem.guest_phys_addr =
2409 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2410 kvm_userspace_mem.memory_size = PAGE_SIZE;
2411 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2412 if (r)
2413 goto out;
2414
b7ebfb05 2415 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2416 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2417out:
79fac95e 2418 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2419 return r;
2420}
2421
2384d2b3
SY		 2422static void allocate_vpid(struct vcpu_vmx *vmx)
2423{
2424 int vpid;
2425
2426 vmx->vpid = 0;
919818ab 2427 if (!enable_vpid)
2384d2b3
SY		 2428 return;
2429 spin_lock(&vmx_vpid_lock);
2430 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2431 if (vpid < VMX_NR_VPIDS) {
2432 vmx->vpid = vpid;
2433 __set_bit(vpid, vmx_vpid_bitmap);
2434 }
2435 spin_unlock(&vmx_vpid_lock);
2436}
2437
cdbecfc3
LJ		 2438static void free_vpid(struct vcpu_vmx *vmx)
2439{
2440 if (!enable_vpid)
2441 return;
2442 spin_lock(&vmx_vpid_lock);
2443 if (vmx->vpid != 0)
2444 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2445 spin_unlock(&vmx_vpid_lock);
2446}
2447
5897297b 2448static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2449{
3e7c73e9 2450 int f = sizeof(unsigned long);
25c5f225
SY		 2451
2452 if (!cpu_has_vmx_msr_bitmap())
2453 return;
2454
2455 /*
2456 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2457 * have the write-low and read-high bitmap offsets the wrong way round.
2458 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2459 */
25c5f225 2460 if (msr <= 0x1fff) {
3e7c73e9
AK		 2461 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2462 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2463 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2464 msr &= 0x1fff;
3e7c73e9
AK		 2465 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2466 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2467 }
25c5f225
SY		 2468}
2469
5897297b
AK		 2470static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2471{
2472 if (!longmode_only)
2473 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2474 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2475}
2476
6aa8b732
AK		 2477/*
2478 * Sets up the vmcs for emulated real mode.
2479 */
8b9cf98c 2480static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2481{
468d472f 2482 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2483 u32 junk;
53f658b3 2484 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2485 unsigned long a;
89a27f4d 2486 struct desc_ptr dt;
6aa8b732 2487 int i;
cd2276a7 2488 unsigned long kvm_vmx_return;
6e5d865c 2489 u32 exec_control;
6aa8b732 2490
6aa8b732 2491 /* I/O */
3e7c73e9
AK		 2492 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2493 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2494
25c5f225 2495 if (cpu_has_vmx_msr_bitmap())
5897297b 2496 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2497
6aa8b732
AK		 2498 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2499
6aa8b732 2500 /* Control */
1c3d14fe
YS		 2501 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2502 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2503
2504 exec_control = vmcs_config.cpu_based_exec_ctrl;
2505 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2506 exec_control &= ~CPU_BASED_TPR_SHADOW;
2507#ifdef CONFIG_X86_64
2508 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2509 CPU_BASED_CR8_LOAD_EXITING;
2510#endif
2511 }
089d034e 2512 if (!enable_ept)
d56f546d 2513 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2514 CPU_BASED_CR3_LOAD_EXITING |
2515 CPU_BASED_INVLPG_EXITING;
6e5d865c 2516 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2517
83ff3b9d
SY		 2518 if (cpu_has_secondary_exec_ctrls()) {
2519 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2520 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2521 exec_control &=
2522 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2523 if (vmx->vpid == 0)
2524 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2525 if (!enable_ept) {
d56f546d 2526 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2527 enable_unrestricted_guest = 0;
2528 }
3a624e29
NK		 2529 if (!enable_unrestricted_guest)
2530 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2531 if (!ple_gap)
2532 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2533 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2534 }
f78e0e2e 2535
4b8d54f9
ZE		 2536 if (ple_gap) {
2537 vmcs_write32(PLE_GAP, ple_gap);
2538 vmcs_write32(PLE_WINDOW, ple_window);
2539 }
2540
c7addb90
AK		 2541 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2542 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2543 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2544
1c11e713 2545 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2546 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2547 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2548
2549 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2550 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2551 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2552 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2553 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2554 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2555#ifdef CONFIG_X86_64
6aa8b732
AK		 2556 rdmsrl(MSR_FS_BASE, a);
2557 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2558 rdmsrl(MSR_GS_BASE, a);
2559 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2560#else
2561 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2562 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2563#endif
2564
2565 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2566
ec68798c 2567 native_store_idt(&dt);
89a27f4d 2568 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2569
d77c26fc 2570 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2571 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2572 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2573 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2574 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2575 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2576 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2577
2578 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2579 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2580 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2581 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2582 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2583 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2584
468d472f
SY		 2585 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2586 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2587 host_pat = msr_low | ((u64) msr_high << 32);
2588 vmcs_write64(HOST_IA32_PAT, host_pat);
2589 }
2590 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2591 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2592 host_pat = msr_low | ((u64) msr_high << 32);
2593 /* Write the default value follow host pat */
2594 vmcs_write64(GUEST_IA32_PAT, host_pat);
2595 /* Keep arch.pat sync with GUEST_IA32_PAT */
2596 vmx->vcpu.arch.pat = host_pat;
2597 }
2598
6aa8b732
AK		 2599 for (i = 0; i < NR_VMX_MSR; ++i) {
2600 u32 index = vmx_msr_index[i];
2601 u32 data_low, data_high;
a2fa3e9f 2602 int j = vmx->nmsrs;
6aa8b732
AK		 2603
2604 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2605 continue;
432bd6cb
AK		 2606 if (wrmsr_safe(index, data_low, data_high) < 0)
2607 continue;
26bb0981
AK		 2608 vmx->guest_msrs[j].index = i;
2609 vmx->guest_msrs[j].data = 0;
d5696725 2610 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2611 ++vmx->nmsrs;
6aa8b732 2612 }
6aa8b732 2613
1c3d14fe 2614 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2615
2616 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2617 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2618
e00c8cf2 2619 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2620 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2621 if (enable_ept)
2622 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2623 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2624
53f658b3
MT		 2625 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2626 rdtscll(tsc_this);
2627 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2628 tsc_base = tsc_this;
2629
2630 guest_write_tsc(0, tsc_base);
f78e0e2e 2631
e00c8cf2
AK		 2632 return 0;
2633}
2634
b7ebfb05
SY		 2635static int init_rmode(struct kvm *kvm)
2636{
2637 if (!init_rmode_tss(kvm))
2638 return 0;
2639 if (!init_rmode_identity_map(kvm))
2640 return 0;
2641 return 1;
2642}
2643
e00c8cf2
AK		 2644static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2645{
2646 struct vcpu_vmx *vmx = to_vmx(vcpu);
2647 u64 msr;
f656ce01 2648 int ret, idx;
e00c8cf2 2649
5fdbf976 2650 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2651 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2652 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2653 ret = -ENOMEM;
2654 goto out;
2655 }
2656
7ffd92c5 2657 vmx->rmode.vm86_active = 0;
e00c8cf2 2658
3b86cd99
JK		 2659 vmx->soft_vnmi_blocked = 0;
2660
ad312c7c 2661 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2662 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2663 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2664 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2665 msr |= MSR_IA32_APICBASE_BSP;
2666 kvm_set_apic_base(&vmx->vcpu, msr);
2667
10ab25cd
JK		 2668 ret = fx_init(&vmx->vcpu);
2669 if (ret != 0)
2670 goto out;
e00c8cf2 2671
5706be0d 2672 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2673 /*
2674 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2675 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2676 */
c5af89b6 2677 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2678 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2679 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2680 } else {
ad312c7c
ZX		 2681 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2682 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2683 }
e00c8cf2
AK		 2684
2685 seg_setup(VCPU_SREG_DS);
2686 seg_setup(VCPU_SREG_ES);
2687 seg_setup(VCPU_SREG_FS);
2688 seg_setup(VCPU_SREG_GS);
2689 seg_setup(VCPU_SREG_SS);
2690
2691 vmcs_write16(GUEST_TR_SELECTOR, 0);
2692 vmcs_writel(GUEST_TR_BASE, 0);
2693 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2694 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2695
2696 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2697 vmcs_writel(GUEST_LDTR_BASE, 0);
2698 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2699 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2700
2701 vmcs_write32(GUEST_SYSENTER_CS, 0);
2702 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2703 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2704
2705 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2706 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2707 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2708 else
5fdbf976
MT		 2709 kvm_rip_write(vcpu, 0);
2710 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2711
e00c8cf2
AK		 2712 vmcs_writel(GUEST_DR7, 0x400);
2713
2714 vmcs_writel(GUEST_GDTR_BASE, 0);
2715 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2716
2717 vmcs_writel(GUEST_IDTR_BASE, 0);
2718 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2719
2720 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2721 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2722 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2723
e00c8cf2
AK		 2724 /* Special registers */
2725 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2726
2727 setup_msrs(vmx);
2728
6aa8b732
AK		 2729 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2730
f78e0e2e
SY		 2731 if (cpu_has_vmx_tpr_shadow()) {
2732 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2733 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2734 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2735 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2736 vmcs_write32(TPR_THRESHOLD, 0);
2737 }
2738
2739 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2740 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2741 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2742
2384d2b3
SY		 2743 if (vmx->vpid != 0)
2744 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2745
fa40052c 2746 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2747 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2748 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2749 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2750 vmx_fpu_activate(&vmx->vcpu);
2751 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2752
2384d2b3
SY		 2753 vpid_sync_vcpu_all(vmx);
2754
3200f405 2755 ret = 0;
6aa8b732 2756
a89a8fb9
MG		 2757 /* HACK: Don't enable emulation on guest boot/reset */
2758 vmx->emulation_required = 0;
2759
6aa8b732 2760out:
f656ce01 2761 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2762 return ret;
2763}
2764
3b86cd99
JK		 2765static void enable_irq_window(struct kvm_vcpu *vcpu)
2766{
2767 u32 cpu_based_vm_exec_control;
2768
2769 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2770 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2771 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2772}
2773
2774static void enable_nmi_window(struct kvm_vcpu *vcpu)
2775{
2776 u32 cpu_based_vm_exec_control;
2777
2778 if (!cpu_has_virtual_nmis()) {
2779 enable_irq_window(vcpu);
2780 return;
2781 }
2782
2783 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2784 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2785 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2786}
2787
66fd3f7f 2788static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2789{
9c8cba37 2790 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2791 uint32_t intr;
2792 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2793
229456fc 2794 trace_kvm_inj_virq(irq);
2714d1d3 2795
fa89a817 2796 ++vcpu->stat.irq_injections;
7ffd92c5 2797 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2798 vmx->rmode.irq.pending = true;
2799 vmx->rmode.irq.vector = irq;
5fdbf976 2800 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2801 if (vcpu->arch.interrupt.soft)
2802 vmx->rmode.irq.rip +=
2803 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2804 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2805 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2806 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2807 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2808 return;
2809 }
66fd3f7f
GN		 2810 intr = irq | INTR_INFO_VALID_MASK;
2811 if (vcpu->arch.interrupt.soft) {
2812 intr |= INTR_TYPE_SOFT_INTR;
2813 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2814 vmx->vcpu.arch.event_exit_inst_len);
2815 } else
2816 intr |= INTR_TYPE_EXT_INTR;
2817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2818}
2819
f08864b4
SY		 2820static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2821{
66a5a347
JK		 2822 struct vcpu_vmx *vmx = to_vmx(vcpu);
2823
3b86cd99
JK		 2824 if (!cpu_has_virtual_nmis()) {
2825 /*
2826 * Tracking the NMI-blocked state in software is built upon
2827 * finding the next open IRQ window. This, in turn, depends on
2828 * well-behaving guests: They have to keep IRQs disabled at
2829 * least as long as the NMI handler runs. Otherwise we may
2830 * cause NMI nesting, maybe breaking the guest. But as this is
2831 * highly unlikely, we can live with the residual risk.
2832 */
2833 vmx->soft_vnmi_blocked = 1;
2834 vmx->vnmi_blocked_time = 0;
2835 }
2836
487b391d 2837 ++vcpu->stat.nmi_injections;
7ffd92c5 2838 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2839 vmx->rmode.irq.pending = true;
2840 vmx->rmode.irq.vector = NMI_VECTOR;
2841 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2842 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2843 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2844 INTR_INFO_VALID_MASK);
2845 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2846 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2847 return;
2848 }
f08864b4
SY		 2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2850 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2851}
2852
c4282df9 2853static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2854{
3b86cd99 2855 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2856 return 0;
33f089ca 2857
c4282df9 2858 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2859 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2860}
2861
3cfc3092
JK		 2862static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2863{
2864 if (!cpu_has_virtual_nmis())
2865 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2866 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2867}
2868
2869static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2870{
2871 struct vcpu_vmx *vmx = to_vmx(vcpu);
2872
2873 if (!cpu_has_virtual_nmis()) {
2874 if (vmx->soft_vnmi_blocked != masked) {
2875 vmx->soft_vnmi_blocked = masked;
2876 vmx->vnmi_blocked_time = 0;
2877 }
2878 } else {
2879 if (masked)
2880 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2881 GUEST_INTR_STATE_NMI);
2882 else
2883 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2884 GUEST_INTR_STATE_NMI);
2885 }
2886}
2887
78646121
GN		 2888static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2889{
c4282df9
GN		 2890 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2891 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2892 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2893}
2894
cbc94022
IE		 2895static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2896{
2897 int ret;
2898 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2899 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2900 .guest_phys_addr = addr,
2901 .memory_size = PAGE_SIZE * 3,
2902 .flags = 0,
2903 };
2904
2905 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2906 if (ret)
2907 return ret;
bfc6d222 2908 kvm->arch.tss_addr = addr;
cbc94022
IE		 2909 return 0;
2910}
2911
6aa8b732
AK		 2912static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2913 int vec, u32 err_code)
2914{
b3f37707
NK		 2915 /*
2916 * Instruction with address size override prefix opcode 0x67
2917 * Cause the #SS fault with 0 error code in VM86 mode.
2918 */
2919 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2920 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2921 return 1;
77ab6db0
JK		 2922 /*
2923 * Forward all other exceptions that are valid in real mode.
2924 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2925 * the required debugging infrastructure rework.
2926 */
2927 switch (vec) {
77ab6db0 2928 case DB_VECTOR:
d0bfb940
JK		 2929 if (vcpu->guest_debug &
2930 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2931 return 0;
2932 kvm_queue_exception(vcpu, vec);
2933 return 1;
77ab6db0 2934 case BP_VECTOR:
c573cd22
JK		 2935 /*
2936 * Update instruction length as we may reinject the exception
2937 * from user space while in guest debugging mode.
2938 */
2939 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2940 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2941 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2942 return 0;
2943 /* fall through */
2944 case DE_VECTOR:
77ab6db0
JK		 2945 case OF_VECTOR:
2946 case BR_VECTOR:
2947 case UD_VECTOR:
2948 case DF_VECTOR:
2949 case SS_VECTOR:
2950 case GP_VECTOR:
2951 case MF_VECTOR:
2952 kvm_queue_exception(vcpu, vec);
2953 return 1;
2954 }
6aa8b732
AK		 2955 return 0;
2956}
2957
a0861c02
AK		 2958/*
2959 * Trigger machine check on the host. We assume all the MSRs are already set up
2960 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2961 * We pass a fake environment to the machine check handler because we want
2962 * the guest to be always treated like user space, no matter what context
2963 * it used internally.
2964 */
2965static void kvm_machine_check(void)
2966{
2967#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2968 struct pt_regs regs = {
2969 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2970 .flags = X86_EFLAGS_IF,
2971 };
2972
2973 do_machine_check(&regs, 0);
2974#endif
2975}
2976
851ba692 2977static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2978{
2979 /* already handled by vcpu_run */
2980 return 1;
2981}
2982
851ba692 2983static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2984{
1155f76a 2985 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2986 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2987 u32 intr_info, ex_no, error_code;
42dbaa5a 2988 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2989 u32 vect_info;
2990 enum emulation_result er;
2991
1155f76a 2992 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2993 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2994
a0861c02 2995 if (is_machine_check(intr_info))
851ba692 2996 return handle_machine_check(vcpu);
a0861c02 2997
6aa8b732 2998 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2999 !is_page_fault(intr_info)) {
3000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3002 vcpu->run->internal.ndata = 2;
3003 vcpu->run->internal.data[0] = vect_info;
3004 vcpu->run->internal.data[1] = intr_info;
3005 return 0;
3006 }
6aa8b732 3007
e4a41889 3008 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3009 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3010
3011 if (is_no_device(intr_info)) {
5fd86fcf 3012 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3013 return 1;
3014 }
3015
7aa81cc0 3016 if (is_invalid_opcode(intr_info)) {
851ba692 3017 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3018 if (er != EMULATE_DONE)
7ee5d940 3019 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3020 return 1;
3021 }
3022
6aa8b732 3023 error_code = 0;
5fdbf976 3024 rip = kvm_rip_read(vcpu);
2e11384c 3025 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3026 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3027 if (is_page_fault(intr_info)) {
1439442c 3028 /* EPT won't cause page fault directly */
089d034e 3029 if (enable_ept)
1439442c 3030 BUG();
6aa8b732 3031 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3032 trace_kvm_page_fault(cr2, error_code);
3033
3298b75c 3034 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3035 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3036 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3037 }
3038
7ffd92c5 3039 if (vmx->rmode.vm86_active &&
6aa8b732 3040 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3041 error_code)) {
ad312c7c
ZX		 3042 if (vcpu->arch.halt_request) {
3043 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3044 return kvm_emulate_halt(vcpu);
3045 }
6aa8b732 3046 return 1;
72d6e5a0 3047 }
6aa8b732 3048
d0bfb940 3049 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3050 switch (ex_no) {
3051 case DB_VECTOR:
3052 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3053 if (!(vcpu->guest_debug &
3054 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3055 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3056 kvm_queue_exception(vcpu, DB_VECTOR);
3057 return 1;
3058 }
3059 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3060 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3061 /* fall through */
3062 case BP_VECTOR:
c573cd22
JK		 3063 /*
3064 * Update instruction length as we may reinject #BP from
3065 * user space while in guest debugging mode. Reading it for
3066 * #DB as well causes no harm, it is not used in that case.
3067 */
3068 vmx->vcpu.arch.event_exit_inst_len =
3069 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3070 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3071 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3072 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3073 break;
3074 default:
d0bfb940
JK		 3075 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3076 kvm_run->ex.exception = ex_no;
3077 kvm_run->ex.error_code = error_code;
42dbaa5a 3078 break;
6aa8b732 3079 }
6aa8b732
AK		 3080 return 0;
3081}
3082
851ba692 3083static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3084{
1165f5fe 3085 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3086 return 1;
3087}
3088
851ba692 3089static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3090{
851ba692 3091 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3092 return 0;
3093}
6aa8b732 3094
851ba692 3095static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3096{
bfdaab09 3097 unsigned long exit_qualification;
34c33d16 3098 int size, in, string;
039576c0 3099 unsigned port;
6aa8b732 3100
bfdaab09 3101 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3102 string = (exit_qualification & 16) != 0;
cf8f70bf 3103 in = (exit_qualification & 8) != 0;
e70669ab 3104
cf8f70bf 3105 ++vcpu->stat.io_exits;
e70669ab 3106
cf8f70bf 3107 if (string || in)
6d77dbfc 3108 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3109
cf8f70bf
GN		 3110 port = exit_qualification >> 16;
3111 size = (exit_qualification & 7) + 1;
e93f36bc 3112 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3113
3114 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3115}
3116
102d8325
IM		 3117static void
3118vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3119{
3120 /*
3121 * Patch in the VMCALL instruction:
3122 */
3123 hypercall[0] = 0x0f;
3124 hypercall[1] = 0x01;
3125 hypercall[2] = 0xc1;
102d8325
IM		 3126}
3127
851ba692 3128static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3129{
229456fc 3130 unsigned long exit_qualification, val;
6aa8b732
AK		 3131 int cr;
3132 int reg;
3133
bfdaab09 3134 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3135 cr = exit_qualification & 15;
3136 reg = (exit_qualification >> 8) & 15;
3137 switch ((exit_qualification >> 4) & 3) {
3138 case 0: /* mov to cr */
229456fc
MT		 3139 val = kvm_register_read(vcpu, reg);
3140 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3141 switch (cr) {
3142 case 0:
229456fc 3143 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3144 skip_emulated_instruction(vcpu);
3145 return 1;
3146 case 3:
229456fc 3147 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3148 skip_emulated_instruction(vcpu);
3149 return 1;
3150 case 4:
229456fc 3151 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3152 skip_emulated_instruction(vcpu);
3153 return 1;
0a5fff19
GN		 3154 case 8: {
3155 u8 cr8_prev = kvm_get_cr8(vcpu);
3156 u8 cr8 = kvm_register_read(vcpu, reg);
3157 kvm_set_cr8(vcpu, cr8);
3158 skip_emulated_instruction(vcpu);
3159 if (irqchip_in_kernel(vcpu->kvm))
3160 return 1;
3161 if (cr8_prev <= cr8)
3162 return 1;
851ba692 3163 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3164 return 0;
3165 }
6aa8b732
AK		 3166 };
3167 break;
25c4c276 3168 case 2: /* clts */
edcafe3c 3169 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3170 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3171 skip_emulated_instruction(vcpu);
6b52d186 3172 vmx_fpu_activate(vcpu);
25c4c276 3173 return 1;
6aa8b732
AK		 3174 case 1: /*mov from cr*/
3175 switch (cr) {
3176 case 3:
5fdbf976 3177 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3178 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3179 skip_emulated_instruction(vcpu);
3180 return 1;
3181 case 8:
229456fc
MT		 3182 val = kvm_get_cr8(vcpu);
3183 kvm_register_write(vcpu, reg, val);
3184 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3185 skip_emulated_instruction(vcpu);
3186 return 1;
3187 }
3188 break;
3189 case 3: /* lmsw */
a1f83a74 3190 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3191 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3192 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3193
3194 skip_emulated_instruction(vcpu);
3195 return 1;
3196 default:
3197 break;
3198 }
851ba692 3199 vcpu->run->exit_reason = 0;
f0242478 3200 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3201 (int)(exit_qualification >> 4) & 3, cr);
3202 return 0;
3203}
3204
851ba692 3205static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3206{
bfdaab09 3207 unsigned long exit_qualification;
6aa8b732
AK		 3208 int dr, reg;
3209
f2483415 3210 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3211 if (!kvm_require_cpl(vcpu, 0))
3212 return 1;
42dbaa5a
JK		 3213 dr = vmcs_readl(GUEST_DR7);
3214 if (dr & DR7_GD) {
3215 /*
3216 * As the vm-exit takes precedence over the debug trap, we
3217 * need to emulate the latter, either for the host or the
3218 * guest debugging itself.
3219 */
3220 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3221 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3222 vcpu->run->debug.arch.dr7 = dr;
3223 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3224 vmcs_readl(GUEST_CS_BASE) +
3225 vmcs_readl(GUEST_RIP);
851ba692
AK		 3226 vcpu->run->debug.arch.exception = DB_VECTOR;
3227 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3228 return 0;
3229 } else {
3230 vcpu->arch.dr7 &= ~DR7_GD;
3231 vcpu->arch.dr6 |= DR6_BD;
3232 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3233 kvm_queue_exception(vcpu, DB_VECTOR);
3234 return 1;
3235 }
3236 }
3237
bfdaab09 3238 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3239 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3240 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3241 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3242 unsigned long val;
3243 if (!kvm_get_dr(vcpu, dr, &val))
3244 kvm_register_write(vcpu, reg, val);
3245 } else
3246 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3247 skip_emulated_instruction(vcpu);
3248 return 1;
3249}
3250
020df079
GN		 3251static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3252{
3253 vmcs_writel(GUEST_DR7, val);
3254}
3255
851ba692 3256static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3257{
06465c5a
AK		 3258 kvm_emulate_cpuid(vcpu);
3259 return 1;
6aa8b732
AK		 3260}
3261
851ba692 3262static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3263{
ad312c7c 3264 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3265 u64 data;
3266
3267 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3268 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3269 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3270 return 1;
3271 }
3272
229456fc 3273 trace_kvm_msr_read(ecx, data);
2714d1d3 3274
6aa8b732 3275 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3276 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3277 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3278 skip_emulated_instruction(vcpu);
3279 return 1;
3280}
3281
851ba692 3282static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3283{
ad312c7c
ZX		 3284 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3285 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3286 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3287
3288 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3289 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3290 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3291 return 1;
3292 }
3293
59200273 3294 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3295 skip_emulated_instruction(vcpu);
3296 return 1;
3297}
3298
851ba692 3299static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3300{
3301 return 1;
3302}
3303
851ba692 3304static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3305{
85f455f7
ED		 3306 u32 cpu_based_vm_exec_control;
3307
3308 /* clear pending irq */
3309 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3310 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3311 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3312
a26bf12a 3313 ++vcpu->stat.irq_window_exits;
2714d1d3 3314
c1150d8c
DL		 3315 /*
3316 * If the user space waits to inject interrupts, exit as soon as
3317 * possible
3318 */
8061823a 3319 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3320 vcpu->run->request_interrupt_window &&
8061823a 3321 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3322 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3323 return 0;
3324 }
6aa8b732
AK		 3325 return 1;
3326}
3327
851ba692 3328static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3329{
3330 skip_emulated_instruction(vcpu);
d3bef15f 3331 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3332}
3333
851ba692 3334static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3335{
510043da 3336 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3337 kvm_emulate_hypercall(vcpu);
3338 return 1;
c21415e8
IM		 3339}
3340
851ba692 3341static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3342{
3343 kvm_queue_exception(vcpu, UD_VECTOR);
3344 return 1;
3345}
3346
851ba692 3347static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3348{
f9c617f6 3349 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3350
3351 kvm_mmu_invlpg(vcpu, exit_qualification);
3352 skip_emulated_instruction(vcpu);
3353 return 1;
3354}
3355
851ba692 3356static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3357{
3358 skip_emulated_instruction(vcpu);
3359 /* TODO: Add support for VT-d/pass-through device */
3360 return 1;
3361}
3362
851ba692 3363static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3364{
6d77dbfc 3365 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3366}
3367
851ba692 3368static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3369{
60637aac 3370 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3371 unsigned long exit_qualification;
e269fb21
JK		 3372 bool has_error_code = false;
3373 u32 error_code = 0;
37817f29 3374 u16 tss_selector;
64a7ec06
GN		 3375 int reason, type, idt_v;
3376
3377 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3378 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3379
3380 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3381
3382 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3383 if (reason == TASK_SWITCH_GATE && idt_v) {
3384 switch (type) {
3385 case INTR_TYPE_NMI_INTR:
3386 vcpu->arch.nmi_injected = false;
3387 if (cpu_has_virtual_nmis())
3388 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3389 GUEST_INTR_STATE_NMI);
3390 break;
3391 case INTR_TYPE_EXT_INTR:
66fd3f7f 3392 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3393 kvm_clear_interrupt_queue(vcpu);
3394 break;
3395 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3396 if (vmx->idt_vectoring_info &
3397 VECTORING_INFO_DELIVER_CODE_MASK) {
3398 has_error_code = true;
3399 error_code =
3400 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3401 }
3402 /* fall through */
64a7ec06
GN		 3403 case INTR_TYPE_SOFT_EXCEPTION:
3404 kvm_clear_exception_queue(vcpu);
3405 break;
3406 default:
3407 break;
3408 }
60637aac 3409 }
37817f29
IE		 3410 tss_selector = exit_qualification;
3411
64a7ec06
GN		 3412 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3413 type != INTR_TYPE_EXT_INTR &&
3414 type != INTR_TYPE_NMI_INTR))
3415 skip_emulated_instruction(vcpu);
3416
acb54517
GN		 3417 if (kvm_task_switch(vcpu, tss_selector, reason,
3418 has_error_code, error_code) == EMULATE_FAIL) {
3419 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3420 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3421 vcpu->run->internal.ndata = 0;
42dbaa5a 3422 return 0;
acb54517 3423 }
42dbaa5a
JK		 3424
3425 /* clear all local breakpoint enable flags */
3426 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3427
3428 /*
3429 * TODO: What about debug traps on tss switch?
3430 * Are we supposed to inject them and update dr6?
3431 */
3432
3433 return 1;
37817f29
IE		 3434}
3435
851ba692 3436static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3437{
f9c617f6 3438 unsigned long exit_qualification;
1439442c 3439 gpa_t gpa;
1439442c 3440 int gla_validity;
1439442c 3441
f9c617f6 3442 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3443
3444 if (exit_qualification & (1 << 6)) {
3445 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3446 return -EINVAL;
1439442c
SY		 3447 }
3448
3449 gla_validity = (exit_qualification >> 7) & 0x3;
3450 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3451 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3452 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3453 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3454 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3455 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3456 (long unsigned int)exit_qualification);
851ba692
AK		 3457 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3458 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3459 return 0;
1439442c
SY		 3460 }
3461
3462 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3463 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3464 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3465}
3466
68f89400
MT		 3467static u64 ept_rsvd_mask(u64 spte, int level)
3468{
3469 int i;
3470 u64 mask = 0;
3471
3472 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3473 mask |= (1ULL << i);
3474
3475 if (level > 2)
3476 /* bits 7:3 reserved */
3477 mask |= 0xf8;
3478 else if (level == 2) {
3479 if (spte & (1ULL << 7))
3480 /* 2MB ref, bits 20:12 reserved */
3481 mask |= 0x1ff000;
3482 else
3483 /* bits 6:3 reserved */
3484 mask |= 0x78;
3485 }
3486
3487 return mask;
3488}
3489
3490static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3491 int level)
3492{
3493 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3494
3495 /* 010b (write-only) */
3496 WARN_ON((spte & 0x7) == 0x2);
3497
3498 /* 110b (write/execute) */
3499 WARN_ON((spte & 0x7) == 0x6);
3500
3501 /* 100b (execute-only) and value not supported by logical processor */
3502 if (!cpu_has_vmx_ept_execute_only())
3503 WARN_ON((spte & 0x7) == 0x4);
3504
3505 /* not 000b */
3506 if ((spte & 0x7)) {
3507 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3508
3509 if (rsvd_bits != 0) {
3510 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3511 __func__, rsvd_bits);
3512 WARN_ON(1);
3513 }
3514
3515 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3516 u64 ept_mem_type = (spte & 0x38) >> 3;
3517
3518 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3519 ept_mem_type == 7) {
3520 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3521 __func__, ept_mem_type);
3522 WARN_ON(1);
3523 }
3524 }
3525 }
3526}
3527
851ba692 3528static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3529{
3530 u64 sptes[4];
3531 int nr_sptes, i;
3532 gpa_t gpa;
3533
3534 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3535
3536 printk(KERN_ERR "EPT: Misconfiguration.\n");
3537 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3538
3539 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3540
3541 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3542 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3543
851ba692
AK		 3544 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3545 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3546
3547 return 0;
3548}
3549
851ba692 3550static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3551{
3552 u32 cpu_based_vm_exec_control;
3553
3554 /* clear pending NMI */
3555 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3556 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3557 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3558 ++vcpu->stat.nmi_window_exits;
3559
3560 return 1;
3561}
3562
80ced186 3563static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3564{
8b3079a5
AK		 3565 struct vcpu_vmx *vmx = to_vmx(vcpu);
3566 enum emulation_result err = EMULATE_DONE;
80ced186 3567 int ret = 1;
ea953ef0
MG		 3568
3569 while (!guest_state_valid(vcpu)) {
851ba692 3570 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3571
80ced186
MG		 3572 if (err == EMULATE_DO_MMIO) {
3573 ret = 0;
3574 goto out;
3575 }
1d5a4d9b 3576
6d77dbfc
GN		 3577 if (err != EMULATE_DONE)
3578 return 0;
ea953ef0
MG		 3579
3580 if (signal_pending(current))
80ced186 3581 goto out;
ea953ef0
MG		 3582 if (need_resched())
3583 schedule();
3584 }
3585
80ced186
MG		 3586 vmx->emulation_required = 0;
3587out:
3588 return ret;
ea953ef0
MG		 3589}
3590
4b8d54f9
ZE		 3591/*
3592 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3593 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3594 */
9fb41ba8 3595static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3596{
3597 skip_emulated_instruction(vcpu);
3598 kvm_vcpu_on_spin(vcpu);
3599
3600 return 1;
3601}
3602
59708670
SY		 3603static int handle_invalid_op(struct kvm_vcpu *vcpu)
3604{
3605 kvm_queue_exception(vcpu, UD_VECTOR);
3606 return 1;
3607}
3608
6aa8b732
AK		 3609/*
3610 * The exit handlers return 1 if the exit was handled fully and guest execution
3611 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3612 * to be done to userspace and return 0.
3613 */
851ba692 3614static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3615 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3616 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3617 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3618 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3619 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3620 [EXIT_REASON_CR_ACCESS] = handle_cr,
3621 [EXIT_REASON_DR_ACCESS] = handle_dr,
3622 [EXIT_REASON_CPUID] = handle_cpuid,
3623 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3624 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3625 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3626 [EXIT_REASON_HLT] = handle_halt,
a7052897 3627 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3628 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3629 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3630 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3631 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3632 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3633 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3634 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3635 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3636 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3637 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3638 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3639 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3640 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3641 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3642 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3643 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3644 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3645 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3646 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3647 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3648};
3649
3650static const int kvm_vmx_max_exit_handlers =
50a3485c 3651 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3652
3653/*
3654 * The guest has exited. See if we can fix it or if we need userspace
3655 * assistance.
3656 */
851ba692 3657static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3658{
29bd8a78 3659 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3660 u32 exit_reason = vmx->exit_reason;
1155f76a 3661 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3662
5bfd8b54 3663 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3664
80ced186
MG		 3665 /* If guest state is invalid, start emulating */
3666 if (vmx->emulation_required && emulate_invalid_guest_state)
3667 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3668
1439442c
SY		 3669 /* Access CR3 don't cause VMExit in paging mode, so we need
3670 * to sync with guest real CR3. */
6de4f3ad 3671 if (enable_ept && is_paging(vcpu))
1439442c 3672 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3673
5120702e
MG		 3674 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3675 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3676 vcpu->run->fail_entry.hardware_entry_failure_reason
3677 = exit_reason;
3678 return 0;
3679 }
3680
29bd8a78 3681 if (unlikely(vmx->fail)) {
851ba692
AK		 3682 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3683 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3684 = vmcs_read32(VM_INSTRUCTION_ERROR);
3685 return 0;
3686 }
6aa8b732 3687
d77c26fc 3688 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3689 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3690 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3691 exit_reason != EXIT_REASON_TASK_SWITCH))
3692 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3693 "(0x%x) and exit reason is 0x%x\n",
3694 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3695
3696 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3697 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3698 vmx->soft_vnmi_blocked = 0;
3b86cd99 3699 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3700 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3701 /*
3702 * This CPU don't support us in finding the end of an
3703 * NMI-blocked window if the guest runs with IRQs
3704 * disabled. So we pull the trigger after 1 s of
3705 * futile waiting, but inform the user about this.
3706 */
3707 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3708 "state on VCPU %d after 1 s timeout\n",
3709 __func__, vcpu->vcpu_id);
3710 vmx->soft_vnmi_blocked = 0;
3b86cd99 3711 }
3b86cd99
JK		 3712 }
3713
6aa8b732
AK		 3714 if (exit_reason < kvm_vmx_max_exit_handlers
3715 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3716 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3717 else {
851ba692
AK		 3718 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3719 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3720 }
3721 return 0;
3722}
3723
95ba8273 3724static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3725{
95ba8273 3726 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3727 vmcs_write32(TPR_THRESHOLD, 0);
3728 return;
3729 }
3730
95ba8273 3731 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3732}
3733
cf393f75
AK		 3734static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3735{
3736 u32 exit_intr_info;
7b4a25cb 3737 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3738 bool unblock_nmi;
3739 u8 vector;
668f612f
AK		 3740 int type;
3741 bool idtv_info_valid;
cf393f75
AK		 3742
3743 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3744
a0861c02
AK		 3745 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3746
3747 /* Handle machine checks before interrupts are enabled */
3748 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3749 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3750 && is_machine_check(exit_intr_info)))
3751 kvm_machine_check();
3752
20f65983
GN		 3753 /* We need to handle NMIs before interrupts are enabled */
3754 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3755 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3756 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3757 asm("int $2");
ff9d07a0
ZY		 3758 kvm_after_handle_nmi(&vmx->vcpu);
3759 }
20f65983
GN		 3760
3761 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3762
cf393f75
AK		 3763 if (cpu_has_virtual_nmis()) {
3764 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3765 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3766 /*
7b4a25cb 3767 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3768 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3769 * a guest IRET fault.
7b4a25cb
GN		 3770 * SDM 3: 23.2.2 (September 2008)
3771 * Bit 12 is undefined in any of the following cases:
3772 * If the VM exit sets the valid bit in the IDT-vectoring
3773 * information field.
3774 * If the VM exit is due to a double fault.
cf393f75 3775 */
7b4a25cb
GN		 3776 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3777 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3778 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3779 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3780 } else if (unlikely(vmx->soft_vnmi_blocked))
3781 vmx->vnmi_blocked_time +=
3782 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3783
37b96e98
GN		 3784 vmx->vcpu.arch.nmi_injected = false;
3785 kvm_clear_exception_queue(&vmx->vcpu);
3786 kvm_clear_interrupt_queue(&vmx->vcpu);
3787
3788 if (!idtv_info_valid)
3789 return;
3790
668f612f
AK		 3791 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3792 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3793
64a7ec06 3794 switch (type) {
37b96e98
GN		 3795 case INTR_TYPE_NMI_INTR:
3796 vmx->vcpu.arch.nmi_injected = true;
668f612f 3797 /*
7b4a25cb 3798 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3799 * Clear bit "block by NMI" before VM entry if a NMI
3800 * delivery faulted.
668f612f 3801 */
37b96e98
GN		 3802 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3803 GUEST_INTR_STATE_NMI);
3804 break;
37b96e98 3805 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3806 vmx->vcpu.arch.event_exit_inst_len =
3807 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3808 /* fall through */
3809 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3810 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3811 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3812 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3813 } else
3814 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3815 break;
66fd3f7f
GN		 3816 case INTR_TYPE_SOFT_INTR:
3817 vmx->vcpu.arch.event_exit_inst_len =
3818 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3819 /* fall through */
37b96e98 3820 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3821 kvm_queue_interrupt(&vmx->vcpu, vector,
3822 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3823 break;
3824 default:
3825 break;
f7d9238f 3826 }
cf393f75
AK		 3827}
3828
9c8cba37
AK		 3829/*
3830 * Failure to inject an interrupt should give us the information
3831 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3832 * when fetching the interrupt redirection bitmap in the real-mode
3833 * tss, this doesn't happen. So we do it ourselves.
3834 */
3835static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3836{
3837 vmx->rmode.irq.pending = 0;
5fdbf976 3838 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3839 return;
5fdbf976 3840 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3841 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3842 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3843 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3844 return;
3845 }
3846 vmx->idt_vectoring_info =
3847 VECTORING_INFO_VALID_MASK
3848 | INTR_TYPE_EXT_INTR
3849 | vmx->rmode.irq.vector;
3850}
3851
c801949d
AK		 3852#ifdef CONFIG_X86_64
3853#define R "r"
3854#define Q "q"
3855#else
3856#define R "e"
3857#define Q "l"
3858#endif
3859
851ba692 3860static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3861{
a2fa3e9f 3862 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3863
3b86cd99
JK		 3864 /* Record the guest's net vcpu time for enforced NMI injections. */
3865 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3866 vmx->entry_time = ktime_get();
3867
80ced186
MG		 3868 /* Don't enter VMX if guest state is invalid, let the exit handler
3869 start emulation until we arrive back to a valid state */
3870 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3871 return;
a89a8fb9 3872
5fdbf976
MT		 3873 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3874 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3875 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3876 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3877
787ff736
GN		 3878 /* When single-stepping over STI and MOV SS, we must clear the
3879 * corresponding interruptibility bits in the guest state. Otherwise
3880 * vmentry fails as it then expects bit 14 (BS) in pending debug
3881 * exceptions being set, but that's not correct for the guest debugging
3882 * case. */
3883 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3884 vmx_set_interrupt_shadow(vcpu, 0);
3885
d77c26fc 3886 asm(
6aa8b732 3887 /* Store host registers */
c801949d
AK		 3888 "push %%"R"dx; push %%"R"bp;"
3889 "push %%"R"cx \n\t"
313dbd49
AK		 3890 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3891 "je 1f \n\t"
3892 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3893 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3894 "1: \n\t"
d3edefc0
AK		 3895 /* Reload cr2 if changed */
3896 "mov %c[cr2](%0), %%"R"ax \n\t"
3897 "mov %%cr2, %%"R"dx \n\t"
3898 "cmp %%"R"ax, %%"R"dx \n\t"
3899 "je 2f \n\t"
3900 "mov %%"R"ax, %%cr2 \n\t"
3901 "2: \n\t"
6aa8b732 3902 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3903 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3904 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3905 "mov %c[rax](%0), %%"R"ax \n\t"
3906 "mov %c[rbx](%0), %%"R"bx \n\t"
3907 "mov %c[rdx](%0), %%"R"dx \n\t"
3908 "mov %c[rsi](%0), %%"R"si \n\t"
3909 "mov %c[rdi](%0), %%"R"di \n\t"
3910 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3911#ifdef CONFIG_X86_64
e08aa78a
AK		 3912 "mov %c[r8](%0), %%r8 \n\t"
3913 "mov %c[r9](%0), %%r9 \n\t"
3914 "mov %c[r10](%0), %%r10 \n\t"
3915 "mov %c[r11](%0), %%r11 \n\t"
3916 "mov %c[r12](%0), %%r12 \n\t"
3917 "mov %c[r13](%0), %%r13 \n\t"
3918 "mov %c[r14](%0), %%r14 \n\t"
3919 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3920#endif
c801949d
AK		 3921 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3922
6aa8b732 3923 /* Enter guest mode */
cd2276a7 3924 "jne .Llaunched \n\t"
4ecac3fd 3925 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3926 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3927 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3928 ".Lkvm_vmx_return: "
6aa8b732 3929 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3930 "xchg %0, (%%"R"sp) \n\t"
3931 "mov %%"R"ax, %c[rax](%0) \n\t"
3932 "mov %%"R"bx, %c[rbx](%0) \n\t"
3933 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3934 "mov %%"R"dx, %c[rdx](%0) \n\t"
3935 "mov %%"R"si, %c[rsi](%0) \n\t"
3936 "mov %%"R"di, %c[rdi](%0) \n\t"
3937 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3938#ifdef CONFIG_X86_64
e08aa78a
AK		 3939 "mov %%r8, %c[r8](%0) \n\t"
3940 "mov %%r9, %c[r9](%0) \n\t"
3941 "mov %%r10, %c[r10](%0) \n\t"
3942 "mov %%r11, %c[r11](%0) \n\t"
3943 "mov %%r12, %c[r12](%0) \n\t"
3944 "mov %%r13, %c[r13](%0) \n\t"
3945 "mov %%r14, %c[r14](%0) \n\t"
3946 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3947#endif
c801949d
AK		 3948 "mov %%cr2, %%"R"ax \n\t"
3949 "mov %%"R"ax, %c[cr2](%0) \n\t"
3950
3951 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3952 "setbe %c[fail](%0) \n\t"
3953 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3954 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3955 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3956 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3957 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3958 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3959 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3960 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3961 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3962 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3963 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3964#ifdef CONFIG_X86_64
ad312c7c
ZX		 3965 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3966 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3967 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3968 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3969 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3970 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3971 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3972 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3973#endif
ad312c7c 3974 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3975 : "cc", "memory"
c801949d 3976 , R"bx", R"di", R"si"
c2036300 3977#ifdef CONFIG_X86_64
c2036300
LV		 3978 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3979#endif
3980 );
6aa8b732 3981
6de4f3ad
AK		 3982 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3983 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3984 vcpu->arch.regs_dirty = 0;
3985
1155f76a 3986 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3987 if (vmx->rmode.irq.pending)
3988 fixup_rmode_irq(vmx);
1155f76a 3989
d77c26fc 3990 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3991 vmx->launched = 1;
1b6269db 3992
cf393f75 3993 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3994}
3995
c801949d
AK		 3996#undef R
3997#undef Q
3998
6aa8b732
AK		 3999static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4000{
a2fa3e9f
GH		 4001 struct vcpu_vmx *vmx = to_vmx(vcpu);
4002
4003 if (vmx->vmcs) {
543e4243 4004 vcpu_clear(vmx);
a2fa3e9f
GH		 4005 free_vmcs(vmx->vmcs);
4006 vmx->vmcs = NULL;
6aa8b732
AK		 4007 }
4008}
4009
4010static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4011{
fb3f0f51
RR		 4012 struct vcpu_vmx *vmx = to_vmx(vcpu);
4013
cdbecfc3 4014 free_vpid(vmx);
6aa8b732 4015 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4016 kfree(vmx->guest_msrs);
4017 kvm_vcpu_uninit(vcpu);
a4770347 4018 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4019}
4020
4610c9cc
DX		 4021static inline void vmcs_init(struct vmcs *vmcs)
4022{
4023 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4024
4025 if (!vmm_exclusive)
4026 kvm_cpu_vmxon(phys_addr);
4027
4028 vmcs_clear(vmcs);
4029
4030 if (!vmm_exclusive)
4031 kvm_cpu_vmxoff();
4032}
4033
fb3f0f51 4034static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4035{
fb3f0f51 4036 int err;
c16f862d 4037 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4038 int cpu;
6aa8b732 4039
a2fa3e9f 4040 if (!vmx)
fb3f0f51
RR		 4041 return ERR_PTR(-ENOMEM);
4042
2384d2b3
SY		 4043 allocate_vpid(vmx);
4044
fb3f0f51
RR		 4045 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4046 if (err)
4047 goto free_vcpu;
965b58a5 4048
a2fa3e9f 4049 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4050 if (!vmx->guest_msrs) {
4051 err = -ENOMEM;
4052 goto uninit_vcpu;
4053 }
965b58a5 4054
a2fa3e9f
GH		 4055 vmx->vmcs = alloc_vmcs();
4056 if (!vmx->vmcs)
fb3f0f51 4057 goto free_msrs;
a2fa3e9f 4058
4610c9cc 4059 vmcs_init(vmx->vmcs);
a2fa3e9f 4060
15ad7146
AK		 4061 cpu = get_cpu();
4062 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4063 err = vmx_vcpu_setup(vmx);
fb3f0f51 4064 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4065 put_cpu();
fb3f0f51
RR		 4066 if (err)
4067 goto free_vmcs;
5e4a0b3c
MT		 4068 if (vm_need_virtualize_apic_accesses(kvm))
4069 if (alloc_apic_access_page(kvm) != 0)
4070 goto free_vmcs;
fb3f0f51 4071
b927a3ce
SY		 4072 if (enable_ept) {
4073 if (!kvm->arch.ept_identity_map_addr)
4074 kvm->arch.ept_identity_map_addr =
4075 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4076 if (alloc_identity_pagetable(kvm) != 0)
4077 goto free_vmcs;
b927a3ce 4078 }
b7ebfb05 4079
fb3f0f51
RR		 4080 return &vmx->vcpu;
4081
4082free_vmcs:
4083 free_vmcs(vmx->vmcs);
4084free_msrs:
fb3f0f51
RR		 4085 kfree(vmx->guest_msrs);
4086uninit_vcpu:
4087 kvm_vcpu_uninit(&vmx->vcpu);
4088free_vcpu:
cdbecfc3 4089 free_vpid(vmx);
a4770347 4090 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4091 return ERR_PTR(err);
6aa8b732
AK		 4092}
4093
002c7f7c
YS		 4094static void __init vmx_check_processor_compat(void *rtn)
4095{
4096 struct vmcs_config vmcs_conf;
4097
4098 *(int *)rtn = 0;
4099 if (setup_vmcs_config(&vmcs_conf) < 0)
4100 *(int *)rtn = -EIO;
4101 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4102 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4103 smp_processor_id());
4104 *(int *)rtn = -EIO;
4105 }
4106}
4107
67253af5
SY		 4108static int get_ept_level(void)
4109{
4110 return VMX_EPT_DEFAULT_GAW + 1;
4111}
4112
4b12f0de 4113static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4114{
4b12f0de
SY		 4115 u64 ret;
4116
522c68c4
SY		 4117 /* For VT-d and EPT combination
4118 * 1. MMIO: always map as UC
4119 * 2. EPT with VT-d:
4120 * a. VT-d without snooping control feature: can't guarantee the
4121 * result, try to trust guest.
4122 * b. VT-d with snooping control feature: snooping control feature of
4123 * VT-d engine can guarantee the cache correctness. Just set it
4124 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4125 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4126 * consistent with host MTRR
4127 */
4b12f0de
SY		 4128 if (is_mmio)
4129 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4130 else if (vcpu->kvm->arch.iommu_domain &&
4131 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4132 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4133 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4134 else
522c68c4 4135 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4136 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4137
4138 return ret;
64d4d521
SY		 4139}
4140
f4c9e87c
AK		 4141#define _ER(x) { EXIT_REASON_##x, #x }
4142
229456fc 4143static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4144 _ER(EXCEPTION_NMI),
4145 _ER(EXTERNAL_INTERRUPT),
4146 _ER(TRIPLE_FAULT),
4147 _ER(PENDING_INTERRUPT),
4148 _ER(NMI_WINDOW),
4149 _ER(TASK_SWITCH),
4150 _ER(CPUID),
4151 _ER(HLT),
4152 _ER(INVLPG),
4153 _ER(RDPMC),
4154 _ER(RDTSC),
4155 _ER(VMCALL),
4156 _ER(VMCLEAR),
4157 _ER(VMLAUNCH),
4158 _ER(VMPTRLD),
4159 _ER(VMPTRST),
4160 _ER(VMREAD),
4161 _ER(VMRESUME),
4162 _ER(VMWRITE),
4163 _ER(VMOFF),
4164 _ER(VMON),
4165 _ER(CR_ACCESS),
4166 _ER(DR_ACCESS),
4167 _ER(IO_INSTRUCTION),
4168 _ER(MSR_READ),
4169 _ER(MSR_WRITE),
4170 _ER(MWAIT_INSTRUCTION),
4171 _ER(MONITOR_INSTRUCTION),
4172 _ER(PAUSE_INSTRUCTION),
4173 _ER(MCE_DURING_VMENTRY),
4174 _ER(TPR_BELOW_THRESHOLD),
4175 _ER(APIC_ACCESS),
4176 _ER(EPT_VIOLATION),
4177 _ER(EPT_MISCONFIG),
4178 _ER(WBINVD),
229456fc
MT		 4179 { -1, NULL }
4180};
4181
f4c9e87c
AK		 4182#undef _ER
4183
17cc3935 4184static int vmx_get_lpage_level(void)
344f414f 4185{
878403b7
SY		 4186 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4187 return PT_DIRECTORY_LEVEL;
4188 else
4189 /* For shadow and EPT supported 1GB page */
4190 return PT_PDPE_LEVEL;
344f414f
JR		 4191}
4192
4e47c7a6
SY		 4193static inline u32 bit(int bitno)
4194{
4195 return 1 << (bitno & 31);
4196}
4197
0e851880
SY		 4198static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4199{
4e47c7a6
SY		 4200 struct kvm_cpuid_entry2 *best;
4201 struct vcpu_vmx *vmx = to_vmx(vcpu);
4202 u32 exec_control;
4203
4204 vmx->rdtscp_enabled = false;
4205 if (vmx_rdtscp_supported()) {
4206 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4207 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4208 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4209 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4210 vmx->rdtscp_enabled = true;
4211 else {
4212 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4213 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4214 exec_control);
4215 }
4216 }
4217 }
0e851880
SY		 4218}
4219
d4330ef2
JR		 4220static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4221{
4222}
4223
cbdd1bea 4224static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4225 .cpu_has_kvm_support = cpu_has_kvm_support,
4226 .disabled_by_bios = vmx_disabled_by_bios,
4227 .hardware_setup = hardware_setup,
4228 .hardware_unsetup = hardware_unsetup,
002c7f7c 4229 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4230 .hardware_enable = hardware_enable,
4231 .hardware_disable = hardware_disable,
04547156 4232 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4233
4234 .vcpu_create = vmx_create_vcpu,
4235 .vcpu_free = vmx_free_vcpu,
04d2cc77 4236 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4237
04d2cc77 4238 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4239 .vcpu_load = vmx_vcpu_load,
4240 .vcpu_put = vmx_vcpu_put,
4241
4242 .set_guest_debug = set_guest_debug,
4243 .get_msr = vmx_get_msr,
4244 .set_msr = vmx_set_msr,
4245 .get_segment_base = vmx_get_segment_base,
4246 .get_segment = vmx_get_segment,
4247 .set_segment = vmx_set_segment,
2e4d2653 4248 .get_cpl = vmx_get_cpl,
6aa8b732 4249 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4250 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4251 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4252 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4253 .set_cr3 = vmx_set_cr3,
4254 .set_cr4 = vmx_set_cr4,
6aa8b732 4255 .set_efer = vmx_set_efer,
6aa8b732
AK		 4256 .get_idt = vmx_get_idt,
4257 .set_idt = vmx_set_idt,
4258 .get_gdt = vmx_get_gdt,
4259 .set_gdt = vmx_set_gdt,
020df079 4260 .set_dr7 = vmx_set_dr7,
5fdbf976 4261 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4262 .get_rflags = vmx_get_rflags,
4263 .set_rflags = vmx_set_rflags,
ebcbab4c 4264 .fpu_activate = vmx_fpu_activate,
02daab21 4265 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4266
4267 .tlb_flush = vmx_flush_tlb,
6aa8b732 4268
6aa8b732 4269 .run = vmx_vcpu_run,
6062d012 4270 .handle_exit = vmx_handle_exit,
6aa8b732 4271 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4272 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4273 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4274 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4275 .set_irq = vmx_inject_irq,
95ba8273 4276 .set_nmi = vmx_inject_nmi,
298101da 4277 .queue_exception = vmx_queue_exception,
78646121 4278 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4279 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4280 .get_nmi_mask = vmx_get_nmi_mask,
4281 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4282 .enable_nmi_window = enable_nmi_window,
4283 .enable_irq_window = enable_irq_window,
4284 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4285
cbc94022 4286 .set_tss_addr = vmx_set_tss_addr,
67253af5 4287 .get_tdp_level = get_ept_level,
4b12f0de 4288 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4289
4290 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4291 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4292
4293 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4294
4295 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4296
4297 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4298};
4299
4300static int __init vmx_init(void)
4301{
26bb0981
AK		 4302 int r, i;
4303
4304 rdmsrl_safe(MSR_EFER, &host_efer);
4305
4306 for (i = 0; i < NR_VMX_MSR; ++i)
4307 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4308
3e7c73e9 4309 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4310 if (!vmx_io_bitmap_a)
4311 return -ENOMEM;
4312
3e7c73e9 4313 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4314 if (!vmx_io_bitmap_b) {
4315 r = -ENOMEM;
4316 goto out;
4317 }
4318
5897297b
AK		 4319 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4320 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4321 r = -ENOMEM;
4322 goto out1;
4323 }
4324
5897297b
AK		 4325 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4326 if (!vmx_msr_bitmap_longmode) {
4327 r = -ENOMEM;
4328 goto out2;
4329 }
4330
fdef3ad1
HQ		 4331 /*
4332 * Allow direct access to the PC debug port (it is often used for I/O
4333 * delays, but the vmexits simply slow things down).
4334 */
3e7c73e9
AK		 4335 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4336 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4337
3e7c73e9 4338 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4339
5897297b
AK		 4340 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4341 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4342
2384d2b3
SY		 4343 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4344
0ee75bea
AK		 4345 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4346 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4347 if (r)
5897297b 4348 goto out3;
25c5f225 4349
5897297b
AK		 4350 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4351 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4352 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4353 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4354 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4355 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4356
089d034e 4357 if (enable_ept) {
1439442c 4358 bypass_guest_pf = 0;
5fdbcb9d 4359 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4360 VMX_EPT_WRITABLE_MASK);
534e38b4 4361 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4362 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4363 kvm_enable_tdp();
4364 } else
4365 kvm_disable_tdp();
1439442c 4366
c7addb90
AK		 4367 if (bypass_guest_pf)
4368 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4369
fdef3ad1
HQ		 4370 return 0;
4371
5897297b
AK		 4372out3:
4373 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4374out2:
5897297b 4375 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4376out1:
3e7c73e9 4377 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4378out:
3e7c73e9 4379 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4380 return r;
6aa8b732
AK		 4381}
4382
4383static void __exit vmx_exit(void)
4384{
5897297b
AK		 4385 free_page((unsigned long)vmx_msr_bitmap_legacy);
4386 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4387 free_page((unsigned long)vmx_io_bitmap_b);
4388 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4389
cb498ea2 4390 kvm_exit();
6aa8b732
AK		 4391}
4392
4393module_init(vmx_init)
4394module_exit(vmx_exit)
Linux kernel - Deliverables
This page took 0.760824 seconds and 5 git commands to generate.