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KVM: x86 emulator: Avoid clearing the whole decode_cache
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
cdc0e244
AK		 77#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
78 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
79#define KVM_GUEST_CR0_MASK \
80 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
81#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 82 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 83#define KVM_VM_CR0_ALWAYS_ON \
84 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 85#define KVM_CR4_GUEST_OWNED_BITS \
86 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
87 | X86_CR4_OSXMMEXCPT)
88
cdc0e244
AK		 89#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
90#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
91
78ac8b47
AK		 92#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
93
4b8d54f9
ZE		 94/*
95 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
96 * ple_gap: upper bound on the amount of time between two successive
97 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 98 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 99 * ple_window: upper bound on the amount of time a guest is allowed to execute
100 * in a PAUSE loop. Tests indicate that most spinlocks are held for
101 * less than 2^12 cycles
102 * Time is measured based on a counter that runs at the same rate as the TSC,
103 * refer SDM volume 3b section 21.6.13 & 22.1.3.
104 */
00c25bce 105#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 106#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
107static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
108module_param(ple_gap, int, S_IRUGO);
109
110static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
111module_param(ple_window, int, S_IRUGO);
112
61d2ef2c
AK		 113#define NR_AUTOLOAD_MSRS 1
114
a2fa3e9f
GH		 115struct vmcs {
116 u32 revision_id;
117 u32 abort;
118 char data[0];
119};
120
d462b819
NHE		 121/*
122 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
123 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
124 * loaded on this CPU (so we can clear them if the CPU goes down).
125 */
126struct loaded_vmcs {
127 struct vmcs *vmcs;
128 int cpu;
129 int launched;
130 struct list_head loaded_vmcss_on_cpu_link;
131};
132
26bb0981
AK		 133struct shared_msr_entry {
134 unsigned index;
135 u64 data;
d5696725 136 u64 mask;
26bb0981
AK		 137};
138
a2fa3e9f 139struct vcpu_vmx {
fb3f0f51 140 struct kvm_vcpu vcpu;
313dbd49 141 unsigned long host_rsp;
29bd8a78 142 u8 fail;
69c73028 143 u8 cpl;
9d58b931 144 bool nmi_known_unmasked;
51aa01d1 145 u32 exit_intr_info;
1155f76a 146 u32 idt_vectoring_info;
6de12732 147 ulong rflags;
26bb0981 148 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 149 int nmsrs;
150 int save_nmsrs;
a2fa3e9f 151#ifdef CONFIG_X86_64
44ea2b17
AK		 152 u64 msr_host_kernel_gs_base;
153 u64 msr_guest_kernel_gs_base;
a2fa3e9f 154#endif
d462b819
NHE		 155 /*
156 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
157 * non-nested (L1) guest, it always points to vmcs01. For a nested
158 * guest (L2), it points to a different VMCS.
159 */
160 struct loaded_vmcs vmcs01;
161 struct loaded_vmcs *loaded_vmcs;
162 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 163 struct msr_autoload {
164 unsigned nr;
165 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
166 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
167 } msr_autoload;
a2fa3e9f
GH		 168 struct {
169 int loaded;
170 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 171 int gs_ldt_reload_needed;
172 int fs_reload_needed;
d77c26fc 173 } host_state;
9c8cba37 174 struct {
7ffd92c5 175 int vm86_active;
78ac8b47 176 ulong save_rflags;
7ffd92c5
AK		 177 struct kvm_save_segment {
178 u16 selector;
179 unsigned long base;
180 u32 limit;
181 u32 ar;
182 } tr, es, ds, fs, gs;
9c8cba37 183 } rmode;
2fb92db1
AK		 184 struct {
185 u32 bitmask; /* 4 bits per segment (1 bit per field) */
186 struct kvm_save_segment seg[8];
187 } segment_cache;
2384d2b3 188 int vpid;
04fa4d32 189 bool emulation_required;
3b86cd99
JK		 190
191 /* Support for vnmi-less CPUs */
192 int soft_vnmi_blocked;
193 ktime_t entry_time;
194 s64 vnmi_blocked_time;
a0861c02 195 u32 exit_reason;
4e47c7a6
SY		 196
197 bool rdtscp_enabled;
a2fa3e9f
GH		 198};
199
2fb92db1
AK		 200enum segment_cache_field {
201 SEG_FIELD_SEL = 0,
202 SEG_FIELD_BASE = 1,
203 SEG_FIELD_LIMIT = 2,
204 SEG_FIELD_AR = 3,
205
206 SEG_FIELD_NR = 4
207};
208
a2fa3e9f
GH		 209static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
210{
fb3f0f51 211 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 212}
213
4e1096d2 214static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 215static void kvm_cpu_vmxon(u64 addr);
216static void kvm_cpu_vmxoff(void);
aff48baa 217static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 218static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 219
6aa8b732
AK		 220static DEFINE_PER_CPU(struct vmcs *, vmxarea);
221static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 222/*
223 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
224 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
225 */
226static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 227static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 228
3e7c73e9
AK		 229static unsigned long *vmx_io_bitmap_a;
230static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 231static unsigned long *vmx_msr_bitmap_legacy;
232static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 233
110312c8
AK		 234static bool cpu_has_load_ia32_efer;
235
2384d2b3
SY		 236static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
237static DEFINE_SPINLOCK(vmx_vpid_lock);
238
1c3d14fe 239static struct vmcs_config {
6aa8b732
AK		 240 int size;
241 int order;
242 u32 revision_id;
1c3d14fe
YS		 243 u32 pin_based_exec_ctrl;
244 u32 cpu_based_exec_ctrl;
f78e0e2e 245 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 246 u32 vmexit_ctrl;
247 u32 vmentry_ctrl;
248} vmcs_config;
6aa8b732 249
efff9e53 250static struct vmx_capability {
d56f546d
SY		 251 u32 ept;
252 u32 vpid;
253} vmx_capability;
254
6aa8b732
AK		 255#define VMX_SEGMENT_FIELD(seg) \
256 [VCPU_SREG_##seg] = { \
257 .selector = GUEST_##seg##_SELECTOR, \
258 .base = GUEST_##seg##_BASE, \
259 .limit = GUEST_##seg##_LIMIT, \
260 .ar_bytes = GUEST_##seg##_AR_BYTES, \
261 }
262
263static struct kvm_vmx_segment_field {
264 unsigned selector;
265 unsigned base;
266 unsigned limit;
267 unsigned ar_bytes;
268} kvm_vmx_segment_fields[] = {
269 VMX_SEGMENT_FIELD(CS),
270 VMX_SEGMENT_FIELD(DS),
271 VMX_SEGMENT_FIELD(ES),
272 VMX_SEGMENT_FIELD(FS),
273 VMX_SEGMENT_FIELD(GS),
274 VMX_SEGMENT_FIELD(SS),
275 VMX_SEGMENT_FIELD(TR),
276 VMX_SEGMENT_FIELD(LDTR),
277};
278
26bb0981
AK		 279static u64 host_efer;
280
6de4f3ad
AK		 281static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
282
4d56c8a7 283/*
8c06585d 284 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 285 * away by decrementing the array size.
286 */
6aa8b732 287static const u32 vmx_msr_index[] = {
05b3e0c2 288#ifdef CONFIG_X86_64
44ea2b17 289 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 290#endif
8c06585d 291 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 292};
9d8f549d 293#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 294
31299944 295static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 296{
297 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
298 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 299 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 300}
301
31299944 302static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 303{
304 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
305 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 306 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 307}
308
31299944 309static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 310{
311 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
312 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 313 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 314}
315
31299944 316static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 317{
318 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
319 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
320}
321
31299944 322static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 323{
324 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
325 INTR_INFO_VALID_MASK)) ==
326 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
327}
328
31299944 329static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 330{
04547156 331 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 332}
333
31299944 334static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 335{
04547156 336 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 337}
338
31299944 339static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 340{
04547156 341 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 342}
343
31299944 344static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 345{
04547156
SY		 346 return vmcs_config.cpu_based_exec_ctrl &
347 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 348}
349
774ead3a 350static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 351{
04547156
SY		 352 return vmcs_config.cpu_based_2nd_exec_ctrl &
353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
354}
355
356static inline bool cpu_has_vmx_flexpriority(void)
357{
358 return cpu_has_vmx_tpr_shadow() &&
359 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 360}
361
e799794e
MT		 362static inline bool cpu_has_vmx_ept_execute_only(void)
363{
31299944 364 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 365}
366
367static inline bool cpu_has_vmx_eptp_uncacheable(void)
368{
31299944 369 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 370}
371
372static inline bool cpu_has_vmx_eptp_writeback(void)
373{
31299944 374 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 375}
376
377static inline bool cpu_has_vmx_ept_2m_page(void)
378{
31299944 379 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 380}
381
878403b7
SY		 382static inline bool cpu_has_vmx_ept_1g_page(void)
383{
31299944 384 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 385}
386
4bc9b982
SY		 387static inline bool cpu_has_vmx_ept_4levels(void)
388{
389 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
390}
391
31299944 392static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 393{
31299944 394 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 395}
396
31299944 397static inline bool cpu_has_vmx_invept_context(void)
d56f546d 398{
31299944 399 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 400}
401
31299944 402static inline bool cpu_has_vmx_invept_global(void)
d56f546d 403{
31299944 404 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 405}
406
518c8aee
GJ		 407static inline bool cpu_has_vmx_invvpid_single(void)
408{
409 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
410}
411
b9d762fa
GJ		 412static inline bool cpu_has_vmx_invvpid_global(void)
413{
414 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
415}
416
31299944 417static inline bool cpu_has_vmx_ept(void)
d56f546d 418{
04547156
SY		 419 return vmcs_config.cpu_based_2nd_exec_ctrl &
420 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 421}
422
31299944 423static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 424{
425 return vmcs_config.cpu_based_2nd_exec_ctrl &
426 SECONDARY_EXEC_UNRESTRICTED_GUEST;
427}
428
31299944 429static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 430{
431 return vmcs_config.cpu_based_2nd_exec_ctrl &
432 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
433}
434
31299944 435static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 436{
6d3e435e 437 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 438}
439
31299944 440static inline bool cpu_has_vmx_vpid(void)
2384d2b3 441{
04547156
SY		 442 return vmcs_config.cpu_based_2nd_exec_ctrl &
443 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 444}
445
31299944 446static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 447{
448 return vmcs_config.cpu_based_2nd_exec_ctrl &
449 SECONDARY_EXEC_RDTSCP;
450}
451
31299944 452static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 453{
454 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
455}
456
f5f48ee1
SY		 457static inline bool cpu_has_vmx_wbinvd_exit(void)
458{
459 return vmcs_config.cpu_based_2nd_exec_ctrl &
460 SECONDARY_EXEC_WBINVD_EXITING;
461}
462
04547156
SY		 463static inline bool report_flexpriority(void)
464{
465 return flexpriority_enabled;
466}
467
8b9cf98c 468static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 469{
470 int i;
471
a2fa3e9f 472 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 473 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 474 return i;
475 return -1;
476}
477
2384d2b3
SY		 478static inline void __invvpid(int ext, u16 vpid, gva_t gva)
479{
480 struct {
481 u64 vpid : 16;
482 u64 rsvd : 48;
483 u64 gva;
484 } operand = { vpid, 0, gva };
485
4ecac3fd 486 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 487 /* CF==1 or ZF==1 --> rc = -1 */
488 "; ja 1f ; ud2 ; 1:"
489 : : "a"(&operand), "c"(ext) : "cc", "memory");
490}
491
1439442c
SY		 492static inline void __invept(int ext, u64 eptp, gpa_t gpa)
493{
494 struct {
495 u64 eptp, gpa;
496 } operand = {eptp, gpa};
497
4ecac3fd 498 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 499 /* CF==1 or ZF==1 --> rc = -1 */
500 "; ja 1f ; ud2 ; 1:\n"
501 : : "a" (&operand), "c" (ext) : "cc", "memory");
502}
503
26bb0981 504static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 505{
506 int i;
507
8b9cf98c 508 i = __find_msr_index(vmx, msr);
a75beee6 509 if (i >= 0)
a2fa3e9f 510 return &vmx->guest_msrs[i];
8b6d44c7 511 return NULL;
7725f0ba
AK		 512}
513
6aa8b732
AK		 514static void vmcs_clear(struct vmcs *vmcs)
515{
516 u64 phys_addr = __pa(vmcs);
517 u8 error;
518
4ecac3fd 519 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 520 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 521 : "cc", "memory");
522 if (error)
523 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
524 vmcs, phys_addr);
525}
526
d462b819
NHE		 527static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
528{
529 vmcs_clear(loaded_vmcs->vmcs);
530 loaded_vmcs->cpu = -1;
531 loaded_vmcs->launched = 0;
532}
533
7725b894
DX		 534static void vmcs_load(struct vmcs *vmcs)
535{
536 u64 phys_addr = __pa(vmcs);
537 u8 error;
538
539 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 540 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 541 : "cc", "memory");
542 if (error)
543 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
544 vmcs, phys_addr);
545}
546
d462b819 547static void __loaded_vmcs_clear(void *arg)
6aa8b732 548{
d462b819 549 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 550 int cpu = raw_smp_processor_id();
6aa8b732 551
d462b819
NHE		 552 if (loaded_vmcs->cpu != cpu)
553 return; /* vcpu migration can race with cpu offline */
554 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 555 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 556 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
557 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 558}
559
d462b819 560static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 561{
d462b819
NHE		 562 if (loaded_vmcs->cpu != -1)
563 smp_call_function_single(
564 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 565}
566
1760dd49 567static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 568{
569 if (vmx->vpid == 0)
570 return;
571
518c8aee
GJ		 572 if (cpu_has_vmx_invvpid_single())
573 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 574}
575
b9d762fa
GJ		 576static inline void vpid_sync_vcpu_global(void)
577{
578 if (cpu_has_vmx_invvpid_global())
579 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
580}
581
582static inline void vpid_sync_context(struct vcpu_vmx *vmx)
583{
584 if (cpu_has_vmx_invvpid_single())
1760dd49 585 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 586 else
587 vpid_sync_vcpu_global();
588}
589
1439442c
SY		 590static inline void ept_sync_global(void)
591{
592 if (cpu_has_vmx_invept_global())
593 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
594}
595
596static inline void ept_sync_context(u64 eptp)
597{
089d034e 598 if (enable_ept) {
1439442c
SY		 599 if (cpu_has_vmx_invept_context())
600 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
601 else
602 ept_sync_global();
603 }
604}
605
606static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
607{
089d034e 608 if (enable_ept) {
1439442c
SY		 609 if (cpu_has_vmx_invept_individual_addr())
610 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
611 eptp, gpa);
612 else
613 ept_sync_context(eptp);
614 }
615}
616
96304217 617static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 618{
5e520e62 619 unsigned long value;
6aa8b732 620
5e520e62
AK		 621 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
622 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 623 return value;
624}
625
96304217 626static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 627{
628 return vmcs_readl(field);
629}
630
96304217 631static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 632{
633 return vmcs_readl(field);
634}
635
96304217 636static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 637{
05b3e0c2 638#ifdef CONFIG_X86_64
6aa8b732
AK		 639 return vmcs_readl(field);
640#else
641 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
642#endif
643}
644
e52de1b8
AK		 645static noinline void vmwrite_error(unsigned long field, unsigned long value)
646{
647 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
648 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
649 dump_stack();
650}
651
6aa8b732
AK		 652static void vmcs_writel(unsigned long field, unsigned long value)
653{
654 u8 error;
655
4ecac3fd 656 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 657 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 658 if (unlikely(error))
659 vmwrite_error(field, value);
6aa8b732
AK		 660}
661
662static void vmcs_write16(unsigned long field, u16 value)
663{
664 vmcs_writel(field, value);
665}
666
667static void vmcs_write32(unsigned long field, u32 value)
668{
669 vmcs_writel(field, value);
670}
671
672static void vmcs_write64(unsigned long field, u64 value)
673{
6aa8b732 674 vmcs_writel(field, value);
7682f2d0 675#ifndef CONFIG_X86_64
6aa8b732
AK		 676 asm volatile ("");
677 vmcs_writel(field+1, value >> 32);
678#endif
679}
680
2ab455cc
AL		 681static void vmcs_clear_bits(unsigned long field, u32 mask)
682{
683 vmcs_writel(field, vmcs_readl(field) & ~mask);
684}
685
686static void vmcs_set_bits(unsigned long field, u32 mask)
687{
688 vmcs_writel(field, vmcs_readl(field) | mask);
689}
690
2fb92db1
AK		 691static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
692{
693 vmx->segment_cache.bitmask = 0;
694}
695
696static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
697 unsigned field)
698{
699 bool ret;
700 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
701
702 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
703 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
704 vmx->segment_cache.bitmask = 0;
705 }
706 ret = vmx->segment_cache.bitmask & mask;
707 vmx->segment_cache.bitmask |= mask;
708 return ret;
709}
710
711static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
712{
713 u16 *p = &vmx->segment_cache.seg[seg].selector;
714
715 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
716 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
717 return *p;
718}
719
720static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
721{
722 ulong *p = &vmx->segment_cache.seg[seg].base;
723
724 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
725 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
726 return *p;
727}
728
729static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
730{
731 u32 *p = &vmx->segment_cache.seg[seg].limit;
732
733 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
734 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
735 return *p;
736}
737
738static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
739{
740 u32 *p = &vmx->segment_cache.seg[seg].ar;
741
742 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
743 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
744 return *p;
745}
746
abd3f2d6
AK		 747static void update_exception_bitmap(struct kvm_vcpu *vcpu)
748{
749 u32 eb;
750
fd7373cc
JK		 751 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
752 (1u << NM_VECTOR) | (1u << DB_VECTOR);
753 if ((vcpu->guest_debug &
754 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
755 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
756 eb |= 1u << BP_VECTOR;
7ffd92c5 757 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 758 eb = ~0;
089d034e 759 if (enable_ept)
1439442c 760 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 761 if (vcpu->fpu_active)
762 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 763 vmcs_write32(EXCEPTION_BITMAP, eb);
764}
765
61d2ef2c
AK		 766static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
767{
768 unsigned i;
769 struct msr_autoload *m = &vmx->msr_autoload;
770
110312c8
AK		 771 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
772 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
773 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
774 return;
775 }
776
61d2ef2c
AK		 777 for (i = 0; i < m->nr; ++i)
778 if (m->guest[i].index == msr)
779 break;
780
781 if (i == m->nr)
782 return;
783 --m->nr;
784 m->guest[i] = m->guest[m->nr];
785 m->host[i] = m->host[m->nr];
786 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
787 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
788}
789
790static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
791 u64 guest_val, u64 host_val)
792{
793 unsigned i;
794 struct msr_autoload *m = &vmx->msr_autoload;
795
110312c8
AK		 796 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
797 vmcs_write64(GUEST_IA32_EFER, guest_val);
798 vmcs_write64(HOST_IA32_EFER, host_val);
799 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
800 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
801 return;
802 }
803
61d2ef2c
AK		 804 for (i = 0; i < m->nr; ++i)
805 if (m->guest[i].index == msr)
806 break;
807
808 if (i == m->nr) {
809 ++m->nr;
810 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
811 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
812 }
813
814 m->guest[i].index = msr;
815 m->guest[i].value = guest_val;
816 m->host[i].index = msr;
817 m->host[i].value = host_val;
818}
819
33ed6329
AK		 820static void reload_tss(void)
821{
33ed6329
AK		 822 /*
823 * VT restores TR but not its size. Useless.
824 */
d359192f 825 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 826 struct desc_struct *descs;
33ed6329 827
d359192f 828 descs = (void *)gdt->address;
33ed6329
AK		 829 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
830 load_TR_desc();
33ed6329
AK		 831}
832
92c0d900 833static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 834{
3a34a881 835 u64 guest_efer;
51c6cf66
AK		 836 u64 ignore_bits;
837
f6801dff 838 guest_efer = vmx->vcpu.arch.efer;
3a34a881 839
51c6cf66
AK		 840 /*
841 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
842 * outside long mode
843 */
844 ignore_bits = EFER_NX | EFER_SCE;
845#ifdef CONFIG_X86_64
846 ignore_bits |= EFER_LMA | EFER_LME;
847 /* SCE is meaningful only in long mode on Intel */
848 if (guest_efer & EFER_LMA)
849 ignore_bits &= ~(u64)EFER_SCE;
850#endif
51c6cf66
AK		 851 guest_efer &= ~ignore_bits;
852 guest_efer |= host_efer & ignore_bits;
26bb0981 853 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 854 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 855
856 clear_atomic_switch_msr(vmx, MSR_EFER);
857 /* On ept, can't emulate nx, and must switch nx atomically */
858 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
859 guest_efer = vmx->vcpu.arch.efer;
860 if (!(guest_efer & EFER_LMA))
861 guest_efer &= ~EFER_LME;
862 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
863 return false;
864 }
865
26bb0981 866 return true;
51c6cf66
AK		 867}
868
2d49ec72
GN		 869static unsigned long segment_base(u16 selector)
870{
d359192f 871 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 872 struct desc_struct *d;
873 unsigned long table_base;
874 unsigned long v;
875
876 if (!(selector & ~3))
877 return 0;
878
d359192f 879 table_base = gdt->address;
2d49ec72
GN		 880
881 if (selector & 4) { /* from ldt */
882 u16 ldt_selector = kvm_read_ldt();
883
884 if (!(ldt_selector & ~3))
885 return 0;
886
887 table_base = segment_base(ldt_selector);
888 }
889 d = (struct desc_struct *)(table_base + (selector & ~7));
890 v = get_desc_base(d);
891#ifdef CONFIG_X86_64
892 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
893 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
894#endif
895 return v;
896}
897
898static inline unsigned long kvm_read_tr_base(void)
899{
900 u16 tr;
901 asm("str %0" : "=g"(tr));
902 return segment_base(tr);
903}
904
04d2cc77 905static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 906{
04d2cc77 907 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 908 int i;
04d2cc77 909
a2fa3e9f 910 if (vmx->host_state.loaded)
33ed6329
AK		 911 return;
912
a2fa3e9f 913 vmx->host_state.loaded = 1;
33ed6329
AK		 914 /*
915 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
916 * allow segment selectors with cpl > 0 or ti == 1.
917 */
d6e88aec 918 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 919 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 920 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 921 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 922 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 923 vmx->host_state.fs_reload_needed = 0;
924 } else {
33ed6329 925 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 926 vmx->host_state.fs_reload_needed = 1;
33ed6329 927 }
9581d442 928 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 929 if (!(vmx->host_state.gs_sel & 7))
930 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 931 else {
932 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 933 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 934 }
935
936#ifdef CONFIG_X86_64
937 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
938 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
939#else
a2fa3e9f
GH		 940 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
941 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 942#endif
707c0874
AK		 943
944#ifdef CONFIG_X86_64
c8770e7b
AK		 945 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
946 if (is_long_mode(&vmx->vcpu))
44ea2b17 947 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 948#endif
26bb0981
AK		 949 for (i = 0; i < vmx->save_nmsrs; ++i)
950 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 951 vmx->guest_msrs[i].data,
952 vmx->guest_msrs[i].mask);
33ed6329
AK		 953}
954
a9b21b62 955static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 956{
a2fa3e9f 957 if (!vmx->host_state.loaded)
33ed6329
AK		 958 return;
959
e1beb1d3 960 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 961 vmx->host_state.loaded = 0;
c8770e7b
AK		 962#ifdef CONFIG_X86_64
963 if (is_long_mode(&vmx->vcpu))
964 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
965#endif
152d3f2f 966 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 967 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 968#ifdef CONFIG_X86_64
9581d442 969 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 970#else
971 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 972#endif
33ed6329 973 }
0a77fe4c
AK		 974 if (vmx->host_state.fs_reload_needed)
975 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 976 reload_tss();
44ea2b17 977#ifdef CONFIG_X86_64
c8770e7b 978 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 979#endif
1c11e713
AK		 980 if (current_thread_info()->status & TS_USEDFPU)
981 clts();
3444d7da 982 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 983}
984
a9b21b62
AK		 985static void vmx_load_host_state(struct vcpu_vmx *vmx)
986{
987 preempt_disable();
988 __vmx_load_host_state(vmx);
989 preempt_enable();
990}
991
6aa8b732
AK		 992/*
993 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
994 * vcpu mutex is already taken.
995 */
15ad7146 996static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 997{
a2fa3e9f 998 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 999 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1000
4610c9cc
DX		 1001 if (!vmm_exclusive)
1002 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1003 else if (vmx->loaded_vmcs->cpu != cpu)
1004 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1005
d462b819
NHE		 1006 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1007 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1008 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1009 }
1010
d462b819 1011 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1012 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1013 unsigned long sysenter_esp;
1014
a8eeb04a 1015 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1016 local_irq_disable();
d462b819
NHE		 1017 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1018 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1019 local_irq_enable();
1020
6aa8b732
AK		 1021 /*
1022 * Linux uses per-cpu TSS and GDT, so set these when switching
1023 * processors.
1024 */
d6e88aec 1025 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1026 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1027
1028 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1029 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1030 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1031 }
6aa8b732
AK		 1032}
1033
1034static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1035{
a9b21b62 1036 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1037 if (!vmm_exclusive) {
d462b819
NHE		 1038 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1039 vcpu->cpu = -1;
4610c9cc
DX		 1040 kvm_cpu_vmxoff();
1041 }
6aa8b732
AK		 1042}
1043
5fd86fcf
AK		 1044static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1045{
81231c69
AK		 1046 ulong cr0;
1047
5fd86fcf
AK		 1048 if (vcpu->fpu_active)
1049 return;
1050 vcpu->fpu_active = 1;
81231c69
AK		 1051 cr0 = vmcs_readl(GUEST_CR0);
1052 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1053 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1054 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1055 update_exception_bitmap(vcpu);
edcafe3c
AK		 1056 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1057 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1058}
1059
edcafe3c
AK		 1060static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1061
5fd86fcf
AK		 1062static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1063{
edcafe3c 1064 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1065 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1066 update_exception_bitmap(vcpu);
edcafe3c
AK		 1067 vcpu->arch.cr0_guest_owned_bits = 0;
1068 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1069 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1070}
1071
6aa8b732
AK		 1072static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1073{
78ac8b47 1074 unsigned long rflags, save_rflags;
345dcaa8 1075
6de12732
AK		 1076 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1077 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1078 rflags = vmcs_readl(GUEST_RFLAGS);
1079 if (to_vmx(vcpu)->rmode.vm86_active) {
1080 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1081 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1082 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1083 }
1084 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1085 }
6de12732 1086 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1087}
1088
1089static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1090{
6de12732 1091 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1092 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1093 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1094 if (to_vmx(vcpu)->rmode.vm86_active) {
1095 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1096 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1097 }
6aa8b732
AK		 1098 vmcs_writel(GUEST_RFLAGS, rflags);
1099}
1100
2809f5d2
GC		 1101static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1102{
1103 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1104 int ret = 0;
1105
1106 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1107 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1108 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1109 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1110
1111 return ret & mask;
1112}
1113
1114static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1115{
1116 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1117 u32 interruptibility = interruptibility_old;
1118
1119 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1120
48005f64 1121 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1122 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1123 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1124 interruptibility |= GUEST_INTR_STATE_STI;
1125
1126 if ((interruptibility != interruptibility_old))
1127 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1128}
1129
6aa8b732
AK		 1130static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1131{
1132 unsigned long rip;
6aa8b732 1133
5fdbf976 1134 rip = kvm_rip_read(vcpu);
6aa8b732 1135 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1136 kvm_rip_write(vcpu, rip);
6aa8b732 1137
2809f5d2
GC		 1138 /* skipping an emulated instruction also counts */
1139 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1140}
1141
443381a8
AL		 1142static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1143{
1144 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1145 * explicitly skip the instruction because if the HLT state is set, then
1146 * the instruction is already executing and RIP has already been
1147 * advanced. */
1148 if (!yield_on_hlt &&
1149 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1150 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1151}
1152
298101da 1153static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1154 bool has_error_code, u32 error_code,
1155 bool reinject)
298101da 1156{
77ab6db0 1157 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1158 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1159
8ab2d2e2 1160 if (has_error_code) {
77ab6db0 1161 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1162 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1163 }
77ab6db0 1164
7ffd92c5 1165 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1166 int inc_eip = 0;
1167 if (kvm_exception_is_soft(nr))
1168 inc_eip = vcpu->arch.event_exit_inst_len;
1169 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1170 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1171 return;
1172 }
1173
66fd3f7f
GN		 1174 if (kvm_exception_is_soft(nr)) {
1175 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1176 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1177 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1178 } else
1179 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1180
1181 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1182 vmx_clear_hlt(vcpu);
298101da
AK		 1183}
1184
4e47c7a6
SY		 1185static bool vmx_rdtscp_supported(void)
1186{
1187 return cpu_has_vmx_rdtscp();
1188}
1189
a75beee6
ED		 1190/*
1191 * Swap MSR entry in host/guest MSR entry array.
1192 */
8b9cf98c 1193static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1194{
26bb0981 1195 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1196
1197 tmp = vmx->guest_msrs[to];
1198 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1199 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1200}
1201
e38aea3e
AK		 1202/*
1203 * Set up the vmcs to automatically save and restore system
1204 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1205 * mode, as fiddling with msrs is very expensive.
1206 */
8b9cf98c 1207static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1208{
26bb0981 1209 int save_nmsrs, index;
5897297b 1210 unsigned long *msr_bitmap;
e38aea3e 1211
33f9c505 1212 vmx_load_host_state(vmx);
a75beee6
ED		 1213 save_nmsrs = 0;
1214#ifdef CONFIG_X86_64
8b9cf98c 1215 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1216 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1217 if (index >= 0)
8b9cf98c
RR		 1218 move_msr_up(vmx, index, save_nmsrs++);
1219 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1220 if (index >= 0)
8b9cf98c
RR		 1221 move_msr_up(vmx, index, save_nmsrs++);
1222 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1223 if (index >= 0)
8b9cf98c 1224 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1225 index = __find_msr_index(vmx, MSR_TSC_AUX);
1226 if (index >= 0 && vmx->rdtscp_enabled)
1227 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1228 /*
8c06585d 1229 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1230 * if efer.sce is enabled.
1231 */
8c06585d 1232 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1233 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1234 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1235 }
1236#endif
92c0d900
AK		 1237 index = __find_msr_index(vmx, MSR_EFER);
1238 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1239 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1240
26bb0981 1241 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1242
1243 if (cpu_has_vmx_msr_bitmap()) {
1244 if (is_long_mode(&vmx->vcpu))
1245 msr_bitmap = vmx_msr_bitmap_longmode;
1246 else
1247 msr_bitmap = vmx_msr_bitmap_legacy;
1248
1249 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1250 }
e38aea3e
AK		 1251}
1252
6aa8b732
AK		 1253/*
1254 * reads and returns guest's timestamp counter "register"
1255 * guest_tsc = host_tsc + tsc_offset -- 21.3
1256 */
1257static u64 guest_read_tsc(void)
1258{
1259 u64 host_tsc, tsc_offset;
1260
1261 rdtscll(host_tsc);
1262 tsc_offset = vmcs_read64(TSC_OFFSET);
1263 return host_tsc + tsc_offset;
1264}
1265
4051b188
JR		 1266/*
1267 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1268 * ioctl. In this case the call-back should update internal vmx state to make
1269 * the changes effective.
1270 */
1271static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1272{
1273 /* Nothing to do here */
1274}
1275
6aa8b732 1276/*
99e3e30a 1277 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1278 */
99e3e30a 1279static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1280{
f4e1b3c8 1281 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1282}
1283
e48672fa
ZA		 1284static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1285{
1286 u64 offset = vmcs_read64(TSC_OFFSET);
1287 vmcs_write64(TSC_OFFSET, offset + adjustment);
1288}
1289
857e4099
JR		 1290static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1291{
1292 return target_tsc - native_read_tsc();
1293}
1294
6aa8b732
AK		 1295/*
1296 * Reads an msr value (of 'msr_index') into 'pdata'.
1297 * Returns 0 on success, non-0 otherwise.
1298 * Assumes vcpu_load() was already called.
1299 */
1300static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1301{
1302 u64 data;
26bb0981 1303 struct shared_msr_entry *msr;
6aa8b732
AK		 1304
1305 if (!pdata) {
1306 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1307 return -EINVAL;
1308 }
1309
1310 switch (msr_index) {
05b3e0c2 1311#ifdef CONFIG_X86_64
6aa8b732
AK		 1312 case MSR_FS_BASE:
1313 data = vmcs_readl(GUEST_FS_BASE);
1314 break;
1315 case MSR_GS_BASE:
1316 data = vmcs_readl(GUEST_GS_BASE);
1317 break;
44ea2b17
AK		 1318 case MSR_KERNEL_GS_BASE:
1319 vmx_load_host_state(to_vmx(vcpu));
1320 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1321 break;
26bb0981 1322#endif
6aa8b732 1323 case MSR_EFER:
3bab1f5d 1324 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1325 case MSR_IA32_TSC:
6aa8b732
AK		 1326 data = guest_read_tsc();
1327 break;
1328 case MSR_IA32_SYSENTER_CS:
1329 data = vmcs_read32(GUEST_SYSENTER_CS);
1330 break;
1331 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1332 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1333 break;
1334 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1335 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1336 break;
4e47c7a6
SY		 1337 case MSR_TSC_AUX:
1338 if (!to_vmx(vcpu)->rdtscp_enabled)
1339 return 1;
1340 /* Otherwise falls through */
6aa8b732 1341 default:
26bb0981 1342 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1343 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1344 if (msr) {
542423b0 1345 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1346 data = msr->data;
1347 break;
6aa8b732 1348 }
3bab1f5d 1349 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1350 }
1351
1352 *pdata = data;
1353 return 0;
1354}
1355
1356/*
1357 * Writes msr value into into the appropriate "register".
1358 * Returns 0 on success, non-0 otherwise.
1359 * Assumes vcpu_load() was already called.
1360 */
1361static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1362{
a2fa3e9f 1363 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1364 struct shared_msr_entry *msr;
2cc51560
ED		 1365 int ret = 0;
1366
6aa8b732 1367 switch (msr_index) {
3bab1f5d 1368 case MSR_EFER:
a9b21b62 1369 vmx_load_host_state(vmx);
2cc51560 1370 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1371 break;
16175a79 1372#ifdef CONFIG_X86_64
6aa8b732 1373 case MSR_FS_BASE:
2fb92db1 1374 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1375 vmcs_writel(GUEST_FS_BASE, data);
1376 break;
1377 case MSR_GS_BASE:
2fb92db1 1378 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1379 vmcs_writel(GUEST_GS_BASE, data);
1380 break;
44ea2b17
AK		 1381 case MSR_KERNEL_GS_BASE:
1382 vmx_load_host_state(vmx);
1383 vmx->msr_guest_kernel_gs_base = data;
1384 break;
6aa8b732
AK		 1385#endif
1386 case MSR_IA32_SYSENTER_CS:
1387 vmcs_write32(GUEST_SYSENTER_CS, data);
1388 break;
1389 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1390 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1391 break;
1392 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1393 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1394 break;
af24a4e4 1395 case MSR_IA32_TSC:
99e3e30a 1396 kvm_write_tsc(vcpu, data);
6aa8b732 1397 break;
468d472f
SY		 1398 case MSR_IA32_CR_PAT:
1399 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1400 vmcs_write64(GUEST_IA32_PAT, data);
1401 vcpu->arch.pat = data;
1402 break;
1403 }
4e47c7a6
SY		 1404 ret = kvm_set_msr_common(vcpu, msr_index, data);
1405 break;
1406 case MSR_TSC_AUX:
1407 if (!vmx->rdtscp_enabled)
1408 return 1;
1409 /* Check reserved bit, higher 32 bits should be zero */
1410 if ((data >> 32) != 0)
1411 return 1;
1412 /* Otherwise falls through */
6aa8b732 1413 default:
8b9cf98c 1414 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1415 if (msr) {
542423b0 1416 vmx_load_host_state(vmx);
3bab1f5d
AK		 1417 msr->data = data;
1418 break;
6aa8b732 1419 }
2cc51560 1420 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1421 }
1422
2cc51560 1423 return ret;
6aa8b732
AK		 1424}
1425
5fdbf976 1426static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1427{
5fdbf976
MT		 1428 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1429 switch (reg) {
1430 case VCPU_REGS_RSP:
1431 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1432 break;
1433 case VCPU_REGS_RIP:
1434 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1435 break;
6de4f3ad
AK		 1436 case VCPU_EXREG_PDPTR:
1437 if (enable_ept)
1438 ept_save_pdptrs(vcpu);
1439 break;
5fdbf976
MT		 1440 default:
1441 break;
1442 }
6aa8b732
AK		 1443}
1444
355be0b9 1445static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1446{
ae675ef0
JK		 1447 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1448 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1449 else
1450 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1451
abd3f2d6 1452 update_exception_bitmap(vcpu);
6aa8b732
AK		 1453}
1454
1455static __init int cpu_has_kvm_support(void)
1456{
6210e37b 1457 return cpu_has_vmx();
6aa8b732
AK		 1458}
1459
1460static __init int vmx_disabled_by_bios(void)
1461{
1462 u64 msr;
1463
1464 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1465 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1466 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1467 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1468 && tboot_enabled())
1469 return 1;
23f3e991 1470 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1471 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1472 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1473 && !tboot_enabled()) {
1474 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1475 "activate TXT before enabling KVM\n");
cafd6659 1476 return 1;
f9335afe 1477 }
23f3e991
JC		 1478 /* launched w/o TXT and VMX disabled */
1479 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1480 && !tboot_enabled())
1481 return 1;
cafd6659
SW		 1482 }
1483
1484 return 0;
6aa8b732
AK		 1485}
1486
7725b894
DX		 1487static void kvm_cpu_vmxon(u64 addr)
1488{
1489 asm volatile (ASM_VMX_VMXON_RAX
1490 : : "a"(&addr), "m"(addr)
1491 : "memory", "cc");
1492}
1493
10474ae8 1494static int hardware_enable(void *garbage)
6aa8b732
AK		 1495{
1496 int cpu = raw_smp_processor_id();
1497 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1498 u64 old, test_bits;
6aa8b732 1499
10474ae8
AG		 1500 if (read_cr4() & X86_CR4_VMXE)
1501 return -EBUSY;
1502
d462b819 1503 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 1504 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1505
1506 test_bits = FEATURE_CONTROL_LOCKED;
1507 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1508 if (tboot_enabled())
1509 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1510
1511 if ((old & test_bits) != test_bits) {
6aa8b732 1512 /* enable and lock */
cafd6659
SW		 1513 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1514 }
66aee91a 1515 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1516
4610c9cc
DX		 1517 if (vmm_exclusive) {
1518 kvm_cpu_vmxon(phys_addr);
1519 ept_sync_global();
1520 }
10474ae8 1521
3444d7da
AK		 1522 store_gdt(&__get_cpu_var(host_gdt));
1523
10474ae8 1524 return 0;
6aa8b732
AK		 1525}
1526
d462b819 1527static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 1528{
1529 int cpu = raw_smp_processor_id();
d462b819 1530 struct loaded_vmcs *v, *n;
543e4243 1531
d462b819
NHE		 1532 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1533 loaded_vmcss_on_cpu_link)
1534 __loaded_vmcs_clear(v);
543e4243
AK		 1535}
1536
710ff4a8
EH		 1537
1538/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1539 * tricks.
1540 */
1541static void kvm_cpu_vmxoff(void)
6aa8b732 1542{
4ecac3fd 1543 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1544}
1545
710ff4a8
EH		 1546static void hardware_disable(void *garbage)
1547{
4610c9cc 1548 if (vmm_exclusive) {
d462b819 1549 vmclear_local_loaded_vmcss();
4610c9cc
DX		 1550 kvm_cpu_vmxoff();
1551 }
7725b894 1552 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1553}
1554
1c3d14fe 1555static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1556 u32 msr, u32 *result)
1c3d14fe
YS		 1557{
1558 u32 vmx_msr_low, vmx_msr_high;
1559 u32 ctl = ctl_min | ctl_opt;
1560
1561 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1562
1563 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1564 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1565
1566 /* Ensure minimum (required) set of control bits are supported. */
1567 if (ctl_min & ~ctl)
002c7f7c 1568 return -EIO;
1c3d14fe
YS		 1569
1570 *result = ctl;
1571 return 0;
1572}
1573
110312c8
AK		 1574static __init bool allow_1_setting(u32 msr, u32 ctl)
1575{
1576 u32 vmx_msr_low, vmx_msr_high;
1577
1578 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1579 return vmx_msr_high & ctl;
1580}
1581
002c7f7c 1582static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1583{
1584 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1585 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1586 u32 _pin_based_exec_control = 0;
1587 u32 _cpu_based_exec_control = 0;
f78e0e2e 1588 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1589 u32 _vmexit_control = 0;
1590 u32 _vmentry_control = 0;
1591
1592 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1593 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1594 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1595 &_pin_based_exec_control) < 0)
002c7f7c 1596 return -EIO;
1c3d14fe 1597
443381a8 1598 min =
1c3d14fe
YS		 1599#ifdef CONFIG_X86_64
1600 CPU_BASED_CR8_LOAD_EXITING |
1601 CPU_BASED_CR8_STORE_EXITING |
1602#endif
d56f546d
SY		 1603 CPU_BASED_CR3_LOAD_EXITING |
1604 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1605 CPU_BASED_USE_IO_BITMAPS |
1606 CPU_BASED_MOV_DR_EXITING |
a7052897 1607 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1608 CPU_BASED_MWAIT_EXITING |
1609 CPU_BASED_MONITOR_EXITING |
a7052897 1610 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1611
1612 if (yield_on_hlt)
1613 min |= CPU_BASED_HLT_EXITING;
1614
f78e0e2e 1615 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1616 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1617 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1618 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1619 &_cpu_based_exec_control) < 0)
002c7f7c 1620 return -EIO;
6e5d865c
YS		 1621#ifdef CONFIG_X86_64
1622 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1623 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1624 ~CPU_BASED_CR8_STORE_EXITING;
1625#endif
f78e0e2e 1626 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1627 min2 = 0;
1628 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1629 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1630 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1631 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1632 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1633 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1634 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1635 if (adjust_vmx_controls(min2, opt2,
1636 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1637 &_cpu_based_2nd_exec_control) < 0)
1638 return -EIO;
1639 }
1640#ifndef CONFIG_X86_64
1641 if (!(_cpu_based_2nd_exec_control &
1642 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1643 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1644#endif
d56f546d 1645 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1646 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1647 enabled */
5fff7d27
GN		 1648 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1649 CPU_BASED_CR3_STORE_EXITING |
1650 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1651 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1652 vmx_capability.ept, vmx_capability.vpid);
1653 }
1c3d14fe
YS		 1654
1655 min = 0;
1656#ifdef CONFIG_X86_64
1657 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1658#endif
468d472f 1659 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1660 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1661 &_vmexit_control) < 0)
002c7f7c 1662 return -EIO;
1c3d14fe 1663
468d472f
SY		 1664 min = 0;
1665 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1666 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1667 &_vmentry_control) < 0)
002c7f7c 1668 return -EIO;
6aa8b732 1669
c68876fd 1670 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1671
1672 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1673 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1674 return -EIO;
1c3d14fe
YS		 1675
1676#ifdef CONFIG_X86_64
1677 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1678 if (vmx_msr_high & (1u<<16))
002c7f7c 1679 return -EIO;
1c3d14fe
YS		 1680#endif
1681
1682 /* Require Write-Back (WB) memory type for VMCS accesses. */
1683 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1684 return -EIO;
1c3d14fe 1685
002c7f7c
YS		 1686 vmcs_conf->size = vmx_msr_high & 0x1fff;
1687 vmcs_conf->order = get_order(vmcs_config.size);
1688 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1689
002c7f7c
YS		 1690 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1691 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1692 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1693 vmcs_conf->vmexit_ctrl = _vmexit_control;
1694 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1695
110312c8
AK		 1696 cpu_has_load_ia32_efer =
1697 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1698 VM_ENTRY_LOAD_IA32_EFER)
1699 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1700 VM_EXIT_LOAD_IA32_EFER);
1701
1c3d14fe 1702 return 0;
c68876fd 1703}
6aa8b732
AK		 1704
1705static struct vmcs *alloc_vmcs_cpu(int cpu)
1706{
1707 int node = cpu_to_node(cpu);
1708 struct page *pages;
1709 struct vmcs *vmcs;
1710
6484eb3e 1711 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1712 if (!pages)
1713 return NULL;
1714 vmcs = page_address(pages);
1c3d14fe
YS		 1715 memset(vmcs, 0, vmcs_config.size);
1716 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1717 return vmcs;
1718}
1719
1720static struct vmcs *alloc_vmcs(void)
1721{
d3b2c338 1722 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1723}
1724
1725static void free_vmcs(struct vmcs *vmcs)
1726{
1c3d14fe 1727 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1728}
1729
d462b819
NHE		 1730/*
1731 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
1732 */
1733static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
1734{
1735 if (!loaded_vmcs->vmcs)
1736 return;
1737 loaded_vmcs_clear(loaded_vmcs);
1738 free_vmcs(loaded_vmcs->vmcs);
1739 loaded_vmcs->vmcs = NULL;
1740}
1741
39959588 1742static void free_kvm_area(void)
6aa8b732
AK		 1743{
1744 int cpu;
1745
3230bb47 1746 for_each_possible_cpu(cpu) {
6aa8b732 1747 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1748 per_cpu(vmxarea, cpu) = NULL;
1749 }
6aa8b732
AK		 1750}
1751
6aa8b732
AK		 1752static __init int alloc_kvm_area(void)
1753{
1754 int cpu;
1755
3230bb47 1756 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1757 struct vmcs *vmcs;
1758
1759 vmcs = alloc_vmcs_cpu(cpu);
1760 if (!vmcs) {
1761 free_kvm_area();
1762 return -ENOMEM;
1763 }
1764
1765 per_cpu(vmxarea, cpu) = vmcs;
1766 }
1767 return 0;
1768}
1769
1770static __init int hardware_setup(void)
1771{
002c7f7c
YS		 1772 if (setup_vmcs_config(&vmcs_config) < 0)
1773 return -EIO;
50a37eb4
JR		 1774
1775 if (boot_cpu_has(X86_FEATURE_NX))
1776 kvm_enable_efer_bits(EFER_NX);
1777
93ba03c2
SY		 1778 if (!cpu_has_vmx_vpid())
1779 enable_vpid = 0;
1780
4bc9b982
SY		 1781 if (!cpu_has_vmx_ept() ||
1782 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1783 enable_ept = 0;
3a624e29
NK		 1784 enable_unrestricted_guest = 0;
1785 }
1786
1787 if (!cpu_has_vmx_unrestricted_guest())
1788 enable_unrestricted_guest = 0;
93ba03c2
SY		 1789
1790 if (!cpu_has_vmx_flexpriority())
1791 flexpriority_enabled = 0;
1792
95ba8273
GN		 1793 if (!cpu_has_vmx_tpr_shadow())
1794 kvm_x86_ops->update_cr8_intercept = NULL;
1795
54dee993
MT		 1796 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1797 kvm_disable_largepages();
1798
4b8d54f9
ZE		 1799 if (!cpu_has_vmx_ple())
1800 ple_gap = 0;
1801
6aa8b732
AK		 1802 return alloc_kvm_area();
1803}
1804
1805static __exit void hardware_unsetup(void)
1806{
1807 free_kvm_area();
1808}
1809
6aa8b732
AK		 1810static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1811{
1812 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1813
6af11b9e 1814 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1815 vmcs_write16(sf->selector, save->selector);
1816 vmcs_writel(sf->base, save->base);
1817 vmcs_write32(sf->limit, save->limit);
1818 vmcs_write32(sf->ar_bytes, save->ar);
1819 } else {
1820 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1821 << AR_DPL_SHIFT;
1822 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1823 }
1824}
1825
1826static void enter_pmode(struct kvm_vcpu *vcpu)
1827{
1828 unsigned long flags;
a89a8fb9 1829 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1830
a89a8fb9 1831 vmx->emulation_required = 1;
7ffd92c5 1832 vmx->rmode.vm86_active = 0;
6aa8b732 1833
2fb92db1
AK		 1834 vmx_segment_cache_clear(vmx);
1835
d0ba64f9 1836 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1837 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1838 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1839 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1840
1841 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1842 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1843 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1844 vmcs_writel(GUEST_RFLAGS, flags);
1845
66aee91a
RR		 1846 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1847 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1848
1849 update_exception_bitmap(vcpu);
1850
a89a8fb9
MG		 1851 if (emulate_invalid_guest_state)
1852 return;
1853
7ffd92c5
AK		 1854 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1855 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1856 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1857 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 1858
2fb92db1
AK		 1859 vmx_segment_cache_clear(vmx);
1860
6aa8b732
AK		 1861 vmcs_write16(GUEST_SS_SELECTOR, 0);
1862 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1863
1864 vmcs_write16(GUEST_CS_SELECTOR,
1865 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1866 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1867}
1868
d77c26fc 1869static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1870{
bfc6d222 1871 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1872 struct kvm_memslots *slots;
1873 gfn_t base_gfn;
1874
90d83dc3 1875 slots = kvm_memslots(kvm);
f495c6e5 1876 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1877 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1878 return base_gfn << PAGE_SHIFT;
1879 }
bfc6d222 1880 return kvm->arch.tss_addr;
6aa8b732
AK		 1881}
1882
1883static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1884{
1885 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1886
1887 save->selector = vmcs_read16(sf->selector);
1888 save->base = vmcs_readl(sf->base);
1889 save->limit = vmcs_read32(sf->limit);
1890 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1891 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1892 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1893 vmcs_write32(sf->limit, 0xffff);
1894 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1895 if (save->base & 0xf)
1896 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1897 " aligned when entering protected mode (seg=%d)",
1898 seg);
6aa8b732
AK		 1899}
1900
1901static void enter_rmode(struct kvm_vcpu *vcpu)
1902{
1903 unsigned long flags;
a89a8fb9 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1905
3a624e29
NK		 1906 if (enable_unrestricted_guest)
1907 return;
1908
a89a8fb9 1909 vmx->emulation_required = 1;
7ffd92c5 1910 vmx->rmode.vm86_active = 1;
6aa8b732 1911
776e58ea
GN		 1912 /*
1913 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1914 * vcpu. Call it here with phys address pointing 16M below 4G.
1915 */
1916 if (!vcpu->kvm->arch.tss_addr) {
1917 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1918 "called before entering vcpu\n");
1919 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1920 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1921 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1922 }
1923
2fb92db1
AK		 1924 vmx_segment_cache_clear(vmx);
1925
d0ba64f9 1926 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1927 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1928 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1929
7ffd92c5 1930 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1931 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1932
7ffd92c5 1933 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1934 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1935
1936 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1937 vmx->rmode.save_rflags = flags;
6aa8b732 1938
053de044 1939 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1940
1941 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1942 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1943 update_exception_bitmap(vcpu);
1944
a89a8fb9
MG		 1945 if (emulate_invalid_guest_state)
1946 goto continue_rmode;
1947
6aa8b732
AK		 1948 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1949 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1950 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1951
1952 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1953 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1954 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1955 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1956 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1957
7ffd92c5
AK		 1958 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1959 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1960 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1961 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1962
a89a8fb9 1963continue_rmode:
8668a3c4 1964 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 1965}
1966
401d10de
AS		 1967static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1968{
1969 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1970 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1971
1972 if (!msr)
1973 return;
401d10de 1974
44ea2b17
AK		 1975 /*
1976 * Force kernel_gs_base reloading before EFER changes, as control
1977 * of this msr depends on is_long_mode().
1978 */
1979 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1980 vcpu->arch.efer = efer;
401d10de
AS		 1981 if (efer & EFER_LMA) {
1982 vmcs_write32(VM_ENTRY_CONTROLS,
1983 vmcs_read32(VM_ENTRY_CONTROLS) |
1984 VM_ENTRY_IA32E_MODE);
1985 msr->data = efer;
1986 } else {
1987 vmcs_write32(VM_ENTRY_CONTROLS,
1988 vmcs_read32(VM_ENTRY_CONTROLS) &
1989 ~VM_ENTRY_IA32E_MODE);
1990
1991 msr->data = efer & ~EFER_LME;
1992 }
1993 setup_msrs(vmx);
1994}
1995
05b3e0c2 1996#ifdef CONFIG_X86_64
6aa8b732
AK		 1997
1998static void enter_lmode(struct kvm_vcpu *vcpu)
1999{
2000 u32 guest_tr_ar;
2001
2fb92db1
AK		 2002 vmx_segment_cache_clear(to_vmx(vcpu));
2003
6aa8b732
AK		 2004 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2005 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2006 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2007 __func__);
6aa8b732
AK		 2008 vmcs_write32(GUEST_TR_AR_BYTES,
2009 (guest_tr_ar & ~AR_TYPE_MASK)
2010 | AR_TYPE_BUSY_64_TSS);
2011 }
da38f438 2012 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2013}
2014
2015static void exit_lmode(struct kvm_vcpu *vcpu)
2016{
6aa8b732
AK		 2017 vmcs_write32(VM_ENTRY_CONTROLS,
2018 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2019 & ~VM_ENTRY_IA32E_MODE);
da38f438 2020 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2021}
2022
2023#endif
2024
2384d2b3
SY		 2025static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2026{
b9d762fa 2027 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2028 if (enable_ept) {
2029 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2030 return;
4e1096d2 2031 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2032 }
2384d2b3
SY		 2033}
2034
e8467fda
AK		 2035static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2036{
2037 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2038
2039 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2040 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2041}
2042
aff48baa
AK		 2043static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2044{
2045 if (enable_ept && is_paging(vcpu))
2046 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2047 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2048}
2049
25c4c276 2050static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2051{
fc78f519
AK		 2052 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2053
2054 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2055 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2056}
2057
1439442c
SY		 2058static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2059{
6de4f3ad
AK		 2060 if (!test_bit(VCPU_EXREG_PDPTR,
2061 (unsigned long *)&vcpu->arch.regs_dirty))
2062 return;
2063
1439442c 2064 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2065 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2066 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2067 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2068 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2069 }
2070}
2071
8f5d549f
AK		 2072static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2073{
2074 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2075 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2076 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2077 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2078 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2079 }
6de4f3ad
AK		 2080
2081 __set_bit(VCPU_EXREG_PDPTR,
2082 (unsigned long *)&vcpu->arch.regs_avail);
2083 __set_bit(VCPU_EXREG_PDPTR,
2084 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2085}
2086
1439442c
SY		 2087static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2088
2089static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2090 unsigned long cr0,
2091 struct kvm_vcpu *vcpu)
2092{
5233dd51
MT		 2093 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2094 vmx_decache_cr3(vcpu);
1439442c
SY		 2095 if (!(cr0 & X86_CR0_PG)) {
2096 /* From paging/starting to nonpaging */
2097 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2098 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2099 (CPU_BASED_CR3_LOAD_EXITING |
2100 CPU_BASED_CR3_STORE_EXITING));
2101 vcpu->arch.cr0 = cr0;
fc78f519 2102 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2103 } else if (!is_paging(vcpu)) {
2104 /* From nonpaging to paging */
2105 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2106 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2107 ~(CPU_BASED_CR3_LOAD_EXITING |
2108 CPU_BASED_CR3_STORE_EXITING));
2109 vcpu->arch.cr0 = cr0;
fc78f519 2110 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2111 }
95eb84a7
SY		 2112
2113 if (!(cr0 & X86_CR0_WP))
2114 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2115}
2116
6aa8b732
AK		 2117static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2118{
7ffd92c5 2119 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2120 unsigned long hw_cr0;
2121
2122 if (enable_unrestricted_guest)
2123 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2124 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2125 else
2126 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2127
7ffd92c5 2128 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2129 enter_pmode(vcpu);
2130
7ffd92c5 2131 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2132 enter_rmode(vcpu);
2133
05b3e0c2 2134#ifdef CONFIG_X86_64
f6801dff 2135 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2136 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2137 enter_lmode(vcpu);
707d92fa 2138 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2139 exit_lmode(vcpu);
2140 }
2141#endif
2142
089d034e 2143 if (enable_ept)
1439442c
SY		 2144 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2145
02daab21 2146 if (!vcpu->fpu_active)
81231c69 2147 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2148
6aa8b732 2149 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2150 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2151 vcpu->arch.cr0 = cr0;
69c73028 2152 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2153}
2154
1439442c
SY		 2155static u64 construct_eptp(unsigned long root_hpa)
2156{
2157 u64 eptp;
2158
2159 /* TODO write the value reading from MSR */
2160 eptp = VMX_EPT_DEFAULT_MT |
2161 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2162 eptp |= (root_hpa & PAGE_MASK);
2163
2164 return eptp;
2165}
2166
6aa8b732
AK		 2167static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2168{
1439442c
SY		 2169 unsigned long guest_cr3;
2170 u64 eptp;
2171
2172 guest_cr3 = cr3;
089d034e 2173 if (enable_ept) {
1439442c
SY		 2174 eptp = construct_eptp(cr3);
2175 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2176 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2177 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2178 ept_load_pdptrs(vcpu);
1439442c
SY		 2179 }
2180
2384d2b3 2181 vmx_flush_tlb(vcpu);
1439442c 2182 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2183}
2184
2185static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2186{
7ffd92c5 2187 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2188 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2189
ad312c7c 2190 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2191 if (enable_ept) {
2192 if (!is_paging(vcpu)) {
2193 hw_cr4 &= ~X86_CR4_PAE;
2194 hw_cr4 |= X86_CR4_PSE;
2195 } else if (!(cr4 & X86_CR4_PAE)) {
2196 hw_cr4 &= ~X86_CR4_PAE;
2197 }
2198 }
1439442c
SY		 2199
2200 vmcs_writel(CR4_READ_SHADOW, cr4);
2201 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2202}
2203
6aa8b732
AK		 2204static void vmx_get_segment(struct kvm_vcpu *vcpu,
2205 struct kvm_segment *var, int seg)
2206{
a9179499 2207 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2208 struct kvm_save_segment *save;
6aa8b732
AK		 2209 u32 ar;
2210
a9179499
AK		 2211 if (vmx->rmode.vm86_active
2212 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2213 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2214 || seg == VCPU_SREG_GS)
2215 && !emulate_invalid_guest_state) {
2216 switch (seg) {
2217 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2218 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2219 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2220 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2221 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2222 default: BUG();
2223 }
2224 var->selector = save->selector;
2225 var->base = save->base;
2226 var->limit = save->limit;
2227 ar = save->ar;
2228 if (seg == VCPU_SREG_TR
2fb92db1 2229 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2230 goto use_saved_rmode_seg;
2231 }
2fb92db1
AK		 2232 var->base = vmx_read_guest_seg_base(vmx, seg);
2233 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2234 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2235 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2236use_saved_rmode_seg:
9fd4a3b7 2237 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2238 ar = 0;
2239 var->type = ar & 15;
2240 var->s = (ar >> 4) & 1;
2241 var->dpl = (ar >> 5) & 3;
2242 var->present = (ar >> 7) & 1;
2243 var->avl = (ar >> 12) & 1;
2244 var->l = (ar >> 13) & 1;
2245 var->db = (ar >> 14) & 1;
2246 var->g = (ar >> 15) & 1;
2247 var->unusable = (ar >> 16) & 1;
2248}
2249
a9179499
AK		 2250static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2251{
a9179499
AK		 2252 struct kvm_segment s;
2253
2254 if (to_vmx(vcpu)->rmode.vm86_active) {
2255 vmx_get_segment(vcpu, &s, seg);
2256 return s.base;
2257 }
2fb92db1 2258 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2259}
2260
69c73028 2261static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2262{
3eeb3288 2263 if (!is_protmode(vcpu))
2e4d2653
IE		 2264 return 0;
2265
f4c63e5d
AK		 2266 if (!is_long_mode(vcpu)
2267 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2268 return 3;
2269
2fb92db1 2270 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 2271}
2272
69c73028
AK		 2273static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2274{
2275 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2276 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2277 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2278 }
2279 return to_vmx(vcpu)->cpl;
2280}
2281
2282
653e3108 2283static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2284{
6aa8b732
AK		 2285 u32 ar;
2286
653e3108 2287 if (var->unusable)
6aa8b732
AK		 2288 ar = 1 << 16;
2289 else {
2290 ar = var->type & 15;
2291 ar |= (var->s & 1) << 4;
2292 ar |= (var->dpl & 3) << 5;
2293 ar |= (var->present & 1) << 7;
2294 ar |= (var->avl & 1) << 12;
2295 ar |= (var->l & 1) << 13;
2296 ar |= (var->db & 1) << 14;
2297 ar |= (var->g & 1) << 15;
2298 }
f7fbf1fd
UL		 2299 if (ar == 0) /* a 0 value means unusable */
2300 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2301
2302 return ar;
2303}
2304
2305static void vmx_set_segment(struct kvm_vcpu *vcpu,
2306 struct kvm_segment *var, int seg)
2307{
7ffd92c5 2308 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2309 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2310 u32 ar;
2311
2fb92db1
AK		 2312 vmx_segment_cache_clear(vmx);
2313
7ffd92c5 2314 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2315 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2316 vmx->rmode.tr.selector = var->selector;
2317 vmx->rmode.tr.base = var->base;
2318 vmx->rmode.tr.limit = var->limit;
2319 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2320 return;
2321 }
2322 vmcs_writel(sf->base, var->base);
2323 vmcs_write32(sf->limit, var->limit);
2324 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2325 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2326 /*
2327 * Hack real-mode segments into vm86 compatibility.
2328 */
2329 if (var->base == 0xffff0000 && var->selector == 0xf000)
2330 vmcs_writel(sf->base, 0xf0000);
2331 ar = 0xf3;
2332 } else
2333 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2334
2335 /*
2336 * Fix the "Accessed" bit in AR field of segment registers for older
2337 * qemu binaries.
2338 * IA32 arch specifies that at the time of processor reset the
2339 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2340 * is setting it to 0 in the usedland code. This causes invalid guest
2341 * state vmexit when "unrestricted guest" mode is turned on.
2342 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2343 * tree. Newer qemu binaries with that qemu fix would not need this
2344 * kvm hack.
2345 */
2346 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2347 ar |= 0x1; /* Accessed */
2348
6aa8b732 2349 vmcs_write32(sf->ar_bytes, ar);
69c73028 2350 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2351}
2352
6aa8b732
AK		 2353static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2354{
2fb92db1 2355 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 2356
2357 *db = (ar >> 14) & 1;
2358 *l = (ar >> 13) & 1;
2359}
2360
89a27f4d 2361static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2362{
89a27f4d
GN		 2363 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2364 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2365}
2366
89a27f4d 2367static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2368{
89a27f4d
GN		 2369 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2370 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2371}
2372
89a27f4d 2373static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2374{
89a27f4d
GN		 2375 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2376 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2377}
2378
89a27f4d 2379static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2380{
89a27f4d
GN		 2381 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2382 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2383}
2384
648dfaa7
MG		 2385static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2386{
2387 struct kvm_segment var;
2388 u32 ar;
2389
2390 vmx_get_segment(vcpu, &var, seg);
2391 ar = vmx_segment_access_rights(&var);
2392
2393 if (var.base != (var.selector << 4))
2394 return false;
2395 if (var.limit != 0xffff)
2396 return false;
2397 if (ar != 0xf3)
2398 return false;
2399
2400 return true;
2401}
2402
2403static bool code_segment_valid(struct kvm_vcpu *vcpu)
2404{
2405 struct kvm_segment cs;
2406 unsigned int cs_rpl;
2407
2408 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2409 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2410
1872a3f4
AK		 2411 if (cs.unusable)
2412 return false;
648dfaa7
MG		 2413 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2414 return false;
2415 if (!cs.s)
2416 return false;
1872a3f4 2417 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2418 if (cs.dpl > cs_rpl)
2419 return false;
1872a3f4 2420 } else {
648dfaa7
MG		 2421 if (cs.dpl != cs_rpl)
2422 return false;
2423 }
2424 if (!cs.present)
2425 return false;
2426
2427 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2428 return true;
2429}
2430
2431static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2432{
2433 struct kvm_segment ss;
2434 unsigned int ss_rpl;
2435
2436 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2437 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2438
1872a3f4
AK		 2439 if (ss.unusable)
2440 return true;
2441 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2442 return false;
2443 if (!ss.s)
2444 return false;
2445 if (ss.dpl != ss_rpl) /* DPL != RPL */
2446 return false;
2447 if (!ss.present)
2448 return false;
2449
2450 return true;
2451}
2452
2453static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2454{
2455 struct kvm_segment var;
2456 unsigned int rpl;
2457
2458 vmx_get_segment(vcpu, &var, seg);
2459 rpl = var.selector & SELECTOR_RPL_MASK;
2460
1872a3f4
AK		 2461 if (var.unusable)
2462 return true;
648dfaa7
MG		 2463 if (!var.s)
2464 return false;
2465 if (!var.present)
2466 return false;
2467 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2468 if (var.dpl < rpl) /* DPL < RPL */
2469 return false;
2470 }
2471
2472 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2473 * rights flags
2474 */
2475 return true;
2476}
2477
2478static bool tr_valid(struct kvm_vcpu *vcpu)
2479{
2480 struct kvm_segment tr;
2481
2482 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2483
1872a3f4
AK		 2484 if (tr.unusable)
2485 return false;
648dfaa7
MG		 2486 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2487 return false;
1872a3f4 2488 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2489 return false;
2490 if (!tr.present)
2491 return false;
2492
2493 return true;
2494}
2495
2496static bool ldtr_valid(struct kvm_vcpu *vcpu)
2497{
2498 struct kvm_segment ldtr;
2499
2500 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2501
1872a3f4
AK		 2502 if (ldtr.unusable)
2503 return true;
648dfaa7
MG		 2504 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2505 return false;
2506 if (ldtr.type != 2)
2507 return false;
2508 if (!ldtr.present)
2509 return false;
2510
2511 return true;
2512}
2513
2514static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2515{
2516 struct kvm_segment cs, ss;
2517
2518 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2519 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2520
2521 return ((cs.selector & SELECTOR_RPL_MASK) ==
2522 (ss.selector & SELECTOR_RPL_MASK));
2523}
2524
2525/*
2526 * Check if guest state is valid. Returns true if valid, false if
2527 * not.
2528 * We assume that registers are always usable
2529 */
2530static bool guest_state_valid(struct kvm_vcpu *vcpu)
2531{
2532 /* real mode guest state checks */
3eeb3288 2533 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2534 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2535 return false;
2536 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2537 return false;
2538 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2539 return false;
2540 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2541 return false;
2542 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2543 return false;
2544 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2545 return false;
2546 } else {
2547 /* protected mode guest state checks */
2548 if (!cs_ss_rpl_check(vcpu))
2549 return false;
2550 if (!code_segment_valid(vcpu))
2551 return false;
2552 if (!stack_segment_valid(vcpu))
2553 return false;
2554 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2555 return false;
2556 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2557 return false;
2558 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2559 return false;
2560 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2561 return false;
2562 if (!tr_valid(vcpu))
2563 return false;
2564 if (!ldtr_valid(vcpu))
2565 return false;
2566 }
2567 /* TODO:
2568 * - Add checks on RIP
2569 * - Add checks on RFLAGS
2570 */
2571
2572 return true;
2573}
2574
d77c26fc 2575static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2576{
40dcaa9f 2577 gfn_t fn;
195aefde 2578 u16 data = 0;
40dcaa9f 2579 int r, idx, ret = 0;
6aa8b732 2580
40dcaa9f
XG		 2581 idx = srcu_read_lock(&kvm->srcu);
2582 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 2583 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2584 if (r < 0)
10589a46 2585 goto out;
195aefde 2586 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2587 r = kvm_write_guest_page(kvm, fn++, &data,
2588 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2589 if (r < 0)
10589a46 2590 goto out;
195aefde
IE		 2591 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2592 if (r < 0)
10589a46 2593 goto out;
195aefde
IE		 2594 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2595 if (r < 0)
10589a46 2596 goto out;
195aefde 2597 data = ~0;
10589a46
MT		 2598 r = kvm_write_guest_page(kvm, fn, &data,
2599 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2600 sizeof(u8));
195aefde 2601 if (r < 0)
10589a46
MT		 2602 goto out;
2603
2604 ret = 1;
2605out:
40dcaa9f 2606 srcu_read_unlock(&kvm->srcu, idx);
10589a46 2607 return ret;
6aa8b732
AK		 2608}
2609
b7ebfb05
SY		 2610static int init_rmode_identity_map(struct kvm *kvm)
2611{
40dcaa9f 2612 int i, idx, r, ret;
b7ebfb05
SY		 2613 pfn_t identity_map_pfn;
2614 u32 tmp;
2615
089d034e 2616 if (!enable_ept)
b7ebfb05
SY		 2617 return 1;
2618 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2619 printk(KERN_ERR "EPT: identity-mapping pagetable "
2620 "haven't been allocated!\n");
2621 return 0;
2622 }
2623 if (likely(kvm->arch.ept_identity_pagetable_done))
2624 return 1;
2625 ret = 0;
b927a3ce 2626 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 2627 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 2628 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2629 if (r < 0)
2630 goto out;
2631 /* Set up identity-mapping pagetable for EPT in real mode */
2632 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2633 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2634 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2635 r = kvm_write_guest_page(kvm, identity_map_pfn,
2636 &tmp, i * sizeof(tmp), sizeof(tmp));
2637 if (r < 0)
2638 goto out;
2639 }
2640 kvm->arch.ept_identity_pagetable_done = true;
2641 ret = 1;
2642out:
40dcaa9f 2643 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 2644 return ret;
2645}
2646
6aa8b732
AK		 2647static void seg_setup(int seg)
2648{
2649 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2650 unsigned int ar;
6aa8b732
AK		 2651
2652 vmcs_write16(sf->selector, 0);
2653 vmcs_writel(sf->base, 0);
2654 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2655 if (enable_unrestricted_guest) {
2656 ar = 0x93;
2657 if (seg == VCPU_SREG_CS)
2658 ar |= 0x08; /* code segment */
2659 } else
2660 ar = 0xf3;
2661
2662 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2663}
2664
f78e0e2e
SY		 2665static int alloc_apic_access_page(struct kvm *kvm)
2666{
2667 struct kvm_userspace_memory_region kvm_userspace_mem;
2668 int r = 0;
2669
79fac95e 2670 mutex_lock(&kvm->slots_lock);
bfc6d222 2671 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2672 goto out;
2673 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2674 kvm_userspace_mem.flags = 0;
2675 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2676 kvm_userspace_mem.memory_size = PAGE_SIZE;
2677 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2678 if (r)
2679 goto out;
72dc67a6 2680
bfc6d222 2681 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2682out:
79fac95e 2683 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2684 return r;
2685}
2686
b7ebfb05
SY		 2687static int alloc_identity_pagetable(struct kvm *kvm)
2688{
2689 struct kvm_userspace_memory_region kvm_userspace_mem;
2690 int r = 0;
2691
79fac95e 2692 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2693 if (kvm->arch.ept_identity_pagetable)
2694 goto out;
2695 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2696 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2697 kvm_userspace_mem.guest_phys_addr =
2698 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2699 kvm_userspace_mem.memory_size = PAGE_SIZE;
2700 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2701 if (r)
2702 goto out;
2703
b7ebfb05 2704 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2705 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2706out:
79fac95e 2707 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2708 return r;
2709}
2710
2384d2b3
SY		 2711static void allocate_vpid(struct vcpu_vmx *vmx)
2712{
2713 int vpid;
2714
2715 vmx->vpid = 0;
919818ab 2716 if (!enable_vpid)
2384d2b3
SY		 2717 return;
2718 spin_lock(&vmx_vpid_lock);
2719 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2720 if (vpid < VMX_NR_VPIDS) {
2721 vmx->vpid = vpid;
2722 __set_bit(vpid, vmx_vpid_bitmap);
2723 }
2724 spin_unlock(&vmx_vpid_lock);
2725}
2726
cdbecfc3
LJ		 2727static void free_vpid(struct vcpu_vmx *vmx)
2728{
2729 if (!enable_vpid)
2730 return;
2731 spin_lock(&vmx_vpid_lock);
2732 if (vmx->vpid != 0)
2733 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2734 spin_unlock(&vmx_vpid_lock);
2735}
2736
5897297b 2737static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2738{
3e7c73e9 2739 int f = sizeof(unsigned long);
25c5f225
SY		 2740
2741 if (!cpu_has_vmx_msr_bitmap())
2742 return;
2743
2744 /*
2745 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2746 * have the write-low and read-high bitmap offsets the wrong way round.
2747 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2748 */
25c5f225 2749 if (msr <= 0x1fff) {
3e7c73e9
AK		 2750 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2751 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2752 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2753 msr &= 0x1fff;
3e7c73e9
AK		 2754 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2755 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2756 }
25c5f225
SY		 2757}
2758
5897297b
AK		 2759static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2760{
2761 if (!longmode_only)
2762 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2763 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2764}
2765
6aa8b732
AK		 2766/*
2767 * Sets up the vmcs for emulated real mode.
2768 */
8b9cf98c 2769static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2770{
468d472f 2771 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2772 u32 junk;
f4e1b3c8 2773 u64 host_pat;
6aa8b732 2774 unsigned long a;
89a27f4d 2775 struct desc_ptr dt;
6aa8b732 2776 int i;
cd2276a7 2777 unsigned long kvm_vmx_return;
6e5d865c 2778 u32 exec_control;
6aa8b732 2779
6aa8b732 2780 /* I/O */
3e7c73e9
AK		 2781 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2782 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2783
25c5f225 2784 if (cpu_has_vmx_msr_bitmap())
5897297b 2785 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2786
6aa8b732
AK		 2787 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2788
6aa8b732 2789 /* Control */
1c3d14fe
YS		 2790 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2791 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2792
2793 exec_control = vmcs_config.cpu_based_exec_ctrl;
2794 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2795 exec_control &= ~CPU_BASED_TPR_SHADOW;
2796#ifdef CONFIG_X86_64
2797 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2798 CPU_BASED_CR8_LOAD_EXITING;
2799#endif
2800 }
089d034e 2801 if (!enable_ept)
d56f546d 2802 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2803 CPU_BASED_CR3_LOAD_EXITING |
2804 CPU_BASED_INVLPG_EXITING;
6e5d865c 2805 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2806
83ff3b9d
SY		 2807 if (cpu_has_secondary_exec_ctrls()) {
2808 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2809 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2810 exec_control &=
2811 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2812 if (vmx->vpid == 0)
2813 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2814 if (!enable_ept) {
d56f546d 2815 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2816 enable_unrestricted_guest = 0;
2817 }
3a624e29
NK		 2818 if (!enable_unrestricted_guest)
2819 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2820 if (!ple_gap)
2821 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2822 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2823 }
f78e0e2e 2824
4b8d54f9
ZE		 2825 if (ple_gap) {
2826 vmcs_write32(PLE_GAP, ple_gap);
2827 vmcs_write32(PLE_WINDOW, ple_window);
2828 }
2829
c7addb90
AK		 2830 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2831 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2832 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2833
1c11e713 2834 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2835 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2836 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2837
2838 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2839 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2840 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2841 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2842 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2843 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2844#ifdef CONFIG_X86_64
6aa8b732
AK		 2845 rdmsrl(MSR_FS_BASE, a);
2846 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2847 rdmsrl(MSR_GS_BASE, a);
2848 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2849#else
2850 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2851 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2852#endif
2853
2854 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2855
ec68798c 2856 native_store_idt(&dt);
89a27f4d 2857 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2858
d77c26fc 2859 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2860 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2861 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2862 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2863 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2864 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2865 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2866
2867 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2868 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2869 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2870 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2871 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2872 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2873
468d472f
SY		 2874 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2875 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2876 host_pat = msr_low | ((u64) msr_high << 32);
2877 vmcs_write64(HOST_IA32_PAT, host_pat);
2878 }
2879 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2880 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2881 host_pat = msr_low | ((u64) msr_high << 32);
2882 /* Write the default value follow host pat */
2883 vmcs_write64(GUEST_IA32_PAT, host_pat);
2884 /* Keep arch.pat sync with GUEST_IA32_PAT */
2885 vmx->vcpu.arch.pat = host_pat;
2886 }
2887
6aa8b732
AK		 2888 for (i = 0; i < NR_VMX_MSR; ++i) {
2889 u32 index = vmx_msr_index[i];
2890 u32 data_low, data_high;
a2fa3e9f 2891 int j = vmx->nmsrs;
6aa8b732
AK		 2892
2893 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2894 continue;
432bd6cb
AK		 2895 if (wrmsr_safe(index, data_low, data_high) < 0)
2896 continue;
26bb0981
AK		 2897 vmx->guest_msrs[j].index = i;
2898 vmx->guest_msrs[j].data = 0;
d5696725 2899 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2900 ++vmx->nmsrs;
6aa8b732 2901 }
6aa8b732 2902
1c3d14fe 2903 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2904
2905 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2906 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2907
e00c8cf2 2908 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2909 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2910 if (enable_ept)
2911 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2912 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2913
99e3e30a 2914 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2915
e00c8cf2
AK		 2916 return 0;
2917}
2918
2919static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2920{
2921 struct vcpu_vmx *vmx = to_vmx(vcpu);
2922 u64 msr;
4b9d3a04 2923 int ret;
e00c8cf2 2924
5fdbf976 2925 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 2926
7ffd92c5 2927 vmx->rmode.vm86_active = 0;
e00c8cf2 2928
3b86cd99
JK		 2929 vmx->soft_vnmi_blocked = 0;
2930
ad312c7c 2931 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2932 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2933 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2934 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2935 msr |= MSR_IA32_APICBASE_BSP;
2936 kvm_set_apic_base(&vmx->vcpu, msr);
2937
10ab25cd
JK		 2938 ret = fx_init(&vmx->vcpu);
2939 if (ret != 0)
2940 goto out;
e00c8cf2 2941
2fb92db1
AK		 2942 vmx_segment_cache_clear(vmx);
2943
5706be0d 2944 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2945 /*
2946 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2947 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2948 */
c5af89b6 2949 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2950 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2951 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2952 } else {
ad312c7c
ZX		 2953 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2954 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2955 }
e00c8cf2
AK		 2956
2957 seg_setup(VCPU_SREG_DS);
2958 seg_setup(VCPU_SREG_ES);
2959 seg_setup(VCPU_SREG_FS);
2960 seg_setup(VCPU_SREG_GS);
2961 seg_setup(VCPU_SREG_SS);
2962
2963 vmcs_write16(GUEST_TR_SELECTOR, 0);
2964 vmcs_writel(GUEST_TR_BASE, 0);
2965 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2966 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2967
2968 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2969 vmcs_writel(GUEST_LDTR_BASE, 0);
2970 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2971 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2972
2973 vmcs_write32(GUEST_SYSENTER_CS, 0);
2974 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2975 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2976
2977 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2978 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2979 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2980 else
5fdbf976
MT		 2981 kvm_rip_write(vcpu, 0);
2982 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2983
e00c8cf2
AK		 2984 vmcs_writel(GUEST_DR7, 0x400);
2985
2986 vmcs_writel(GUEST_GDTR_BASE, 0);
2987 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2988
2989 vmcs_writel(GUEST_IDTR_BASE, 0);
2990 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2991
443381a8 2992 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2993 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2994 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2995
e00c8cf2
AK		 2996 /* Special registers */
2997 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2998
2999 setup_msrs(vmx);
3000
6aa8b732
AK		 3001 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3002
f78e0e2e
SY		 3003 if (cpu_has_vmx_tpr_shadow()) {
3004 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3005 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3007 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3008 vmcs_write32(TPR_THRESHOLD, 0);
3009 }
3010
3011 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3012 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3013 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3014
2384d2b3
SY		 3015 if (vmx->vpid != 0)
3016 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3017
fa40052c 3018 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3019 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3020 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3021 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3022 vmx_fpu_activate(&vmx->vcpu);
3023 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3024
b9d762fa 3025 vpid_sync_context(vmx);
2384d2b3 3026
3200f405 3027 ret = 0;
6aa8b732 3028
a89a8fb9
MG		 3029 /* HACK: Don't enable emulation on guest boot/reset */
3030 vmx->emulation_required = 0;
3031
6aa8b732
AK		 3032out:
3033 return ret;
3034}
3035
3b86cd99
JK		 3036static void enable_irq_window(struct kvm_vcpu *vcpu)
3037{
3038 u32 cpu_based_vm_exec_control;
3039
3040 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3041 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3042 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3043}
3044
3045static void enable_nmi_window(struct kvm_vcpu *vcpu)
3046{
3047 u32 cpu_based_vm_exec_control;
3048
3049 if (!cpu_has_virtual_nmis()) {
3050 enable_irq_window(vcpu);
3051 return;
3052 }
3053
30bd0c4c
AK		 3054 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3055 enable_irq_window(vcpu);
3056 return;
3057 }
3b86cd99
JK		 3058 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3059 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3060 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3061}
3062
66fd3f7f 3063static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3064{
9c8cba37 3065 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3066 uint32_t intr;
3067 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3068
229456fc 3069 trace_kvm_inj_virq(irq);
2714d1d3 3070
fa89a817 3071 ++vcpu->stat.irq_injections;
7ffd92c5 3072 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3073 int inc_eip = 0;
3074 if (vcpu->arch.interrupt.soft)
3075 inc_eip = vcpu->arch.event_exit_inst_len;
3076 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3077 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3078 return;
3079 }
66fd3f7f
GN		 3080 intr = irq | INTR_INFO_VALID_MASK;
3081 if (vcpu->arch.interrupt.soft) {
3082 intr |= INTR_TYPE_SOFT_INTR;
3083 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3084 vmx->vcpu.arch.event_exit_inst_len);
3085 } else
3086 intr |= INTR_TYPE_EXT_INTR;
3087 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3088 vmx_clear_hlt(vcpu);
85f455f7
ED		 3089}
3090
f08864b4
SY		 3091static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3092{
66a5a347
JK		 3093 struct vcpu_vmx *vmx = to_vmx(vcpu);
3094
3b86cd99
JK		 3095 if (!cpu_has_virtual_nmis()) {
3096 /*
3097 * Tracking the NMI-blocked state in software is built upon
3098 * finding the next open IRQ window. This, in turn, depends on
3099 * well-behaving guests: They have to keep IRQs disabled at
3100 * least as long as the NMI handler runs. Otherwise we may
3101 * cause NMI nesting, maybe breaking the guest. But as this is
3102 * highly unlikely, we can live with the residual risk.
3103 */
3104 vmx->soft_vnmi_blocked = 1;
3105 vmx->vnmi_blocked_time = 0;
3106 }
3107
487b391d 3108 ++vcpu->stat.nmi_injections;
9d58b931 3109 vmx->nmi_known_unmasked = false;
7ffd92c5 3110 if (vmx->rmode.vm86_active) {
71f9833b 3111 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3112 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3113 return;
3114 }
f08864b4
SY		 3115 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3116 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3117 vmx_clear_hlt(vcpu);
f08864b4
SY		 3118}
3119
c4282df9 3120static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3121{
3b86cd99 3122 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3123 return 0;
33f089ca 3124
c4282df9 3125 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3126 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3127 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3128}
3129
3cfc3092
JK		 3130static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3131{
3132 if (!cpu_has_virtual_nmis())
3133 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3134 if (to_vmx(vcpu)->nmi_known_unmasked)
3135 return false;
c332c83a 3136 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3137}
3138
3139static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3140{
3141 struct vcpu_vmx *vmx = to_vmx(vcpu);
3142
3143 if (!cpu_has_virtual_nmis()) {
3144 if (vmx->soft_vnmi_blocked != masked) {
3145 vmx->soft_vnmi_blocked = masked;
3146 vmx->vnmi_blocked_time = 0;
3147 }
3148 } else {
9d58b931 3149 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3150 if (masked)
3151 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3152 GUEST_INTR_STATE_NMI);
3153 else
3154 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3155 GUEST_INTR_STATE_NMI);
3156 }
3157}
3158
78646121
GN		 3159static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3160{
c4282df9
GN		 3161 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3162 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3163 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3164}
3165
cbc94022
IE		 3166static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3167{
3168 int ret;
3169 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3170 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3171 .guest_phys_addr = addr,
3172 .memory_size = PAGE_SIZE * 3,
3173 .flags = 0,
3174 };
3175
3176 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3177 if (ret)
3178 return ret;
bfc6d222 3179 kvm->arch.tss_addr = addr;
93ea5388
GN		 3180 if (!init_rmode_tss(kvm))
3181 return -ENOMEM;
3182
cbc94022
IE		 3183 return 0;
3184}
3185
6aa8b732
AK		 3186static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3187 int vec, u32 err_code)
3188{
b3f37707
NK		 3189 /*
3190 * Instruction with address size override prefix opcode 0x67
3191 * Cause the #SS fault with 0 error code in VM86 mode.
3192 */
3193 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3194 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3195 return 1;
77ab6db0
JK		 3196 /*
3197 * Forward all other exceptions that are valid in real mode.
3198 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3199 * the required debugging infrastructure rework.
3200 */
3201 switch (vec) {
77ab6db0 3202 case DB_VECTOR:
d0bfb940
JK		 3203 if (vcpu->guest_debug &
3204 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3205 return 0;
3206 kvm_queue_exception(vcpu, vec);
3207 return 1;
77ab6db0 3208 case BP_VECTOR:
c573cd22
JK		 3209 /*
3210 * Update instruction length as we may reinject the exception
3211 * from user space while in guest debugging mode.
3212 */
3213 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3214 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3215 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3216 return 0;
3217 /* fall through */
3218 case DE_VECTOR:
77ab6db0
JK		 3219 case OF_VECTOR:
3220 case BR_VECTOR:
3221 case UD_VECTOR:
3222 case DF_VECTOR:
3223 case SS_VECTOR:
3224 case GP_VECTOR:
3225 case MF_VECTOR:
3226 kvm_queue_exception(vcpu, vec);
3227 return 1;
3228 }
6aa8b732
AK		 3229 return 0;
3230}
3231
a0861c02
AK		 3232/*
3233 * Trigger machine check on the host. We assume all the MSRs are already set up
3234 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3235 * We pass a fake environment to the machine check handler because we want
3236 * the guest to be always treated like user space, no matter what context
3237 * it used internally.
3238 */
3239static void kvm_machine_check(void)
3240{
3241#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3242 struct pt_regs regs = {
3243 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3244 .flags = X86_EFLAGS_IF,
3245 };
3246
3247 do_machine_check(&regs, 0);
3248#endif
3249}
3250
851ba692 3251static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3252{
3253 /* already handled by vcpu_run */
3254 return 1;
3255}
3256
851ba692 3257static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3258{
1155f76a 3259 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3260 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3261 u32 intr_info, ex_no, error_code;
42dbaa5a 3262 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3263 u32 vect_info;
3264 enum emulation_result er;
3265
1155f76a 3266 vect_info = vmx->idt_vectoring_info;
88786475 3267 intr_info = vmx->exit_intr_info;
6aa8b732 3268
a0861c02 3269 if (is_machine_check(intr_info))
851ba692 3270 return handle_machine_check(vcpu);
a0861c02 3271
6aa8b732 3272 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3273 !is_page_fault(intr_info)) {
3274 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3275 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3276 vcpu->run->internal.ndata = 2;
3277 vcpu->run->internal.data[0] = vect_info;
3278 vcpu->run->internal.data[1] = intr_info;
3279 return 0;
3280 }
6aa8b732 3281
e4a41889 3282 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3283 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3284
3285 if (is_no_device(intr_info)) {
5fd86fcf 3286 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3287 return 1;
3288 }
3289
7aa81cc0 3290 if (is_invalid_opcode(intr_info)) {
51d8b661 3291 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3292 if (er != EMULATE_DONE)
7ee5d940 3293 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3294 return 1;
3295 }
3296
6aa8b732 3297 error_code = 0;
2e11384c 3298 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3299 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3300 if (is_page_fault(intr_info)) {
1439442c 3301 /* EPT won't cause page fault directly */
089d034e 3302 if (enable_ept)
1439442c 3303 BUG();
6aa8b732 3304 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3305 trace_kvm_page_fault(cr2, error_code);
3306
3298b75c 3307 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3308 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3309 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3310 }
3311
7ffd92c5 3312 if (vmx->rmode.vm86_active &&
6aa8b732 3313 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3314 error_code)) {
ad312c7c
ZX		 3315 if (vcpu->arch.halt_request) {
3316 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3317 return kvm_emulate_halt(vcpu);
3318 }
6aa8b732 3319 return 1;
72d6e5a0 3320 }
6aa8b732 3321
d0bfb940 3322 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3323 switch (ex_no) {
3324 case DB_VECTOR:
3325 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3326 if (!(vcpu->guest_debug &
3327 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3328 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3329 kvm_queue_exception(vcpu, DB_VECTOR);
3330 return 1;
3331 }
3332 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3333 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3334 /* fall through */
3335 case BP_VECTOR:
c573cd22
JK		 3336 /*
3337 * Update instruction length as we may reinject #BP from
3338 * user space while in guest debugging mode. Reading it for
3339 * #DB as well causes no harm, it is not used in that case.
3340 */
3341 vmx->vcpu.arch.event_exit_inst_len =
3342 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3343 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 3344 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 3345 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3346 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3347 break;
3348 default:
d0bfb940
JK		 3349 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3350 kvm_run->ex.exception = ex_no;
3351 kvm_run->ex.error_code = error_code;
42dbaa5a 3352 break;
6aa8b732 3353 }
6aa8b732
AK		 3354 return 0;
3355}
3356
851ba692 3357static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3358{
1165f5fe 3359 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3360 return 1;
3361}
3362
851ba692 3363static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3364{
851ba692 3365 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3366 return 0;
3367}
6aa8b732 3368
851ba692 3369static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3370{
bfdaab09 3371 unsigned long exit_qualification;
34c33d16 3372 int size, in, string;
039576c0 3373 unsigned port;
6aa8b732 3374
bfdaab09 3375 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3376 string = (exit_qualification & 16) != 0;
cf8f70bf 3377 in = (exit_qualification & 8) != 0;
e70669ab 3378
cf8f70bf 3379 ++vcpu->stat.io_exits;
e70669ab 3380
cf8f70bf 3381 if (string || in)
51d8b661 3382 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3383
cf8f70bf
GN		 3384 port = exit_qualification >> 16;
3385 size = (exit_qualification & 7) + 1;
e93f36bc 3386 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3387
3388 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3389}
3390
102d8325
IM		 3391static void
3392vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3393{
3394 /*
3395 * Patch in the VMCALL instruction:
3396 */
3397 hypercall[0] = 0x0f;
3398 hypercall[1] = 0x01;
3399 hypercall[2] = 0xc1;
102d8325
IM		 3400}
3401
851ba692 3402static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3403{
229456fc 3404 unsigned long exit_qualification, val;
6aa8b732
AK		 3405 int cr;
3406 int reg;
49a9b07e 3407 int err;
6aa8b732 3408
bfdaab09 3409 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3410 cr = exit_qualification & 15;
3411 reg = (exit_qualification >> 8) & 15;
3412 switch ((exit_qualification >> 4) & 3) {
3413 case 0: /* mov to cr */
229456fc
MT		 3414 val = kvm_register_read(vcpu, reg);
3415 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3416 switch (cr) {
3417 case 0:
49a9b07e 3418 err = kvm_set_cr0(vcpu, val);
db8fcefa 3419 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3420 return 1;
3421 case 3:
2390218b 3422 err = kvm_set_cr3(vcpu, val);
db8fcefa 3423 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3424 return 1;
3425 case 4:
a83b29c6 3426 err = kvm_set_cr4(vcpu, val);
db8fcefa 3427 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3428 return 1;
0a5fff19
GN		 3429 case 8: {
3430 u8 cr8_prev = kvm_get_cr8(vcpu);
3431 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3432 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3433 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3434 if (irqchip_in_kernel(vcpu->kvm))
3435 return 1;
3436 if (cr8_prev <= cr8)
3437 return 1;
851ba692 3438 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3439 return 0;
3440 }
6aa8b732
AK		 3441 };
3442 break;
25c4c276 3443 case 2: /* clts */
edcafe3c 3444 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3445 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3446 skip_emulated_instruction(vcpu);
6b52d186 3447 vmx_fpu_activate(vcpu);
25c4c276 3448 return 1;
6aa8b732
AK		 3449 case 1: /*mov from cr*/
3450 switch (cr) {
3451 case 3:
9f8fe504
AK		 3452 val = kvm_read_cr3(vcpu);
3453 kvm_register_write(vcpu, reg, val);
3454 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3455 skip_emulated_instruction(vcpu);
3456 return 1;
3457 case 8:
229456fc
MT		 3458 val = kvm_get_cr8(vcpu);
3459 kvm_register_write(vcpu, reg, val);
3460 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3461 skip_emulated_instruction(vcpu);
3462 return 1;
3463 }
3464 break;
3465 case 3: /* lmsw */
a1f83a74 3466 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3467 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3468 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3469
3470 skip_emulated_instruction(vcpu);
3471 return 1;
3472 default:
3473 break;
3474 }
851ba692 3475 vcpu->run->exit_reason = 0;
f0242478 3476 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3477 (int)(exit_qualification >> 4) & 3, cr);
3478 return 0;
3479}
3480
851ba692 3481static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3482{
bfdaab09 3483 unsigned long exit_qualification;
6aa8b732
AK		 3484 int dr, reg;
3485
f2483415 3486 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3487 if (!kvm_require_cpl(vcpu, 0))
3488 return 1;
42dbaa5a
JK		 3489 dr = vmcs_readl(GUEST_DR7);
3490 if (dr & DR7_GD) {
3491 /*
3492 * As the vm-exit takes precedence over the debug trap, we
3493 * need to emulate the latter, either for the host or the
3494 * guest debugging itself.
3495 */
3496 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3497 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3498 vcpu->run->debug.arch.dr7 = dr;
3499 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3500 vmcs_readl(GUEST_CS_BASE) +
3501 vmcs_readl(GUEST_RIP);
851ba692
AK		 3502 vcpu->run->debug.arch.exception = DB_VECTOR;
3503 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3504 return 0;
3505 } else {
3506 vcpu->arch.dr7 &= ~DR7_GD;
3507 vcpu->arch.dr6 |= DR6_BD;
3508 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3509 kvm_queue_exception(vcpu, DB_VECTOR);
3510 return 1;
3511 }
3512 }
3513
bfdaab09 3514 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3515 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3516 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3517 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3518 unsigned long val;
3519 if (!kvm_get_dr(vcpu, dr, &val))
3520 kvm_register_write(vcpu, reg, val);
3521 } else
3522 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3523 skip_emulated_instruction(vcpu);
3524 return 1;
3525}
3526
020df079
GN		 3527static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3528{
3529 vmcs_writel(GUEST_DR7, val);
3530}
3531
851ba692 3532static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3533{
06465c5a
AK		 3534 kvm_emulate_cpuid(vcpu);
3535 return 1;
6aa8b732
AK		 3536}
3537
851ba692 3538static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3539{
ad312c7c 3540 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3541 u64 data;
3542
3543 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3544 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3545 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3546 return 1;
3547 }
3548
229456fc 3549 trace_kvm_msr_read(ecx, data);
2714d1d3 3550
6aa8b732 3551 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3552 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3553 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3554 skip_emulated_instruction(vcpu);
3555 return 1;
3556}
3557
851ba692 3558static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3559{
ad312c7c
ZX		 3560 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3561 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3562 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3563
3564 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3565 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3566 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3567 return 1;
3568 }
3569
59200273 3570 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3571 skip_emulated_instruction(vcpu);
3572 return 1;
3573}
3574
851ba692 3575static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3576{
3842d135 3577 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3578 return 1;
3579}
3580
851ba692 3581static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3582{
85f455f7
ED		 3583 u32 cpu_based_vm_exec_control;
3584
3585 /* clear pending irq */
3586 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3587 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3588 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3589
3842d135
AK		 3590 kvm_make_request(KVM_REQ_EVENT, vcpu);
3591
a26bf12a 3592 ++vcpu->stat.irq_window_exits;
2714d1d3 3593
c1150d8c
DL		 3594 /*
3595 * If the user space waits to inject interrupts, exit as soon as
3596 * possible
3597 */
8061823a 3598 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3599 vcpu->run->request_interrupt_window &&
8061823a 3600 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3601 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3602 return 0;
3603 }
6aa8b732
AK		 3604 return 1;
3605}
3606
851ba692 3607static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3608{
3609 skip_emulated_instruction(vcpu);
d3bef15f 3610 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3611}
3612
851ba692 3613static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3614{
510043da 3615 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3616 kvm_emulate_hypercall(vcpu);
3617 return 1;
c21415e8
IM		 3618}
3619
851ba692 3620static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3621{
3622 kvm_queue_exception(vcpu, UD_VECTOR);
3623 return 1;
3624}
3625
ec25d5e6
GN		 3626static int handle_invd(struct kvm_vcpu *vcpu)
3627{
51d8b661 3628 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3629}
3630
851ba692 3631static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3632{
f9c617f6 3633 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3634
3635 kvm_mmu_invlpg(vcpu, exit_qualification);
3636 skip_emulated_instruction(vcpu);
3637 return 1;
3638}
3639
851ba692 3640static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3641{
3642 skip_emulated_instruction(vcpu);
f5f48ee1 3643 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3644 return 1;
3645}
3646
2acf923e
DC		 3647static int handle_xsetbv(struct kvm_vcpu *vcpu)
3648{
3649 u64 new_bv = kvm_read_edx_eax(vcpu);
3650 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3651
3652 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3653 skip_emulated_instruction(vcpu);
3654 return 1;
3655}
3656
851ba692 3657static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3658{
51d8b661 3659 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3660}
3661
851ba692 3662static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3663{
60637aac 3664 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3665 unsigned long exit_qualification;
e269fb21
JK		 3666 bool has_error_code = false;
3667 u32 error_code = 0;
37817f29 3668 u16 tss_selector;
64a7ec06
GN		 3669 int reason, type, idt_v;
3670
3671 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3672 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3673
3674 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3675
3676 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3677 if (reason == TASK_SWITCH_GATE && idt_v) {
3678 switch (type) {
3679 case INTR_TYPE_NMI_INTR:
3680 vcpu->arch.nmi_injected = false;
654f06fc 3681 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 3682 break;
3683 case INTR_TYPE_EXT_INTR:
66fd3f7f 3684 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3685 kvm_clear_interrupt_queue(vcpu);
3686 break;
3687 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3688 if (vmx->idt_vectoring_info &
3689 VECTORING_INFO_DELIVER_CODE_MASK) {
3690 has_error_code = true;
3691 error_code =
3692 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3693 }
3694 /* fall through */
64a7ec06
GN		 3695 case INTR_TYPE_SOFT_EXCEPTION:
3696 kvm_clear_exception_queue(vcpu);
3697 break;
3698 default:
3699 break;
3700 }
60637aac 3701 }
37817f29
IE		 3702 tss_selector = exit_qualification;
3703
64a7ec06
GN		 3704 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3705 type != INTR_TYPE_EXT_INTR &&
3706 type != INTR_TYPE_NMI_INTR))
3707 skip_emulated_instruction(vcpu);
3708
acb54517
GN		 3709 if (kvm_task_switch(vcpu, tss_selector, reason,
3710 has_error_code, error_code) == EMULATE_FAIL) {
3711 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3712 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3713 vcpu->run->internal.ndata = 0;
42dbaa5a 3714 return 0;
acb54517 3715 }
42dbaa5a
JK		 3716
3717 /* clear all local breakpoint enable flags */
3718 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3719
3720 /*
3721 * TODO: What about debug traps on tss switch?
3722 * Are we supposed to inject them and update dr6?
3723 */
3724
3725 return 1;
37817f29
IE		 3726}
3727
851ba692 3728static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3729{
f9c617f6 3730 unsigned long exit_qualification;
1439442c 3731 gpa_t gpa;
1439442c 3732 int gla_validity;
1439442c 3733
f9c617f6 3734 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3735
3736 if (exit_qualification & (1 << 6)) {
3737 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3738 return -EINVAL;
1439442c
SY		 3739 }
3740
3741 gla_validity = (exit_qualification >> 7) & 0x3;
3742 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3743 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3744 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3745 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3746 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3747 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3748 (long unsigned int)exit_qualification);
851ba692
AK		 3749 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3750 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3751 return 0;
1439442c
SY		 3752 }
3753
3754 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3755 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3756 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3757}
3758
68f89400
MT		 3759static u64 ept_rsvd_mask(u64 spte, int level)
3760{
3761 int i;
3762 u64 mask = 0;
3763
3764 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3765 mask |= (1ULL << i);
3766
3767 if (level > 2)
3768 /* bits 7:3 reserved */
3769 mask |= 0xf8;
3770 else if (level == 2) {
3771 if (spte & (1ULL << 7))
3772 /* 2MB ref, bits 20:12 reserved */
3773 mask |= 0x1ff000;
3774 else
3775 /* bits 6:3 reserved */
3776 mask |= 0x78;
3777 }
3778
3779 return mask;
3780}
3781
3782static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3783 int level)
3784{
3785 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3786
3787 /* 010b (write-only) */
3788 WARN_ON((spte & 0x7) == 0x2);
3789
3790 /* 110b (write/execute) */
3791 WARN_ON((spte & 0x7) == 0x6);
3792
3793 /* 100b (execute-only) and value not supported by logical processor */
3794 if (!cpu_has_vmx_ept_execute_only())
3795 WARN_ON((spte & 0x7) == 0x4);
3796
3797 /* not 000b */
3798 if ((spte & 0x7)) {
3799 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3800
3801 if (rsvd_bits != 0) {
3802 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3803 __func__, rsvd_bits);
3804 WARN_ON(1);
3805 }
3806
3807 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3808 u64 ept_mem_type = (spte & 0x38) >> 3;
3809
3810 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3811 ept_mem_type == 7) {
3812 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3813 __func__, ept_mem_type);
3814 WARN_ON(1);
3815 }
3816 }
3817 }
3818}
3819
851ba692 3820static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3821{
3822 u64 sptes[4];
3823 int nr_sptes, i;
3824 gpa_t gpa;
3825
3826 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3827
3828 printk(KERN_ERR "EPT: Misconfiguration.\n");
3829 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3830
3831 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3832
3833 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3834 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3835
851ba692
AK		 3836 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3837 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3838
3839 return 0;
3840}
3841
851ba692 3842static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3843{
3844 u32 cpu_based_vm_exec_control;
3845
3846 /* clear pending NMI */
3847 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3848 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3849 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3850 ++vcpu->stat.nmi_window_exits;
3842d135 3851 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3852
3853 return 1;
3854}
3855
80ced186 3856static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3857{
8b3079a5
AK		 3858 struct vcpu_vmx *vmx = to_vmx(vcpu);
3859 enum emulation_result err = EMULATE_DONE;
80ced186 3860 int ret = 1;
49e9d557
AK		 3861 u32 cpu_exec_ctrl;
3862 bool intr_window_requested;
3863
3864 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3865 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3866
3867 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3868 if (intr_window_requested
3869 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3870 return handle_interrupt_window(&vmx->vcpu);
3871
51d8b661 3872 err = emulate_instruction(vcpu, 0);
ea953ef0 3873
80ced186
MG		 3874 if (err == EMULATE_DO_MMIO) {
3875 ret = 0;
3876 goto out;
3877 }
1d5a4d9b 3878
6d77dbfc
GN		 3879 if (err != EMULATE_DONE)
3880 return 0;
ea953ef0
MG		 3881
3882 if (signal_pending(current))
80ced186 3883 goto out;
ea953ef0
MG		 3884 if (need_resched())
3885 schedule();
3886 }
3887
80ced186
MG		 3888 vmx->emulation_required = 0;
3889out:
3890 return ret;
ea953ef0
MG		 3891}
3892
4b8d54f9
ZE		 3893/*
3894 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3895 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3896 */
9fb41ba8 3897static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3898{
3899 skip_emulated_instruction(vcpu);
3900 kvm_vcpu_on_spin(vcpu);
3901
3902 return 1;
3903}
3904
59708670
SY		 3905static int handle_invalid_op(struct kvm_vcpu *vcpu)
3906{
3907 kvm_queue_exception(vcpu, UD_VECTOR);
3908 return 1;
3909}
3910
6aa8b732
AK		 3911/*
3912 * The exit handlers return 1 if the exit was handled fully and guest execution
3913 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3914 * to be done to userspace and return 0.
3915 */
851ba692 3916static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3917 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3918 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3919 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3920 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3921 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3922 [EXIT_REASON_CR_ACCESS] = handle_cr,
3923 [EXIT_REASON_DR_ACCESS] = handle_dr,
3924 [EXIT_REASON_CPUID] = handle_cpuid,
3925 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3926 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3927 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3928 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3929 [EXIT_REASON_INVD] = handle_invd,
a7052897 3930 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3931 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3932 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3933 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3934 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3935 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3936 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3937 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3938 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3939 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3940 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3941 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3942 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3943 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3944 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3945 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3946 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3947 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3948 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3949 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3950 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3951 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3952};
3953
3954static const int kvm_vmx_max_exit_handlers =
50a3485c 3955 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3956
586f9607
AK		 3957static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3958{
3959 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3960 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3961}
3962
6aa8b732
AK		 3963/*
3964 * The guest has exited. See if we can fix it or if we need userspace
3965 * assistance.
3966 */
851ba692 3967static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3968{
29bd8a78 3969 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3970 u32 exit_reason = vmx->exit_reason;
1155f76a 3971 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3972
aa17911e 3973 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3974
80ced186
MG		 3975 /* If guest state is invalid, start emulating */
3976 if (vmx->emulation_required && emulate_invalid_guest_state)
3977 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3978
5120702e
MG		 3979 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3980 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3981 vcpu->run->fail_entry.hardware_entry_failure_reason
3982 = exit_reason;
3983 return 0;
3984 }
3985
29bd8a78 3986 if (unlikely(vmx->fail)) {
851ba692
AK		 3987 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3988 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3989 = vmcs_read32(VM_INSTRUCTION_ERROR);
3990 return 0;
3991 }
6aa8b732 3992
d77c26fc 3993 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3994 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3995 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3996 exit_reason != EXIT_REASON_TASK_SWITCH))
3997 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3998 "(0x%x) and exit reason is 0x%x\n",
3999 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 4000
4001 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 4002 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 4003 vmx->soft_vnmi_blocked = 0;
3b86cd99 4004 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 4005 vcpu->arch.nmi_pending) {
3b86cd99
JK		 4006 /*
4007 * This CPU don't support us in finding the end of an
4008 * NMI-blocked window if the guest runs with IRQs
4009 * disabled. So we pull the trigger after 1 s of
4010 * futile waiting, but inform the user about this.
4011 */
4012 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4013 "state on VCPU %d after 1 s timeout\n",
4014 __func__, vcpu->vcpu_id);
4015 vmx->soft_vnmi_blocked = 0;
3b86cd99 4016 }
3b86cd99
JK		 4017 }
4018
6aa8b732
AK		 4019 if (exit_reason < kvm_vmx_max_exit_handlers
4020 && kvm_vmx_exit_handlers[exit_reason])
851ba692 4021 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 4022 else {
851ba692
AK		 4023 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4024 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 4025 }
4026 return 0;
4027}
4028
95ba8273 4029static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 4030{
95ba8273 4031 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 4032 vmcs_write32(TPR_THRESHOLD, 0);
4033 return;
4034 }
4035
95ba8273 4036 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 4037}
4038
51aa01d1 4039static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 4040{
00eba012
AK		 4041 u32 exit_intr_info;
4042
4043 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4044 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4045 return;
4046
c5ca8e57 4047 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 4048 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 4049
4050 /* Handle machine checks before interrupts are enabled */
00eba012 4051 if (is_machine_check(exit_intr_info))
a0861c02
AK		 4052 kvm_machine_check();
4053
20f65983 4054 /* We need to handle NMIs before interrupts are enabled */
00eba012 4055 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 4056 (exit_intr_info & INTR_INFO_VALID_MASK)) {
4057 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 4058 asm("int $2");
ff9d07a0
ZY		 4059 kvm_after_handle_nmi(&vmx->vcpu);
4060 }
51aa01d1 4061}
20f65983 4062
51aa01d1
AK		 4063static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4064{
c5ca8e57 4065 u32 exit_intr_info;
51aa01d1
AK		 4066 bool unblock_nmi;
4067 u8 vector;
4068 bool idtv_info_valid;
4069
4070 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 4071
cf393f75 4072 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 4073 if (vmx->nmi_known_unmasked)
4074 return;
c5ca8e57
AK		 4075 /*
4076 * Can't use vmx->exit_intr_info since we're not sure what
4077 * the exit reason is.
4078 */
4079 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 4080 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4081 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4082 /*
7b4a25cb 4083 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 4084 * Re-set bit "block by NMI" before VM entry if vmexit caused by
4085 * a guest IRET fault.
7b4a25cb
GN		 4086 * SDM 3: 23.2.2 (September 2008)
4087 * Bit 12 is undefined in any of the following cases:
4088 * If the VM exit sets the valid bit in the IDT-vectoring
4089 * information field.
4090 * If the VM exit is due to a double fault.
cf393f75 4091 */
7b4a25cb
GN		 4092 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4093 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 4094 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4095 GUEST_INTR_STATE_NMI);
9d58b931
AK		 4096 else
4097 vmx->nmi_known_unmasked =
4098 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4099 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 4100 } else if (unlikely(vmx->soft_vnmi_blocked))
4101 vmx->vnmi_blocked_time +=
4102 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 4103}
4104
83422e17
AK		 4105static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4106 u32 idt_vectoring_info,
4107 int instr_len_field,
4108 int error_code_field)
51aa01d1 4109{
51aa01d1
AK		 4110 u8 vector;
4111 int type;
4112 bool idtv_info_valid;
4113
4114 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 4115
37b96e98
GN		 4116 vmx->vcpu.arch.nmi_injected = false;
4117 kvm_clear_exception_queue(&vmx->vcpu);
4118 kvm_clear_interrupt_queue(&vmx->vcpu);
4119
4120 if (!idtv_info_valid)
4121 return;
4122
3842d135
AK		 4123 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4124
668f612f
AK		 4125 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4126 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 4127
64a7ec06 4128 switch (type) {
37b96e98
GN		 4129 case INTR_TYPE_NMI_INTR:
4130 vmx->vcpu.arch.nmi_injected = true;
668f612f 4131 /*
7b4a25cb 4132 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 4133 * Clear bit "block by NMI" before VM entry if a NMI
4134 * delivery faulted.
668f612f 4135 */
654f06fc 4136 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 4137 break;
37b96e98 4138 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 4139 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4140 vmcs_read32(instr_len_field);
66fd3f7f
GN		 4141 /* fall through */
4142 case INTR_TYPE_HARD_EXCEPTION:
35920a35 4143 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 4144 u32 err = vmcs_read32(error_code_field);
37b96e98 4145 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 4146 } else
4147 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 4148 break;
66fd3f7f
GN		 4149 case INTR_TYPE_SOFT_INTR:
4150 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4151 vmcs_read32(instr_len_field);
66fd3f7f 4152 /* fall through */
37b96e98 4153 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 4154 kvm_queue_interrupt(&vmx->vcpu, vector,
4155 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 4156 break;
4157 default:
4158 break;
f7d9238f 4159 }
cf393f75
AK		 4160}
4161
83422e17
AK		 4162static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4163{
4164 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4165 VM_EXIT_INSTRUCTION_LEN,
4166 IDT_VECTORING_ERROR_CODE);
4167}
4168
b463a6f7
AK		 4169static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4170{
4171 __vmx_complete_interrupts(to_vmx(vcpu),
4172 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4173 VM_ENTRY_INSTRUCTION_LEN,
4174 VM_ENTRY_EXCEPTION_ERROR_CODE);
4175
4176 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4177}
4178
c801949d
AK		 4179#ifdef CONFIG_X86_64
4180#define R "r"
4181#define Q "q"
4182#else
4183#define R "e"
4184#define Q "l"
4185#endif
4186
a3b5ba49 4187static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 4188{
a2fa3e9f 4189 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 4190
4191 /* Record the guest's net vcpu time for enforced NMI injections. */
4192 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4193 vmx->entry_time = ktime_get();
4194
4195 /* Don't enter VMX if guest state is invalid, let the exit handler
4196 start emulation until we arrive back to a valid state */
4197 if (vmx->emulation_required && emulate_invalid_guest_state)
4198 return;
4199
4200 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4201 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4202 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4203 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4204
4205 /* When single-stepping over STI and MOV SS, we must clear the
4206 * corresponding interruptibility bits in the guest state. Otherwise
4207 * vmentry fails as it then expects bit 14 (BS) in pending debug
4208 * exceptions being set, but that's not correct for the guest debugging
4209 * case. */
4210 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4211 vmx_set_interrupt_shadow(vcpu, 0);
4212
d462b819 4213 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 4214 asm(
6aa8b732 4215 /* Store host registers */
c801949d 4216 "push %%"R"dx; push %%"R"bp;"
40712fae 4217 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 4218 "push %%"R"cx \n\t"
313dbd49
AK		 4219 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4220 "je 1f \n\t"
4221 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4222 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4223 "1: \n\t"
d3edefc0
AK		 4224 /* Reload cr2 if changed */
4225 "mov %c[cr2](%0), %%"R"ax \n\t"
4226 "mov %%cr2, %%"R"dx \n\t"
4227 "cmp %%"R"ax, %%"R"dx \n\t"
4228 "je 2f \n\t"
4229 "mov %%"R"ax, %%cr2 \n\t"
4230 "2: \n\t"
6aa8b732 4231 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4232 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4233 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4234 "mov %c[rax](%0), %%"R"ax \n\t"
4235 "mov %c[rbx](%0), %%"R"bx \n\t"
4236 "mov %c[rdx](%0), %%"R"dx \n\t"
4237 "mov %c[rsi](%0), %%"R"si \n\t"
4238 "mov %c[rdi](%0), %%"R"di \n\t"
4239 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4240#ifdef CONFIG_X86_64
e08aa78a
AK		 4241 "mov %c[r8](%0), %%r8 \n\t"
4242 "mov %c[r9](%0), %%r9 \n\t"
4243 "mov %c[r10](%0), %%r10 \n\t"
4244 "mov %c[r11](%0), %%r11 \n\t"
4245 "mov %c[r12](%0), %%r12 \n\t"
4246 "mov %c[r13](%0), %%r13 \n\t"
4247 "mov %c[r14](%0), %%r14 \n\t"
4248 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4249#endif
c801949d
AK		 4250 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4251
6aa8b732 4252 /* Enter guest mode */
cd2276a7 4253 "jne .Llaunched \n\t"
4ecac3fd 4254 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4255 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4256 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4257 ".Lkvm_vmx_return: "
6aa8b732 4258 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 4259 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4260 "pop %0 \n\t"
c801949d
AK		 4261 "mov %%"R"ax, %c[rax](%0) \n\t"
4262 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 4263 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 4264 "mov %%"R"dx, %c[rdx](%0) \n\t"
4265 "mov %%"R"si, %c[rsi](%0) \n\t"
4266 "mov %%"R"di, %c[rdi](%0) \n\t"
4267 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4268#ifdef CONFIG_X86_64
e08aa78a
AK		 4269 "mov %%r8, %c[r8](%0) \n\t"
4270 "mov %%r9, %c[r9](%0) \n\t"
4271 "mov %%r10, %c[r10](%0) \n\t"
4272 "mov %%r11, %c[r11](%0) \n\t"
4273 "mov %%r12, %c[r12](%0) \n\t"
4274 "mov %%r13, %c[r13](%0) \n\t"
4275 "mov %%r14, %c[r14](%0) \n\t"
4276 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4277#endif
c801949d
AK		 4278 "mov %%cr2, %%"R"ax \n\t"
4279 "mov %%"R"ax, %c[cr2](%0) \n\t"
4280
1c696d0e 4281 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4282 "setbe %c[fail](%0) \n\t"
4283 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 4284 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 4285 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4286 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4287 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4288 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4289 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4290 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4291 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4292 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4293 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4294#ifdef CONFIG_X86_64
ad312c7c
ZX		 4295 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4296 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4297 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4298 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4299 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4300 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4301 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4302 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4303#endif
40712fae
AK		 4304 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4305 [wordsize]"i"(sizeof(ulong))
c2036300 4306 : "cc", "memory"
07d6f555 4307 , R"ax", R"bx", R"di", R"si"
c2036300 4308#ifdef CONFIG_X86_64
c2036300
LV		 4309 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4310#endif
4311 );
6aa8b732 4312
6de4f3ad 4313 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 4314 | (1 << VCPU_EXREG_RFLAGS)
69c73028 4315 | (1 << VCPU_EXREG_CPL)
aff48baa 4316 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 4317 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 4318 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4319 vcpu->arch.regs_dirty = 0;
4320
1155f76a
AK		 4321 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4322
d77c26fc 4323 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 4324 vmx->loaded_vmcs->launched = 1;
1b6269db 4325
51aa01d1 4326 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 4327
4328 vmx_complete_atomic_exit(vmx);
4329 vmx_recover_nmi_blocking(vmx);
cf393f75 4330 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4331}
4332
c801949d
AK		 4333#undef R
4334#undef Q
4335
6aa8b732
AK		 4336static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4337{
fb3f0f51
RR		 4338 struct vcpu_vmx *vmx = to_vmx(vcpu);
4339
cdbecfc3 4340 free_vpid(vmx);
d462b819 4341 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 4342 kfree(vmx->guest_msrs);
4343 kvm_vcpu_uninit(vcpu);
a4770347 4344 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4345}
4346
fb3f0f51 4347static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4348{
fb3f0f51 4349 int err;
c16f862d 4350 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4351 int cpu;
6aa8b732 4352
a2fa3e9f 4353 if (!vmx)
fb3f0f51
RR		 4354 return ERR_PTR(-ENOMEM);
4355
2384d2b3
SY		 4356 allocate_vpid(vmx);
4357
fb3f0f51
RR		 4358 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4359 if (err)
4360 goto free_vcpu;
965b58a5 4361
a2fa3e9f 4362 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 4363 err = -ENOMEM;
fb3f0f51 4364 if (!vmx->guest_msrs) {
fb3f0f51
RR		 4365 goto uninit_vcpu;
4366 }
965b58a5 4367
d462b819
NHE		 4368 vmx->loaded_vmcs = &vmx->vmcs01;
4369 vmx->loaded_vmcs->vmcs = alloc_vmcs();
4370 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 4371 goto free_msrs;
d462b819
NHE		 4372 if (!vmm_exclusive)
4373 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
4374 loaded_vmcs_init(vmx->loaded_vmcs);
4375 if (!vmm_exclusive)
4376 kvm_cpu_vmxoff();
a2fa3e9f 4377
15ad7146
AK		 4378 cpu = get_cpu();
4379 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4380 vmx->vcpu.cpu = cpu;
8b9cf98c 4381 err = vmx_vcpu_setup(vmx);
fb3f0f51 4382 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4383 put_cpu();
fb3f0f51
RR		 4384 if (err)
4385 goto free_vmcs;
5e4a0b3c 4386 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 4387 err = alloc_apic_access_page(kvm);
4388 if (err)
5e4a0b3c 4389 goto free_vmcs;
fb3f0f51 4390
b927a3ce
SY		 4391 if (enable_ept) {
4392 if (!kvm->arch.ept_identity_map_addr)
4393 kvm->arch.ept_identity_map_addr =
4394 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 4395 err = -ENOMEM;
b7ebfb05
SY		 4396 if (alloc_identity_pagetable(kvm) != 0)
4397 goto free_vmcs;
93ea5388
GN		 4398 if (!init_rmode_identity_map(kvm))
4399 goto free_vmcs;
b927a3ce 4400 }
b7ebfb05 4401
fb3f0f51
RR		 4402 return &vmx->vcpu;
4403
4404free_vmcs:
d462b819 4405 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 4406free_msrs:
fb3f0f51
RR		 4407 kfree(vmx->guest_msrs);
4408uninit_vcpu:
4409 kvm_vcpu_uninit(&vmx->vcpu);
4410free_vcpu:
cdbecfc3 4411 free_vpid(vmx);
a4770347 4412 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4413 return ERR_PTR(err);
6aa8b732
AK		 4414}
4415
002c7f7c
YS		 4416static void __init vmx_check_processor_compat(void *rtn)
4417{
4418 struct vmcs_config vmcs_conf;
4419
4420 *(int *)rtn = 0;
4421 if (setup_vmcs_config(&vmcs_conf) < 0)
4422 *(int *)rtn = -EIO;
4423 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4424 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4425 smp_processor_id());
4426 *(int *)rtn = -EIO;
4427 }
4428}
4429
67253af5
SY		 4430static int get_ept_level(void)
4431{
4432 return VMX_EPT_DEFAULT_GAW + 1;
4433}
4434
4b12f0de 4435static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4436{
4b12f0de
SY		 4437 u64 ret;
4438
522c68c4
SY		 4439 /* For VT-d and EPT combination
4440 * 1. MMIO: always map as UC
4441 * 2. EPT with VT-d:
4442 * a. VT-d without snooping control feature: can't guarantee the
4443 * result, try to trust guest.
4444 * b. VT-d with snooping control feature: snooping control feature of
4445 * VT-d engine can guarantee the cache correctness. Just set it
4446 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4447 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4448 * consistent with host MTRR
4449 */
4b12f0de
SY		 4450 if (is_mmio)
4451 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4452 else if (vcpu->kvm->arch.iommu_domain &&
4453 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4454 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4455 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4456 else
522c68c4 4457 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4458 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4459
4460 return ret;
64d4d521
SY		 4461}
4462
f4c9e87c
AK		 4463#define _ER(x) { EXIT_REASON_##x, #x }
4464
229456fc 4465static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4466 _ER(EXCEPTION_NMI),
4467 _ER(EXTERNAL_INTERRUPT),
4468 _ER(TRIPLE_FAULT),
4469 _ER(PENDING_INTERRUPT),
4470 _ER(NMI_WINDOW),
4471 _ER(TASK_SWITCH),
4472 _ER(CPUID),
4473 _ER(HLT),
4474 _ER(INVLPG),
4475 _ER(RDPMC),
4476 _ER(RDTSC),
4477 _ER(VMCALL),
4478 _ER(VMCLEAR),
4479 _ER(VMLAUNCH),
4480 _ER(VMPTRLD),
4481 _ER(VMPTRST),
4482 _ER(VMREAD),
4483 _ER(VMRESUME),
4484 _ER(VMWRITE),
4485 _ER(VMOFF),
4486 _ER(VMON),
4487 _ER(CR_ACCESS),
4488 _ER(DR_ACCESS),
4489 _ER(IO_INSTRUCTION),
4490 _ER(MSR_READ),
4491 _ER(MSR_WRITE),
4492 _ER(MWAIT_INSTRUCTION),
4493 _ER(MONITOR_INSTRUCTION),
4494 _ER(PAUSE_INSTRUCTION),
4495 _ER(MCE_DURING_VMENTRY),
4496 _ER(TPR_BELOW_THRESHOLD),
4497 _ER(APIC_ACCESS),
4498 _ER(EPT_VIOLATION),
4499 _ER(EPT_MISCONFIG),
4500 _ER(WBINVD),
229456fc
MT		 4501 { -1, NULL }
4502};
4503
f4c9e87c
AK		 4504#undef _ER
4505
17cc3935 4506static int vmx_get_lpage_level(void)
344f414f 4507{
878403b7
SY		 4508 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4509 return PT_DIRECTORY_LEVEL;
4510 else
4511 /* For shadow and EPT supported 1GB page */
4512 return PT_PDPE_LEVEL;
344f414f
JR		 4513}
4514
0e851880
SY		 4515static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4516{
4e47c7a6
SY		 4517 struct kvm_cpuid_entry2 *best;
4518 struct vcpu_vmx *vmx = to_vmx(vcpu);
4519 u32 exec_control;
4520
4521 vmx->rdtscp_enabled = false;
4522 if (vmx_rdtscp_supported()) {
4523 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4524 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4525 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4526 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4527 vmx->rdtscp_enabled = true;
4528 else {
4529 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4530 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4531 exec_control);
4532 }
4533 }
4534 }
0e851880
SY		 4535}
4536
d4330ef2
JR		 4537static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4538{
4539}
4540
8a76d7f2
JR		 4541static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4542 struct x86_instruction_info *info,
4543 enum x86_intercept_stage stage)
4544{
4545 return X86EMUL_CONTINUE;
4546}
4547
cbdd1bea 4548static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4549 .cpu_has_kvm_support = cpu_has_kvm_support,
4550 .disabled_by_bios = vmx_disabled_by_bios,
4551 .hardware_setup = hardware_setup,
4552 .hardware_unsetup = hardware_unsetup,
002c7f7c 4553 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4554 .hardware_enable = hardware_enable,
4555 .hardware_disable = hardware_disable,
04547156 4556 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4557
4558 .vcpu_create = vmx_create_vcpu,
4559 .vcpu_free = vmx_free_vcpu,
04d2cc77 4560 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4561
04d2cc77 4562 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4563 .vcpu_load = vmx_vcpu_load,
4564 .vcpu_put = vmx_vcpu_put,
4565
4566 .set_guest_debug = set_guest_debug,
4567 .get_msr = vmx_get_msr,
4568 .set_msr = vmx_set_msr,
4569 .get_segment_base = vmx_get_segment_base,
4570 .get_segment = vmx_get_segment,
4571 .set_segment = vmx_set_segment,
2e4d2653 4572 .get_cpl = vmx_get_cpl,
6aa8b732 4573 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4574 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4575 .decache_cr3 = vmx_decache_cr3,
25c4c276 4576 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4577 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4578 .set_cr3 = vmx_set_cr3,
4579 .set_cr4 = vmx_set_cr4,
6aa8b732 4580 .set_efer = vmx_set_efer,
6aa8b732
AK		 4581 .get_idt = vmx_get_idt,
4582 .set_idt = vmx_set_idt,
4583 .get_gdt = vmx_get_gdt,
4584 .set_gdt = vmx_set_gdt,
020df079 4585 .set_dr7 = vmx_set_dr7,
5fdbf976 4586 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4587 .get_rflags = vmx_get_rflags,
4588 .set_rflags = vmx_set_rflags,
ebcbab4c 4589 .fpu_activate = vmx_fpu_activate,
02daab21 4590 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4591
4592 .tlb_flush = vmx_flush_tlb,
6aa8b732 4593
6aa8b732 4594 .run = vmx_vcpu_run,
6062d012 4595 .handle_exit = vmx_handle_exit,
6aa8b732 4596 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4597 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4598 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4599 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4600 .set_irq = vmx_inject_irq,
95ba8273 4601 .set_nmi = vmx_inject_nmi,
298101da 4602 .queue_exception = vmx_queue_exception,
b463a6f7 4603 .cancel_injection = vmx_cancel_injection,
78646121 4604 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4605 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4606 .get_nmi_mask = vmx_get_nmi_mask,
4607 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4608 .enable_nmi_window = enable_nmi_window,
4609 .enable_irq_window = enable_irq_window,
4610 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4611
cbc94022 4612 .set_tss_addr = vmx_set_tss_addr,
67253af5 4613 .get_tdp_level = get_ept_level,
4b12f0de 4614 .get_mt_mask = vmx_get_mt_mask,
229456fc 4615
586f9607 4616 .get_exit_info = vmx_get_exit_info,
229456fc 4617 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4618
17cc3935 4619 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4620
4621 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4622
4623 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4624
4625 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4626
4627 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 4628
4051b188 4629 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 4630 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4631 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 4632 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 4633
4634 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 4635
4636 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 4637};
4638
4639static int __init vmx_init(void)
4640{
26bb0981
AK		 4641 int r, i;
4642
4643 rdmsrl_safe(MSR_EFER, &host_efer);
4644
4645 for (i = 0; i < NR_VMX_MSR; ++i)
4646 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4647
3e7c73e9 4648 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4649 if (!vmx_io_bitmap_a)
4650 return -ENOMEM;
4651
3e7c73e9 4652 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4653 if (!vmx_io_bitmap_b) {
4654 r = -ENOMEM;
4655 goto out;
4656 }
4657
5897297b
AK		 4658 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4659 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4660 r = -ENOMEM;
4661 goto out1;
4662 }
4663
5897297b
AK		 4664 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4665 if (!vmx_msr_bitmap_longmode) {
4666 r = -ENOMEM;
4667 goto out2;
4668 }
4669
fdef3ad1
HQ		 4670 /*
4671 * Allow direct access to the PC debug port (it is often used for I/O
4672 * delays, but the vmexits simply slow things down).
4673 */
3e7c73e9
AK		 4674 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4675 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4676
3e7c73e9 4677 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4678
5897297b
AK		 4679 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4680 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4681
2384d2b3
SY		 4682 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4683
0ee75bea
AK		 4684 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4685 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4686 if (r)
5897297b 4687 goto out3;
25c5f225 4688
5897297b
AK		 4689 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4690 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4691 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4692 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4693 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4694 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4695
089d034e 4696 if (enable_ept) {
1439442c 4697 bypass_guest_pf = 0;
534e38b4 4698 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4699 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4700 kvm_enable_tdp();
4701 } else
4702 kvm_disable_tdp();
1439442c 4703
c7addb90
AK		 4704 if (bypass_guest_pf)
4705 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4706
fdef3ad1
HQ		 4707 return 0;
4708
5897297b
AK		 4709out3:
4710 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4711out2:
5897297b 4712 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4713out1:
3e7c73e9 4714 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4715out:
3e7c73e9 4716 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4717 return r;
6aa8b732
AK		 4718}
4719
4720static void __exit vmx_exit(void)
4721{
5897297b
AK		 4722 free_page((unsigned long)vmx_msr_bitmap_legacy);
4723 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4724 free_page((unsigned long)vmx_io_bitmap_b);
4725 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4726
cb498ea2 4727 kvm_exit();
6aa8b732
AK		 4728}
4729
4730module_init(vmx_init)
4731module_exit(vmx_exit)
Linux kernel - Deliverables
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