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KVM: nVMX: Correct handling of interrupt injection
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
61d2ef2c 121#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
fe3ef05c 348 u64 vmcs01_tsc_offset;
644d711a
NHE		 349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
fe3ef05c
NHE		 351 /*
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
354 */
355 struct page *apic_access_page;
ec378aee
NHE		 356};
357
a2fa3e9f 358struct vcpu_vmx {
fb3f0f51 359 struct kvm_vcpu vcpu;
313dbd49 360 unsigned long host_rsp;
29bd8a78 361 u8 fail;
69c73028 362 u8 cpl;
9d58b931 363 bool nmi_known_unmasked;
51aa01d1 364 u32 exit_intr_info;
1155f76a 365 u32 idt_vectoring_info;
6de12732 366 ulong rflags;
26bb0981 367 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 368 int nmsrs;
369 int save_nmsrs;
a2fa3e9f 370#ifdef CONFIG_X86_64
44ea2b17
AK		 371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
a2fa3e9f 373#endif
d462b819
NHE		 374 /*
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
378 */
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 382 struct msr_autoload {
383 unsigned nr;
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386 } msr_autoload;
a2fa3e9f
GH		 387 struct {
388 int loaded;
389 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
d77c26fc 392 } host_state;
9c8cba37 393 struct {
7ffd92c5 394 int vm86_active;
78ac8b47 395 ulong save_rflags;
7ffd92c5
AK		 396 struct kvm_save_segment {
397 u16 selector;
398 unsigned long base;
399 u32 limit;
400 u32 ar;
401 } tr, es, ds, fs, gs;
9c8cba37 402 } rmode;
2fb92db1
AK		 403 struct {
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
406 } segment_cache;
2384d2b3 407 int vpid;
04fa4d32 408 bool emulation_required;
3b86cd99
JK		 409
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
412 ktime_t entry_time;
413 s64 vnmi_blocked_time;
a0861c02 414 u32 exit_reason;
4e47c7a6
SY		 415
416 bool rdtscp_enabled;
ec378aee
NHE		 417
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
a2fa3e9f
GH		 420};
421
2fb92db1
AK		 422enum segment_cache_field {
423 SEG_FIELD_SEL = 0,
424 SEG_FIELD_BASE = 1,
425 SEG_FIELD_LIMIT = 2,
426 SEG_FIELD_AR = 3,
427
428 SEG_FIELD_NR = 4
429};
430
a2fa3e9f
GH		 431static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432{
fb3f0f51 433 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 434}
435
22bd0358
NHE		 436#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
569};
570static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572static inline short vmcs_field_to_offset(unsigned long field)
573{
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return -1;
576 return vmcs_field_to_offset_table[field];
577}
578
a9d30f33
NHE		 579static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580{
581 return to_vmx(vcpu)->nested.current_vmcs12;
582}
583
584static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585{
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
589 return NULL;
590 }
591 return page;
592}
593
594static void nested_release_page(struct page *page)
595{
596 kvm_release_page_dirty(page);
597}
598
599static void nested_release_page_clean(struct page *page)
600{
601 kvm_release_page_clean(page);
602}
603
4e1096d2 604static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 605static void kvm_cpu_vmxon(u64 addr);
606static void kvm_cpu_vmxoff(void);
aff48baa 607static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 609
6aa8b732
AK		 610static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 612/*
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 */
616static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 617static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 618
3e7c73e9
AK		 619static unsigned long *vmx_io_bitmap_a;
620static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 621static unsigned long *vmx_msr_bitmap_legacy;
622static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 623
110312c8
AK		 624static bool cpu_has_load_ia32_efer;
625
2384d2b3
SY		 626static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627static DEFINE_SPINLOCK(vmx_vpid_lock);
628
1c3d14fe 629static struct vmcs_config {
6aa8b732
AK		 630 int size;
631 int order;
632 u32 revision_id;
1c3d14fe
YS		 633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
f78e0e2e 635 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 636 u32 vmexit_ctrl;
637 u32 vmentry_ctrl;
638} vmcs_config;
6aa8b732 639
efff9e53 640static struct vmx_capability {
d56f546d
SY		 641 u32 ept;
642 u32 vpid;
643} vmx_capability;
644
6aa8b732
AK		 645#define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
651 }
652
653static struct kvm_vmx_segment_field {
654 unsigned selector;
655 unsigned base;
656 unsigned limit;
657 unsigned ar_bytes;
658} kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
667};
668
26bb0981
AK		 669static u64 host_efer;
670
6de4f3ad
AK		 671static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
4d56c8a7 673/*
8c06585d 674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 675 * away by decrementing the array size.
676 */
6aa8b732 677static const u32 vmx_msr_index[] = {
05b3e0c2 678#ifdef CONFIG_X86_64
44ea2b17 679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 680#endif
8c06585d 681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 682};
9d8f549d 683#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 684
31299944 685static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 686{
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 690}
691
31299944 692static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 693{
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 697}
698
31299944 699static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 700{
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 704}
705
31299944 706static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710}
711
31299944 712static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 713{
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717}
718
31299944 719static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 720{
04547156 721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 722}
723
31299944 724static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 725{
04547156 726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 727}
728
31299944 729static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 730{
04547156 731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 732}
733
31299944 734static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 735{
04547156
SY		 736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 738}
739
774ead3a 740static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 741{
04547156
SY		 742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744}
745
746static inline bool cpu_has_vmx_flexpriority(void)
747{
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 750}
751
e799794e
MT		 752static inline bool cpu_has_vmx_ept_execute_only(void)
753{
31299944 754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 755}
756
757static inline bool cpu_has_vmx_eptp_uncacheable(void)
758{
31299944 759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 760}
761
762static inline bool cpu_has_vmx_eptp_writeback(void)
763{
31299944 764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 765}
766
767static inline bool cpu_has_vmx_ept_2m_page(void)
768{
31299944 769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 770}
771
878403b7
SY		 772static inline bool cpu_has_vmx_ept_1g_page(void)
773{
31299944 774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 775}
776
4bc9b982
SY		 777static inline bool cpu_has_vmx_ept_4levels(void)
778{
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780}
781
31299944 782static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 783{
31299944 784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 785}
786
31299944 787static inline bool cpu_has_vmx_invept_context(void)
d56f546d 788{
31299944 789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 790}
791
31299944 792static inline bool cpu_has_vmx_invept_global(void)
d56f546d 793{
31299944 794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 795}
796
518c8aee
GJ		 797static inline bool cpu_has_vmx_invvpid_single(void)
798{
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800}
801
b9d762fa
GJ		 802static inline bool cpu_has_vmx_invvpid_global(void)
803{
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805}
806
31299944 807static inline bool cpu_has_vmx_ept(void)
d56f546d 808{
04547156
SY		 809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 814{
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817}
818
31299944 819static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 820{
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823}
824
31299944 825static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 826{
6d3e435e 827 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 828}
829
31299944 830static inline bool cpu_has_vmx_vpid(void)
2384d2b3 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
840}
841
31299944 842static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 843{
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845}
846
f5f48ee1
SY		 847static inline bool cpu_has_vmx_wbinvd_exit(void)
848{
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
851}
852
04547156
SY		 853static inline bool report_flexpriority(void)
854{
855 return flexpriority_enabled;
856}
857
fe3ef05c
NHE		 858static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859{
860 return vmcs12->cpu_based_vm_exec_control & bit;
861}
862
863static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864{
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
868}
869
644d711a
NHE		 870static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
872{
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874}
875
876static inline bool is_exception(u32 intr_info)
877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880}
881
882static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 883static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
886
8b9cf98c 887static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 888{
889 int i;
890
a2fa3e9f 891 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 893 return i;
894 return -1;
895}
896
2384d2b3
SY		 897static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898{
899 struct {
900 u64 vpid : 16;
901 u64 rsvd : 48;
902 u64 gva;
903 } operand = { vpid, 0, gva };
904
4ecac3fd 905 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 906 /* CF==1 or ZF==1 --> rc = -1 */
907 "; ja 1f ; ud2 ; 1:"
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
909}
910
1439442c
SY		 911static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912{
913 struct {
914 u64 eptp, gpa;
915 } operand = {eptp, gpa};
916
4ecac3fd 917 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
921}
922
26bb0981 923static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 924{
925 int i;
926
8b9cf98c 927 i = __find_msr_index(vmx, msr);
a75beee6 928 if (i >= 0)
a2fa3e9f 929 return &vmx->guest_msrs[i];
8b6d44c7 930 return NULL;
7725f0ba
AK		 931}
932
6aa8b732
AK		 933static void vmcs_clear(struct vmcs *vmcs)
934{
935 u64 phys_addr = __pa(vmcs);
936 u8 error;
937
4ecac3fd 938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 940 : "cc", "memory");
941 if (error)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943 vmcs, phys_addr);
944}
945
d462b819
NHE		 946static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947{
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
951}
952
7725b894
DX		 953static void vmcs_load(struct vmcs *vmcs)
954{
955 u64 phys_addr = __pa(vmcs);
956 u8 error;
957
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 960 : "cc", "memory");
961 if (error)
962 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
963 vmcs, phys_addr);
964}
965
d462b819 966static void __loaded_vmcs_clear(void *arg)
6aa8b732 967{
d462b819 968 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 969 int cpu = raw_smp_processor_id();
6aa8b732 970
d462b819
NHE		 971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 974 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 977}
978
d462b819 979static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 980{
d462b819
NHE		 981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 984}
985
1760dd49 986static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 987{
988 if (vmx->vpid == 0)
989 return;
990
518c8aee
GJ		 991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 993}
994
b9d762fa
GJ		 995static inline void vpid_sync_vcpu_global(void)
996{
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999}
1000
1001static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002{
1003 if (cpu_has_vmx_invvpid_single())
1760dd49 1004 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1005 else
1006 vpid_sync_vcpu_global();
1007}
1008
1439442c
SY		 1009static inline void ept_sync_global(void)
1010{
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013}
1014
1015static inline void ept_sync_context(u64 eptp)
1016{
089d034e 1017 if (enable_ept) {
1439442c
SY		 1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020 else
1021 ept_sync_global();
1022 }
1023}
1024
1025static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026{
089d034e 1027 if (enable_ept) {
1439442c
SY		 1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030 eptp, gpa);
1031 else
1032 ept_sync_context(eptp);
1033 }
1034}
1035
96304217 1036static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1037{
5e520e62 1038 unsigned long value;
6aa8b732 1039
5e520e62
AK		 1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1042 return value;
1043}
1044
96304217 1045static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1046{
1047 return vmcs_readl(field);
1048}
1049
96304217 1050static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1051{
1052 return vmcs_readl(field);
1053}
1054
96304217 1055static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1056{
05b3e0c2 1057#ifdef CONFIG_X86_64
6aa8b732
AK		 1058 return vmcs_readl(field);
1059#else
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061#endif
1062}
1063
e52de1b8
AK		 1064static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065{
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068 dump_stack();
1069}
1070
6aa8b732
AK		 1071static void vmcs_writel(unsigned long field, unsigned long value)
1072{
1073 u8 error;
1074
4ecac3fd 1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1077 if (unlikely(error))
1078 vmwrite_error(field, value);
6aa8b732
AK		 1079}
1080
1081static void vmcs_write16(unsigned long field, u16 value)
1082{
1083 vmcs_writel(field, value);
1084}
1085
1086static void vmcs_write32(unsigned long field, u32 value)
1087{
1088 vmcs_writel(field, value);
1089}
1090
1091static void vmcs_write64(unsigned long field, u64 value)
1092{
6aa8b732 1093 vmcs_writel(field, value);
7682f2d0 1094#ifndef CONFIG_X86_64
6aa8b732
AK		 1095 asm volatile ("");
1096 vmcs_writel(field+1, value >> 32);
1097#endif
1098}
1099
2ab455cc
AL		 1100static void vmcs_clear_bits(unsigned long field, u32 mask)
1101{
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1103}
1104
1105static void vmcs_set_bits(unsigned long field, u32 mask)
1106{
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1108}
1109
2fb92db1
AK		 1110static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111{
1112 vmx->segment_cache.bitmask = 0;
1113}
1114
1115static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116 unsigned field)
1117{
1118 bool ret;
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1124 }
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1127 return ret;
1128}
1129
1130static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131{
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136 return *p;
1137}
1138
1139static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140{
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145 return *p;
1146}
1147
1148static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149{
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154 return *p;
1155}
1156
1157static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163 return *p;
1164}
1165
abd3f2d6
AK		 1166static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167{
1168 u32 eb;
1169
fd7373cc
JK		 1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
7ffd92c5 1176 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1177 eb = ~0;
089d034e 1178 if (enable_ept)
1439442c 1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 1182 vmcs_write32(EXCEPTION_BITMAP, eb);
1183}
1184
61d2ef2c
AK		 1185static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1186{
1187 unsigned i;
1188 struct msr_autoload *m = &vmx->msr_autoload;
1189
110312c8
AK		 1190 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1191 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1192 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1193 return;
1194 }
1195
61d2ef2c
AK		 1196 for (i = 0; i < m->nr; ++i)
1197 if (m->guest[i].index == msr)
1198 break;
1199
1200 if (i == m->nr)
1201 return;
1202 --m->nr;
1203 m->guest[i] = m->guest[m->nr];
1204 m->host[i] = m->host[m->nr];
1205 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1206 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1207}
1208
1209static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1210 u64 guest_val, u64 host_val)
1211{
1212 unsigned i;
1213 struct msr_autoload *m = &vmx->msr_autoload;
1214
110312c8
AK		 1215 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1216 vmcs_write64(GUEST_IA32_EFER, guest_val);
1217 vmcs_write64(HOST_IA32_EFER, host_val);
1218 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1219 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1220 return;
1221 }
1222
61d2ef2c
AK		 1223 for (i = 0; i < m->nr; ++i)
1224 if (m->guest[i].index == msr)
1225 break;
1226
1227 if (i == m->nr) {
1228 ++m->nr;
1229 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1230 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1231 }
1232
1233 m->guest[i].index = msr;
1234 m->guest[i].value = guest_val;
1235 m->host[i].index = msr;
1236 m->host[i].value = host_val;
1237}
1238
33ed6329
AK		 1239static void reload_tss(void)
1240{
33ed6329
AK		 1241 /*
1242 * VT restores TR but not its size. Useless.
1243 */
d359192f 1244 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1245 struct desc_struct *descs;
33ed6329 1246
d359192f 1247 descs = (void *)gdt->address;
33ed6329
AK		 1248 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1249 load_TR_desc();
33ed6329
AK		 1250}
1251
92c0d900 1252static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1253{
3a34a881 1254 u64 guest_efer;
51c6cf66
AK		 1255 u64 ignore_bits;
1256
f6801dff 1257 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1258
51c6cf66
AK		 1259 /*
1260 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1261 * outside long mode
1262 */
1263 ignore_bits = EFER_NX | EFER_SCE;
1264#ifdef CONFIG_X86_64
1265 ignore_bits |= EFER_LMA | EFER_LME;
1266 /* SCE is meaningful only in long mode on Intel */
1267 if (guest_efer & EFER_LMA)
1268 ignore_bits &= ~(u64)EFER_SCE;
1269#endif
51c6cf66
AK		 1270 guest_efer &= ~ignore_bits;
1271 guest_efer |= host_efer & ignore_bits;
26bb0981 1272 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1273 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1274
1275 clear_atomic_switch_msr(vmx, MSR_EFER);
1276 /* On ept, can't emulate nx, and must switch nx atomically */
1277 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1278 guest_efer = vmx->vcpu.arch.efer;
1279 if (!(guest_efer & EFER_LMA))
1280 guest_efer &= ~EFER_LME;
1281 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1282 return false;
1283 }
1284
26bb0981 1285 return true;
51c6cf66
AK		 1286}
1287
2d49ec72
GN		 1288static unsigned long segment_base(u16 selector)
1289{
d359192f 1290 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1291 struct desc_struct *d;
1292 unsigned long table_base;
1293 unsigned long v;
1294
1295 if (!(selector & ~3))
1296 return 0;
1297
d359192f 1298 table_base = gdt->address;
2d49ec72
GN		 1299
1300 if (selector & 4) { /* from ldt */
1301 u16 ldt_selector = kvm_read_ldt();
1302
1303 if (!(ldt_selector & ~3))
1304 return 0;
1305
1306 table_base = segment_base(ldt_selector);
1307 }
1308 d = (struct desc_struct *)(table_base + (selector & ~7));
1309 v = get_desc_base(d);
1310#ifdef CONFIG_X86_64
1311 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1312 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1313#endif
1314 return v;
1315}
1316
1317static inline unsigned long kvm_read_tr_base(void)
1318{
1319 u16 tr;
1320 asm("str %0" : "=g"(tr));
1321 return segment_base(tr);
1322}
1323
04d2cc77 1324static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1325{
04d2cc77 1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1327 int i;
04d2cc77 1328
a2fa3e9f 1329 if (vmx->host_state.loaded)
33ed6329
AK		 1330 return;
1331
a2fa3e9f 1332 vmx->host_state.loaded = 1;
33ed6329
AK		 1333 /*
1334 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1335 * allow segment selectors with cpl > 0 or ti == 1.
1336 */
d6e88aec 1337 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1338 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1339 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1340 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1341 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1342 vmx->host_state.fs_reload_needed = 0;
1343 } else {
33ed6329 1344 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1345 vmx->host_state.fs_reload_needed = 1;
33ed6329 1346 }
9581d442 1347 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1348 if (!(vmx->host_state.gs_sel & 7))
1349 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1350 else {
1351 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1352 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1353 }
1354
1355#ifdef CONFIG_X86_64
1356 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1357 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1358#else
a2fa3e9f
GH		 1359 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1360 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1361#endif
707c0874
AK		 1362
1363#ifdef CONFIG_X86_64
c8770e7b
AK		 1364 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1365 if (is_long_mode(&vmx->vcpu))
44ea2b17 1366 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1367#endif
26bb0981
AK		 1368 for (i = 0; i < vmx->save_nmsrs; ++i)
1369 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1370 vmx->guest_msrs[i].data,
1371 vmx->guest_msrs[i].mask);
33ed6329
AK		 1372}
1373
a9b21b62 1374static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1375{
a2fa3e9f 1376 if (!vmx->host_state.loaded)
33ed6329
AK		 1377 return;
1378
e1beb1d3 1379 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1380 vmx->host_state.loaded = 0;
c8770e7b
AK		 1381#ifdef CONFIG_X86_64
1382 if (is_long_mode(&vmx->vcpu))
1383 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1384#endif
152d3f2f 1385 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1386 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1387#ifdef CONFIG_X86_64
9581d442 1388 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1389#else
1390 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1391#endif
33ed6329 1392 }
0a77fe4c
AK		 1393 if (vmx->host_state.fs_reload_needed)
1394 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1395 reload_tss();
44ea2b17 1396#ifdef CONFIG_X86_64
c8770e7b 1397 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1398#endif
1c11e713
AK		 1399 if (current_thread_info()->status & TS_USEDFPU)
1400 clts();
3444d7da 1401 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1402}
1403
a9b21b62
AK		 1404static void vmx_load_host_state(struct vcpu_vmx *vmx)
1405{
1406 preempt_disable();
1407 __vmx_load_host_state(vmx);
1408 preempt_enable();
1409}
1410
6aa8b732
AK		 1411/*
1412 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1413 * vcpu mutex is already taken.
1414 */
15ad7146 1415static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1416{
a2fa3e9f 1417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1418 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1419
4610c9cc
DX		 1420 if (!vmm_exclusive)
1421 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1422 else if (vmx->loaded_vmcs->cpu != cpu)
1423 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1424
d462b819
NHE		 1425 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1426 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1427 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1428 }
1429
d462b819 1430 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1431 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1432 unsigned long sysenter_esp;
1433
a8eeb04a 1434 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1435 local_irq_disable();
d462b819
NHE		 1436 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1437 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1438 local_irq_enable();
1439
6aa8b732
AK		 1440 /*
1441 * Linux uses per-cpu TSS and GDT, so set these when switching
1442 * processors.
1443 */
d6e88aec 1444 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1445 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1446
1447 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1448 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1449 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1450 }
6aa8b732
AK		 1451}
1452
1453static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1454{
a9b21b62 1455 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1456 if (!vmm_exclusive) {
d462b819
NHE		 1457 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1458 vcpu->cpu = -1;
4610c9cc
DX		 1459 kvm_cpu_vmxoff();
1460 }
6aa8b732
AK		 1461}
1462
5fd86fcf
AK		 1463static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1464{
81231c69
AK		 1465 ulong cr0;
1466
5fd86fcf
AK		 1467 if (vcpu->fpu_active)
1468 return;
1469 vcpu->fpu_active = 1;
81231c69
AK		 1470 cr0 = vmcs_readl(GUEST_CR0);
1471 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1472 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1473 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1474 update_exception_bitmap(vcpu);
edcafe3c
AK		 1475 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1476 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1477}
1478
edcafe3c
AK		 1479static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1480
fe3ef05c
NHE		 1481/*
1482 * Return the cr0 value that a nested guest would read. This is a combination
1483 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1484 * its hypervisor (cr0_read_shadow).
1485 */
1486static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1487{
1488 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1489 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1490}
1491static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1492{
1493 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1494 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1495}
1496
5fd86fcf
AK		 1497static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1498{
edcafe3c 1499 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1500 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1501 update_exception_bitmap(vcpu);
edcafe3c
AK		 1502 vcpu->arch.cr0_guest_owned_bits = 0;
1503 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1504 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1505}
1506
6aa8b732
AK		 1507static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1508{
78ac8b47 1509 unsigned long rflags, save_rflags;
345dcaa8 1510
6de12732
AK		 1511 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1512 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1513 rflags = vmcs_readl(GUEST_RFLAGS);
1514 if (to_vmx(vcpu)->rmode.vm86_active) {
1515 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1516 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1517 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1518 }
1519 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1520 }
6de12732 1521 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1522}
1523
1524static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1525{
6de12732 1526 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1527 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1528 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1529 if (to_vmx(vcpu)->rmode.vm86_active) {
1530 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1531 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1532 }
6aa8b732
AK		 1533 vmcs_writel(GUEST_RFLAGS, rflags);
1534}
1535
2809f5d2
GC		 1536static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1537{
1538 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1539 int ret = 0;
1540
1541 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1542 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1543 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1544 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1545
1546 return ret & mask;
1547}
1548
1549static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1550{
1551 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1552 u32 interruptibility = interruptibility_old;
1553
1554 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1555
48005f64 1556 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1557 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1558 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1559 interruptibility |= GUEST_INTR_STATE_STI;
1560
1561 if ((interruptibility != interruptibility_old))
1562 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1563}
1564
6aa8b732
AK		 1565static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1566{
1567 unsigned long rip;
6aa8b732 1568
5fdbf976 1569 rip = kvm_rip_read(vcpu);
6aa8b732 1570 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1571 kvm_rip_write(vcpu, rip);
6aa8b732 1572
2809f5d2
GC		 1573 /* skipping an emulated instruction also counts */
1574 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1575}
1576
443381a8
AL		 1577static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1578{
1579 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1580 * explicitly skip the instruction because if the HLT state is set, then
1581 * the instruction is already executing and RIP has already been
1582 * advanced. */
1583 if (!yield_on_hlt &&
1584 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1585 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1586}
1587
298101da 1588static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1589 bool has_error_code, u32 error_code,
1590 bool reinject)
298101da 1591{
77ab6db0 1592 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1593 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1594
8ab2d2e2 1595 if (has_error_code) {
77ab6db0 1596 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1597 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1598 }
77ab6db0 1599
7ffd92c5 1600 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1601 int inc_eip = 0;
1602 if (kvm_exception_is_soft(nr))
1603 inc_eip = vcpu->arch.event_exit_inst_len;
1604 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1605 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1606 return;
1607 }
1608
66fd3f7f
GN		 1609 if (kvm_exception_is_soft(nr)) {
1610 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1611 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1612 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1613 } else
1614 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1615
1616 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1617 vmx_clear_hlt(vcpu);
298101da
AK		 1618}
1619
4e47c7a6
SY		 1620static bool vmx_rdtscp_supported(void)
1621{
1622 return cpu_has_vmx_rdtscp();
1623}
1624
a75beee6
ED		 1625/*
1626 * Swap MSR entry in host/guest MSR entry array.
1627 */
8b9cf98c 1628static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1629{
26bb0981 1630 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1631
1632 tmp = vmx->guest_msrs[to];
1633 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1634 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1635}
1636
e38aea3e
AK		 1637/*
1638 * Set up the vmcs to automatically save and restore system
1639 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1640 * mode, as fiddling with msrs is very expensive.
1641 */
8b9cf98c 1642static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1643{
26bb0981 1644 int save_nmsrs, index;
5897297b 1645 unsigned long *msr_bitmap;
e38aea3e 1646
33f9c505 1647 vmx_load_host_state(vmx);
a75beee6
ED		 1648 save_nmsrs = 0;
1649#ifdef CONFIG_X86_64
8b9cf98c 1650 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1651 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1652 if (index >= 0)
8b9cf98c
RR		 1653 move_msr_up(vmx, index, save_nmsrs++);
1654 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1655 if (index >= 0)
8b9cf98c
RR		 1656 move_msr_up(vmx, index, save_nmsrs++);
1657 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1658 if (index >= 0)
8b9cf98c 1659 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1660 index = __find_msr_index(vmx, MSR_TSC_AUX);
1661 if (index >= 0 && vmx->rdtscp_enabled)
1662 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1663 /*
8c06585d 1664 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1665 * if efer.sce is enabled.
1666 */
8c06585d 1667 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1668 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1669 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1670 }
1671#endif
92c0d900
AK		 1672 index = __find_msr_index(vmx, MSR_EFER);
1673 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1674 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1675
26bb0981 1676 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1677
1678 if (cpu_has_vmx_msr_bitmap()) {
1679 if (is_long_mode(&vmx->vcpu))
1680 msr_bitmap = vmx_msr_bitmap_longmode;
1681 else
1682 msr_bitmap = vmx_msr_bitmap_legacy;
1683
1684 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1685 }
e38aea3e
AK		 1686}
1687
6aa8b732
AK		 1688/*
1689 * reads and returns guest's timestamp counter "register"
1690 * guest_tsc = host_tsc + tsc_offset -- 21.3
1691 */
1692static u64 guest_read_tsc(void)
1693{
1694 u64 host_tsc, tsc_offset;
1695
1696 rdtscll(host_tsc);
1697 tsc_offset = vmcs_read64(TSC_OFFSET);
1698 return host_tsc + tsc_offset;
1699}
1700
4051b188
JR		 1701/*
1702 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1703 * ioctl. In this case the call-back should update internal vmx state to make
1704 * the changes effective.
1705 */
1706static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1707{
1708 /* Nothing to do here */
1709}
1710
6aa8b732 1711/*
99e3e30a 1712 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1713 */
99e3e30a 1714static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1715{
f4e1b3c8 1716 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1717}
1718
e48672fa
ZA		 1719static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1720{
1721 u64 offset = vmcs_read64(TSC_OFFSET);
1722 vmcs_write64(TSC_OFFSET, offset + adjustment);
1723}
1724
857e4099
JR		 1725static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1726{
1727 return target_tsc - native_read_tsc();
1728}
1729
801d3424
NHE		 1730static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1731{
1732 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1733 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1734}
1735
1736/*
1737 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1738 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1739 * all guests if the "nested" module option is off, and can also be disabled
1740 * for a single guest by disabling its VMX cpuid bit.
1741 */
1742static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1743{
1744 return nested && guest_cpuid_has_vmx(vcpu);
1745}
1746
b87a51ae
NHE		 1747/*
1748 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1749 * returned for the various VMX controls MSRs when nested VMX is enabled.
1750 * The same values should also be used to verify that vmcs12 control fields are
1751 * valid during nested entry from L1 to L2.
1752 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1753 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1754 * bit in the high half is on if the corresponding bit in the control field
1755 * may be on. See also vmx_control_verify().
1756 * TODO: allow these variables to be modified (downgraded) by module options
1757 * or other means.
1758 */
1759static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1760static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1761static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1762static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1763static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1764static __init void nested_vmx_setup_ctls_msrs(void)
1765{
1766 /*
1767 * Note that as a general rule, the high half of the MSRs (bits in
1768 * the control fields which may be 1) should be initialized by the
1769 * intersection of the underlying hardware's MSR (i.e., features which
1770 * can be supported) and the list of features we want to expose -
1771 * because they are known to be properly supported in our code.
1772 * Also, usually, the low half of the MSRs (bits which must be 1) can
1773 * be set to 0, meaning that L1 may turn off any of these bits. The
1774 * reason is that if one of these bits is necessary, it will appear
1775 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1776 * fields of vmcs01 and vmcs02, will turn these bits off - and
1777 * nested_vmx_exit_handled() will not pass related exits to L1.
1778 * These rules have exceptions below.
1779 */
1780
1781 /* pin-based controls */
1782 /*
1783 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1784 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1785 */
1786 nested_vmx_pinbased_ctls_low = 0x16 ;
1787 nested_vmx_pinbased_ctls_high = 0x16 |
1788 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1789 PIN_BASED_VIRTUAL_NMIS;
1790
1791 /* exit controls */
1792 nested_vmx_exit_ctls_low = 0;
b6f1250e 1793 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1794#ifdef CONFIG_X86_64
1795 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1796#else
1797 nested_vmx_exit_ctls_high = 0;
1798#endif
1799
1800 /* entry controls */
1801 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1802 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1803 nested_vmx_entry_ctls_low = 0;
1804 nested_vmx_entry_ctls_high &=
1805 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1806
1807 /* cpu-based controls */
1808 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1809 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1810 nested_vmx_procbased_ctls_low = 0;
1811 nested_vmx_procbased_ctls_high &=
1812 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1813 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1814 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1815 CPU_BASED_CR3_STORE_EXITING |
1816#ifdef CONFIG_X86_64
1817 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1818#endif
1819 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1820 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1821 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1822 /*
1823 * We can allow some features even when not supported by the
1824 * hardware. For example, L1 can specify an MSR bitmap - and we
1825 * can use it to avoid exits to L1 - even when L0 runs L2
1826 * without MSR bitmaps.
1827 */
1828 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1829
1830 /* secondary cpu-based controls */
1831 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1832 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1833 nested_vmx_secondary_ctls_low = 0;
1834 nested_vmx_secondary_ctls_high &=
1835 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1836}
1837
1838static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1839{
1840 /*
1841 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1842 */
1843 return ((control & high) | low) == control;
1844}
1845
1846static inline u64 vmx_control_msr(u32 low, u32 high)
1847{
1848 return low | ((u64)high << 32);
1849}
1850
1851/*
1852 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1853 * also let it use VMX-specific MSRs.
1854 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1855 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1856 * like all other MSRs).
1857 */
1858static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1859{
1860 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1861 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1862 /*
1863 * According to the spec, processors which do not support VMX
1864 * should throw a #GP(0) when VMX capability MSRs are read.
1865 */
1866 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1867 return 1;
1868 }
1869
1870 switch (msr_index) {
1871 case MSR_IA32_FEATURE_CONTROL:
1872 *pdata = 0;
1873 break;
1874 case MSR_IA32_VMX_BASIC:
1875 /*
1876 * This MSR reports some information about VMX support. We
1877 * should return information about the VMX we emulate for the
1878 * guest, and the VMCS structure we give it - not about the
1879 * VMX support of the underlying hardware.
1880 */
1881 *pdata = VMCS12_REVISION |
1882 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1883 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1884 break;
1885 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1886 case MSR_IA32_VMX_PINBASED_CTLS:
1887 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1888 nested_vmx_pinbased_ctls_high);
1889 break;
1890 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1891 case MSR_IA32_VMX_PROCBASED_CTLS:
1892 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1893 nested_vmx_procbased_ctls_high);
1894 break;
1895 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1896 case MSR_IA32_VMX_EXIT_CTLS:
1897 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1898 nested_vmx_exit_ctls_high);
1899 break;
1900 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1901 case MSR_IA32_VMX_ENTRY_CTLS:
1902 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1903 nested_vmx_entry_ctls_high);
1904 break;
1905 case MSR_IA32_VMX_MISC:
1906 *pdata = 0;
1907 break;
1908 /*
1909 * These MSRs specify bits which the guest must keep fixed (on or off)
1910 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1911 * We picked the standard core2 setting.
1912 */
1913#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1914#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1915 case MSR_IA32_VMX_CR0_FIXED0:
1916 *pdata = VMXON_CR0_ALWAYSON;
1917 break;
1918 case MSR_IA32_VMX_CR0_FIXED1:
1919 *pdata = -1ULL;
1920 break;
1921 case MSR_IA32_VMX_CR4_FIXED0:
1922 *pdata = VMXON_CR4_ALWAYSON;
1923 break;
1924 case MSR_IA32_VMX_CR4_FIXED1:
1925 *pdata = -1ULL;
1926 break;
1927 case MSR_IA32_VMX_VMCS_ENUM:
1928 *pdata = 0x1f;
1929 break;
1930 case MSR_IA32_VMX_PROCBASED_CTLS2:
1931 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1932 nested_vmx_secondary_ctls_high);
1933 break;
1934 case MSR_IA32_VMX_EPT_VPID_CAP:
1935 /* Currently, no nested ept or nested vpid */
1936 *pdata = 0;
1937 break;
1938 default:
1939 return 0;
1940 }
1941
1942 return 1;
1943}
1944
1945static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1946{
1947 if (!nested_vmx_allowed(vcpu))
1948 return 0;
1949
1950 if (msr_index == MSR_IA32_FEATURE_CONTROL)
1951 /* TODO: the right thing. */
1952 return 1;
1953 /*
1954 * No need to treat VMX capability MSRs specially: If we don't handle
1955 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1956 */
1957 return 0;
1958}
1959
6aa8b732
AK		 1960/*
1961 * Reads an msr value (of 'msr_index') into 'pdata'.
1962 * Returns 0 on success, non-0 otherwise.
1963 * Assumes vcpu_load() was already called.
1964 */
1965static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1966{
1967 u64 data;
26bb0981 1968 struct shared_msr_entry *msr;
6aa8b732
AK		 1969
1970 if (!pdata) {
1971 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1972 return -EINVAL;
1973 }
1974
1975 switch (msr_index) {
05b3e0c2 1976#ifdef CONFIG_X86_64
6aa8b732
AK		 1977 case MSR_FS_BASE:
1978 data = vmcs_readl(GUEST_FS_BASE);
1979 break;
1980 case MSR_GS_BASE:
1981 data = vmcs_readl(GUEST_GS_BASE);
1982 break;
44ea2b17
AK		 1983 case MSR_KERNEL_GS_BASE:
1984 vmx_load_host_state(to_vmx(vcpu));
1985 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1986 break;
26bb0981 1987#endif
6aa8b732 1988 case MSR_EFER:
3bab1f5d 1989 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1990 case MSR_IA32_TSC:
6aa8b732
AK		 1991 data = guest_read_tsc();
1992 break;
1993 case MSR_IA32_SYSENTER_CS:
1994 data = vmcs_read32(GUEST_SYSENTER_CS);
1995 break;
1996 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1997 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1998 break;
1999 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2000 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2001 break;
4e47c7a6
SY		 2002 case MSR_TSC_AUX:
2003 if (!to_vmx(vcpu)->rdtscp_enabled)
2004 return 1;
2005 /* Otherwise falls through */
6aa8b732 2006 default:
26bb0981 2007 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2008 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2009 return 0;
8b9cf98c 2010 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2011 if (msr) {
542423b0 2012 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2013 data = msr->data;
2014 break;
6aa8b732 2015 }
3bab1f5d 2016 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2017 }
2018
2019 *pdata = data;
2020 return 0;
2021}
2022
2023/*
2024 * Writes msr value into into the appropriate "register".
2025 * Returns 0 on success, non-0 otherwise.
2026 * Assumes vcpu_load() was already called.
2027 */
2028static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2029{
a2fa3e9f 2030 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2031 struct shared_msr_entry *msr;
2cc51560
ED		 2032 int ret = 0;
2033
6aa8b732 2034 switch (msr_index) {
3bab1f5d 2035 case MSR_EFER:
a9b21b62 2036 vmx_load_host_state(vmx);
2cc51560 2037 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2038 break;
16175a79 2039#ifdef CONFIG_X86_64
6aa8b732 2040 case MSR_FS_BASE:
2fb92db1 2041 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2042 vmcs_writel(GUEST_FS_BASE, data);
2043 break;
2044 case MSR_GS_BASE:
2fb92db1 2045 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2046 vmcs_writel(GUEST_GS_BASE, data);
2047 break;
44ea2b17
AK		 2048 case MSR_KERNEL_GS_BASE:
2049 vmx_load_host_state(vmx);
2050 vmx->msr_guest_kernel_gs_base = data;
2051 break;
6aa8b732
AK		 2052#endif
2053 case MSR_IA32_SYSENTER_CS:
2054 vmcs_write32(GUEST_SYSENTER_CS, data);
2055 break;
2056 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2057 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2058 break;
2059 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2060 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2061 break;
af24a4e4 2062 case MSR_IA32_TSC:
99e3e30a 2063 kvm_write_tsc(vcpu, data);
6aa8b732 2064 break;
468d472f
SY		 2065 case MSR_IA32_CR_PAT:
2066 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2067 vmcs_write64(GUEST_IA32_PAT, data);
2068 vcpu->arch.pat = data;
2069 break;
2070 }
4e47c7a6
SY		 2071 ret = kvm_set_msr_common(vcpu, msr_index, data);
2072 break;
2073 case MSR_TSC_AUX:
2074 if (!vmx->rdtscp_enabled)
2075 return 1;
2076 /* Check reserved bit, higher 32 bits should be zero */
2077 if ((data >> 32) != 0)
2078 return 1;
2079 /* Otherwise falls through */
6aa8b732 2080 default:
b87a51ae
NHE		 2081 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2082 break;
8b9cf98c 2083 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2084 if (msr) {
542423b0 2085 vmx_load_host_state(vmx);
3bab1f5d
AK		 2086 msr->data = data;
2087 break;
6aa8b732 2088 }
2cc51560 2089 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2090 }
2091
2cc51560 2092 return ret;
6aa8b732
AK		 2093}
2094
5fdbf976 2095static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2096{
5fdbf976
MT		 2097 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2098 switch (reg) {
2099 case VCPU_REGS_RSP:
2100 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2101 break;
2102 case VCPU_REGS_RIP:
2103 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2104 break;
6de4f3ad
AK		 2105 case VCPU_EXREG_PDPTR:
2106 if (enable_ept)
2107 ept_save_pdptrs(vcpu);
2108 break;
5fdbf976
MT		 2109 default:
2110 break;
2111 }
6aa8b732
AK		 2112}
2113
355be0b9 2114static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2115{
ae675ef0
JK		 2116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2117 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2118 else
2119 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2120
abd3f2d6 2121 update_exception_bitmap(vcpu);
6aa8b732
AK		 2122}
2123
2124static __init int cpu_has_kvm_support(void)
2125{
6210e37b 2126 return cpu_has_vmx();
6aa8b732
AK		 2127}
2128
2129static __init int vmx_disabled_by_bios(void)
2130{
2131 u64 msr;
2132
2133 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2134 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2135 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2136 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2137 && tboot_enabled())
2138 return 1;
23f3e991 2139 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2140 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2141 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2142 && !tboot_enabled()) {
2143 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2144 "activate TXT before enabling KVM\n");
cafd6659 2145 return 1;
f9335afe 2146 }
23f3e991
JC		 2147 /* launched w/o TXT and VMX disabled */
2148 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2149 && !tboot_enabled())
2150 return 1;
cafd6659
SW		 2151 }
2152
2153 return 0;
6aa8b732
AK		 2154}
2155
7725b894
DX		 2156static void kvm_cpu_vmxon(u64 addr)
2157{
2158 asm volatile (ASM_VMX_VMXON_RAX
2159 : : "a"(&addr), "m"(addr)
2160 : "memory", "cc");
2161}
2162
10474ae8 2163static int hardware_enable(void *garbage)
6aa8b732
AK		 2164{
2165 int cpu = raw_smp_processor_id();
2166 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2167 u64 old, test_bits;
6aa8b732 2168
10474ae8
AG		 2169 if (read_cr4() & X86_CR4_VMXE)
2170 return -EBUSY;
2171
d462b819 2172 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2173 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2174
2175 test_bits = FEATURE_CONTROL_LOCKED;
2176 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2177 if (tboot_enabled())
2178 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2179
2180 if ((old & test_bits) != test_bits) {
6aa8b732 2181 /* enable and lock */
cafd6659
SW		 2182 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2183 }
66aee91a 2184 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2185
4610c9cc
DX		 2186 if (vmm_exclusive) {
2187 kvm_cpu_vmxon(phys_addr);
2188 ept_sync_global();
2189 }
10474ae8 2190
3444d7da
AK		 2191 store_gdt(&__get_cpu_var(host_gdt));
2192
10474ae8 2193 return 0;
6aa8b732
AK		 2194}
2195
d462b819 2196static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2197{
2198 int cpu = raw_smp_processor_id();
d462b819 2199 struct loaded_vmcs *v, *n;
543e4243 2200
d462b819
NHE		 2201 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2202 loaded_vmcss_on_cpu_link)
2203 __loaded_vmcs_clear(v);
543e4243
AK		 2204}
2205
710ff4a8
EH		 2206
2207/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2208 * tricks.
2209 */
2210static void kvm_cpu_vmxoff(void)
6aa8b732 2211{
4ecac3fd 2212 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2213}
2214
710ff4a8
EH		 2215static void hardware_disable(void *garbage)
2216{
4610c9cc 2217 if (vmm_exclusive) {
d462b819 2218 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2219 kvm_cpu_vmxoff();
2220 }
7725b894 2221 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2222}
2223
1c3d14fe 2224static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2225 u32 msr, u32 *result)
1c3d14fe
YS		 2226{
2227 u32 vmx_msr_low, vmx_msr_high;
2228 u32 ctl = ctl_min | ctl_opt;
2229
2230 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2231
2232 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2233 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2234
2235 /* Ensure minimum (required) set of control bits are supported. */
2236 if (ctl_min & ~ctl)
002c7f7c 2237 return -EIO;
1c3d14fe
YS		 2238
2239 *result = ctl;
2240 return 0;
2241}
2242
110312c8
AK		 2243static __init bool allow_1_setting(u32 msr, u32 ctl)
2244{
2245 u32 vmx_msr_low, vmx_msr_high;
2246
2247 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2248 return vmx_msr_high & ctl;
2249}
2250
002c7f7c 2251static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2252{
2253 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2254 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2255 u32 _pin_based_exec_control = 0;
2256 u32 _cpu_based_exec_control = 0;
f78e0e2e 2257 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2258 u32 _vmexit_control = 0;
2259 u32 _vmentry_control = 0;
2260
2261 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2262 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2263 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2264 &_pin_based_exec_control) < 0)
002c7f7c 2265 return -EIO;
1c3d14fe 2266
443381a8 2267 min =
1c3d14fe
YS		 2268#ifdef CONFIG_X86_64
2269 CPU_BASED_CR8_LOAD_EXITING |
2270 CPU_BASED_CR8_STORE_EXITING |
2271#endif
d56f546d
SY		 2272 CPU_BASED_CR3_LOAD_EXITING |
2273 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2274 CPU_BASED_USE_IO_BITMAPS |
2275 CPU_BASED_MOV_DR_EXITING |
a7052897 2276 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2277 CPU_BASED_MWAIT_EXITING |
2278 CPU_BASED_MONITOR_EXITING |
a7052897 2279 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2280
2281 if (yield_on_hlt)
2282 min |= CPU_BASED_HLT_EXITING;
2283
f78e0e2e 2284 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2285 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2287 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2288 &_cpu_based_exec_control) < 0)
002c7f7c 2289 return -EIO;
6e5d865c
YS		 2290#ifdef CONFIG_X86_64
2291 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2292 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2293 ~CPU_BASED_CR8_STORE_EXITING;
2294#endif
f78e0e2e 2295 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2296 min2 = 0;
2297 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2298 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2299 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2300 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2301 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2302 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2303 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2304 if (adjust_vmx_controls(min2, opt2,
2305 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2306 &_cpu_based_2nd_exec_control) < 0)
2307 return -EIO;
2308 }
2309#ifndef CONFIG_X86_64
2310 if (!(_cpu_based_2nd_exec_control &
2311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2312 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2313#endif
d56f546d 2314 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2315 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2316 enabled */
5fff7d27
GN		 2317 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2318 CPU_BASED_CR3_STORE_EXITING |
2319 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2320 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2321 vmx_capability.ept, vmx_capability.vpid);
2322 }
1c3d14fe
YS		 2323
2324 min = 0;
2325#ifdef CONFIG_X86_64
2326 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2327#endif
468d472f 2328 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2329 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2330 &_vmexit_control) < 0)
002c7f7c 2331 return -EIO;
1c3d14fe 2332
468d472f
SY		 2333 min = 0;
2334 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2335 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2336 &_vmentry_control) < 0)
002c7f7c 2337 return -EIO;
6aa8b732 2338
c68876fd 2339 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2340
2341 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2342 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2343 return -EIO;
1c3d14fe
YS		 2344
2345#ifdef CONFIG_X86_64
2346 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2347 if (vmx_msr_high & (1u<<16))
002c7f7c 2348 return -EIO;
1c3d14fe
YS		 2349#endif
2350
2351 /* Require Write-Back (WB) memory type for VMCS accesses. */
2352 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2353 return -EIO;
1c3d14fe 2354
002c7f7c
YS		 2355 vmcs_conf->size = vmx_msr_high & 0x1fff;
2356 vmcs_conf->order = get_order(vmcs_config.size);
2357 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2358
002c7f7c
YS		 2359 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2360 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2361 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2362 vmcs_conf->vmexit_ctrl = _vmexit_control;
2363 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2364
110312c8
AK		 2365 cpu_has_load_ia32_efer =
2366 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2367 VM_ENTRY_LOAD_IA32_EFER)
2368 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2369 VM_EXIT_LOAD_IA32_EFER);
2370
1c3d14fe 2371 return 0;
c68876fd 2372}
6aa8b732
AK		 2373
2374static struct vmcs *alloc_vmcs_cpu(int cpu)
2375{
2376 int node = cpu_to_node(cpu);
2377 struct page *pages;
2378 struct vmcs *vmcs;
2379
6484eb3e 2380 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2381 if (!pages)
2382 return NULL;
2383 vmcs = page_address(pages);
1c3d14fe
YS		 2384 memset(vmcs, 0, vmcs_config.size);
2385 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2386 return vmcs;
2387}
2388
2389static struct vmcs *alloc_vmcs(void)
2390{
d3b2c338 2391 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2392}
2393
2394static void free_vmcs(struct vmcs *vmcs)
2395{
1c3d14fe 2396 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2397}
2398
d462b819
NHE		 2399/*
2400 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2401 */
2402static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2403{
2404 if (!loaded_vmcs->vmcs)
2405 return;
2406 loaded_vmcs_clear(loaded_vmcs);
2407 free_vmcs(loaded_vmcs->vmcs);
2408 loaded_vmcs->vmcs = NULL;
2409}
2410
39959588 2411static void free_kvm_area(void)
6aa8b732
AK		 2412{
2413 int cpu;
2414
3230bb47 2415 for_each_possible_cpu(cpu) {
6aa8b732 2416 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2417 per_cpu(vmxarea, cpu) = NULL;
2418 }
6aa8b732
AK		 2419}
2420
6aa8b732
AK		 2421static __init int alloc_kvm_area(void)
2422{
2423 int cpu;
2424
3230bb47 2425 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2426 struct vmcs *vmcs;
2427
2428 vmcs = alloc_vmcs_cpu(cpu);
2429 if (!vmcs) {
2430 free_kvm_area();
2431 return -ENOMEM;
2432 }
2433
2434 per_cpu(vmxarea, cpu) = vmcs;
2435 }
2436 return 0;
2437}
2438
2439static __init int hardware_setup(void)
2440{
002c7f7c
YS		 2441 if (setup_vmcs_config(&vmcs_config) < 0)
2442 return -EIO;
50a37eb4
JR		 2443
2444 if (boot_cpu_has(X86_FEATURE_NX))
2445 kvm_enable_efer_bits(EFER_NX);
2446
93ba03c2
SY		 2447 if (!cpu_has_vmx_vpid())
2448 enable_vpid = 0;
2449
4bc9b982
SY		 2450 if (!cpu_has_vmx_ept() ||
2451 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2452 enable_ept = 0;
3a624e29
NK		 2453 enable_unrestricted_guest = 0;
2454 }
2455
2456 if (!cpu_has_vmx_unrestricted_guest())
2457 enable_unrestricted_guest = 0;
93ba03c2
SY		 2458
2459 if (!cpu_has_vmx_flexpriority())
2460 flexpriority_enabled = 0;
2461
95ba8273
GN		 2462 if (!cpu_has_vmx_tpr_shadow())
2463 kvm_x86_ops->update_cr8_intercept = NULL;
2464
54dee993
MT		 2465 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2466 kvm_disable_largepages();
2467
4b8d54f9
ZE		 2468 if (!cpu_has_vmx_ple())
2469 ple_gap = 0;
2470
b87a51ae
NHE		 2471 if (nested)
2472 nested_vmx_setup_ctls_msrs();
2473
6aa8b732
AK		 2474 return alloc_kvm_area();
2475}
2476
2477static __exit void hardware_unsetup(void)
2478{
2479 free_kvm_area();
2480}
2481
6aa8b732
AK		 2482static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2483{
2484 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2485
6af11b9e 2486 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2487 vmcs_write16(sf->selector, save->selector);
2488 vmcs_writel(sf->base, save->base);
2489 vmcs_write32(sf->limit, save->limit);
2490 vmcs_write32(sf->ar_bytes, save->ar);
2491 } else {
2492 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2493 << AR_DPL_SHIFT;
2494 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2495 }
2496}
2497
2498static void enter_pmode(struct kvm_vcpu *vcpu)
2499{
2500 unsigned long flags;
a89a8fb9 2501 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2502
a89a8fb9 2503 vmx->emulation_required = 1;
7ffd92c5 2504 vmx->rmode.vm86_active = 0;
6aa8b732 2505
2fb92db1
AK		 2506 vmx_segment_cache_clear(vmx);
2507
d0ba64f9 2508 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2509 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2510 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2511 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2512
2513 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2514 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2515 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2516 vmcs_writel(GUEST_RFLAGS, flags);
2517
66aee91a
RR		 2518 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2519 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2520
2521 update_exception_bitmap(vcpu);
2522
a89a8fb9
MG		 2523 if (emulate_invalid_guest_state)
2524 return;
2525
7ffd92c5
AK		 2526 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2527 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2528 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2529 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2530
2fb92db1
AK		 2531 vmx_segment_cache_clear(vmx);
2532
6aa8b732
AK		 2533 vmcs_write16(GUEST_SS_SELECTOR, 0);
2534 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2535
2536 vmcs_write16(GUEST_CS_SELECTOR,
2537 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2538 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2539}
2540
d77c26fc 2541static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2542{
bfc6d222 2543 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2544 struct kvm_memslots *slots;
2545 gfn_t base_gfn;
2546
90d83dc3 2547 slots = kvm_memslots(kvm);
f495c6e5 2548 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2549 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2550 return base_gfn << PAGE_SHIFT;
2551 }
bfc6d222 2552 return kvm->arch.tss_addr;
6aa8b732
AK		 2553}
2554
2555static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2556{
2557 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2558
2559 save->selector = vmcs_read16(sf->selector);
2560 save->base = vmcs_readl(sf->base);
2561 save->limit = vmcs_read32(sf->limit);
2562 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2563 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2564 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2565 vmcs_write32(sf->limit, 0xffff);
2566 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2567 if (save->base & 0xf)
2568 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2569 " aligned when entering protected mode (seg=%d)",
2570 seg);
6aa8b732
AK		 2571}
2572
2573static void enter_rmode(struct kvm_vcpu *vcpu)
2574{
2575 unsigned long flags;
a89a8fb9 2576 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2577
3a624e29
NK		 2578 if (enable_unrestricted_guest)
2579 return;
2580
a89a8fb9 2581 vmx->emulation_required = 1;
7ffd92c5 2582 vmx->rmode.vm86_active = 1;
6aa8b732 2583
776e58ea
GN		 2584 /*
2585 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2586 * vcpu. Call it here with phys address pointing 16M below 4G.
2587 */
2588 if (!vcpu->kvm->arch.tss_addr) {
2589 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2590 "called before entering vcpu\n");
2591 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2592 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2593 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2594 }
2595
2fb92db1
AK		 2596 vmx_segment_cache_clear(vmx);
2597
d0ba64f9 2598 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2599 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2600 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2601
7ffd92c5 2602 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2603 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2604
7ffd92c5 2605 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2606 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2607
2608 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2609 vmx->rmode.save_rflags = flags;
6aa8b732 2610
053de044 2611 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2612
2613 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2614 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2615 update_exception_bitmap(vcpu);
2616
a89a8fb9
MG		 2617 if (emulate_invalid_guest_state)
2618 goto continue_rmode;
2619
6aa8b732
AK		 2620 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2621 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2622 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2623
2624 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2625 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2626 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2627 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2628 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2629
7ffd92c5
AK		 2630 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2631 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2632 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2633 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2634
a89a8fb9 2635continue_rmode:
8668a3c4 2636 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2637}
2638
401d10de
AS		 2639static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2640{
2641 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2642 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2643
2644 if (!msr)
2645 return;
401d10de 2646
44ea2b17
AK		 2647 /*
2648 * Force kernel_gs_base reloading before EFER changes, as control
2649 * of this msr depends on is_long_mode().
2650 */
2651 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2652 vcpu->arch.efer = efer;
401d10de
AS		 2653 if (efer & EFER_LMA) {
2654 vmcs_write32(VM_ENTRY_CONTROLS,
2655 vmcs_read32(VM_ENTRY_CONTROLS) |
2656 VM_ENTRY_IA32E_MODE);
2657 msr->data = efer;
2658 } else {
2659 vmcs_write32(VM_ENTRY_CONTROLS,
2660 vmcs_read32(VM_ENTRY_CONTROLS) &
2661 ~VM_ENTRY_IA32E_MODE);
2662
2663 msr->data = efer & ~EFER_LME;
2664 }
2665 setup_msrs(vmx);
2666}
2667
05b3e0c2 2668#ifdef CONFIG_X86_64
6aa8b732
AK		 2669
2670static void enter_lmode(struct kvm_vcpu *vcpu)
2671{
2672 u32 guest_tr_ar;
2673
2fb92db1
AK		 2674 vmx_segment_cache_clear(to_vmx(vcpu));
2675
6aa8b732
AK		 2676 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2677 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2678 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2679 __func__);
6aa8b732
AK		 2680 vmcs_write32(GUEST_TR_AR_BYTES,
2681 (guest_tr_ar & ~AR_TYPE_MASK)
2682 | AR_TYPE_BUSY_64_TSS);
2683 }
da38f438 2684 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2685}
2686
2687static void exit_lmode(struct kvm_vcpu *vcpu)
2688{
6aa8b732
AK		 2689 vmcs_write32(VM_ENTRY_CONTROLS,
2690 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2691 & ~VM_ENTRY_IA32E_MODE);
da38f438 2692 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2693}
2694
2695#endif
2696
2384d2b3
SY		 2697static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2698{
b9d762fa 2699 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2700 if (enable_ept) {
2701 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2702 return;
4e1096d2 2703 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2704 }
2384d2b3
SY		 2705}
2706
e8467fda
AK		 2707static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2708{
2709 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2710
2711 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2712 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2713}
2714
aff48baa
AK		 2715static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2716{
2717 if (enable_ept && is_paging(vcpu))
2718 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2719 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2720}
2721
25c4c276 2722static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2723{
fc78f519
AK		 2724 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2725
2726 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2727 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2728}
2729
1439442c
SY		 2730static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2731{
6de4f3ad
AK		 2732 if (!test_bit(VCPU_EXREG_PDPTR,
2733 (unsigned long *)&vcpu->arch.regs_dirty))
2734 return;
2735
1439442c 2736 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2737 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2738 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2739 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2740 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2741 }
2742}
2743
8f5d549f
AK		 2744static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2745{
2746 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2747 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2748 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2749 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2750 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2751 }
6de4f3ad
AK		 2752
2753 __set_bit(VCPU_EXREG_PDPTR,
2754 (unsigned long *)&vcpu->arch.regs_avail);
2755 __set_bit(VCPU_EXREG_PDPTR,
2756 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2757}
2758
5e1746d6 2759static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2760
2761static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2762 unsigned long cr0,
2763 struct kvm_vcpu *vcpu)
2764{
5233dd51
MT		 2765 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2766 vmx_decache_cr3(vcpu);
1439442c
SY		 2767 if (!(cr0 & X86_CR0_PG)) {
2768 /* From paging/starting to nonpaging */
2769 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2770 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2771 (CPU_BASED_CR3_LOAD_EXITING |
2772 CPU_BASED_CR3_STORE_EXITING));
2773 vcpu->arch.cr0 = cr0;
fc78f519 2774 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2775 } else if (!is_paging(vcpu)) {
2776 /* From nonpaging to paging */
2777 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2778 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2779 ~(CPU_BASED_CR3_LOAD_EXITING |
2780 CPU_BASED_CR3_STORE_EXITING));
2781 vcpu->arch.cr0 = cr0;
fc78f519 2782 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2783 }
95eb84a7
SY		 2784
2785 if (!(cr0 & X86_CR0_WP))
2786 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2787}
2788
6aa8b732
AK		 2789static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2790{
7ffd92c5 2791 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2792 unsigned long hw_cr0;
2793
2794 if (enable_unrestricted_guest)
2795 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2796 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2797 else
2798 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2799
7ffd92c5 2800 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2801 enter_pmode(vcpu);
2802
7ffd92c5 2803 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2804 enter_rmode(vcpu);
2805
05b3e0c2 2806#ifdef CONFIG_X86_64
f6801dff 2807 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2808 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2809 enter_lmode(vcpu);
707d92fa 2810 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2811 exit_lmode(vcpu);
2812 }
2813#endif
2814
089d034e 2815 if (enable_ept)
1439442c
SY		 2816 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2817
02daab21 2818 if (!vcpu->fpu_active)
81231c69 2819 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2820
6aa8b732 2821 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2822 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2823 vcpu->arch.cr0 = cr0;
69c73028 2824 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2825}
2826
1439442c
SY		 2827static u64 construct_eptp(unsigned long root_hpa)
2828{
2829 u64 eptp;
2830
2831 /* TODO write the value reading from MSR */
2832 eptp = VMX_EPT_DEFAULT_MT |
2833 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2834 eptp |= (root_hpa & PAGE_MASK);
2835
2836 return eptp;
2837}
2838
6aa8b732
AK		 2839static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2840{
1439442c
SY		 2841 unsigned long guest_cr3;
2842 u64 eptp;
2843
2844 guest_cr3 = cr3;
089d034e 2845 if (enable_ept) {
1439442c
SY		 2846 eptp = construct_eptp(cr3);
2847 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2848 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2849 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2850 ept_load_pdptrs(vcpu);
1439442c
SY		 2851 }
2852
2384d2b3 2853 vmx_flush_tlb(vcpu);
1439442c 2854 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2855}
2856
5e1746d6 2857static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2858{
7ffd92c5 2859 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2860 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2861
5e1746d6
NHE		 2862 if (cr4 & X86_CR4_VMXE) {
2863 /*
2864 * To use VMXON (and later other VMX instructions), a guest
2865 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2866 * So basically the check on whether to allow nested VMX
2867 * is here.
2868 */
2869 if (!nested_vmx_allowed(vcpu))
2870 return 1;
2871 } else if (to_vmx(vcpu)->nested.vmxon)
2872 return 1;
2873
ad312c7c 2874 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2875 if (enable_ept) {
2876 if (!is_paging(vcpu)) {
2877 hw_cr4 &= ~X86_CR4_PAE;
2878 hw_cr4 |= X86_CR4_PSE;
2879 } else if (!(cr4 & X86_CR4_PAE)) {
2880 hw_cr4 &= ~X86_CR4_PAE;
2881 }
2882 }
1439442c
SY		 2883
2884 vmcs_writel(CR4_READ_SHADOW, cr4);
2885 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2886 return 0;
6aa8b732
AK		 2887}
2888
6aa8b732
AK		 2889static void vmx_get_segment(struct kvm_vcpu *vcpu,
2890 struct kvm_segment *var, int seg)
2891{
a9179499 2892 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2893 struct kvm_save_segment *save;
6aa8b732
AK		 2894 u32 ar;
2895
a9179499
AK		 2896 if (vmx->rmode.vm86_active
2897 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2898 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2899 || seg == VCPU_SREG_GS)
2900 && !emulate_invalid_guest_state) {
2901 switch (seg) {
2902 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2903 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2904 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2905 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2906 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2907 default: BUG();
2908 }
2909 var->selector = save->selector;
2910 var->base = save->base;
2911 var->limit = save->limit;
2912 ar = save->ar;
2913 if (seg == VCPU_SREG_TR
2fb92db1 2914 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2915 goto use_saved_rmode_seg;
2916 }
2fb92db1
AK		 2917 var->base = vmx_read_guest_seg_base(vmx, seg);
2918 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2919 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2920 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2921use_saved_rmode_seg:
9fd4a3b7 2922 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2923 ar = 0;
2924 var->type = ar & 15;
2925 var->s = (ar >> 4) & 1;
2926 var->dpl = (ar >> 5) & 3;
2927 var->present = (ar >> 7) & 1;
2928 var->avl = (ar >> 12) & 1;
2929 var->l = (ar >> 13) & 1;
2930 var->db = (ar >> 14) & 1;
2931 var->g = (ar >> 15) & 1;
2932 var->unusable = (ar >> 16) & 1;
2933}
2934
a9179499
AK		 2935static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2936{
a9179499
AK		 2937 struct kvm_segment s;
2938
2939 if (to_vmx(vcpu)->rmode.vm86_active) {
2940 vmx_get_segment(vcpu, &s, seg);
2941 return s.base;
2942 }
2fb92db1 2943 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2944}
2945
69c73028 2946static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2947{
3eeb3288 2948 if (!is_protmode(vcpu))
2e4d2653
IE		 2949 return 0;
2950
f4c63e5d
AK		 2951 if (!is_long_mode(vcpu)
2952 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2953 return 3;
2954
2fb92db1 2955 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 2956}
2957
69c73028
AK		 2958static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2959{
2960 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2961 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2962 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2963 }
2964 return to_vmx(vcpu)->cpl;
2965}
2966
2967
653e3108 2968static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2969{
6aa8b732
AK		 2970 u32 ar;
2971
653e3108 2972 if (var->unusable)
6aa8b732
AK		 2973 ar = 1 << 16;
2974 else {
2975 ar = var->type & 15;
2976 ar |= (var->s & 1) << 4;
2977 ar |= (var->dpl & 3) << 5;
2978 ar |= (var->present & 1) << 7;
2979 ar |= (var->avl & 1) << 12;
2980 ar |= (var->l & 1) << 13;
2981 ar |= (var->db & 1) << 14;
2982 ar |= (var->g & 1) << 15;
2983 }
f7fbf1fd
UL		 2984 if (ar == 0) /* a 0 value means unusable */
2985 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2986
2987 return ar;
2988}
2989
2990static void vmx_set_segment(struct kvm_vcpu *vcpu,
2991 struct kvm_segment *var, int seg)
2992{
7ffd92c5 2993 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2994 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2995 u32 ar;
2996
2fb92db1
AK		 2997 vmx_segment_cache_clear(vmx);
2998
7ffd92c5 2999 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3000 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3001 vmx->rmode.tr.selector = var->selector;
3002 vmx->rmode.tr.base = var->base;
3003 vmx->rmode.tr.limit = var->limit;
3004 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3005 return;
3006 }
3007 vmcs_writel(sf->base, var->base);
3008 vmcs_write32(sf->limit, var->limit);
3009 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3010 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3011 /*
3012 * Hack real-mode segments into vm86 compatibility.
3013 */
3014 if (var->base == 0xffff0000 && var->selector == 0xf000)
3015 vmcs_writel(sf->base, 0xf0000);
3016 ar = 0xf3;
3017 } else
3018 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3019
3020 /*
3021 * Fix the "Accessed" bit in AR field of segment registers for older
3022 * qemu binaries.
3023 * IA32 arch specifies that at the time of processor reset the
3024 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3025 * is setting it to 0 in the usedland code. This causes invalid guest
3026 * state vmexit when "unrestricted guest" mode is turned on.
3027 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3028 * tree. Newer qemu binaries with that qemu fix would not need this
3029 * kvm hack.
3030 */
3031 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3032 ar |= 0x1; /* Accessed */
3033
6aa8b732 3034 vmcs_write32(sf->ar_bytes, ar);
69c73028 3035 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3036}
3037
6aa8b732
AK		 3038static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3039{
2fb92db1 3040 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3041
3042 *db = (ar >> 14) & 1;
3043 *l = (ar >> 13) & 1;
3044}
3045
89a27f4d 3046static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3047{
89a27f4d
GN		 3048 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3049 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3050}
3051
89a27f4d 3052static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3053{
89a27f4d
GN		 3054 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3055 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3056}
3057
89a27f4d 3058static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3059{
89a27f4d
GN		 3060 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3061 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3062}
3063
89a27f4d 3064static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3065{
89a27f4d
GN		 3066 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3067 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3068}
3069
648dfaa7
MG		 3070static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3071{
3072 struct kvm_segment var;
3073 u32 ar;
3074
3075 vmx_get_segment(vcpu, &var, seg);
3076 ar = vmx_segment_access_rights(&var);
3077
3078 if (var.base != (var.selector << 4))
3079 return false;
3080 if (var.limit != 0xffff)
3081 return false;
3082 if (ar != 0xf3)
3083 return false;
3084
3085 return true;
3086}
3087
3088static bool code_segment_valid(struct kvm_vcpu *vcpu)
3089{
3090 struct kvm_segment cs;
3091 unsigned int cs_rpl;
3092
3093 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3094 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3095
1872a3f4
AK		 3096 if (cs.unusable)
3097 return false;
648dfaa7
MG		 3098 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3099 return false;
3100 if (!cs.s)
3101 return false;
1872a3f4 3102 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3103 if (cs.dpl > cs_rpl)
3104 return false;
1872a3f4 3105 } else {
648dfaa7
MG		 3106 if (cs.dpl != cs_rpl)
3107 return false;
3108 }
3109 if (!cs.present)
3110 return false;
3111
3112 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3113 return true;
3114}
3115
3116static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3117{
3118 struct kvm_segment ss;
3119 unsigned int ss_rpl;
3120
3121 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3122 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3123
1872a3f4
AK		 3124 if (ss.unusable)
3125 return true;
3126 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3127 return false;
3128 if (!ss.s)
3129 return false;
3130 if (ss.dpl != ss_rpl) /* DPL != RPL */
3131 return false;
3132 if (!ss.present)
3133 return false;
3134
3135 return true;
3136}
3137
3138static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3139{
3140 struct kvm_segment var;
3141 unsigned int rpl;
3142
3143 vmx_get_segment(vcpu, &var, seg);
3144 rpl = var.selector & SELECTOR_RPL_MASK;
3145
1872a3f4
AK		 3146 if (var.unusable)
3147 return true;
648dfaa7
MG		 3148 if (!var.s)
3149 return false;
3150 if (!var.present)
3151 return false;
3152 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3153 if (var.dpl < rpl) /* DPL < RPL */
3154 return false;
3155 }
3156
3157 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3158 * rights flags
3159 */
3160 return true;
3161}
3162
3163static bool tr_valid(struct kvm_vcpu *vcpu)
3164{
3165 struct kvm_segment tr;
3166
3167 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3168
1872a3f4
AK		 3169 if (tr.unusable)
3170 return false;
648dfaa7
MG		 3171 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3172 return false;
1872a3f4 3173 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3174 return false;
3175 if (!tr.present)
3176 return false;
3177
3178 return true;
3179}
3180
3181static bool ldtr_valid(struct kvm_vcpu *vcpu)
3182{
3183 struct kvm_segment ldtr;
3184
3185 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3186
1872a3f4
AK		 3187 if (ldtr.unusable)
3188 return true;
648dfaa7
MG		 3189 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3190 return false;
3191 if (ldtr.type != 2)
3192 return false;
3193 if (!ldtr.present)
3194 return false;
3195
3196 return true;
3197}
3198
3199static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3200{
3201 struct kvm_segment cs, ss;
3202
3203 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3204 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3205
3206 return ((cs.selector & SELECTOR_RPL_MASK) ==
3207 (ss.selector & SELECTOR_RPL_MASK));
3208}
3209
3210/*
3211 * Check if guest state is valid. Returns true if valid, false if
3212 * not.
3213 * We assume that registers are always usable
3214 */
3215static bool guest_state_valid(struct kvm_vcpu *vcpu)
3216{
3217 /* real mode guest state checks */
3eeb3288 3218 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3219 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3220 return false;
3221 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3222 return false;
3223 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3224 return false;
3225 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3226 return false;
3227 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3228 return false;
3229 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3230 return false;
3231 } else {
3232 /* protected mode guest state checks */
3233 if (!cs_ss_rpl_check(vcpu))
3234 return false;
3235 if (!code_segment_valid(vcpu))
3236 return false;
3237 if (!stack_segment_valid(vcpu))
3238 return false;
3239 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3240 return false;
3241 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3242 return false;
3243 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3244 return false;
3245 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3246 return false;
3247 if (!tr_valid(vcpu))
3248 return false;
3249 if (!ldtr_valid(vcpu))
3250 return false;
3251 }
3252 /* TODO:
3253 * - Add checks on RIP
3254 * - Add checks on RFLAGS
3255 */
3256
3257 return true;
3258}
3259
d77c26fc 3260static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3261{
40dcaa9f 3262 gfn_t fn;
195aefde 3263 u16 data = 0;
40dcaa9f 3264 int r, idx, ret = 0;
6aa8b732 3265
40dcaa9f
XG		 3266 idx = srcu_read_lock(&kvm->srcu);
3267 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3268 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3269 if (r < 0)
10589a46 3270 goto out;
195aefde 3271 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3272 r = kvm_write_guest_page(kvm, fn++, &data,
3273 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3274 if (r < 0)
10589a46 3275 goto out;
195aefde
IE		 3276 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3277 if (r < 0)
10589a46 3278 goto out;
195aefde
IE		 3279 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3280 if (r < 0)
10589a46 3281 goto out;
195aefde 3282 data = ~0;
10589a46
MT		 3283 r = kvm_write_guest_page(kvm, fn, &data,
3284 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3285 sizeof(u8));
195aefde 3286 if (r < 0)
10589a46
MT		 3287 goto out;
3288
3289 ret = 1;
3290out:
40dcaa9f 3291 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3292 return ret;
6aa8b732
AK		 3293}
3294
b7ebfb05
SY		 3295static int init_rmode_identity_map(struct kvm *kvm)
3296{
40dcaa9f 3297 int i, idx, r, ret;
b7ebfb05
SY		 3298 pfn_t identity_map_pfn;
3299 u32 tmp;
3300
089d034e 3301 if (!enable_ept)
b7ebfb05
SY		 3302 return 1;
3303 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3304 printk(KERN_ERR "EPT: identity-mapping pagetable "
3305 "haven't been allocated!\n");
3306 return 0;
3307 }
3308 if (likely(kvm->arch.ept_identity_pagetable_done))
3309 return 1;
3310 ret = 0;
b927a3ce 3311 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3312 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3313 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3314 if (r < 0)
3315 goto out;
3316 /* Set up identity-mapping pagetable for EPT in real mode */
3317 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3318 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3319 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3320 r = kvm_write_guest_page(kvm, identity_map_pfn,
3321 &tmp, i * sizeof(tmp), sizeof(tmp));
3322 if (r < 0)
3323 goto out;
3324 }
3325 kvm->arch.ept_identity_pagetable_done = true;
3326 ret = 1;
3327out:
40dcaa9f 3328 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3329 return ret;
3330}
3331
6aa8b732
AK		 3332static void seg_setup(int seg)
3333{
3334 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3335 unsigned int ar;
6aa8b732
AK		 3336
3337 vmcs_write16(sf->selector, 0);
3338 vmcs_writel(sf->base, 0);
3339 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3340 if (enable_unrestricted_guest) {
3341 ar = 0x93;
3342 if (seg == VCPU_SREG_CS)
3343 ar |= 0x08; /* code segment */
3344 } else
3345 ar = 0xf3;
3346
3347 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3348}
3349
f78e0e2e
SY		 3350static int alloc_apic_access_page(struct kvm *kvm)
3351{
3352 struct kvm_userspace_memory_region kvm_userspace_mem;
3353 int r = 0;
3354
79fac95e 3355 mutex_lock(&kvm->slots_lock);
bfc6d222 3356 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3357 goto out;
3358 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3359 kvm_userspace_mem.flags = 0;
3360 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3361 kvm_userspace_mem.memory_size = PAGE_SIZE;
3362 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3363 if (r)
3364 goto out;
72dc67a6 3365
bfc6d222 3366 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3367out:
79fac95e 3368 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3369 return r;
3370}
3371
b7ebfb05
SY		 3372static int alloc_identity_pagetable(struct kvm *kvm)
3373{
3374 struct kvm_userspace_memory_region kvm_userspace_mem;
3375 int r = 0;
3376
79fac95e 3377 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3378 if (kvm->arch.ept_identity_pagetable)
3379 goto out;
3380 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3381 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3382 kvm_userspace_mem.guest_phys_addr =
3383 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3384 kvm_userspace_mem.memory_size = PAGE_SIZE;
3385 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3386 if (r)
3387 goto out;
3388
b7ebfb05 3389 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3390 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3391out:
79fac95e 3392 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3393 return r;
3394}
3395
2384d2b3
SY		 3396static void allocate_vpid(struct vcpu_vmx *vmx)
3397{
3398 int vpid;
3399
3400 vmx->vpid = 0;
919818ab 3401 if (!enable_vpid)
2384d2b3
SY		 3402 return;
3403 spin_lock(&vmx_vpid_lock);
3404 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3405 if (vpid < VMX_NR_VPIDS) {
3406 vmx->vpid = vpid;
3407 __set_bit(vpid, vmx_vpid_bitmap);
3408 }
3409 spin_unlock(&vmx_vpid_lock);
3410}
3411
cdbecfc3
LJ		 3412static void free_vpid(struct vcpu_vmx *vmx)
3413{
3414 if (!enable_vpid)
3415 return;
3416 spin_lock(&vmx_vpid_lock);
3417 if (vmx->vpid != 0)
3418 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3419 spin_unlock(&vmx_vpid_lock);
3420}
3421
5897297b 3422static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3423{
3e7c73e9 3424 int f = sizeof(unsigned long);
25c5f225
SY		 3425
3426 if (!cpu_has_vmx_msr_bitmap())
3427 return;
3428
3429 /*
3430 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3431 * have the write-low and read-high bitmap offsets the wrong way round.
3432 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3433 */
25c5f225 3434 if (msr <= 0x1fff) {
3e7c73e9
AK		 3435 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3436 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3437 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3438 msr &= 0x1fff;
3e7c73e9
AK		 3439 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3440 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3441 }
25c5f225
SY		 3442}
3443
5897297b
AK		 3444static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3445{
3446 if (!longmode_only)
3447 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3448 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3449}
3450
a3a8ff8e
NHE		 3451/*
3452 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3453 * will not change in the lifetime of the guest.
3454 * Note that host-state that does change is set elsewhere. E.g., host-state
3455 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3456 */
3457static void vmx_set_constant_host_state(void)
3458{
3459 u32 low32, high32;
3460 unsigned long tmpl;
3461 struct desc_ptr dt;
3462
3463 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3464 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3465 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3466
3467 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3468 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3469 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3470 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3471 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3472
3473 native_store_idt(&dt);
3474 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3475
3476 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3477 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3478
3479 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3480 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3481 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3482 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3483
3484 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3485 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3486 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3487 }
3488}
3489
bf8179a0
NHE		 3490static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3491{
3492 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3493 if (enable_ept)
3494 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3495 if (is_guest_mode(&vmx->vcpu))
3496 vmx->vcpu.arch.cr4_guest_owned_bits &=
3497 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3498 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3499}
3500
3501static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3502{
3503 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3504 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3505 exec_control &= ~CPU_BASED_TPR_SHADOW;
3506#ifdef CONFIG_X86_64
3507 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3508 CPU_BASED_CR8_LOAD_EXITING;
3509#endif
3510 }
3511 if (!enable_ept)
3512 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3513 CPU_BASED_CR3_LOAD_EXITING |
3514 CPU_BASED_INVLPG_EXITING;
3515 return exec_control;
3516}
3517
3518static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3519{
3520 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3521 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3522 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3523 if (vmx->vpid == 0)
3524 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3525 if (!enable_ept) {
3526 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3527 enable_unrestricted_guest = 0;
3528 }
3529 if (!enable_unrestricted_guest)
3530 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3531 if (!ple_gap)
3532 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3533 return exec_control;
3534}
3535
6aa8b732
AK		 3536/*
3537 * Sets up the vmcs for emulated real mode.
3538 */
8b9cf98c 3539static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3540{
6aa8b732 3541 unsigned long a;
6aa8b732 3542 int i;
6aa8b732 3543
6aa8b732 3544 /* I/O */
3e7c73e9
AK		 3545 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3546 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3547
25c5f225 3548 if (cpu_has_vmx_msr_bitmap())
5897297b 3549 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3550
6aa8b732
AK		 3551 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3552
6aa8b732 3553 /* Control */
1c3d14fe
YS		 3554 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3555 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3556
bf8179a0 3557 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3558
83ff3b9d 3559 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3560 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3561 vmx_secondary_exec_control(vmx));
83ff3b9d 3562 }
f78e0e2e 3563
4b8d54f9
ZE		 3564 if (ple_gap) {
3565 vmcs_write32(PLE_GAP, ple_gap);
3566 vmcs_write32(PLE_WINDOW, ple_window);
3567 }
3568
c7addb90
AK		 3569 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3570 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 3571 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3572
9581d442
AK		 3573 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3574 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3575 vmx_set_constant_host_state();
05b3e0c2 3576#ifdef CONFIG_X86_64
6aa8b732
AK		 3577 rdmsrl(MSR_FS_BASE, a);
3578 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3579 rdmsrl(MSR_GS_BASE, a);
3580 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3581#else
3582 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3583 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3584#endif
3585
2cc51560
ED		 3586 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3587 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3588 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3589 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3590 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3591
468d472f 3592 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3593 u32 msr_low, msr_high;
3594 u64 host_pat;
468d472f
SY		 3595 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3596 host_pat = msr_low | ((u64) msr_high << 32);
3597 /* Write the default value follow host pat */
3598 vmcs_write64(GUEST_IA32_PAT, host_pat);
3599 /* Keep arch.pat sync with GUEST_IA32_PAT */
3600 vmx->vcpu.arch.pat = host_pat;
3601 }
3602
6aa8b732
AK		 3603 for (i = 0; i < NR_VMX_MSR; ++i) {
3604 u32 index = vmx_msr_index[i];
3605 u32 data_low, data_high;
a2fa3e9f 3606 int j = vmx->nmsrs;
6aa8b732
AK		 3607
3608 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3609 continue;
432bd6cb
AK		 3610 if (wrmsr_safe(index, data_low, data_high) < 0)
3611 continue;
26bb0981
AK		 3612 vmx->guest_msrs[j].index = i;
3613 vmx->guest_msrs[j].data = 0;
d5696725 3614 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3615 ++vmx->nmsrs;
6aa8b732 3616 }
6aa8b732 3617
1c3d14fe 3618 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3619
3620 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3621 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3622
e00c8cf2 3623 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3624 set_cr4_guest_host_mask(vmx);
e00c8cf2 3625
99e3e30a 3626 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3627
e00c8cf2
AK		 3628 return 0;
3629}
3630
3631static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3632{
3633 struct vcpu_vmx *vmx = to_vmx(vcpu);
3634 u64 msr;
4b9d3a04 3635 int ret;
e00c8cf2 3636
5fdbf976 3637 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3638
7ffd92c5 3639 vmx->rmode.vm86_active = 0;
e00c8cf2 3640
3b86cd99
JK		 3641 vmx->soft_vnmi_blocked = 0;
3642
ad312c7c 3643 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3644 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3645 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3646 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3647 msr |= MSR_IA32_APICBASE_BSP;
3648 kvm_set_apic_base(&vmx->vcpu, msr);
3649
10ab25cd
JK		 3650 ret = fx_init(&vmx->vcpu);
3651 if (ret != 0)
3652 goto out;
e00c8cf2 3653
2fb92db1
AK		 3654 vmx_segment_cache_clear(vmx);
3655
5706be0d 3656 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3657 /*
3658 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3659 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3660 */
c5af89b6 3661 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3662 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3663 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3664 } else {
ad312c7c
ZX		 3665 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3666 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3667 }
e00c8cf2
AK		 3668
3669 seg_setup(VCPU_SREG_DS);
3670 seg_setup(VCPU_SREG_ES);
3671 seg_setup(VCPU_SREG_FS);
3672 seg_setup(VCPU_SREG_GS);
3673 seg_setup(VCPU_SREG_SS);
3674
3675 vmcs_write16(GUEST_TR_SELECTOR, 0);
3676 vmcs_writel(GUEST_TR_BASE, 0);
3677 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3678 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3679
3680 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3681 vmcs_writel(GUEST_LDTR_BASE, 0);
3682 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3683 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3684
3685 vmcs_write32(GUEST_SYSENTER_CS, 0);
3686 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3687 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3688
3689 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3690 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3691 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3692 else
5fdbf976
MT		 3693 kvm_rip_write(vcpu, 0);
3694 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3695
e00c8cf2
AK		 3696 vmcs_writel(GUEST_DR7, 0x400);
3697
3698 vmcs_writel(GUEST_GDTR_BASE, 0);
3699 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3700
3701 vmcs_writel(GUEST_IDTR_BASE, 0);
3702 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3703
443381a8 3704 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3705 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3706 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3707
e00c8cf2
AK		 3708 /* Special registers */
3709 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3710
3711 setup_msrs(vmx);
3712
6aa8b732
AK		 3713 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3714
f78e0e2e
SY		 3715 if (cpu_has_vmx_tpr_shadow()) {
3716 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3717 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3718 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3719 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3720 vmcs_write32(TPR_THRESHOLD, 0);
3721 }
3722
3723 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3724 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3725 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3726
2384d2b3
SY		 3727 if (vmx->vpid != 0)
3728 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3729
fa40052c 3730 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3731 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3732 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3733 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3734 vmx_fpu_activate(&vmx->vcpu);
3735 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3736
b9d762fa 3737 vpid_sync_context(vmx);
2384d2b3 3738
3200f405 3739 ret = 0;
6aa8b732 3740
a89a8fb9
MG		 3741 /* HACK: Don't enable emulation on guest boot/reset */
3742 vmx->emulation_required = 0;
3743
6aa8b732
AK		 3744out:
3745 return ret;
3746}
3747
b6f1250e
NHE		 3748/*
3749 * In nested virtualization, check if L1 asked to exit on external interrupts.
3750 * For most existing hypervisors, this will always return true.
3751 */
3752static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3753{
3754 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3755 PIN_BASED_EXT_INTR_MASK;
3756}
3757
3b86cd99
JK		 3758static void enable_irq_window(struct kvm_vcpu *vcpu)
3759{
3760 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3761 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3762 /* We can get here when nested_run_pending caused
3763 * vmx_interrupt_allowed() to return false. In this case, do
3764 * nothing - the interrupt will be injected later.
3765 */
3766 return;
3b86cd99
JK		 3767
3768 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3769 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3770 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3771}
3772
3773static void enable_nmi_window(struct kvm_vcpu *vcpu)
3774{
3775 u32 cpu_based_vm_exec_control;
3776
3777 if (!cpu_has_virtual_nmis()) {
3778 enable_irq_window(vcpu);
3779 return;
3780 }
3781
30bd0c4c
AK		 3782 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3783 enable_irq_window(vcpu);
3784 return;
3785 }
3b86cd99
JK		 3786 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3787 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3788 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3789}
3790
66fd3f7f 3791static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3792{
9c8cba37 3793 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3794 uint32_t intr;
3795 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3796
229456fc 3797 trace_kvm_inj_virq(irq);
2714d1d3 3798
fa89a817 3799 ++vcpu->stat.irq_injections;
7ffd92c5 3800 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3801 int inc_eip = 0;
3802 if (vcpu->arch.interrupt.soft)
3803 inc_eip = vcpu->arch.event_exit_inst_len;
3804 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3805 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3806 return;
3807 }
66fd3f7f
GN		 3808 intr = irq | INTR_INFO_VALID_MASK;
3809 if (vcpu->arch.interrupt.soft) {
3810 intr |= INTR_TYPE_SOFT_INTR;
3811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3812 vmx->vcpu.arch.event_exit_inst_len);
3813 } else
3814 intr |= INTR_TYPE_EXT_INTR;
3815 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3816 vmx_clear_hlt(vcpu);
85f455f7
ED		 3817}
3818
f08864b4
SY		 3819static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3820{
66a5a347
JK		 3821 struct vcpu_vmx *vmx = to_vmx(vcpu);
3822
3b86cd99
JK		 3823 if (!cpu_has_virtual_nmis()) {
3824 /*
3825 * Tracking the NMI-blocked state in software is built upon
3826 * finding the next open IRQ window. This, in turn, depends on
3827 * well-behaving guests: They have to keep IRQs disabled at
3828 * least as long as the NMI handler runs. Otherwise we may
3829 * cause NMI nesting, maybe breaking the guest. But as this is
3830 * highly unlikely, we can live with the residual risk.
3831 */
3832 vmx->soft_vnmi_blocked = 1;
3833 vmx->vnmi_blocked_time = 0;
3834 }
3835
487b391d 3836 ++vcpu->stat.nmi_injections;
9d58b931 3837 vmx->nmi_known_unmasked = false;
7ffd92c5 3838 if (vmx->rmode.vm86_active) {
71f9833b 3839 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3840 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3841 return;
3842 }
f08864b4
SY		 3843 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3844 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3845 vmx_clear_hlt(vcpu);
f08864b4
SY		 3846}
3847
c4282df9 3848static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3849{
3b86cd99 3850 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3851 return 0;
33f089ca 3852
c4282df9 3853 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3854 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3855 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3856}
3857
3cfc3092
JK		 3858static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3859{
3860 if (!cpu_has_virtual_nmis())
3861 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3862 if (to_vmx(vcpu)->nmi_known_unmasked)
3863 return false;
c332c83a 3864 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3865}
3866
3867static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3868{
3869 struct vcpu_vmx *vmx = to_vmx(vcpu);
3870
3871 if (!cpu_has_virtual_nmis()) {
3872 if (vmx->soft_vnmi_blocked != masked) {
3873 vmx->soft_vnmi_blocked = masked;
3874 vmx->vnmi_blocked_time = 0;
3875 }
3876 } else {
9d58b931 3877 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3878 if (masked)
3879 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3880 GUEST_INTR_STATE_NMI);
3881 else
3882 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3883 GUEST_INTR_STATE_NMI);
3884 }
3885}
3886
78646121
GN		 3887static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3888{
b6f1250e
NHE		 3889 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3890 struct vmcs12 *vmcs12;
3891 if (to_vmx(vcpu)->nested.nested_run_pending)
3892 return 0;
3893 nested_vmx_vmexit(vcpu);
3894 vmcs12 = get_vmcs12(vcpu);
3895 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3896 vmcs12->vm_exit_intr_info = 0;
3897 /* fall through to normal code, but now in L1, not L2 */
3898 }
3899
c4282df9
GN		 3900 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3901 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3902 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3903}
3904
cbc94022
IE		 3905static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3906{
3907 int ret;
3908 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3909 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3910 .guest_phys_addr = addr,
3911 .memory_size = PAGE_SIZE * 3,
3912 .flags = 0,
3913 };
3914
3915 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3916 if (ret)
3917 return ret;
bfc6d222 3918 kvm->arch.tss_addr = addr;
93ea5388
GN		 3919 if (!init_rmode_tss(kvm))
3920 return -ENOMEM;
3921
cbc94022
IE		 3922 return 0;
3923}
3924
6aa8b732
AK		 3925static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3926 int vec, u32 err_code)
3927{
b3f37707
NK		 3928 /*
3929 * Instruction with address size override prefix opcode 0x67
3930 * Cause the #SS fault with 0 error code in VM86 mode.
3931 */
3932 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3933 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3934 return 1;
77ab6db0
JK		 3935 /*
3936 * Forward all other exceptions that are valid in real mode.
3937 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3938 * the required debugging infrastructure rework.
3939 */
3940 switch (vec) {
77ab6db0 3941 case DB_VECTOR:
d0bfb940
JK		 3942 if (vcpu->guest_debug &
3943 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3944 return 0;
3945 kvm_queue_exception(vcpu, vec);
3946 return 1;
77ab6db0 3947 case BP_VECTOR:
c573cd22
JK		 3948 /*
3949 * Update instruction length as we may reinject the exception
3950 * from user space while in guest debugging mode.
3951 */
3952 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3953 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3954 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3955 return 0;
3956 /* fall through */
3957 case DE_VECTOR:
77ab6db0
JK		 3958 case OF_VECTOR:
3959 case BR_VECTOR:
3960 case UD_VECTOR:
3961 case DF_VECTOR:
3962 case SS_VECTOR:
3963 case GP_VECTOR:
3964 case MF_VECTOR:
3965 kvm_queue_exception(vcpu, vec);
3966 return 1;
3967 }
6aa8b732
AK		 3968 return 0;
3969}
3970
a0861c02
AK		 3971/*
3972 * Trigger machine check on the host. We assume all the MSRs are already set up
3973 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3974 * We pass a fake environment to the machine check handler because we want
3975 * the guest to be always treated like user space, no matter what context
3976 * it used internally.
3977 */
3978static void kvm_machine_check(void)
3979{
3980#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3981 struct pt_regs regs = {
3982 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3983 .flags = X86_EFLAGS_IF,
3984 };
3985
3986 do_machine_check(&regs, 0);
3987#endif
3988}
3989
851ba692 3990static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3991{
3992 /* already handled by vcpu_run */
3993 return 1;
3994}
3995
851ba692 3996static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3997{
1155f76a 3998 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3999 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4000 u32 intr_info, ex_no, error_code;
42dbaa5a 4001 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4002 u32 vect_info;
4003 enum emulation_result er;
4004
1155f76a 4005 vect_info = vmx->idt_vectoring_info;
88786475 4006 intr_info = vmx->exit_intr_info;
6aa8b732 4007
a0861c02 4008 if (is_machine_check(intr_info))
851ba692 4009 return handle_machine_check(vcpu);
a0861c02 4010
6aa8b732 4011 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4012 !is_page_fault(intr_info)) {
4013 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4014 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4015 vcpu->run->internal.ndata = 2;
4016 vcpu->run->internal.data[0] = vect_info;
4017 vcpu->run->internal.data[1] = intr_info;
4018 return 0;
4019 }
6aa8b732 4020
e4a41889 4021 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4022 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4023
4024 if (is_no_device(intr_info)) {
5fd86fcf 4025 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4026 return 1;
4027 }
4028
7aa81cc0 4029 if (is_invalid_opcode(intr_info)) {
51d8b661 4030 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4031 if (er != EMULATE_DONE)
7ee5d940 4032 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4033 return 1;
4034 }
4035
6aa8b732 4036 error_code = 0;
2e11384c 4037 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4038 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4039 if (is_page_fault(intr_info)) {
1439442c 4040 /* EPT won't cause page fault directly */
089d034e 4041 if (enable_ept)
1439442c 4042 BUG();
6aa8b732 4043 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4044 trace_kvm_page_fault(cr2, error_code);
4045
3298b75c 4046 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4047 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4048 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4049 }
4050
7ffd92c5 4051 if (vmx->rmode.vm86_active &&
6aa8b732 4052 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4053 error_code)) {
ad312c7c
ZX		 4054 if (vcpu->arch.halt_request) {
4055 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4056 return kvm_emulate_halt(vcpu);
4057 }
6aa8b732 4058 return 1;
72d6e5a0 4059 }
6aa8b732 4060
d0bfb940 4061 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4062 switch (ex_no) {
4063 case DB_VECTOR:
4064 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4065 if (!(vcpu->guest_debug &
4066 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4067 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4068 kvm_queue_exception(vcpu, DB_VECTOR);
4069 return 1;
4070 }
4071 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4072 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4073 /* fall through */
4074 case BP_VECTOR:
c573cd22
JK		 4075 /*
4076 * Update instruction length as we may reinject #BP from
4077 * user space while in guest debugging mode. Reading it for
4078 * #DB as well causes no harm, it is not used in that case.
4079 */
4080 vmx->vcpu.arch.event_exit_inst_len =
4081 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4082 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4083 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4084 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4085 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4086 break;
4087 default:
d0bfb940
JK		 4088 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4089 kvm_run->ex.exception = ex_no;
4090 kvm_run->ex.error_code = error_code;
42dbaa5a 4091 break;
6aa8b732 4092 }
6aa8b732
AK		 4093 return 0;
4094}
4095
851ba692 4096static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4097{
1165f5fe 4098 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4099 return 1;
4100}
4101
851ba692 4102static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4103{
851ba692 4104 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4105 return 0;
4106}
6aa8b732 4107
851ba692 4108static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4109{
bfdaab09 4110 unsigned long exit_qualification;
34c33d16 4111 int size, in, string;
039576c0 4112 unsigned port;
6aa8b732 4113
bfdaab09 4114 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4115 string = (exit_qualification & 16) != 0;
cf8f70bf 4116 in = (exit_qualification & 8) != 0;
e70669ab 4117
cf8f70bf 4118 ++vcpu->stat.io_exits;
e70669ab 4119
cf8f70bf 4120 if (string || in)
51d8b661 4121 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4122
cf8f70bf
GN		 4123 port = exit_qualification >> 16;
4124 size = (exit_qualification & 7) + 1;
e93f36bc 4125 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4126
4127 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4128}
4129
102d8325
IM		 4130static void
4131vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4132{
4133 /*
4134 * Patch in the VMCALL instruction:
4135 */
4136 hypercall[0] = 0x0f;
4137 hypercall[1] = 0x01;
4138 hypercall[2] = 0xc1;
102d8325
IM		 4139}
4140
851ba692 4141static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4142{
229456fc 4143 unsigned long exit_qualification, val;
6aa8b732
AK		 4144 int cr;
4145 int reg;
49a9b07e 4146 int err;
6aa8b732 4147
bfdaab09 4148 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4149 cr = exit_qualification & 15;
4150 reg = (exit_qualification >> 8) & 15;
4151 switch ((exit_qualification >> 4) & 3) {
4152 case 0: /* mov to cr */
229456fc
MT		 4153 val = kvm_register_read(vcpu, reg);
4154 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4155 switch (cr) {
4156 case 0:
49a9b07e 4157 err = kvm_set_cr0(vcpu, val);
db8fcefa 4158 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4159 return 1;
4160 case 3:
2390218b 4161 err = kvm_set_cr3(vcpu, val);
db8fcefa 4162 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4163 return 1;
4164 case 4:
a83b29c6 4165 err = kvm_set_cr4(vcpu, val);
db8fcefa 4166 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4167 return 1;
0a5fff19
GN		 4168 case 8: {
4169 u8 cr8_prev = kvm_get_cr8(vcpu);
4170 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4171 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4172 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4173 if (irqchip_in_kernel(vcpu->kvm))
4174 return 1;
4175 if (cr8_prev <= cr8)
4176 return 1;
851ba692 4177 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4178 return 0;
4179 }
6aa8b732
AK		 4180 };
4181 break;
25c4c276 4182 case 2: /* clts */
edcafe3c 4183 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4184 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4185 skip_emulated_instruction(vcpu);
6b52d186 4186 vmx_fpu_activate(vcpu);
25c4c276 4187 return 1;
6aa8b732
AK		 4188 case 1: /*mov from cr*/
4189 switch (cr) {
4190 case 3:
9f8fe504
AK		 4191 val = kvm_read_cr3(vcpu);
4192 kvm_register_write(vcpu, reg, val);
4193 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4194 skip_emulated_instruction(vcpu);
4195 return 1;
4196 case 8:
229456fc
MT		 4197 val = kvm_get_cr8(vcpu);
4198 kvm_register_write(vcpu, reg, val);
4199 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4200 skip_emulated_instruction(vcpu);
4201 return 1;
4202 }
4203 break;
4204 case 3: /* lmsw */
a1f83a74 4205 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4206 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4207 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4208
4209 skip_emulated_instruction(vcpu);
4210 return 1;
4211 default:
4212 break;
4213 }
851ba692 4214 vcpu->run->exit_reason = 0;
f0242478 4215 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4216 (int)(exit_qualification >> 4) & 3, cr);
4217 return 0;
4218}
4219
851ba692 4220static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4221{
bfdaab09 4222 unsigned long exit_qualification;
6aa8b732
AK		 4223 int dr, reg;
4224
f2483415 4225 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4226 if (!kvm_require_cpl(vcpu, 0))
4227 return 1;
42dbaa5a
JK		 4228 dr = vmcs_readl(GUEST_DR7);
4229 if (dr & DR7_GD) {
4230 /*
4231 * As the vm-exit takes precedence over the debug trap, we
4232 * need to emulate the latter, either for the host or the
4233 * guest debugging itself.
4234 */
4235 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4236 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4237 vcpu->run->debug.arch.dr7 = dr;
4238 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4239 vmcs_readl(GUEST_CS_BASE) +
4240 vmcs_readl(GUEST_RIP);
851ba692
AK		 4241 vcpu->run->debug.arch.exception = DB_VECTOR;
4242 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4243 return 0;
4244 } else {
4245 vcpu->arch.dr7 &= ~DR7_GD;
4246 vcpu->arch.dr6 |= DR6_BD;
4247 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4248 kvm_queue_exception(vcpu, DB_VECTOR);
4249 return 1;
4250 }
4251 }
4252
bfdaab09 4253 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4254 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4255 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4256 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4257 unsigned long val;
4258 if (!kvm_get_dr(vcpu, dr, &val))
4259 kvm_register_write(vcpu, reg, val);
4260 } else
4261 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4262 skip_emulated_instruction(vcpu);
4263 return 1;
4264}
4265
020df079
GN		 4266static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4267{
4268 vmcs_writel(GUEST_DR7, val);
4269}
4270
851ba692 4271static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4272{
06465c5a
AK		 4273 kvm_emulate_cpuid(vcpu);
4274 return 1;
6aa8b732
AK		 4275}
4276
851ba692 4277static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4278{
ad312c7c 4279 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4280 u64 data;
4281
4282 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4283 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4284 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4285 return 1;
4286 }
4287
229456fc 4288 trace_kvm_msr_read(ecx, data);
2714d1d3 4289
6aa8b732 4290 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4291 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4292 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4293 skip_emulated_instruction(vcpu);
4294 return 1;
4295}
4296
851ba692 4297static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4298{
ad312c7c
ZX		 4299 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4300 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4301 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4302
4303 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4304 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4305 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4306 return 1;
4307 }
4308
59200273 4309 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4310 skip_emulated_instruction(vcpu);
4311 return 1;
4312}
4313
851ba692 4314static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4315{
3842d135 4316 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4317 return 1;
4318}
4319
851ba692 4320static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4321{
85f455f7
ED		 4322 u32 cpu_based_vm_exec_control;
4323
4324 /* clear pending irq */
4325 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4326 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4327 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4328
3842d135
AK		 4329 kvm_make_request(KVM_REQ_EVENT, vcpu);
4330
a26bf12a 4331 ++vcpu->stat.irq_window_exits;
2714d1d3 4332
c1150d8c
DL		 4333 /*
4334 * If the user space waits to inject interrupts, exit as soon as
4335 * possible
4336 */
8061823a 4337 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4338 vcpu->run->request_interrupt_window &&
8061823a 4339 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4340 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4341 return 0;
4342 }
6aa8b732
AK		 4343 return 1;
4344}
4345
851ba692 4346static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4347{
4348 skip_emulated_instruction(vcpu);
d3bef15f 4349 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4350}
4351
851ba692 4352static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4353{
510043da 4354 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4355 kvm_emulate_hypercall(vcpu);
4356 return 1;
c21415e8
IM		 4357}
4358
ec25d5e6
GN		 4359static int handle_invd(struct kvm_vcpu *vcpu)
4360{
51d8b661 4361 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4362}
4363
851ba692 4364static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4365{
f9c617f6 4366 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4367
4368 kvm_mmu_invlpg(vcpu, exit_qualification);
4369 skip_emulated_instruction(vcpu);
4370 return 1;
4371}
4372
851ba692 4373static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4374{
4375 skip_emulated_instruction(vcpu);
f5f48ee1 4376 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4377 return 1;
4378}
4379
2acf923e
DC		 4380static int handle_xsetbv(struct kvm_vcpu *vcpu)
4381{
4382 u64 new_bv = kvm_read_edx_eax(vcpu);
4383 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4384
4385 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4386 skip_emulated_instruction(vcpu);
4387 return 1;
4388}
4389
851ba692 4390static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4391{
51d8b661 4392 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4393}
4394
851ba692 4395static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4396{
60637aac 4397 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4398 unsigned long exit_qualification;
e269fb21
JK		 4399 bool has_error_code = false;
4400 u32 error_code = 0;
37817f29 4401 u16 tss_selector;
64a7ec06
GN		 4402 int reason, type, idt_v;
4403
4404 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4405 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4406
4407 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4408
4409 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4410 if (reason == TASK_SWITCH_GATE && idt_v) {
4411 switch (type) {
4412 case INTR_TYPE_NMI_INTR:
4413 vcpu->arch.nmi_injected = false;
654f06fc 4414 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4415 break;
4416 case INTR_TYPE_EXT_INTR:
66fd3f7f 4417 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4418 kvm_clear_interrupt_queue(vcpu);
4419 break;
4420 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4421 if (vmx->idt_vectoring_info &
4422 VECTORING_INFO_DELIVER_CODE_MASK) {
4423 has_error_code = true;
4424 error_code =
4425 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4426 }
4427 /* fall through */
64a7ec06
GN		 4428 case INTR_TYPE_SOFT_EXCEPTION:
4429 kvm_clear_exception_queue(vcpu);
4430 break;
4431 default:
4432 break;
4433 }
60637aac 4434 }
37817f29
IE		 4435 tss_selector = exit_qualification;
4436
64a7ec06
GN		 4437 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4438 type != INTR_TYPE_EXT_INTR &&
4439 type != INTR_TYPE_NMI_INTR))
4440 skip_emulated_instruction(vcpu);
4441
acb54517
GN		 4442 if (kvm_task_switch(vcpu, tss_selector, reason,
4443 has_error_code, error_code) == EMULATE_FAIL) {
4444 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4445 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4446 vcpu->run->internal.ndata = 0;
42dbaa5a 4447 return 0;
acb54517 4448 }
42dbaa5a
JK		 4449
4450 /* clear all local breakpoint enable flags */
4451 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4452
4453 /*
4454 * TODO: What about debug traps on tss switch?
4455 * Are we supposed to inject them and update dr6?
4456 */
4457
4458 return 1;
37817f29
IE		 4459}
4460
851ba692 4461static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4462{
f9c617f6 4463 unsigned long exit_qualification;
1439442c 4464 gpa_t gpa;
1439442c 4465 int gla_validity;
1439442c 4466
f9c617f6 4467 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4468
4469 if (exit_qualification & (1 << 6)) {
4470 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4471 return -EINVAL;
1439442c
SY		 4472 }
4473
4474 gla_validity = (exit_qualification >> 7) & 0x3;
4475 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4476 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4477 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4478 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4479 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4480 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4481 (long unsigned int)exit_qualification);
851ba692
AK		 4482 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4483 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4484 return 0;
1439442c
SY		 4485 }
4486
4487 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4488 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4489 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4490}
4491
68f89400
MT		 4492static u64 ept_rsvd_mask(u64 spte, int level)
4493{
4494 int i;
4495 u64 mask = 0;
4496
4497 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4498 mask |= (1ULL << i);
4499
4500 if (level > 2)
4501 /* bits 7:3 reserved */
4502 mask |= 0xf8;
4503 else if (level == 2) {
4504 if (spte & (1ULL << 7))
4505 /* 2MB ref, bits 20:12 reserved */
4506 mask |= 0x1ff000;
4507 else
4508 /* bits 6:3 reserved */
4509 mask |= 0x78;
4510 }
4511
4512 return mask;
4513}
4514
4515static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4516 int level)
4517{
4518 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4519
4520 /* 010b (write-only) */
4521 WARN_ON((spte & 0x7) == 0x2);
4522
4523 /* 110b (write/execute) */
4524 WARN_ON((spte & 0x7) == 0x6);
4525
4526 /* 100b (execute-only) and value not supported by logical processor */
4527 if (!cpu_has_vmx_ept_execute_only())
4528 WARN_ON((spte & 0x7) == 0x4);
4529
4530 /* not 000b */
4531 if ((spte & 0x7)) {
4532 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4533
4534 if (rsvd_bits != 0) {
4535 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4536 __func__, rsvd_bits);
4537 WARN_ON(1);
4538 }
4539
4540 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4541 u64 ept_mem_type = (spte & 0x38) >> 3;
4542
4543 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4544 ept_mem_type == 7) {
4545 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4546 __func__, ept_mem_type);
4547 WARN_ON(1);
4548 }
4549 }
4550 }
4551}
4552
851ba692 4553static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4554{
4555 u64 sptes[4];
4556 int nr_sptes, i;
4557 gpa_t gpa;
4558
4559 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4560
4561 printk(KERN_ERR "EPT: Misconfiguration.\n");
4562 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4563
4564 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4565
4566 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4567 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4568
851ba692
AK		 4569 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4570 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4571
4572 return 0;
4573}
4574
851ba692 4575static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4576{
4577 u32 cpu_based_vm_exec_control;
4578
4579 /* clear pending NMI */
4580 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4581 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4582 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4583 ++vcpu->stat.nmi_window_exits;
3842d135 4584 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4585
4586 return 1;
4587}
4588
80ced186 4589static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4590{
8b3079a5
AK		 4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
4592 enum emulation_result err = EMULATE_DONE;
80ced186 4593 int ret = 1;
49e9d557
AK		 4594 u32 cpu_exec_ctrl;
4595 bool intr_window_requested;
4596
4597 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4598 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4599
4600 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4601 if (intr_window_requested
4602 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4603 return handle_interrupt_window(&vmx->vcpu);
4604
51d8b661 4605 err = emulate_instruction(vcpu, 0);
ea953ef0 4606
80ced186
MG		 4607 if (err == EMULATE_DO_MMIO) {
4608 ret = 0;
4609 goto out;
4610 }
1d5a4d9b 4611
6d77dbfc
GN		 4612 if (err != EMULATE_DONE)
4613 return 0;
ea953ef0
MG		 4614
4615 if (signal_pending(current))
80ced186 4616 goto out;
ea953ef0
MG		 4617 if (need_resched())
4618 schedule();
4619 }
4620
80ced186
MG		 4621 vmx->emulation_required = 0;
4622out:
4623 return ret;
ea953ef0
MG		 4624}
4625
4b8d54f9
ZE		 4626/*
4627 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4628 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4629 */
9fb41ba8 4630static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4631{
4632 skip_emulated_instruction(vcpu);
4633 kvm_vcpu_on_spin(vcpu);
4634
4635 return 1;
4636}
4637
59708670
SY		 4638static int handle_invalid_op(struct kvm_vcpu *vcpu)
4639{
4640 kvm_queue_exception(vcpu, UD_VECTOR);
4641 return 1;
4642}
4643
ff2f6fe9
NHE		 4644/*
4645 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4646 * We could reuse a single VMCS for all the L2 guests, but we also want the
4647 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4648 * allows keeping them loaded on the processor, and in the future will allow
4649 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4650 * every entry if they never change.
4651 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4652 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4653 *
4654 * The following functions allocate and free a vmcs02 in this pool.
4655 */
4656
4657/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4658static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4659{
4660 struct vmcs02_list *item;
4661 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4662 if (item->vmptr == vmx->nested.current_vmptr) {
4663 list_move(&item->list, &vmx->nested.vmcs02_pool);
4664 return &item->vmcs02;
4665 }
4666
4667 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4668 /* Recycle the least recently used VMCS. */
4669 item = list_entry(vmx->nested.vmcs02_pool.prev,
4670 struct vmcs02_list, list);
4671 item->vmptr = vmx->nested.current_vmptr;
4672 list_move(&item->list, &vmx->nested.vmcs02_pool);
4673 return &item->vmcs02;
4674 }
4675
4676 /* Create a new VMCS */
4677 item = (struct vmcs02_list *)
4678 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4679 if (!item)
4680 return NULL;
4681 item->vmcs02.vmcs = alloc_vmcs();
4682 if (!item->vmcs02.vmcs) {
4683 kfree(item);
4684 return NULL;
4685 }
4686 loaded_vmcs_init(&item->vmcs02);
4687 item->vmptr = vmx->nested.current_vmptr;
4688 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4689 vmx->nested.vmcs02_num++;
4690 return &item->vmcs02;
4691}
4692
4693/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4694static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4695{
4696 struct vmcs02_list *item;
4697 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4698 if (item->vmptr == vmptr) {
4699 free_loaded_vmcs(&item->vmcs02);
4700 list_del(&item->list);
4701 kfree(item);
4702 vmx->nested.vmcs02_num--;
4703 return;
4704 }
4705}
4706
4707/*
4708 * Free all VMCSs saved for this vcpu, except the one pointed by
4709 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4710 * currently used, if running L2), and vmcs01 when running L2.
4711 */
4712static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4713{
4714 struct vmcs02_list *item, *n;
4715 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4716 if (vmx->loaded_vmcs != &item->vmcs02)
4717 free_loaded_vmcs(&item->vmcs02);
4718 list_del(&item->list);
4719 kfree(item);
4720 }
4721 vmx->nested.vmcs02_num = 0;
4722
4723 if (vmx->loaded_vmcs != &vmx->vmcs01)
4724 free_loaded_vmcs(&vmx->vmcs01);
4725}
4726
ec378aee
NHE		 4727/*
4728 * Emulate the VMXON instruction.
4729 * Currently, we just remember that VMX is active, and do not save or even
4730 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4731 * do not currently need to store anything in that guest-allocated memory
4732 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4733 * argument is different from the VMXON pointer (which the spec says they do).
4734 */
4735static int handle_vmon(struct kvm_vcpu *vcpu)
4736{
4737 struct kvm_segment cs;
4738 struct vcpu_vmx *vmx = to_vmx(vcpu);
4739
4740 /* The Intel VMX Instruction Reference lists a bunch of bits that
4741 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4742 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4743 * Otherwise, we should fail with #UD. We test these now:
4744 */
4745 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4746 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4747 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4748 kvm_queue_exception(vcpu, UD_VECTOR);
4749 return 1;
4750 }
4751
4752 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4753 if (is_long_mode(vcpu) && !cs.l) {
4754 kvm_queue_exception(vcpu, UD_VECTOR);
4755 return 1;
4756 }
4757
4758 if (vmx_get_cpl(vcpu)) {
4759 kvm_inject_gp(vcpu, 0);
4760 return 1;
4761 }
4762
ff2f6fe9
NHE		 4763 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4764 vmx->nested.vmcs02_num = 0;
4765
ec378aee
NHE		 4766 vmx->nested.vmxon = true;
4767
4768 skip_emulated_instruction(vcpu);
4769 return 1;
4770}
4771
4772/*
4773 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4774 * for running VMX instructions (except VMXON, whose prerequisites are
4775 * slightly different). It also specifies what exception to inject otherwise.
4776 */
4777static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4778{
4779 struct kvm_segment cs;
4780 struct vcpu_vmx *vmx = to_vmx(vcpu);
4781
4782 if (!vmx->nested.vmxon) {
4783 kvm_queue_exception(vcpu, UD_VECTOR);
4784 return 0;
4785 }
4786
4787 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4788 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4789 (is_long_mode(vcpu) && !cs.l)) {
4790 kvm_queue_exception(vcpu, UD_VECTOR);
4791 return 0;
4792 }
4793
4794 if (vmx_get_cpl(vcpu)) {
4795 kvm_inject_gp(vcpu, 0);
4796 return 0;
4797 }
4798
4799 return 1;
4800}
4801
4802/*
4803 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4804 * just stops using VMX.
4805 */
4806static void free_nested(struct vcpu_vmx *vmx)
4807{
4808 if (!vmx->nested.vmxon)
4809 return;
4810 vmx->nested.vmxon = false;
a9d30f33
NHE		 4811 if (vmx->nested.current_vmptr != -1ull) {
4812 kunmap(vmx->nested.current_vmcs12_page);
4813 nested_release_page(vmx->nested.current_vmcs12_page);
4814 vmx->nested.current_vmptr = -1ull;
4815 vmx->nested.current_vmcs12 = NULL;
4816 }
fe3ef05c
NHE		 4817 /* Unpin physical memory we referred to in current vmcs02 */
4818 if (vmx->nested.apic_access_page) {
4819 nested_release_page(vmx->nested.apic_access_page);
4820 vmx->nested.apic_access_page = 0;
4821 }
ff2f6fe9
NHE		 4822
4823 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4824}
4825
4826/* Emulate the VMXOFF instruction */
4827static int handle_vmoff(struct kvm_vcpu *vcpu)
4828{
4829 if (!nested_vmx_check_permission(vcpu))
4830 return 1;
4831 free_nested(to_vmx(vcpu));
4832 skip_emulated_instruction(vcpu);
4833 return 1;
4834}
4835
064aea77
NHE		 4836/*
4837 * Decode the memory-address operand of a vmx instruction, as recorded on an
4838 * exit caused by such an instruction (run by a guest hypervisor).
4839 * On success, returns 0. When the operand is invalid, returns 1 and throws
4840 * #UD or #GP.
4841 */
4842static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4843 unsigned long exit_qualification,
4844 u32 vmx_instruction_info, gva_t *ret)
4845{
4846 /*
4847 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4848 * Execution", on an exit, vmx_instruction_info holds most of the
4849 * addressing components of the operand. Only the displacement part
4850 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4851 * For how an actual address is calculated from all these components,
4852 * refer to Vol. 1, "Operand Addressing".
4853 */
4854 int scaling = vmx_instruction_info & 3;
4855 int addr_size = (vmx_instruction_info >> 7) & 7;
4856 bool is_reg = vmx_instruction_info & (1u << 10);
4857 int seg_reg = (vmx_instruction_info >> 15) & 7;
4858 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4859 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4860 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4861 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4862
4863 if (is_reg) {
4864 kvm_queue_exception(vcpu, UD_VECTOR);
4865 return 1;
4866 }
4867
4868 /* Addr = segment_base + offset */
4869 /* offset = base + [index * scale] + displacement */
4870 *ret = vmx_get_segment_base(vcpu, seg_reg);
4871 if (base_is_valid)
4872 *ret += kvm_register_read(vcpu, base_reg);
4873 if (index_is_valid)
4874 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4875 *ret += exit_qualification; /* holds the displacement */
4876
4877 if (addr_size == 1) /* 32 bit */
4878 *ret &= 0xffffffff;
4879
4880 /*
4881 * TODO: throw #GP (and return 1) in various cases that the VM*
4882 * instructions require it - e.g., offset beyond segment limit,
4883 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4884 * address, and so on. Currently these are not checked.
4885 */
4886 return 0;
4887}
4888
0140caea
NHE		 4889/*
4890 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4891 * set the success or error code of an emulated VMX instruction, as specified
4892 * by Vol 2B, VMX Instruction Reference, "Conventions".
4893 */
4894static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4895{
4896 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4897 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4898 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4899}
4900
4901static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4902{
4903 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4904 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4905 X86_EFLAGS_SF | X86_EFLAGS_OF))
4906 | X86_EFLAGS_CF);
4907}
4908
4909static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4910 u32 vm_instruction_error)
4911{
4912 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4913 /*
4914 * failValid writes the error number to the current VMCS, which
4915 * can't be done there isn't a current VMCS.
4916 */
4917 nested_vmx_failInvalid(vcpu);
4918 return;
4919 }
4920 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4921 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4922 X86_EFLAGS_SF | X86_EFLAGS_OF))
4923 | X86_EFLAGS_ZF);
4924 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4925}
4926
27d6c865
NHE		 4927/* Emulate the VMCLEAR instruction */
4928static int handle_vmclear(struct kvm_vcpu *vcpu)
4929{
4930 struct vcpu_vmx *vmx = to_vmx(vcpu);
4931 gva_t gva;
4932 gpa_t vmptr;
4933 struct vmcs12 *vmcs12;
4934 struct page *page;
4935 struct x86_exception e;
4936
4937 if (!nested_vmx_check_permission(vcpu))
4938 return 1;
4939
4940 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4941 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4942 return 1;
4943
4944 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4945 sizeof(vmptr), &e)) {
4946 kvm_inject_page_fault(vcpu, &e);
4947 return 1;
4948 }
4949
4950 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4951 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4952 skip_emulated_instruction(vcpu);
4953 return 1;
4954 }
4955
4956 if (vmptr == vmx->nested.current_vmptr) {
4957 kunmap(vmx->nested.current_vmcs12_page);
4958 nested_release_page(vmx->nested.current_vmcs12_page);
4959 vmx->nested.current_vmptr = -1ull;
4960 vmx->nested.current_vmcs12 = NULL;
4961 }
4962
4963 page = nested_get_page(vcpu, vmptr);
4964 if (page == NULL) {
4965 /*
4966 * For accurate processor emulation, VMCLEAR beyond available
4967 * physical memory should do nothing at all. However, it is
4968 * possible that a nested vmx bug, not a guest hypervisor bug,
4969 * resulted in this case, so let's shut down before doing any
4970 * more damage:
4971 */
4972 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4973 return 1;
4974 }
4975 vmcs12 = kmap(page);
4976 vmcs12->launch_state = 0;
4977 kunmap(page);
4978 nested_release_page(page);
4979
4980 nested_free_vmcs02(vmx, vmptr);
4981
4982 skip_emulated_instruction(vcpu);
4983 nested_vmx_succeed(vcpu);
4984 return 1;
4985}
4986
cd232ad0
NHE		 4987static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
4988
4989/* Emulate the VMLAUNCH instruction */
4990static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4991{
4992 return nested_vmx_run(vcpu, true);
4993}
4994
4995/* Emulate the VMRESUME instruction */
4996static int handle_vmresume(struct kvm_vcpu *vcpu)
4997{
4998
4999 return nested_vmx_run(vcpu, false);
5000}
5001
49f705c5
NHE		 5002enum vmcs_field_type {
5003 VMCS_FIELD_TYPE_U16 = 0,
5004 VMCS_FIELD_TYPE_U64 = 1,
5005 VMCS_FIELD_TYPE_U32 = 2,
5006 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5007};
5008
5009static inline int vmcs_field_type(unsigned long field)
5010{
5011 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5012 return VMCS_FIELD_TYPE_U32;
5013 return (field >> 13) & 0x3 ;
5014}
5015
5016static inline int vmcs_field_readonly(unsigned long field)
5017{
5018 return (((field >> 10) & 0x3) == 1);
5019}
5020
5021/*
5022 * Read a vmcs12 field. Since these can have varying lengths and we return
5023 * one type, we chose the biggest type (u64) and zero-extend the return value
5024 * to that size. Note that the caller, handle_vmread, might need to use only
5025 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5026 * 64-bit fields are to be returned).
5027 */
5028static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5029 unsigned long field, u64 *ret)
5030{
5031 short offset = vmcs_field_to_offset(field);
5032 char *p;
5033
5034 if (offset < 0)
5035 return 0;
5036
5037 p = ((char *)(get_vmcs12(vcpu))) + offset;
5038
5039 switch (vmcs_field_type(field)) {
5040 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5041 *ret = *((natural_width *)p);
5042 return 1;
5043 case VMCS_FIELD_TYPE_U16:
5044 *ret = *((u16 *)p);
5045 return 1;
5046 case VMCS_FIELD_TYPE_U32:
5047 *ret = *((u32 *)p);
5048 return 1;
5049 case VMCS_FIELD_TYPE_U64:
5050 *ret = *((u64 *)p);
5051 return 1;
5052 default:
5053 return 0; /* can never happen. */
5054 }
5055}
5056
5057/*
5058 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5059 * used before) all generate the same failure when it is missing.
5060 */
5061static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5062{
5063 struct vcpu_vmx *vmx = to_vmx(vcpu);
5064 if (vmx->nested.current_vmptr == -1ull) {
5065 nested_vmx_failInvalid(vcpu);
5066 skip_emulated_instruction(vcpu);
5067 return 0;
5068 }
5069 return 1;
5070}
5071
5072static int handle_vmread(struct kvm_vcpu *vcpu)
5073{
5074 unsigned long field;
5075 u64 field_value;
5076 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5077 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5078 gva_t gva = 0;
5079
5080 if (!nested_vmx_check_permission(vcpu) ||
5081 !nested_vmx_check_vmcs12(vcpu))
5082 return 1;
5083
5084 /* Decode instruction info and find the field to read */
5085 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5086 /* Read the field, zero-extended to a u64 field_value */
5087 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5088 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5089 skip_emulated_instruction(vcpu);
5090 return 1;
5091 }
5092 /*
5093 * Now copy part of this value to register or memory, as requested.
5094 * Note that the number of bits actually copied is 32 or 64 depending
5095 * on the guest's mode (32 or 64 bit), not on the given field's length.
5096 */
5097 if (vmx_instruction_info & (1u << 10)) {
5098 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5099 field_value);
5100 } else {
5101 if (get_vmx_mem_address(vcpu, exit_qualification,
5102 vmx_instruction_info, &gva))
5103 return 1;
5104 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5105 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5106 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5107 }
5108
5109 nested_vmx_succeed(vcpu);
5110 skip_emulated_instruction(vcpu);
5111 return 1;
5112}
5113
5114
5115static int handle_vmwrite(struct kvm_vcpu *vcpu)
5116{
5117 unsigned long field;
5118 gva_t gva;
5119 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5120 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5121 char *p;
5122 short offset;
5123 /* The value to write might be 32 or 64 bits, depending on L1's long
5124 * mode, and eventually we need to write that into a field of several
5125 * possible lengths. The code below first zero-extends the value to 64
5126 * bit (field_value), and then copies only the approriate number of
5127 * bits into the vmcs12 field.
5128 */
5129 u64 field_value = 0;
5130 struct x86_exception e;
5131
5132 if (!nested_vmx_check_permission(vcpu) ||
5133 !nested_vmx_check_vmcs12(vcpu))
5134 return 1;
5135
5136 if (vmx_instruction_info & (1u << 10))
5137 field_value = kvm_register_read(vcpu,
5138 (((vmx_instruction_info) >> 3) & 0xf));
5139 else {
5140 if (get_vmx_mem_address(vcpu, exit_qualification,
5141 vmx_instruction_info, &gva))
5142 return 1;
5143 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5144 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5145 kvm_inject_page_fault(vcpu, &e);
5146 return 1;
5147 }
5148 }
5149
5150
5151 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5152 if (vmcs_field_readonly(field)) {
5153 nested_vmx_failValid(vcpu,
5154 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5155 skip_emulated_instruction(vcpu);
5156 return 1;
5157 }
5158
5159 offset = vmcs_field_to_offset(field);
5160 if (offset < 0) {
5161 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5162 skip_emulated_instruction(vcpu);
5163 return 1;
5164 }
5165 p = ((char *) get_vmcs12(vcpu)) + offset;
5166
5167 switch (vmcs_field_type(field)) {
5168 case VMCS_FIELD_TYPE_U16:
5169 *(u16 *)p = field_value;
5170 break;
5171 case VMCS_FIELD_TYPE_U32:
5172 *(u32 *)p = field_value;
5173 break;
5174 case VMCS_FIELD_TYPE_U64:
5175 *(u64 *)p = field_value;
5176 break;
5177 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5178 *(natural_width *)p = field_value;
5179 break;
5180 default:
5181 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5182 skip_emulated_instruction(vcpu);
5183 return 1;
5184 }
5185
5186 nested_vmx_succeed(vcpu);
5187 skip_emulated_instruction(vcpu);
5188 return 1;
5189}
5190
63846663
NHE		 5191/* Emulate the VMPTRLD instruction */
5192static int handle_vmptrld(struct kvm_vcpu *vcpu)
5193{
5194 struct vcpu_vmx *vmx = to_vmx(vcpu);
5195 gva_t gva;
5196 gpa_t vmptr;
5197 struct x86_exception e;
5198
5199 if (!nested_vmx_check_permission(vcpu))
5200 return 1;
5201
5202 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5203 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5204 return 1;
5205
5206 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5207 sizeof(vmptr), &e)) {
5208 kvm_inject_page_fault(vcpu, &e);
5209 return 1;
5210 }
5211
5212 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5213 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5214 skip_emulated_instruction(vcpu);
5215 return 1;
5216 }
5217
5218 if (vmx->nested.current_vmptr != vmptr) {
5219 struct vmcs12 *new_vmcs12;
5220 struct page *page;
5221 page = nested_get_page(vcpu, vmptr);
5222 if (page == NULL) {
5223 nested_vmx_failInvalid(vcpu);
5224 skip_emulated_instruction(vcpu);
5225 return 1;
5226 }
5227 new_vmcs12 = kmap(page);
5228 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5229 kunmap(page);
5230 nested_release_page_clean(page);
5231 nested_vmx_failValid(vcpu,
5232 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5233 skip_emulated_instruction(vcpu);
5234 return 1;
5235 }
5236 if (vmx->nested.current_vmptr != -1ull) {
5237 kunmap(vmx->nested.current_vmcs12_page);
5238 nested_release_page(vmx->nested.current_vmcs12_page);
5239 }
5240
5241 vmx->nested.current_vmptr = vmptr;
5242 vmx->nested.current_vmcs12 = new_vmcs12;
5243 vmx->nested.current_vmcs12_page = page;
5244 }
5245
5246 nested_vmx_succeed(vcpu);
5247 skip_emulated_instruction(vcpu);
5248 return 1;
5249}
5250
6a4d7550
NHE		 5251/* Emulate the VMPTRST instruction */
5252static int handle_vmptrst(struct kvm_vcpu *vcpu)
5253{
5254 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5255 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5256 gva_t vmcs_gva;
5257 struct x86_exception e;
5258
5259 if (!nested_vmx_check_permission(vcpu))
5260 return 1;
5261
5262 if (get_vmx_mem_address(vcpu, exit_qualification,
5263 vmx_instruction_info, &vmcs_gva))
5264 return 1;
5265 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5266 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5267 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5268 sizeof(u64), &e)) {
5269 kvm_inject_page_fault(vcpu, &e);
5270 return 1;
5271 }
5272 nested_vmx_succeed(vcpu);
5273 skip_emulated_instruction(vcpu);
5274 return 1;
5275}
5276
6aa8b732
AK		 5277/*
5278 * The exit handlers return 1 if the exit was handled fully and guest execution
5279 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5280 * to be done to userspace and return 0.
5281 */
851ba692 5282static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5283 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5284 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5285 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5286 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5287 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5288 [EXIT_REASON_CR_ACCESS] = handle_cr,
5289 [EXIT_REASON_DR_ACCESS] = handle_dr,
5290 [EXIT_REASON_CPUID] = handle_cpuid,
5291 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5292 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5293 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5294 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5295 [EXIT_REASON_INVD] = handle_invd,
a7052897 5296 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5297 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5298 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5299 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5300 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5301 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5302 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5303 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5304 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5305 [EXIT_REASON_VMOFF] = handle_vmoff,
5306 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5307 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5308 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5309 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5310 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5311 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5312 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5313 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5314 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5315 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5316 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5317 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5318};
5319
5320static const int kvm_vmx_max_exit_handlers =
50a3485c 5321 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5322
644d711a
NHE		 5323/*
5324 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5325 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5326 * disinterest in the current event (read or write a specific MSR) by using an
5327 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5328 */
5329static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5330 struct vmcs12 *vmcs12, u32 exit_reason)
5331{
5332 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5333 gpa_t bitmap;
5334
5335 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5336 return 1;
5337
5338 /*
5339 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5340 * for the four combinations of read/write and low/high MSR numbers.
5341 * First we need to figure out which of the four to use:
5342 */
5343 bitmap = vmcs12->msr_bitmap;
5344 if (exit_reason == EXIT_REASON_MSR_WRITE)
5345 bitmap += 2048;
5346 if (msr_index >= 0xc0000000) {
5347 msr_index -= 0xc0000000;
5348 bitmap += 1024;
5349 }
5350
5351 /* Then read the msr_index'th bit from this bitmap: */
5352 if (msr_index < 1024*8) {
5353 unsigned char b;
5354 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5355 return 1 & (b >> (msr_index & 7));
5356 } else
5357 return 1; /* let L1 handle the wrong parameter */
5358}
5359
5360/*
5361 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5362 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5363 * intercept (via guest_host_mask etc.) the current event.
5364 */
5365static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5366 struct vmcs12 *vmcs12)
5367{
5368 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5369 int cr = exit_qualification & 15;
5370 int reg = (exit_qualification >> 8) & 15;
5371 unsigned long val = kvm_register_read(vcpu, reg);
5372
5373 switch ((exit_qualification >> 4) & 3) {
5374 case 0: /* mov to cr */
5375 switch (cr) {
5376 case 0:
5377 if (vmcs12->cr0_guest_host_mask &
5378 (val ^ vmcs12->cr0_read_shadow))
5379 return 1;
5380 break;
5381 case 3:
5382 if ((vmcs12->cr3_target_count >= 1 &&
5383 vmcs12->cr3_target_value0 == val) ||
5384 (vmcs12->cr3_target_count >= 2 &&
5385 vmcs12->cr3_target_value1 == val) ||
5386 (vmcs12->cr3_target_count >= 3 &&
5387 vmcs12->cr3_target_value2 == val) ||
5388 (vmcs12->cr3_target_count >= 4 &&
5389 vmcs12->cr3_target_value3 == val))
5390 return 0;
5391 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5392 return 1;
5393 break;
5394 case 4:
5395 if (vmcs12->cr4_guest_host_mask &
5396 (vmcs12->cr4_read_shadow ^ val))
5397 return 1;
5398 break;
5399 case 8:
5400 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5401 return 1;
5402 break;
5403 }
5404 break;
5405 case 2: /* clts */
5406 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5407 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5408 return 1;
5409 break;
5410 case 1: /* mov from cr */
5411 switch (cr) {
5412 case 3:
5413 if (vmcs12->cpu_based_vm_exec_control &
5414 CPU_BASED_CR3_STORE_EXITING)
5415 return 1;
5416 break;
5417 case 8:
5418 if (vmcs12->cpu_based_vm_exec_control &
5419 CPU_BASED_CR8_STORE_EXITING)
5420 return 1;
5421 break;
5422 }
5423 break;
5424 case 3: /* lmsw */
5425 /*
5426 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5427 * cr0. Other attempted changes are ignored, with no exit.
5428 */
5429 if (vmcs12->cr0_guest_host_mask & 0xe &
5430 (val ^ vmcs12->cr0_read_shadow))
5431 return 1;
5432 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5433 !(vmcs12->cr0_read_shadow & 0x1) &&
5434 (val & 0x1))
5435 return 1;
5436 break;
5437 }
5438 return 0;
5439}
5440
5441/*
5442 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5443 * should handle it ourselves in L0 (and then continue L2). Only call this
5444 * when in is_guest_mode (L2).
5445 */
5446static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5447{
5448 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5449 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5450 struct vcpu_vmx *vmx = to_vmx(vcpu);
5451 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5452
5453 if (vmx->nested.nested_run_pending)
5454 return 0;
5455
5456 if (unlikely(vmx->fail)) {
5457 printk(KERN_INFO "%s failed vm entry %x\n",
5458 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5459 return 1;
5460 }
5461
5462 switch (exit_reason) {
5463 case EXIT_REASON_EXCEPTION_NMI:
5464 if (!is_exception(intr_info))
5465 return 0;
5466 else if (is_page_fault(intr_info))
5467 return enable_ept;
5468 return vmcs12->exception_bitmap &
5469 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5470 case EXIT_REASON_EXTERNAL_INTERRUPT:
5471 return 0;
5472 case EXIT_REASON_TRIPLE_FAULT:
5473 return 1;
5474 case EXIT_REASON_PENDING_INTERRUPT:
5475 case EXIT_REASON_NMI_WINDOW:
5476 /*
5477 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5478 * (aka Interrupt Window Exiting) only when L1 turned it on,
5479 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5480 * Same for NMI Window Exiting.
5481 */
5482 return 1;
5483 case EXIT_REASON_TASK_SWITCH:
5484 return 1;
5485 case EXIT_REASON_CPUID:
5486 return 1;
5487 case EXIT_REASON_HLT:
5488 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5489 case EXIT_REASON_INVD:
5490 return 1;
5491 case EXIT_REASON_INVLPG:
5492 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5493 case EXIT_REASON_RDPMC:
5494 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5495 case EXIT_REASON_RDTSC:
5496 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5497 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5498 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5499 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5500 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5501 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5502 /*
5503 * VMX instructions trap unconditionally. This allows L1 to
5504 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5505 */
5506 return 1;
5507 case EXIT_REASON_CR_ACCESS:
5508 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5509 case EXIT_REASON_DR_ACCESS:
5510 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5511 case EXIT_REASON_IO_INSTRUCTION:
5512 /* TODO: support IO bitmaps */
5513 return 1;
5514 case EXIT_REASON_MSR_READ:
5515 case EXIT_REASON_MSR_WRITE:
5516 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5517 case EXIT_REASON_INVALID_STATE:
5518 return 1;
5519 case EXIT_REASON_MWAIT_INSTRUCTION:
5520 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5521 case EXIT_REASON_MONITOR_INSTRUCTION:
5522 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5523 case EXIT_REASON_PAUSE_INSTRUCTION:
5524 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5525 nested_cpu_has2(vmcs12,
5526 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5527 case EXIT_REASON_MCE_DURING_VMENTRY:
5528 return 0;
5529 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5530 return 1;
5531 case EXIT_REASON_APIC_ACCESS:
5532 return nested_cpu_has2(vmcs12,
5533 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5534 case EXIT_REASON_EPT_VIOLATION:
5535 case EXIT_REASON_EPT_MISCONFIG:
5536 return 0;
5537 case EXIT_REASON_WBINVD:
5538 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5539 case EXIT_REASON_XSETBV:
5540 return 1;
5541 default:
5542 return 1;
5543 }
5544}
5545
586f9607
AK		 5546static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5547{
5548 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5549 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5550}
5551
6aa8b732
AK		 5552/*
5553 * The guest has exited. See if we can fix it or if we need userspace
5554 * assistance.
5555 */
851ba692 5556static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5557{
29bd8a78 5558 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5559 u32 exit_reason = vmx->exit_reason;
1155f76a 5560 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5561
aa17911e 5562 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5563
80ced186
MG		 5564 /* If guest state is invalid, start emulating */
5565 if (vmx->emulation_required && emulate_invalid_guest_state)
5566 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5567
b6f1250e
NHE		 5568 /*
5569 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5570 * we did not inject a still-pending event to L1 now because of
5571 * nested_run_pending, we need to re-enable this bit.
5572 */
5573 if (vmx->nested.nested_run_pending)
5574 kvm_make_request(KVM_REQ_EVENT, vcpu);
5575
644d711a
NHE		 5576 if (exit_reason == EXIT_REASON_VMLAUNCH ||
5577 exit_reason == EXIT_REASON_VMRESUME)
5578 vmx->nested.nested_run_pending = 1;
5579 else
5580 vmx->nested.nested_run_pending = 0;
5581
5582 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5583 nested_vmx_vmexit(vcpu);
5584 return 1;
5585 }
5586
5120702e
MG		 5587 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5588 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5589 vcpu->run->fail_entry.hardware_entry_failure_reason
5590 = exit_reason;
5591 return 0;
5592 }
5593
29bd8a78 5594 if (unlikely(vmx->fail)) {
851ba692
AK		 5595 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5596 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5597 = vmcs_read32(VM_INSTRUCTION_ERROR);
5598 return 0;
5599 }
6aa8b732 5600
d77c26fc 5601 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5602 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5603 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5604 exit_reason != EXIT_REASON_TASK_SWITCH))
5605 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5606 "(0x%x) and exit reason is 0x%x\n",
5607 __func__, vectoring_info, exit_reason);
3b86cd99 5608
644d711a
NHE		 5609 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5610 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5611 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5612 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5613 vmx->soft_vnmi_blocked = 0;
3b86cd99 5614 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5615 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5616 /*
5617 * This CPU don't support us in finding the end of an
5618 * NMI-blocked window if the guest runs with IRQs
5619 * disabled. So we pull the trigger after 1 s of
5620 * futile waiting, but inform the user about this.
5621 */
5622 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5623 "state on VCPU %d after 1 s timeout\n",
5624 __func__, vcpu->vcpu_id);
5625 vmx->soft_vnmi_blocked = 0;
3b86cd99 5626 }
3b86cd99
JK		 5627 }
5628
6aa8b732
AK		 5629 if (exit_reason < kvm_vmx_max_exit_handlers
5630 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5631 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5632 else {
851ba692
AK		 5633 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5634 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5635 }
5636 return 0;
5637}
5638
95ba8273 5639static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5640{
95ba8273 5641 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5642 vmcs_write32(TPR_THRESHOLD, 0);
5643 return;
5644 }
5645
95ba8273 5646 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5647}
5648
51aa01d1 5649static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5650{
00eba012
AK		 5651 u32 exit_intr_info;
5652
5653 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5654 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5655 return;
5656
c5ca8e57 5657 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5658 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5659
5660 /* Handle machine checks before interrupts are enabled */
00eba012 5661 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5662 kvm_machine_check();
5663
20f65983 5664 /* We need to handle NMIs before interrupts are enabled */
00eba012 5665 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5666 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5667 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5668 asm("int $2");
ff9d07a0
ZY		 5669 kvm_after_handle_nmi(&vmx->vcpu);
5670 }
51aa01d1 5671}
20f65983 5672
51aa01d1
AK		 5673static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5674{
c5ca8e57 5675 u32 exit_intr_info;
51aa01d1
AK		 5676 bool unblock_nmi;
5677 u8 vector;
5678 bool idtv_info_valid;
5679
5680 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5681
cf393f75 5682 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5683 if (vmx->nmi_known_unmasked)
5684 return;
c5ca8e57
AK		 5685 /*
5686 * Can't use vmx->exit_intr_info since we're not sure what
5687 * the exit reason is.
5688 */
5689 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5690 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5691 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5692 /*
7b4a25cb 5693 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5694 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5695 * a guest IRET fault.
7b4a25cb
GN		 5696 * SDM 3: 23.2.2 (September 2008)
5697 * Bit 12 is undefined in any of the following cases:
5698 * If the VM exit sets the valid bit in the IDT-vectoring
5699 * information field.
5700 * If the VM exit is due to a double fault.
cf393f75 5701 */
7b4a25cb
GN		 5702 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5703 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5704 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5705 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5706 else
5707 vmx->nmi_known_unmasked =
5708 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5709 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5710 } else if (unlikely(vmx->soft_vnmi_blocked))
5711 vmx->vnmi_blocked_time +=
5712 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5713}
5714
83422e17
AK		 5715static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5716 u32 idt_vectoring_info,
5717 int instr_len_field,
5718 int error_code_field)
51aa01d1 5719{
51aa01d1
AK		 5720 u8 vector;
5721 int type;
5722 bool idtv_info_valid;
5723
5724 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5725
37b96e98
GN		 5726 vmx->vcpu.arch.nmi_injected = false;
5727 kvm_clear_exception_queue(&vmx->vcpu);
5728 kvm_clear_interrupt_queue(&vmx->vcpu);
5729
5730 if (!idtv_info_valid)
5731 return;
5732
3842d135
AK		 5733 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5734
668f612f
AK		 5735 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5736 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5737
64a7ec06 5738 switch (type) {
37b96e98
GN		 5739 case INTR_TYPE_NMI_INTR:
5740 vmx->vcpu.arch.nmi_injected = true;
668f612f 5741 /*
7b4a25cb 5742 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5743 * Clear bit "block by NMI" before VM entry if a NMI
5744 * delivery faulted.
668f612f 5745 */
654f06fc 5746 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5747 break;
37b96e98 5748 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5749 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5750 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5751 /* fall through */
5752 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5753 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5754 u32 err = vmcs_read32(error_code_field);
37b96e98 5755 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5756 } else
5757 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5758 break;
66fd3f7f
GN		 5759 case INTR_TYPE_SOFT_INTR:
5760 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5761 vmcs_read32(instr_len_field);
66fd3f7f 5762 /* fall through */
37b96e98 5763 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5764 kvm_queue_interrupt(&vmx->vcpu, vector,
5765 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5766 break;
5767 default:
5768 break;
f7d9238f 5769 }
cf393f75
AK		 5770}
5771
83422e17
AK		 5772static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5773{
5774 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5775 VM_EXIT_INSTRUCTION_LEN,
5776 IDT_VECTORING_ERROR_CODE);
5777}
5778
b463a6f7
AK		 5779static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5780{
5781 __vmx_complete_interrupts(to_vmx(vcpu),
5782 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5783 VM_ENTRY_INSTRUCTION_LEN,
5784 VM_ENTRY_EXCEPTION_ERROR_CODE);
5785
5786 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5787}
5788
c801949d
AK		 5789#ifdef CONFIG_X86_64
5790#define R "r"
5791#define Q "q"
5792#else
5793#define R "e"
5794#define Q "l"
5795#endif
5796
a3b5ba49 5797static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5798{
a2fa3e9f 5799 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 5800
5801 /* Record the guest's net vcpu time for enforced NMI injections. */
5802 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5803 vmx->entry_time = ktime_get();
5804
5805 /* Don't enter VMX if guest state is invalid, let the exit handler
5806 start emulation until we arrive back to a valid state */
5807 if (vmx->emulation_required && emulate_invalid_guest_state)
5808 return;
5809
5810 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5811 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5812 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5813 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5814
5815 /* When single-stepping over STI and MOV SS, we must clear the
5816 * corresponding interruptibility bits in the guest state. Otherwise
5817 * vmentry fails as it then expects bit 14 (BS) in pending debug
5818 * exceptions being set, but that's not correct for the guest debugging
5819 * case. */
5820 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5821 vmx_set_interrupt_shadow(vcpu, 0);
5822
d462b819 5823 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5824 asm(
6aa8b732 5825 /* Store host registers */
c801949d 5826 "push %%"R"dx; push %%"R"bp;"
40712fae 5827 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5828 "push %%"R"cx \n\t"
313dbd49
AK		 5829 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5830 "je 1f \n\t"
5831 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5832 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5833 "1: \n\t"
d3edefc0
AK		 5834 /* Reload cr2 if changed */
5835 "mov %c[cr2](%0), %%"R"ax \n\t"
5836 "mov %%cr2, %%"R"dx \n\t"
5837 "cmp %%"R"ax, %%"R"dx \n\t"
5838 "je 2f \n\t"
5839 "mov %%"R"ax, %%cr2 \n\t"
5840 "2: \n\t"
6aa8b732 5841 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5842 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5843 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5844 "mov %c[rax](%0), %%"R"ax \n\t"
5845 "mov %c[rbx](%0), %%"R"bx \n\t"
5846 "mov %c[rdx](%0), %%"R"dx \n\t"
5847 "mov %c[rsi](%0), %%"R"si \n\t"
5848 "mov %c[rdi](%0), %%"R"di \n\t"
5849 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 5850#ifdef CONFIG_X86_64
e08aa78a
AK		 5851 "mov %c[r8](%0), %%r8 \n\t"
5852 "mov %c[r9](%0), %%r9 \n\t"
5853 "mov %c[r10](%0), %%r10 \n\t"
5854 "mov %c[r11](%0), %%r11 \n\t"
5855 "mov %c[r12](%0), %%r12 \n\t"
5856 "mov %c[r13](%0), %%r13 \n\t"
5857 "mov %c[r14](%0), %%r14 \n\t"
5858 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 5859#endif
c801949d
AK		 5860 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5861
6aa8b732 5862 /* Enter guest mode */
cd2276a7 5863 "jne .Llaunched \n\t"
4ecac3fd 5864 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 5865 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 5866 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 5867 ".Lkvm_vmx_return: "
6aa8b732 5868 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 5869 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5870 "pop %0 \n\t"
c801949d
AK		 5871 "mov %%"R"ax, %c[rax](%0) \n\t"
5872 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 5873 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 5874 "mov %%"R"dx, %c[rdx](%0) \n\t"
5875 "mov %%"R"si, %c[rsi](%0) \n\t"
5876 "mov %%"R"di, %c[rdi](%0) \n\t"
5877 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 5878#ifdef CONFIG_X86_64
e08aa78a
AK		 5879 "mov %%r8, %c[r8](%0) \n\t"
5880 "mov %%r9, %c[r9](%0) \n\t"
5881 "mov %%r10, %c[r10](%0) \n\t"
5882 "mov %%r11, %c[r11](%0) \n\t"
5883 "mov %%r12, %c[r12](%0) \n\t"
5884 "mov %%r13, %c[r13](%0) \n\t"
5885 "mov %%r14, %c[r14](%0) \n\t"
5886 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 5887#endif
c801949d
AK		 5888 "mov %%cr2, %%"R"ax \n\t"
5889 "mov %%"R"ax, %c[cr2](%0) \n\t"
5890
1c696d0e 5891 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 5892 "setbe %c[fail](%0) \n\t"
5893 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 5894 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 5895 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 5896 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 5897 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5898 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5899 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5900 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5901 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5902 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5903 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 5904#ifdef CONFIG_X86_64
ad312c7c
ZX		 5905 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5906 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5907 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5908 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5909 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5910 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5911 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5912 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 5913#endif
40712fae
AK		 5914 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5915 [wordsize]"i"(sizeof(ulong))
c2036300 5916 : "cc", "memory"
07d6f555 5917 , R"ax", R"bx", R"di", R"si"
c2036300 5918#ifdef CONFIG_X86_64
c2036300
LV		 5919 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5920#endif
5921 );
6aa8b732 5922
6de4f3ad 5923 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 5924 | (1 << VCPU_EXREG_RFLAGS)
69c73028 5925 | (1 << VCPU_EXREG_CPL)
aff48baa 5926 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 5927 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 5928 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 5929 vcpu->arch.regs_dirty = 0;
5930
1155f76a
AK		 5931 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5932
d77c26fc 5933 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 5934 vmx->loaded_vmcs->launched = 1;
1b6269db 5935
51aa01d1 5936 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 5937
5938 vmx_complete_atomic_exit(vmx);
5939 vmx_recover_nmi_blocking(vmx);
cf393f75 5940 vmx_complete_interrupts(vmx);
6aa8b732
AK		 5941}
5942
c801949d
AK		 5943#undef R
5944#undef Q
5945
6aa8b732
AK		 5946static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5947{
fb3f0f51
RR		 5948 struct vcpu_vmx *vmx = to_vmx(vcpu);
5949
cdbecfc3 5950 free_vpid(vmx);
ec378aee 5951 free_nested(vmx);
d462b819 5952 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 5953 kfree(vmx->guest_msrs);
5954 kvm_vcpu_uninit(vcpu);
a4770347 5955 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 5956}
5957
fb3f0f51 5958static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 5959{
fb3f0f51 5960 int err;
c16f862d 5961 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 5962 int cpu;
6aa8b732 5963
a2fa3e9f 5964 if (!vmx)
fb3f0f51
RR		 5965 return ERR_PTR(-ENOMEM);
5966
2384d2b3
SY		 5967 allocate_vpid(vmx);
5968
fb3f0f51
RR		 5969 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5970 if (err)
5971 goto free_vcpu;
965b58a5 5972
a2fa3e9f 5973 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 5974 err = -ENOMEM;
fb3f0f51 5975 if (!vmx->guest_msrs) {
fb3f0f51
RR		 5976 goto uninit_vcpu;
5977 }
965b58a5 5978
d462b819
NHE		 5979 vmx->loaded_vmcs = &vmx->vmcs01;
5980 vmx->loaded_vmcs->vmcs = alloc_vmcs();
5981 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 5982 goto free_msrs;
d462b819
NHE		 5983 if (!vmm_exclusive)
5984 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5985 loaded_vmcs_init(vmx->loaded_vmcs);
5986 if (!vmm_exclusive)
5987 kvm_cpu_vmxoff();
a2fa3e9f 5988
15ad7146
AK		 5989 cpu = get_cpu();
5990 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 5991 vmx->vcpu.cpu = cpu;
8b9cf98c 5992 err = vmx_vcpu_setup(vmx);
fb3f0f51 5993 vmx_vcpu_put(&vmx->vcpu);
15ad7146 5994 put_cpu();
fb3f0f51
RR		 5995 if (err)
5996 goto free_vmcs;
5e4a0b3c 5997 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 5998 err = alloc_apic_access_page(kvm);
5999 if (err)
5e4a0b3c 6000 goto free_vmcs;
fb3f0f51 6001
b927a3ce
SY		 6002 if (enable_ept) {
6003 if (!kvm->arch.ept_identity_map_addr)
6004 kvm->arch.ept_identity_map_addr =
6005 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6006 err = -ENOMEM;
b7ebfb05
SY		 6007 if (alloc_identity_pagetable(kvm) != 0)
6008 goto free_vmcs;
93ea5388
GN		 6009 if (!init_rmode_identity_map(kvm))
6010 goto free_vmcs;
b927a3ce 6011 }
b7ebfb05 6012
a9d30f33
NHE		 6013 vmx->nested.current_vmptr = -1ull;
6014 vmx->nested.current_vmcs12 = NULL;
6015
fb3f0f51
RR		 6016 return &vmx->vcpu;
6017
6018free_vmcs:
d462b819 6019 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6020free_msrs:
fb3f0f51
RR		 6021 kfree(vmx->guest_msrs);
6022uninit_vcpu:
6023 kvm_vcpu_uninit(&vmx->vcpu);
6024free_vcpu:
cdbecfc3 6025 free_vpid(vmx);
a4770347 6026 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6027 return ERR_PTR(err);
6aa8b732
AK		 6028}
6029
002c7f7c
YS		 6030static void __init vmx_check_processor_compat(void *rtn)
6031{
6032 struct vmcs_config vmcs_conf;
6033
6034 *(int *)rtn = 0;
6035 if (setup_vmcs_config(&vmcs_conf) < 0)
6036 *(int *)rtn = -EIO;
6037 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6038 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6039 smp_processor_id());
6040 *(int *)rtn = -EIO;
6041 }
6042}
6043
67253af5
SY		 6044static int get_ept_level(void)
6045{
6046 return VMX_EPT_DEFAULT_GAW + 1;
6047}
6048
4b12f0de 6049static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6050{
4b12f0de
SY		 6051 u64 ret;
6052
522c68c4
SY		 6053 /* For VT-d and EPT combination
6054 * 1. MMIO: always map as UC
6055 * 2. EPT with VT-d:
6056 * a. VT-d without snooping control feature: can't guarantee the
6057 * result, try to trust guest.
6058 * b. VT-d with snooping control feature: snooping control feature of
6059 * VT-d engine can guarantee the cache correctness. Just set it
6060 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6061 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6062 * consistent with host MTRR
6063 */
4b12f0de
SY		 6064 if (is_mmio)
6065 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6066 else if (vcpu->kvm->arch.iommu_domain &&
6067 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6068 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6069 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6070 else
522c68c4 6071 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6072 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6073
6074 return ret;
64d4d521
SY		 6075}
6076
f4c9e87c
AK		 6077#define _ER(x) { EXIT_REASON_##x, #x }
6078
229456fc 6079static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 6080 _ER(EXCEPTION_NMI),
6081 _ER(EXTERNAL_INTERRUPT),
6082 _ER(TRIPLE_FAULT),
6083 _ER(PENDING_INTERRUPT),
6084 _ER(NMI_WINDOW),
6085 _ER(TASK_SWITCH),
6086 _ER(CPUID),
6087 _ER(HLT),
6088 _ER(INVLPG),
6089 _ER(RDPMC),
6090 _ER(RDTSC),
6091 _ER(VMCALL),
6092 _ER(VMCLEAR),
6093 _ER(VMLAUNCH),
6094 _ER(VMPTRLD),
6095 _ER(VMPTRST),
6096 _ER(VMREAD),
6097 _ER(VMRESUME),
6098 _ER(VMWRITE),
6099 _ER(VMOFF),
6100 _ER(VMON),
6101 _ER(CR_ACCESS),
6102 _ER(DR_ACCESS),
6103 _ER(IO_INSTRUCTION),
6104 _ER(MSR_READ),
6105 _ER(MSR_WRITE),
6106 _ER(MWAIT_INSTRUCTION),
6107 _ER(MONITOR_INSTRUCTION),
6108 _ER(PAUSE_INSTRUCTION),
6109 _ER(MCE_DURING_VMENTRY),
6110 _ER(TPR_BELOW_THRESHOLD),
6111 _ER(APIC_ACCESS),
6112 _ER(EPT_VIOLATION),
6113 _ER(EPT_MISCONFIG),
6114 _ER(WBINVD),
229456fc
MT		 6115 { -1, NULL }
6116};
6117
f4c9e87c
AK		 6118#undef _ER
6119
17cc3935 6120static int vmx_get_lpage_level(void)
344f414f 6121{
878403b7
SY		 6122 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6123 return PT_DIRECTORY_LEVEL;
6124 else
6125 /* For shadow and EPT supported 1GB page */
6126 return PT_PDPE_LEVEL;
344f414f
JR		 6127}
6128
0e851880
SY		 6129static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6130{
4e47c7a6
SY		 6131 struct kvm_cpuid_entry2 *best;
6132 struct vcpu_vmx *vmx = to_vmx(vcpu);
6133 u32 exec_control;
6134
6135 vmx->rdtscp_enabled = false;
6136 if (vmx_rdtscp_supported()) {
6137 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6138 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6139 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6140 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6141 vmx->rdtscp_enabled = true;
6142 else {
6143 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6144 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6145 exec_control);
6146 }
6147 }
6148 }
0e851880
SY		 6149}
6150
d4330ef2
JR		 6151static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6152{
6153}
6154
fe3ef05c
NHE		 6155/*
6156 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6157 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6158 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6159 * guest in a way that will both be appropriate to L1's requests, and our
6160 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6161 * function also has additional necessary side-effects, like setting various
6162 * vcpu->arch fields.
6163 */
6164static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6165{
6166 struct vcpu_vmx *vmx = to_vmx(vcpu);
6167 u32 exec_control;
6168
6169 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6170 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6171 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6172 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6173 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6174 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6175 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6176 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6177 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6178 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6179 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6180 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6181 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6182 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6183 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6184 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6185 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6186 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6187 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6188 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6189 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6190 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6191 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6192 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6193 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6194 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6195 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6196 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6197 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6198 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6199 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6200 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6201 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6202 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6203 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6204 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6205
6206 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6207 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6208 vmcs12->vm_entry_intr_info_field);
6209 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6210 vmcs12->vm_entry_exception_error_code);
6211 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6212 vmcs12->vm_entry_instruction_len);
6213 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6214 vmcs12->guest_interruptibility_info);
6215 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6216 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6217 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6218 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6219 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6220 vmcs12->guest_pending_dbg_exceptions);
6221 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6222 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6223
6224 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6225
6226 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6227 (vmcs_config.pin_based_exec_ctrl |
6228 vmcs12->pin_based_vm_exec_control));
6229
6230 /*
6231 * Whether page-faults are trapped is determined by a combination of
6232 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6233 * If enable_ept, L0 doesn't care about page faults and we should
6234 * set all of these to L1's desires. However, if !enable_ept, L0 does
6235 * care about (at least some) page faults, and because it is not easy
6236 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6237 * to exit on each and every L2 page fault. This is done by setting
6238 * MASK=MATCH=0 and (see below) EB.PF=1.
6239 * Note that below we don't need special code to set EB.PF beyond the
6240 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6241 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6242 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6243 *
6244 * A problem with this approach (when !enable_ept) is that L1 may be
6245 * injected with more page faults than it asked for. This could have
6246 * caused problems, but in practice existing hypervisors don't care.
6247 * To fix this, we will need to emulate the PFEC checking (on the L1
6248 * page tables), using walk_addr(), when injecting PFs to L1.
6249 */
6250 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6251 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6252 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6253 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6254
6255 if (cpu_has_secondary_exec_ctrls()) {
6256 u32 exec_control = vmx_secondary_exec_control(vmx);
6257 if (!vmx->rdtscp_enabled)
6258 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6259 /* Take the following fields only from vmcs12 */
6260 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6261 if (nested_cpu_has(vmcs12,
6262 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6263 exec_control |= vmcs12->secondary_vm_exec_control;
6264
6265 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6266 /*
6267 * Translate L1 physical address to host physical
6268 * address for vmcs02. Keep the page pinned, so this
6269 * physical address remains valid. We keep a reference
6270 * to it so we can release it later.
6271 */
6272 if (vmx->nested.apic_access_page) /* shouldn't happen */
6273 nested_release_page(vmx->nested.apic_access_page);
6274 vmx->nested.apic_access_page =
6275 nested_get_page(vcpu, vmcs12->apic_access_addr);
6276 /*
6277 * If translation failed, no matter: This feature asks
6278 * to exit when accessing the given address, and if it
6279 * can never be accessed, this feature won't do
6280 * anything anyway.
6281 */
6282 if (!vmx->nested.apic_access_page)
6283 exec_control &=
6284 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6285 else
6286 vmcs_write64(APIC_ACCESS_ADDR,
6287 page_to_phys(vmx->nested.apic_access_page));
6288 }
6289
6290 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6291 }
6292
6293
6294 /*
6295 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6296 * Some constant fields are set here by vmx_set_constant_host_state().
6297 * Other fields are different per CPU, and will be set later when
6298 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6299 */
6300 vmx_set_constant_host_state();
6301
6302 /*
6303 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6304 * entry, but only if the current (host) sp changed from the value
6305 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6306 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6307 * here we just force the write to happen on entry.
6308 */
6309 vmx->host_rsp = 0;
6310
6311 exec_control = vmx_exec_control(vmx); /* L0's desires */
6312 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6313 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6314 exec_control &= ~CPU_BASED_TPR_SHADOW;
6315 exec_control |= vmcs12->cpu_based_vm_exec_control;
6316 /*
6317 * Merging of IO and MSR bitmaps not currently supported.
6318 * Rather, exit every time.
6319 */
6320 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6321 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6322 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6323
6324 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6325
6326 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6327 * bitwise-or of what L1 wants to trap for L2, and what we want to
6328 * trap. Note that CR0.TS also needs updating - we do this later.
6329 */
6330 update_exception_bitmap(vcpu);
6331 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6332 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6333
6334 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6335 vmcs_write32(VM_EXIT_CONTROLS,
6336 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6337 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6338 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6339
6340 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6341 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6342 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6343 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6344
6345
6346 set_cr4_guest_host_mask(vmx);
6347
6348 vmcs_write64(TSC_OFFSET,
6349 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6350
6351 if (enable_vpid) {
6352 /*
6353 * Trivially support vpid by letting L2s share their parent
6354 * L1's vpid. TODO: move to a more elaborate solution, giving
6355 * each L2 its own vpid and exposing the vpid feature to L1.
6356 */
6357 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6358 vmx_flush_tlb(vcpu);
6359 }
6360
6361 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6362 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6363 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6364 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6365 else
6366 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6367 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6368 vmx_set_efer(vcpu, vcpu->arch.efer);
6369
6370 /*
6371 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6372 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6373 * The CR0_READ_SHADOW is what L2 should have expected to read given
6374 * the specifications by L1; It's not enough to take
6375 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6376 * have more bits than L1 expected.
6377 */
6378 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6379 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6380
6381 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6382 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6383
6384 /* shadow page tables on either EPT or shadow page tables */
6385 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6386 kvm_mmu_reset_context(vcpu);
6387
6388 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6389 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6390}
6391
cd232ad0
NHE		 6392/*
6393 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6394 * for running an L2 nested guest.
6395 */
6396static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6397{
6398 struct vmcs12 *vmcs12;
6399 struct vcpu_vmx *vmx = to_vmx(vcpu);
6400 int cpu;
6401 struct loaded_vmcs *vmcs02;
6402
6403 if (!nested_vmx_check_permission(vcpu) ||
6404 !nested_vmx_check_vmcs12(vcpu))
6405 return 1;
6406
6407 skip_emulated_instruction(vcpu);
6408 vmcs12 = get_vmcs12(vcpu);
6409
7c177938
NHE		 6410 /*
6411 * The nested entry process starts with enforcing various prerequisites
6412 * on vmcs12 as required by the Intel SDM, and act appropriately when
6413 * they fail: As the SDM explains, some conditions should cause the
6414 * instruction to fail, while others will cause the instruction to seem
6415 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6416 * To speed up the normal (success) code path, we should avoid checking
6417 * for misconfigurations which will anyway be caught by the processor
6418 * when using the merged vmcs02.
6419 */
6420 if (vmcs12->launch_state == launch) {
6421 nested_vmx_failValid(vcpu,
6422 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6423 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6424 return 1;
6425 }
6426
6427 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6428 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6429 /*TODO: Also verify bits beyond physical address width are 0*/
6430 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6431 return 1;
6432 }
6433
6434 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6435 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6436 /*TODO: Also verify bits beyond physical address width are 0*/
6437 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6438 return 1;
6439 }
6440
6441 if (vmcs12->vm_entry_msr_load_count > 0 ||
6442 vmcs12->vm_exit_msr_load_count > 0 ||
6443 vmcs12->vm_exit_msr_store_count > 0) {
6444 if (printk_ratelimit())
6445 printk(KERN_WARNING
6446 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6447 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6448 return 1;
6449 }
6450
6451 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6452 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6453 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6454 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6455 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6456 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6457 !vmx_control_verify(vmcs12->vm_exit_controls,
6458 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6459 !vmx_control_verify(vmcs12->vm_entry_controls,
6460 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6461 {
6462 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6463 return 1;
6464 }
6465
6466 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6467 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6468 nested_vmx_failValid(vcpu,
6469 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6470 return 1;
6471 }
6472
6473 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6474 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6475 nested_vmx_entry_failure(vcpu, vmcs12,
6476 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6477 return 1;
6478 }
6479 if (vmcs12->vmcs_link_pointer != -1ull) {
6480 nested_vmx_entry_failure(vcpu, vmcs12,
6481 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6482 return 1;
6483 }
6484
6485 /*
6486 * We're finally done with prerequisite checking, and can start with
6487 * the nested entry.
6488 */
6489
cd232ad0
NHE		 6490 vmcs02 = nested_get_current_vmcs02(vmx);
6491 if (!vmcs02)
6492 return -ENOMEM;
6493
6494 enter_guest_mode(vcpu);
6495
6496 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6497
6498 cpu = get_cpu();
6499 vmx->loaded_vmcs = vmcs02;
6500 vmx_vcpu_put(vcpu);
6501 vmx_vcpu_load(vcpu, cpu);
6502 vcpu->cpu = cpu;
6503 put_cpu();
6504
6505 vmcs12->launch_state = 1;
6506
6507 prepare_vmcs02(vcpu, vmcs12);
6508
6509 /*
6510 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6511 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6512 * returned as far as L1 is concerned. It will only return (and set
6513 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6514 */
6515 return 1;
6516}
6517
4704d0be
NHE		 6518/*
6519 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6520 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6521 * This function returns the new value we should put in vmcs12.guest_cr0.
6522 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6523 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6524 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6525 * didn't trap the bit, because if L1 did, so would L0).
6526 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6527 * been modified by L2, and L1 knows it. So just leave the old value of
6528 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6529 * isn't relevant, because if L0 traps this bit it can set it to anything.
6530 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6531 * changed these bits, and therefore they need to be updated, but L0
6532 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6533 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6534 */
6535static inline unsigned long
6536vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6537{
6538 return
6539 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6540 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6541 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6542 vcpu->arch.cr0_guest_owned_bits));
6543}
6544
6545static inline unsigned long
6546vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6547{
6548 return
6549 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6550 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6551 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6552 vcpu->arch.cr4_guest_owned_bits));
6553}
6554
6555/*
6556 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6557 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6558 * and this function updates it to reflect the changes to the guest state while
6559 * L2 was running (and perhaps made some exits which were handled directly by L0
6560 * without going back to L1), and to reflect the exit reason.
6561 * Note that we do not have to copy here all VMCS fields, just those that
6562 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6563 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6564 * which already writes to vmcs12 directly.
6565 */
6566void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6567{
6568 /* update guest state fields: */
6569 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6570 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6571
6572 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6573 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6574 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6575 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6576
6577 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6578 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6579 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6580 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6581 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6582 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6583 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6584 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6585 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6586 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6587 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6588 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6589 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6590 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6591 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6592 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6593 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6594 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6595 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6596 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6597 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6598 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6599 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6600 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6601 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6602 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6603 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6604 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6605 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6606 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6607 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6608 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6609 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6610 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6611 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6612 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6613
6614 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6615 vmcs12->guest_interruptibility_info =
6616 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6617 vmcs12->guest_pending_dbg_exceptions =
6618 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6619
6620 /* TODO: These cannot have changed unless we have MSR bitmaps and
6621 * the relevant bit asks not to trap the change */
6622 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6623 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6624 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6625 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6626 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6627 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6628
6629 /* update exit information fields: */
6630
6631 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6632 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6633
6634 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6635 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6636 vmcs12->idt_vectoring_info_field =
6637 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6638 vmcs12->idt_vectoring_error_code =
6639 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6640 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6641 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6642
6643 /* clear vm-entry fields which are to be cleared on exit */
6644 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6645 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6646}
6647
6648/*
6649 * A part of what we need to when the nested L2 guest exits and we want to
6650 * run its L1 parent, is to reset L1's guest state to the host state specified
6651 * in vmcs12.
6652 * This function is to be called not only on normal nested exit, but also on
6653 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6654 * Failures During or After Loading Guest State").
6655 * This function should be called when the active VMCS is L1's (vmcs01).
6656 */
6657void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6658{
6659 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6660 vcpu->arch.efer = vmcs12->host_ia32_efer;
6661 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6662 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6663 else
6664 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6665 vmx_set_efer(vcpu, vcpu->arch.efer);
6666
6667 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6668 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6669 /*
6670 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6671 * actually changed, because it depends on the current state of
6672 * fpu_active (which may have changed).
6673 * Note that vmx_set_cr0 refers to efer set above.
6674 */
6675 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6676 /*
6677 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6678 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6679 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6680 */
6681 update_exception_bitmap(vcpu);
6682 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6683 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6684
6685 /*
6686 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6687 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6688 */
6689 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6690 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6691
6692 /* shadow page tables on either EPT or shadow page tables */
6693 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6694 kvm_mmu_reset_context(vcpu);
6695
6696 if (enable_vpid) {
6697 /*
6698 * Trivially support vpid by letting L2s share their parent
6699 * L1's vpid. TODO: move to a more elaborate solution, giving
6700 * each L2 its own vpid and exposing the vpid feature to L1.
6701 */
6702 vmx_flush_tlb(vcpu);
6703 }
6704
6705
6706 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6707 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6708 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6709 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6710 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6711 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6712 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6713 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6714 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6715 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6716 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6717 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6718 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6719 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6720 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6721
6722 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6723 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6724 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6725 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6726 vmcs12->host_ia32_perf_global_ctrl);
6727}
6728
6729/*
6730 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6731 * and modify vmcs12 to make it see what it would expect to see there if
6732 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6733 */
6734static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6735{
6736 struct vcpu_vmx *vmx = to_vmx(vcpu);
6737 int cpu;
6738 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6739
6740 leave_guest_mode(vcpu);
6741 prepare_vmcs12(vcpu, vmcs12);
6742
6743 cpu = get_cpu();
6744 vmx->loaded_vmcs = &vmx->vmcs01;
6745 vmx_vcpu_put(vcpu);
6746 vmx_vcpu_load(vcpu, cpu);
6747 vcpu->cpu = cpu;
6748 put_cpu();
6749
6750 /* if no vmcs02 cache requested, remove the one we used */
6751 if (VMCS02_POOL_SIZE == 0)
6752 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6753
6754 load_vmcs12_host_state(vcpu, vmcs12);
6755
6756 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6757 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6758
6759 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6760 vmx->host_rsp = 0;
6761
6762 /* Unpin physical memory we referred to in vmcs02 */
6763 if (vmx->nested.apic_access_page) {
6764 nested_release_page(vmx->nested.apic_access_page);
6765 vmx->nested.apic_access_page = 0;
6766 }
6767
6768 /*
6769 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6770 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6771 * success or failure flag accordingly.
6772 */
6773 if (unlikely(vmx->fail)) {
6774 vmx->fail = 0;
6775 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6776 } else
6777 nested_vmx_succeed(vcpu);
6778}
6779
7c177938
NHE		 6780/*
6781 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6782 * 23.7 "VM-entry failures during or after loading guest state" (this also
6783 * lists the acceptable exit-reason and exit-qualification parameters).
6784 * It should only be called before L2 actually succeeded to run, and when
6785 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6786 */
6787static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6788 struct vmcs12 *vmcs12,
6789 u32 reason, unsigned long qualification)
6790{
6791 load_vmcs12_host_state(vcpu, vmcs12);
6792 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6793 vmcs12->exit_qualification = qualification;
6794 nested_vmx_succeed(vcpu);
6795}
6796
8a76d7f2
JR		 6797static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6798 struct x86_instruction_info *info,
6799 enum x86_intercept_stage stage)
6800{
6801 return X86EMUL_CONTINUE;
6802}
6803
cbdd1bea 6804static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 6805 .cpu_has_kvm_support = cpu_has_kvm_support,
6806 .disabled_by_bios = vmx_disabled_by_bios,
6807 .hardware_setup = hardware_setup,
6808 .hardware_unsetup = hardware_unsetup,
002c7f7c 6809 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 6810 .hardware_enable = hardware_enable,
6811 .hardware_disable = hardware_disable,
04547156 6812 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 6813
6814 .vcpu_create = vmx_create_vcpu,
6815 .vcpu_free = vmx_free_vcpu,
04d2cc77 6816 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 6817
04d2cc77 6818 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 6819 .vcpu_load = vmx_vcpu_load,
6820 .vcpu_put = vmx_vcpu_put,
6821
6822 .set_guest_debug = set_guest_debug,
6823 .get_msr = vmx_get_msr,
6824 .set_msr = vmx_set_msr,
6825 .get_segment_base = vmx_get_segment_base,
6826 .get_segment = vmx_get_segment,
6827 .set_segment = vmx_set_segment,
2e4d2653 6828 .get_cpl = vmx_get_cpl,
6aa8b732 6829 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 6830 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 6831 .decache_cr3 = vmx_decache_cr3,
25c4c276 6832 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 6833 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 6834 .set_cr3 = vmx_set_cr3,
6835 .set_cr4 = vmx_set_cr4,
6aa8b732 6836 .set_efer = vmx_set_efer,
6aa8b732
AK		 6837 .get_idt = vmx_get_idt,
6838 .set_idt = vmx_set_idt,
6839 .get_gdt = vmx_get_gdt,
6840 .set_gdt = vmx_set_gdt,
020df079 6841 .set_dr7 = vmx_set_dr7,
5fdbf976 6842 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 6843 .get_rflags = vmx_get_rflags,
6844 .set_rflags = vmx_set_rflags,
ebcbab4c 6845 .fpu_activate = vmx_fpu_activate,
02daab21 6846 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 6847
6848 .tlb_flush = vmx_flush_tlb,
6aa8b732 6849
6aa8b732 6850 .run = vmx_vcpu_run,
6062d012 6851 .handle_exit = vmx_handle_exit,
6aa8b732 6852 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 6853 .set_interrupt_shadow = vmx_set_interrupt_shadow,
6854 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 6855 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 6856 .set_irq = vmx_inject_irq,
95ba8273 6857 .set_nmi = vmx_inject_nmi,
298101da 6858 .queue_exception = vmx_queue_exception,
b463a6f7 6859 .cancel_injection = vmx_cancel_injection,
78646121 6860 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 6861 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 6862 .get_nmi_mask = vmx_get_nmi_mask,
6863 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 6864 .enable_nmi_window = enable_nmi_window,
6865 .enable_irq_window = enable_irq_window,
6866 .update_cr8_intercept = update_cr8_intercept,
95ba8273 6867
cbc94022 6868 .set_tss_addr = vmx_set_tss_addr,
67253af5 6869 .get_tdp_level = get_ept_level,
4b12f0de 6870 .get_mt_mask = vmx_get_mt_mask,
229456fc 6871
586f9607 6872 .get_exit_info = vmx_get_exit_info,
229456fc 6873 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 6874
17cc3935 6875 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 6876
6877 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 6878
6879 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 6880
6881 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 6882
6883 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 6884
4051b188 6885 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 6886 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 6887 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 6888 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 6889
6890 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 6891
6892 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 6893};
6894
6895static int __init vmx_init(void)
6896{
26bb0981
AK		 6897 int r, i;
6898
6899 rdmsrl_safe(MSR_EFER, &host_efer);
6900
6901 for (i = 0; i < NR_VMX_MSR; ++i)
6902 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 6903
3e7c73e9 6904 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 6905 if (!vmx_io_bitmap_a)
6906 return -ENOMEM;
6907
3e7c73e9 6908 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 6909 if (!vmx_io_bitmap_b) {
6910 r = -ENOMEM;
6911 goto out;
6912 }
6913
5897297b
AK		 6914 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6915 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 6916 r = -ENOMEM;
6917 goto out1;
6918 }
6919
5897297b
AK		 6920 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6921 if (!vmx_msr_bitmap_longmode) {
6922 r = -ENOMEM;
6923 goto out2;
6924 }
6925
fdef3ad1
HQ		 6926 /*
6927 * Allow direct access to the PC debug port (it is often used for I/O
6928 * delays, but the vmexits simply slow things down).
6929 */
3e7c73e9
AK		 6930 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6931 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 6932
3e7c73e9 6933 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 6934
5897297b
AK		 6935 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6936 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 6937
2384d2b3
SY		 6938 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6939
0ee75bea
AK		 6940 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
6941 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 6942 if (r)
5897297b 6943 goto out3;
25c5f225 6944
5897297b
AK		 6945 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6946 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6947 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6948 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6949 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6950 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 6951
089d034e 6952 if (enable_ept) {
1439442c 6953 bypass_guest_pf = 0;
534e38b4 6954 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 6955 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 6956 kvm_enable_tdp();
6957 } else
6958 kvm_disable_tdp();
1439442c 6959
c7addb90
AK		 6960 if (bypass_guest_pf)
6961 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
6962
fdef3ad1
HQ		 6963 return 0;
6964
5897297b
AK		 6965out3:
6966 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 6967out2:
5897297b 6968 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 6969out1:
3e7c73e9 6970 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 6971out:
3e7c73e9 6972 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 6973 return r;
6aa8b732
AK		 6974}
6975
6976static void __exit vmx_exit(void)
6977{
5897297b
AK		 6978 free_page((unsigned long)vmx_msr_bitmap_legacy);
6979 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 6980 free_page((unsigned long)vmx_io_bitmap_b);
6981 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 6982
cb498ea2 6983 kvm_exit();
6aa8b732
AK		 6984}
6985
6986module_init(vmx_init)
6987module_exit(vmx_exit)
Linux kernel - Deliverables
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