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KVM: nVMX: Clean up and fix pin-based execution controls
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
257090f7 87static bool __read_mostly enable_apicv_reg_vid;
83d4c286 88
801d3424
NHE		 89/*
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
93 */
476bc001 94static bool __read_mostly nested = 0;
801d3424
NHE		 95module_param(nested, bool, S_IRUGO);
96
5037878e
GN		 97#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 99#define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 101#define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
104
cdc0e244
AK		 105#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
107
78ac8b47
AK		 108#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
109
4b8d54f9
ZE		 110/*
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 114 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
120 */
00c25bce 121#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 122#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
124module_param(ple_gap, int, S_IRUGO);
125
126static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
127module_param(ple_window, int, S_IRUGO);
128
83287ea4
AK		 129extern const ulong vmx_return;
130
8bf00a52 131#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 132#define VMCS02_POOL_SIZE 1
61d2ef2c 133
a2fa3e9f
GH		 134struct vmcs {
135 u32 revision_id;
136 u32 abort;
137 char data[0];
138};
139
d462b819
NHE		 140/*
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
144 */
145struct loaded_vmcs {
146 struct vmcs *vmcs;
147 int cpu;
148 int launched;
149 struct list_head loaded_vmcss_on_cpu_link;
150};
151
26bb0981
AK		 152struct shared_msr_entry {
153 unsigned index;
154 u64 data;
d5696725 155 u64 mask;
26bb0981
AK		 156};
157
a9d30f33
NHE		 158/*
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 */
22bd0358 171typedef u64 natural_width;
a9d30f33
NHE		 172struct __packed vmcs12 {
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
175 */
176 u32 revision_id;
177 u32 abort;
22bd0358 178
27d6c865
NHE		 179 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding[7]; /* room for future expansion */
181
22bd0358
NHE		 182 u64 io_bitmap_a;
183 u64 io_bitmap_b;
184 u64 msr_bitmap;
185 u64 vm_exit_msr_store_addr;
186 u64 vm_exit_msr_load_addr;
187 u64 vm_entry_msr_load_addr;
188 u64 tsc_offset;
189 u64 virtual_apic_page_addr;
190 u64 apic_access_addr;
191 u64 ept_pointer;
192 u64 guest_physical_address;
193 u64 vmcs_link_pointer;
194 u64 guest_ia32_debugctl;
195 u64 guest_ia32_pat;
196 u64 guest_ia32_efer;
197 u64 guest_ia32_perf_global_ctrl;
198 u64 guest_pdptr0;
199 u64 guest_pdptr1;
200 u64 guest_pdptr2;
201 u64 guest_pdptr3;
202 u64 host_ia32_pat;
203 u64 host_ia32_efer;
204 u64 host_ia32_perf_global_ctrl;
205 u64 padding64[8]; /* room for future expansion */
206 /*
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
211 */
212 natural_width cr0_guest_host_mask;
213 natural_width cr4_guest_host_mask;
214 natural_width cr0_read_shadow;
215 natural_width cr4_read_shadow;
216 natural_width cr3_target_value0;
217 natural_width cr3_target_value1;
218 natural_width cr3_target_value2;
219 natural_width cr3_target_value3;
220 natural_width exit_qualification;
221 natural_width guest_linear_address;
222 natural_width guest_cr0;
223 natural_width guest_cr3;
224 natural_width guest_cr4;
225 natural_width guest_es_base;
226 natural_width guest_cs_base;
227 natural_width guest_ss_base;
228 natural_width guest_ds_base;
229 natural_width guest_fs_base;
230 natural_width guest_gs_base;
231 natural_width guest_ldtr_base;
232 natural_width guest_tr_base;
233 natural_width guest_gdtr_base;
234 natural_width guest_idtr_base;
235 natural_width guest_dr7;
236 natural_width guest_rsp;
237 natural_width guest_rip;
238 natural_width guest_rflags;
239 natural_width guest_pending_dbg_exceptions;
240 natural_width guest_sysenter_esp;
241 natural_width guest_sysenter_eip;
242 natural_width host_cr0;
243 natural_width host_cr3;
244 natural_width host_cr4;
245 natural_width host_fs_base;
246 natural_width host_gs_base;
247 natural_width host_tr_base;
248 natural_width host_gdtr_base;
249 natural_width host_idtr_base;
250 natural_width host_ia32_sysenter_esp;
251 natural_width host_ia32_sysenter_eip;
252 natural_width host_rsp;
253 natural_width host_rip;
254 natural_width paddingl[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control;
256 u32 cpu_based_vm_exec_control;
257 u32 exception_bitmap;
258 u32 page_fault_error_code_mask;
259 u32 page_fault_error_code_match;
260 u32 cr3_target_count;
261 u32 vm_exit_controls;
262 u32 vm_exit_msr_store_count;
263 u32 vm_exit_msr_load_count;
264 u32 vm_entry_controls;
265 u32 vm_entry_msr_load_count;
266 u32 vm_entry_intr_info_field;
267 u32 vm_entry_exception_error_code;
268 u32 vm_entry_instruction_len;
269 u32 tpr_threshold;
270 u32 secondary_vm_exec_control;
271 u32 vm_instruction_error;
272 u32 vm_exit_reason;
273 u32 vm_exit_intr_info;
274 u32 vm_exit_intr_error_code;
275 u32 idt_vectoring_info_field;
276 u32 idt_vectoring_error_code;
277 u32 vm_exit_instruction_len;
278 u32 vmx_instruction_info;
279 u32 guest_es_limit;
280 u32 guest_cs_limit;
281 u32 guest_ss_limit;
282 u32 guest_ds_limit;
283 u32 guest_fs_limit;
284 u32 guest_gs_limit;
285 u32 guest_ldtr_limit;
286 u32 guest_tr_limit;
287 u32 guest_gdtr_limit;
288 u32 guest_idtr_limit;
289 u32 guest_es_ar_bytes;
290 u32 guest_cs_ar_bytes;
291 u32 guest_ss_ar_bytes;
292 u32 guest_ds_ar_bytes;
293 u32 guest_fs_ar_bytes;
294 u32 guest_gs_ar_bytes;
295 u32 guest_ldtr_ar_bytes;
296 u32 guest_tr_ar_bytes;
297 u32 guest_interruptibility_info;
298 u32 guest_activity_state;
299 u32 guest_sysenter_cs;
300 u32 host_ia32_sysenter_cs;
301 u32 padding32[8]; /* room for future expansion */
302 u16 virtual_processor_id;
303 u16 guest_es_selector;
304 u16 guest_cs_selector;
305 u16 guest_ss_selector;
306 u16 guest_ds_selector;
307 u16 guest_fs_selector;
308 u16 guest_gs_selector;
309 u16 guest_ldtr_selector;
310 u16 guest_tr_selector;
311 u16 host_es_selector;
312 u16 host_cs_selector;
313 u16 host_ss_selector;
314 u16 host_ds_selector;
315 u16 host_fs_selector;
316 u16 host_gs_selector;
317 u16 host_tr_selector;
a9d30f33
NHE		 318};
319
320/*
321 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
322 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
323 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
324 */
325#define VMCS12_REVISION 0x11e57ed0
326
327/*
328 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
329 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
330 * current implementation, 4K are reserved to avoid future complications.
331 */
332#define VMCS12_SIZE 0x1000
333
ff2f6fe9
NHE		 334/* Used to remember the last vmcs02 used for some recently used vmcs12s */
335struct vmcs02_list {
336 struct list_head list;
337 gpa_t vmptr;
338 struct loaded_vmcs vmcs02;
339};
340
ec378aee
NHE		 341/*
342 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
343 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
344 */
345struct nested_vmx {
346 /* Has the level1 guest done vmxon? */
347 bool vmxon;
a9d30f33
NHE		 348
349 /* The guest-physical address of the current VMCS L1 keeps for L2 */
350 gpa_t current_vmptr;
351 /* The host-usable pointer to the above */
352 struct page *current_vmcs12_page;
353 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 354
355 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
356 struct list_head vmcs02_pool;
357 int vmcs02_num;
fe3ef05c 358 u64 vmcs01_tsc_offset;
644d711a
NHE		 359 /* L2 must run next, and mustn't decide to exit to L1. */
360 bool nested_run_pending;
fe3ef05c
NHE		 361 /*
362 * Guest pages referred to in vmcs02 with host-physical pointers, so
363 * we must keep them pinned while L2 runs.
364 */
365 struct page *apic_access_page;
ec378aee
NHE		 366};
367
a2fa3e9f 368struct vcpu_vmx {
fb3f0f51 369 struct kvm_vcpu vcpu;
313dbd49 370 unsigned long host_rsp;
29bd8a78 371 u8 fail;
69c73028 372 u8 cpl;
9d58b931 373 bool nmi_known_unmasked;
51aa01d1 374 u32 exit_intr_info;
1155f76a 375 u32 idt_vectoring_info;
6de12732 376 ulong rflags;
26bb0981 377 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 378 int nmsrs;
379 int save_nmsrs;
a2fa3e9f 380#ifdef CONFIG_X86_64
44ea2b17
AK		 381 u64 msr_host_kernel_gs_base;
382 u64 msr_guest_kernel_gs_base;
a2fa3e9f 383#endif
d462b819
NHE		 384 /*
385 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
386 * non-nested (L1) guest, it always points to vmcs01. For a nested
387 * guest (L2), it points to a different VMCS.
388 */
389 struct loaded_vmcs vmcs01;
390 struct loaded_vmcs *loaded_vmcs;
391 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 392 struct msr_autoload {
393 unsigned nr;
394 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
395 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
396 } msr_autoload;
a2fa3e9f
GH		 397 struct {
398 int loaded;
399 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 400#ifdef CONFIG_X86_64
401 u16 ds_sel, es_sel;
402#endif
152d3f2f
LV		 403 int gs_ldt_reload_needed;
404 int fs_reload_needed;
d77c26fc 405 } host_state;
9c8cba37 406 struct {
7ffd92c5 407 int vm86_active;
78ac8b47 408 ulong save_rflags;
f5f7b2fe
AK		 409 struct kvm_segment segs[8];
410 } rmode;
411 struct {
412 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 413 struct kvm_save_segment {
414 u16 selector;
415 unsigned long base;
416 u32 limit;
417 u32 ar;
f5f7b2fe 418 } seg[8];
2fb92db1 419 } segment_cache;
2384d2b3 420 int vpid;
04fa4d32 421 bool emulation_required;
3b86cd99
JK		 422
423 /* Support for vnmi-less CPUs */
424 int soft_vnmi_blocked;
425 ktime_t entry_time;
426 s64 vnmi_blocked_time;
a0861c02 427 u32 exit_reason;
4e47c7a6
SY		 428
429 bool rdtscp_enabled;
ec378aee
NHE		 430
431 /* Support for a guest hypervisor (nested VMX) */
432 struct nested_vmx nested;
a2fa3e9f
GH		 433};
434
2fb92db1
AK		 435enum segment_cache_field {
436 SEG_FIELD_SEL = 0,
437 SEG_FIELD_BASE = 1,
438 SEG_FIELD_LIMIT = 2,
439 SEG_FIELD_AR = 3,
440
441 SEG_FIELD_NR = 4
442};
443
a2fa3e9f
GH		 444static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
445{
fb3f0f51 446 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 447}
448
22bd0358
NHE		 449#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
450#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
451#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
452 [number##_HIGH] = VMCS12_OFFSET(name)+4
453
772e0318 454static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 455 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
456 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
457 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
458 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
459 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
460 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
461 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
462 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
463 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
464 FIELD(HOST_ES_SELECTOR, host_es_selector),
465 FIELD(HOST_CS_SELECTOR, host_cs_selector),
466 FIELD(HOST_SS_SELECTOR, host_ss_selector),
467 FIELD(HOST_DS_SELECTOR, host_ds_selector),
468 FIELD(HOST_FS_SELECTOR, host_fs_selector),
469 FIELD(HOST_GS_SELECTOR, host_gs_selector),
470 FIELD(HOST_TR_SELECTOR, host_tr_selector),
471 FIELD64(IO_BITMAP_A, io_bitmap_a),
472 FIELD64(IO_BITMAP_B, io_bitmap_b),
473 FIELD64(MSR_BITMAP, msr_bitmap),
474 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
475 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
476 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
477 FIELD64(TSC_OFFSET, tsc_offset),
478 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
479 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
480 FIELD64(EPT_POINTER, ept_pointer),
481 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
482 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
483 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
484 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
485 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
486 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
487 FIELD64(GUEST_PDPTR0, guest_pdptr0),
488 FIELD64(GUEST_PDPTR1, guest_pdptr1),
489 FIELD64(GUEST_PDPTR2, guest_pdptr2),
490 FIELD64(GUEST_PDPTR3, guest_pdptr3),
491 FIELD64(HOST_IA32_PAT, host_ia32_pat),
492 FIELD64(HOST_IA32_EFER, host_ia32_efer),
493 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
494 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
495 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
496 FIELD(EXCEPTION_BITMAP, exception_bitmap),
497 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
498 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
499 FIELD(CR3_TARGET_COUNT, cr3_target_count),
500 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
501 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
502 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
503 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
504 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
505 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
506 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
507 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
508 FIELD(TPR_THRESHOLD, tpr_threshold),
509 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
510 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
511 FIELD(VM_EXIT_REASON, vm_exit_reason),
512 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
513 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
514 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
515 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
516 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
517 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
518 FIELD(GUEST_ES_LIMIT, guest_es_limit),
519 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
520 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
521 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
522 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
523 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
524 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
525 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
526 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
527 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
528 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
529 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
530 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
531 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
532 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
533 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
534 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
535 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
536 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
537 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
538 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
539 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
540 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
541 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
542 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
543 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
544 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
545 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
546 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
547 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
548 FIELD(EXIT_QUALIFICATION, exit_qualification),
549 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
550 FIELD(GUEST_CR0, guest_cr0),
551 FIELD(GUEST_CR3, guest_cr3),
552 FIELD(GUEST_CR4, guest_cr4),
553 FIELD(GUEST_ES_BASE, guest_es_base),
554 FIELD(GUEST_CS_BASE, guest_cs_base),
555 FIELD(GUEST_SS_BASE, guest_ss_base),
556 FIELD(GUEST_DS_BASE, guest_ds_base),
557 FIELD(GUEST_FS_BASE, guest_fs_base),
558 FIELD(GUEST_GS_BASE, guest_gs_base),
559 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
560 FIELD(GUEST_TR_BASE, guest_tr_base),
561 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
562 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
563 FIELD(GUEST_DR7, guest_dr7),
564 FIELD(GUEST_RSP, guest_rsp),
565 FIELD(GUEST_RIP, guest_rip),
566 FIELD(GUEST_RFLAGS, guest_rflags),
567 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
568 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
569 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
570 FIELD(HOST_CR0, host_cr0),
571 FIELD(HOST_CR3, host_cr3),
572 FIELD(HOST_CR4, host_cr4),
573 FIELD(HOST_FS_BASE, host_fs_base),
574 FIELD(HOST_GS_BASE, host_gs_base),
575 FIELD(HOST_TR_BASE, host_tr_base),
576 FIELD(HOST_GDTR_BASE, host_gdtr_base),
577 FIELD(HOST_IDTR_BASE, host_idtr_base),
578 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
579 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
580 FIELD(HOST_RSP, host_rsp),
581 FIELD(HOST_RIP, host_rip),
582};
583static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
584
585static inline short vmcs_field_to_offset(unsigned long field)
586{
587 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
588 return -1;
589 return vmcs_field_to_offset_table[field];
590}
591
a9d30f33
NHE		 592static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
593{
594 return to_vmx(vcpu)->nested.current_vmcs12;
595}
596
597static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
598{
599 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 600 if (is_error_page(page))
a9d30f33 601 return NULL;
32cad84f 602
a9d30f33
NHE		 603 return page;
604}
605
606static void nested_release_page(struct page *page)
607{
608 kvm_release_page_dirty(page);
609}
610
611static void nested_release_page_clean(struct page *page)
612{
613 kvm_release_page_clean(page);
614}
615
4e1096d2 616static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 617static void kvm_cpu_vmxon(u64 addr);
618static void kvm_cpu_vmxoff(void);
aff48baa 619static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 620static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 621static void vmx_set_segment(struct kvm_vcpu *vcpu,
622 struct kvm_segment *var, int seg);
623static void vmx_get_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
d99e4152
GN		 625static bool guest_state_valid(struct kvm_vcpu *vcpu);
626static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 627
6aa8b732
AK		 628static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 630/*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 635static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 636
3e7c73e9
AK		 637static unsigned long *vmx_io_bitmap_a;
638static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 639static unsigned long *vmx_msr_bitmap_legacy;
640static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 641static unsigned long *vmx_msr_bitmap_legacy_x2apic;
642static unsigned long *vmx_msr_bitmap_longmode_x2apic;
fdef3ad1 643
110312c8 644static bool cpu_has_load_ia32_efer;
8bf00a52 645static bool cpu_has_load_perf_global_ctrl;
110312c8 646
2384d2b3
SY		 647static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
648static DEFINE_SPINLOCK(vmx_vpid_lock);
649
1c3d14fe 650static struct vmcs_config {
6aa8b732
AK		 651 int size;
652 int order;
653 u32 revision_id;
1c3d14fe
YS		 654 u32 pin_based_exec_ctrl;
655 u32 cpu_based_exec_ctrl;
f78e0e2e 656 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 657 u32 vmexit_ctrl;
658 u32 vmentry_ctrl;
659} vmcs_config;
6aa8b732 660
efff9e53 661static struct vmx_capability {
d56f546d
SY		 662 u32 ept;
663 u32 vpid;
664} vmx_capability;
665
6aa8b732
AK		 666#define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
672 }
673
772e0318 674static const struct kvm_vmx_segment_field {
6aa8b732
AK		 675 unsigned selector;
676 unsigned base;
677 unsigned limit;
678 unsigned ar_bytes;
679} kvm_vmx_segment_fields[] = {
680 VMX_SEGMENT_FIELD(CS),
681 VMX_SEGMENT_FIELD(DS),
682 VMX_SEGMENT_FIELD(ES),
683 VMX_SEGMENT_FIELD(FS),
684 VMX_SEGMENT_FIELD(GS),
685 VMX_SEGMENT_FIELD(SS),
686 VMX_SEGMENT_FIELD(TR),
687 VMX_SEGMENT_FIELD(LDTR),
688};
689
26bb0981
AK		 690static u64 host_efer;
691
6de4f3ad
AK		 692static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
693
4d56c8a7 694/*
8c06585d 695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 696 * away by decrementing the array size.
697 */
6aa8b732 698static const u32 vmx_msr_index[] = {
05b3e0c2 699#ifdef CONFIG_X86_64
44ea2b17 700 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 701#endif
8c06585d 702 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 703};
9d8f549d 704#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 705
31299944 706static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
709 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 710 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 711}
712
31299944 713static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 717 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 718}
719
31299944 720static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 721{
722 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
723 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 724 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 725}
726
31299944 727static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 728{
729 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
730 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
731}
732
31299944 733static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 734{
735 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
736 INTR_INFO_VALID_MASK)) ==
737 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
738}
739
31299944 740static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 743}
744
31299944 745static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 746{
04547156 747 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 748}
749
31299944 750static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 751{
04547156 752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 753}
754
31299944 755static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 756{
04547156
SY		 757 return vmcs_config.cpu_based_exec_ctrl &
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 759}
760
774ead3a 761static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 762{
04547156
SY		 763 return vmcs_config.cpu_based_2nd_exec_ctrl &
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
765}
766
8d14695f
YZ		 767static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
768{
769 return vmcs_config.cpu_based_2nd_exec_ctrl &
770 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
771}
772
83d4c286
YZ		 773static inline bool cpu_has_vmx_apic_register_virt(void)
774{
775 return vmcs_config.cpu_based_2nd_exec_ctrl &
776 SECONDARY_EXEC_APIC_REGISTER_VIRT;
777}
778
c7c9c56c
YZ		 779static inline bool cpu_has_vmx_virtual_intr_delivery(void)
780{
781 return vmcs_config.cpu_based_2nd_exec_ctrl &
782 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
783}
784
04547156
SY		 785static inline bool cpu_has_vmx_flexpriority(void)
786{
787 return cpu_has_vmx_tpr_shadow() &&
788 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 789}
790
e799794e
MT		 791static inline bool cpu_has_vmx_ept_execute_only(void)
792{
31299944 793 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 794}
795
796static inline bool cpu_has_vmx_eptp_uncacheable(void)
797{
31299944 798 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 799}
800
801static inline bool cpu_has_vmx_eptp_writeback(void)
802{
31299944 803 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 804}
805
806static inline bool cpu_has_vmx_ept_2m_page(void)
807{
31299944 808 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 809}
810
878403b7
SY		 811static inline bool cpu_has_vmx_ept_1g_page(void)
812{
31299944 813 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 814}
815
4bc9b982
SY		 816static inline bool cpu_has_vmx_ept_4levels(void)
817{
818 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
819}
820
83c3a331
XH		 821static inline bool cpu_has_vmx_ept_ad_bits(void)
822{
823 return vmx_capability.ept & VMX_EPT_AD_BIT;
824}
825
31299944 826static inline bool cpu_has_vmx_invept_context(void)
d56f546d 827{
31299944 828 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 829}
830
31299944 831static inline bool cpu_has_vmx_invept_global(void)
d56f546d 832{
31299944 833 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 834}
835
518c8aee
GJ		 836static inline bool cpu_has_vmx_invvpid_single(void)
837{
838 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
839}
840
b9d762fa
GJ		 841static inline bool cpu_has_vmx_invvpid_global(void)
842{
843 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
844}
845
31299944 846static inline bool cpu_has_vmx_ept(void)
d56f546d 847{
04547156
SY		 848 return vmcs_config.cpu_based_2nd_exec_ctrl &
849 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 853{
854 return vmcs_config.cpu_based_2nd_exec_ctrl &
855 SECONDARY_EXEC_UNRESTRICTED_GUEST;
856}
857
31299944 858static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 859{
860 return vmcs_config.cpu_based_2nd_exec_ctrl &
861 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
862}
863
31299944 864static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 865{
6d3e435e 866 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 867}
868
31299944 869static inline bool cpu_has_vmx_vpid(void)
2384d2b3 870{
04547156
SY		 871 return vmcs_config.cpu_based_2nd_exec_ctrl &
872 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 873}
874
31299944 875static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 876{
877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_RDTSCP;
879}
880
ad756a16
MJ		 881static inline bool cpu_has_vmx_invpcid(void)
882{
883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_ENABLE_INVPCID;
885}
886
31299944 887static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 888{
889 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
890}
891
f5f48ee1
SY		 892static inline bool cpu_has_vmx_wbinvd_exit(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_WBINVD_EXITING;
896}
897
04547156
SY		 898static inline bool report_flexpriority(void)
899{
900 return flexpriority_enabled;
901}
902
fe3ef05c
NHE		 903static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
904{
905 return vmcs12->cpu_based_vm_exec_control & bit;
906}
907
908static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
909{
910 return (vmcs12->cpu_based_vm_exec_control &
911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
912 (vmcs12->secondary_vm_exec_control & bit);
913}
914
644d711a
NHE		 915static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
916 struct kvm_vcpu *vcpu)
917{
918 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
919}
920
921static inline bool is_exception(u32 intr_info)
922{
923 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
924 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
925}
926
927static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 928static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
929 struct vmcs12 *vmcs12,
930 u32 reason, unsigned long qualification);
931
8b9cf98c 932static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 933{
934 int i;
935
a2fa3e9f 936 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 937 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 938 return i;
939 return -1;
940}
941
2384d2b3
SY		 942static inline void __invvpid(int ext, u16 vpid, gva_t gva)
943{
944 struct {
945 u64 vpid : 16;
946 u64 rsvd : 48;
947 u64 gva;
948 } operand = { vpid, 0, gva };
949
4ecac3fd 950 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 951 /* CF==1 or ZF==1 --> rc = -1 */
952 "; ja 1f ; ud2 ; 1:"
953 : : "a"(&operand), "c"(ext) : "cc", "memory");
954}
955
1439442c
SY		 956static inline void __invept(int ext, u64 eptp, gpa_t gpa)
957{
958 struct {
959 u64 eptp, gpa;
960 } operand = {eptp, gpa};
961
4ecac3fd 962 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 963 /* CF==1 or ZF==1 --> rc = -1 */
964 "; ja 1f ; ud2 ; 1:\n"
965 : : "a" (&operand), "c" (ext) : "cc", "memory");
966}
967
26bb0981 968static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 969{
970 int i;
971
8b9cf98c 972 i = __find_msr_index(vmx, msr);
a75beee6 973 if (i >= 0)
a2fa3e9f 974 return &vmx->guest_msrs[i];
8b6d44c7 975 return NULL;
7725f0ba
AK		 976}
977
6aa8b732
AK		 978static void vmcs_clear(struct vmcs *vmcs)
979{
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
4ecac3fd 983 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 985 : "cc", "memory");
986 if (error)
987 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
988 vmcs, phys_addr);
989}
990
d462b819
NHE		 991static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
992{
993 vmcs_clear(loaded_vmcs->vmcs);
994 loaded_vmcs->cpu = -1;
995 loaded_vmcs->launched = 0;
996}
997
7725b894
DX		 998static void vmcs_load(struct vmcs *vmcs)
999{
1000 u64 phys_addr = __pa(vmcs);
1001 u8 error;
1002
1003 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1004 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1005 : "cc", "memory");
1006 if (error)
2844d849 1007 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1008 vmcs, phys_addr);
1009}
1010
8f536b76
ZY		 1011#ifdef CONFIG_KEXEC
1012/*
1013 * This bitmap is used to indicate whether the vmclear
1014 * operation is enabled on all cpus. All disabled by
1015 * default.
1016 */
1017static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1018
1019static inline void crash_enable_local_vmclear(int cpu)
1020{
1021 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1022}
1023
1024static inline void crash_disable_local_vmclear(int cpu)
1025{
1026 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1027}
1028
1029static inline int crash_local_vmclear_enabled(int cpu)
1030{
1031 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1032}
1033
1034static void crash_vmclear_local_loaded_vmcss(void)
1035{
1036 int cpu = raw_smp_processor_id();
1037 struct loaded_vmcs *v;
1038
1039 if (!crash_local_vmclear_enabled(cpu))
1040 return;
1041
1042 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1043 loaded_vmcss_on_cpu_link)
1044 vmcs_clear(v->vmcs);
1045}
1046#else
1047static inline void crash_enable_local_vmclear(int cpu) { }
1048static inline void crash_disable_local_vmclear(int cpu) { }
1049#endif /* CONFIG_KEXEC */
1050
d462b819 1051static void __loaded_vmcs_clear(void *arg)
6aa8b732 1052{
d462b819 1053 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1054 int cpu = raw_smp_processor_id();
6aa8b732 1055
d462b819
NHE		 1056 if (loaded_vmcs->cpu != cpu)
1057 return; /* vcpu migration can race with cpu offline */
1058 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1059 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1060 crash_disable_local_vmclear(cpu);
d462b819 1061 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1062
1063 /*
1064 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065 * is before setting loaded_vmcs->vcpu to -1 which is done in
1066 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067 * then adds the vmcs into percpu list before it is deleted.
1068 */
1069 smp_wmb();
1070
d462b819 1071 loaded_vmcs_init(loaded_vmcs);
8f536b76 1072 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1073}
1074
d462b819 1075static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1076{
e6c7d321
XG		 1077 int cpu = loaded_vmcs->cpu;
1078
1079 if (cpu != -1)
1080 smp_call_function_single(cpu,
1081 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1082}
1083
1760dd49 1084static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1085{
1086 if (vmx->vpid == 0)
1087 return;
1088
518c8aee
GJ		 1089 if (cpu_has_vmx_invvpid_single())
1090 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1091}
1092
b9d762fa
GJ		 1093static inline void vpid_sync_vcpu_global(void)
1094{
1095 if (cpu_has_vmx_invvpid_global())
1096 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1097}
1098
1099static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1100{
1101 if (cpu_has_vmx_invvpid_single())
1760dd49 1102 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1103 else
1104 vpid_sync_vcpu_global();
1105}
1106
1439442c
SY		 1107static inline void ept_sync_global(void)
1108{
1109 if (cpu_has_vmx_invept_global())
1110 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1111}
1112
1113static inline void ept_sync_context(u64 eptp)
1114{
089d034e 1115 if (enable_ept) {
1439442c
SY		 1116 if (cpu_has_vmx_invept_context())
1117 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1118 else
1119 ept_sync_global();
1120 }
1121}
1122
96304217 1123static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1124{
5e520e62 1125 unsigned long value;
6aa8b732 1126
5e520e62
AK		 1127 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1128 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1129 return value;
1130}
1131
96304217 1132static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1133{
1134 return vmcs_readl(field);
1135}
1136
96304217 1137static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1138{
1139 return vmcs_readl(field);
1140}
1141
96304217 1142static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1143{
05b3e0c2 1144#ifdef CONFIG_X86_64
6aa8b732
AK		 1145 return vmcs_readl(field);
1146#else
1147 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1148#endif
1149}
1150
e52de1b8
AK		 1151static noinline void vmwrite_error(unsigned long field, unsigned long value)
1152{
1153 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1154 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1155 dump_stack();
1156}
1157
6aa8b732
AK		 1158static void vmcs_writel(unsigned long field, unsigned long value)
1159{
1160 u8 error;
1161
4ecac3fd 1162 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1163 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1164 if (unlikely(error))
1165 vmwrite_error(field, value);
6aa8b732
AK		 1166}
1167
1168static void vmcs_write16(unsigned long field, u16 value)
1169{
1170 vmcs_writel(field, value);
1171}
1172
1173static void vmcs_write32(unsigned long field, u32 value)
1174{
1175 vmcs_writel(field, value);
1176}
1177
1178static void vmcs_write64(unsigned long field, u64 value)
1179{
6aa8b732 1180 vmcs_writel(field, value);
7682f2d0 1181#ifndef CONFIG_X86_64
6aa8b732
AK		 1182 asm volatile ("");
1183 vmcs_writel(field+1, value >> 32);
1184#endif
1185}
1186
2ab455cc
AL		 1187static void vmcs_clear_bits(unsigned long field, u32 mask)
1188{
1189 vmcs_writel(field, vmcs_readl(field) & ~mask);
1190}
1191
1192static void vmcs_set_bits(unsigned long field, u32 mask)
1193{
1194 vmcs_writel(field, vmcs_readl(field) | mask);
1195}
1196
2fb92db1
AK		 1197static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1198{
1199 vmx->segment_cache.bitmask = 0;
1200}
1201
1202static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1203 unsigned field)
1204{
1205 bool ret;
1206 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1207
1208 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1209 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1210 vmx->segment_cache.bitmask = 0;
1211 }
1212 ret = vmx->segment_cache.bitmask & mask;
1213 vmx->segment_cache.bitmask |= mask;
1214 return ret;
1215}
1216
1217static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1218{
1219 u16 *p = &vmx->segment_cache.seg[seg].selector;
1220
1221 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1222 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1223 return *p;
1224}
1225
1226static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1227{
1228 ulong *p = &vmx->segment_cache.seg[seg].base;
1229
1230 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1231 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1232 return *p;
1233}
1234
1235static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1236{
1237 u32 *p = &vmx->segment_cache.seg[seg].limit;
1238
1239 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1240 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1241 return *p;
1242}
1243
1244static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1245{
1246 u32 *p = &vmx->segment_cache.seg[seg].ar;
1247
1248 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1249 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1250 return *p;
1251}
1252
abd3f2d6
AK		 1253static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1254{
1255 u32 eb;
1256
fd7373cc
JK		 1257 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1258 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1259 if ((vcpu->guest_debug &
1260 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1261 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1262 eb |= 1u << BP_VECTOR;
7ffd92c5 1263 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1264 eb = ~0;
089d034e 1265 if (enable_ept)
1439442c 1266 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1267 if (vcpu->fpu_active)
1268 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1269
1270 /* When we are running a nested L2 guest and L1 specified for it a
1271 * certain exception bitmap, we must trap the same exceptions and pass
1272 * them to L1. When running L2, we will only handle the exceptions
1273 * specified above if L1 did not want them.
1274 */
1275 if (is_guest_mode(vcpu))
1276 eb |= get_vmcs12(vcpu)->exception_bitmap;
1277
abd3f2d6
AK		 1278 vmcs_write32(EXCEPTION_BITMAP, eb);
1279}
1280
8bf00a52
GN		 1281static void clear_atomic_switch_msr_special(unsigned long entry,
1282 unsigned long exit)
1283{
1284 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1285 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1286}
1287
61d2ef2c
AK		 1288static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1289{
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
8bf00a52
GN		 1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER);
1298 return;
1299 }
1300 break;
1301 case MSR_CORE_PERF_GLOBAL_CTRL:
1302 if (cpu_has_load_perf_global_ctrl) {
1303 clear_atomic_switch_msr_special(
1304 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1305 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1306 return;
1307 }
1308 break;
110312c8
AK		 1309 }
1310
61d2ef2c
AK		 1311 for (i = 0; i < m->nr; ++i)
1312 if (m->guest[i].index == msr)
1313 break;
1314
1315 if (i == m->nr)
1316 return;
1317 --m->nr;
1318 m->guest[i] = m->guest[m->nr];
1319 m->host[i] = m->host[m->nr];
1320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1321 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1322}
1323
8bf00a52
GN		 1324static void add_atomic_switch_msr_special(unsigned long entry,
1325 unsigned long exit, unsigned long guest_val_vmcs,
1326 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1327{
1328 vmcs_write64(guest_val_vmcs, guest_val);
1329 vmcs_write64(host_val_vmcs, host_val);
1330 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1331 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1332}
1333
61d2ef2c
AK		 1334static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1335 u64 guest_val, u64 host_val)
1336{
1337 unsigned i;
1338 struct msr_autoload *m = &vmx->msr_autoload;
1339
8bf00a52
GN		 1340 switch (msr) {
1341 case MSR_EFER:
1342 if (cpu_has_load_ia32_efer) {
1343 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1344 VM_EXIT_LOAD_IA32_EFER,
1345 GUEST_IA32_EFER,
1346 HOST_IA32_EFER,
1347 guest_val, host_val);
1348 return;
1349 }
1350 break;
1351 case MSR_CORE_PERF_GLOBAL_CTRL:
1352 if (cpu_has_load_perf_global_ctrl) {
1353 add_atomic_switch_msr_special(
1354 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1356 GUEST_IA32_PERF_GLOBAL_CTRL,
1357 HOST_IA32_PERF_GLOBAL_CTRL,
1358 guest_val, host_val);
1359 return;
1360 }
1361 break;
110312c8
AK		 1362 }
1363
61d2ef2c
AK		 1364 for (i = 0; i < m->nr; ++i)
1365 if (m->guest[i].index == msr)
1366 break;
1367
e7fc6f93
GN		 1368 if (i == NR_AUTOLOAD_MSRS) {
1369 printk_once(KERN_WARNING"Not enough mst switch entries. "
1370 "Can't add msr %x\n", msr);
1371 return;
1372 } else if (i == m->nr) {
61d2ef2c
AK		 1373 ++m->nr;
1374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1376 }
1377
1378 m->guest[i].index = msr;
1379 m->guest[i].value = guest_val;
1380 m->host[i].index = msr;
1381 m->host[i].value = host_val;
1382}
1383
33ed6329
AK		 1384static void reload_tss(void)
1385{
33ed6329
AK		 1386 /*
1387 * VT restores TR but not its size. Useless.
1388 */
d359192f 1389 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1390 struct desc_struct *descs;
33ed6329 1391
d359192f 1392 descs = (void *)gdt->address;
33ed6329
AK		 1393 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1394 load_TR_desc();
33ed6329
AK		 1395}
1396
92c0d900 1397static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1398{
3a34a881 1399 u64 guest_efer;
51c6cf66
AK		 1400 u64 ignore_bits;
1401
f6801dff 1402 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1403
51c6cf66 1404 /*
0fa06071 1405 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1406 * outside long mode
1407 */
1408 ignore_bits = EFER_NX | EFER_SCE;
1409#ifdef CONFIG_X86_64
1410 ignore_bits |= EFER_LMA | EFER_LME;
1411 /* SCE is meaningful only in long mode on Intel */
1412 if (guest_efer & EFER_LMA)
1413 ignore_bits &= ~(u64)EFER_SCE;
1414#endif
51c6cf66
AK		 1415 guest_efer &= ~ignore_bits;
1416 guest_efer |= host_efer & ignore_bits;
26bb0981 1417 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1418 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1419
1420 clear_atomic_switch_msr(vmx, MSR_EFER);
1421 /* On ept, can't emulate nx, and must switch nx atomically */
1422 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1423 guest_efer = vmx->vcpu.arch.efer;
1424 if (!(guest_efer & EFER_LMA))
1425 guest_efer &= ~EFER_LME;
1426 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1427 return false;
1428 }
1429
26bb0981 1430 return true;
51c6cf66
AK		 1431}
1432
2d49ec72
GN		 1433static unsigned long segment_base(u16 selector)
1434{
d359192f 1435 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1436 struct desc_struct *d;
1437 unsigned long table_base;
1438 unsigned long v;
1439
1440 if (!(selector & ~3))
1441 return 0;
1442
d359192f 1443 table_base = gdt->address;
2d49ec72
GN		 1444
1445 if (selector & 4) { /* from ldt */
1446 u16 ldt_selector = kvm_read_ldt();
1447
1448 if (!(ldt_selector & ~3))
1449 return 0;
1450
1451 table_base = segment_base(ldt_selector);
1452 }
1453 d = (struct desc_struct *)(table_base + (selector & ~7));
1454 v = get_desc_base(d);
1455#ifdef CONFIG_X86_64
1456 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1457 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1458#endif
1459 return v;
1460}
1461
1462static inline unsigned long kvm_read_tr_base(void)
1463{
1464 u16 tr;
1465 asm("str %0" : "=g"(tr));
1466 return segment_base(tr);
1467}
1468
04d2cc77 1469static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1470{
04d2cc77 1471 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1472 int i;
04d2cc77 1473
a2fa3e9f 1474 if (vmx->host_state.loaded)
33ed6329
AK		 1475 return;
1476
a2fa3e9f 1477 vmx->host_state.loaded = 1;
33ed6329
AK		 1478 /*
1479 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1480 * allow segment selectors with cpl > 0 or ti == 1.
1481 */
d6e88aec 1482 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1483 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1484 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1485 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1486 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1487 vmx->host_state.fs_reload_needed = 0;
1488 } else {
33ed6329 1489 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1490 vmx->host_state.fs_reload_needed = 1;
33ed6329 1491 }
9581d442 1492 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1493 if (!(vmx->host_state.gs_sel & 7))
1494 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1495 else {
1496 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1497 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1498 }
1499
b2da15ac
AK		 1500#ifdef CONFIG_X86_64
1501 savesegment(ds, vmx->host_state.ds_sel);
1502 savesegment(es, vmx->host_state.es_sel);
1503#endif
1504
33ed6329
AK		 1505#ifdef CONFIG_X86_64
1506 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1507 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1508#else
a2fa3e9f
GH		 1509 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1510 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1511#endif
707c0874
AK		 1512
1513#ifdef CONFIG_X86_64
c8770e7b
AK		 1514 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1515 if (is_long_mode(&vmx->vcpu))
44ea2b17 1516 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1517#endif
26bb0981
AK		 1518 for (i = 0; i < vmx->save_nmsrs; ++i)
1519 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1520 vmx->guest_msrs[i].data,
1521 vmx->guest_msrs[i].mask);
33ed6329
AK		 1522}
1523
a9b21b62 1524static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1525{
a2fa3e9f 1526 if (!vmx->host_state.loaded)
33ed6329
AK		 1527 return;
1528
e1beb1d3 1529 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1530 vmx->host_state.loaded = 0;
c8770e7b
AK		 1531#ifdef CONFIG_X86_64
1532 if (is_long_mode(&vmx->vcpu))
1533 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1534#endif
152d3f2f 1535 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1536 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1537#ifdef CONFIG_X86_64
9581d442 1538 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1539#else
1540 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1541#endif
33ed6329 1542 }
0a77fe4c
AK		 1543 if (vmx->host_state.fs_reload_needed)
1544 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1545#ifdef CONFIG_X86_64
1546 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1547 loadsegment(ds, vmx->host_state.ds_sel);
1548 loadsegment(es, vmx->host_state.es_sel);
1549 }
b2da15ac 1550#endif
152d3f2f 1551 reload_tss();
44ea2b17 1552#ifdef CONFIG_X86_64
c8770e7b 1553 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1554#endif
b1a74bf8
SS		 1555 /*
1556 * If the FPU is not active (through the host task or
1557 * the guest vcpu), then restore the cr0.TS bit.
1558 */
1559 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1560 stts();
3444d7da 1561 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1562}
1563
a9b21b62
AK		 1564static void vmx_load_host_state(struct vcpu_vmx *vmx)
1565{
1566 preempt_disable();
1567 __vmx_load_host_state(vmx);
1568 preempt_enable();
1569}
1570
6aa8b732
AK		 1571/*
1572 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573 * vcpu mutex is already taken.
1574 */
15ad7146 1575static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1576{
a2fa3e9f 1577 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1578 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1579
4610c9cc
DX		 1580 if (!vmm_exclusive)
1581 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1582 else if (vmx->loaded_vmcs->cpu != cpu)
1583 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1584
d462b819
NHE		 1585 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1586 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1587 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1588 }
1589
d462b819 1590 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1591 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1592 unsigned long sysenter_esp;
1593
a8eeb04a 1594 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1595 local_irq_disable();
8f536b76 1596 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1597
1598 /*
1599 * Read loaded_vmcs->cpu should be before fetching
1600 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601 * See the comments in __loaded_vmcs_clear().
1602 */
1603 smp_rmb();
1604
d462b819
NHE		 1605 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1606 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1607 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1608 local_irq_enable();
1609
6aa8b732
AK		 1610 /*
1611 * Linux uses per-cpu TSS and GDT, so set these when switching
1612 * processors.
1613 */
d6e88aec 1614 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1615 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1616
1617 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1618 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1619 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1620 }
6aa8b732
AK		 1621}
1622
1623static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1624{
a9b21b62 1625 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1626 if (!vmm_exclusive) {
d462b819
NHE		 1627 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1628 vcpu->cpu = -1;
4610c9cc
DX		 1629 kvm_cpu_vmxoff();
1630 }
6aa8b732
AK		 1631}
1632
5fd86fcf
AK		 1633static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1634{
81231c69
AK		 1635 ulong cr0;
1636
5fd86fcf
AK		 1637 if (vcpu->fpu_active)
1638 return;
1639 vcpu->fpu_active = 1;
81231c69
AK		 1640 cr0 = vmcs_readl(GUEST_CR0);
1641 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1642 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1643 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1644 update_exception_bitmap(vcpu);
edcafe3c 1645 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1646 if (is_guest_mode(vcpu))
1647 vcpu->arch.cr0_guest_owned_bits &=
1648 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1649 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1650}
1651
edcafe3c
AK		 1652static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1653
fe3ef05c
NHE		 1654/*
1655 * Return the cr0 value that a nested guest would read. This is a combination
1656 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657 * its hypervisor (cr0_read_shadow).
1658 */
1659static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1660{
1661 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1662 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1663}
1664static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1665{
1666 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1667 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1668}
1669
5fd86fcf
AK		 1670static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1671{
36cf24e0
NHE		 1672 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673 * set this *before* calling this function.
1674 */
edcafe3c 1675 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1676 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1677 update_exception_bitmap(vcpu);
edcafe3c
AK		 1678 vcpu->arch.cr0_guest_owned_bits = 0;
1679 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1680 if (is_guest_mode(vcpu)) {
1681 /*
1682 * L1's specified read shadow might not contain the TS bit,
1683 * so now that we turned on shadowing of this bit, we need to
1684 * set this bit of the shadow. Like in nested_vmx_run we need
1685 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686 * up-to-date here because we just decached cr0.TS (and we'll
1687 * only update vmcs12->guest_cr0 on nested exit).
1688 */
1689 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1690 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1691 (vcpu->arch.cr0 & X86_CR0_TS);
1692 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1693 } else
1694 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1695}
1696
6aa8b732
AK		 1697static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1698{
78ac8b47 1699 unsigned long rflags, save_rflags;
345dcaa8 1700
6de12732
AK		 1701 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1702 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1703 rflags = vmcs_readl(GUEST_RFLAGS);
1704 if (to_vmx(vcpu)->rmode.vm86_active) {
1705 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1706 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1707 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1708 }
1709 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1710 }
6de12732 1711 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1712}
1713
1714static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1715{
6de12732
AK		 1716 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1717 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1718 if (to_vmx(vcpu)->rmode.vm86_active) {
1719 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1720 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1721 }
6aa8b732
AK		 1722 vmcs_writel(GUEST_RFLAGS, rflags);
1723}
1724
2809f5d2
GC		 1725static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1726{
1727 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1728 int ret = 0;
1729
1730 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1731 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1732 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1733 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1734
1735 return ret & mask;
1736}
1737
1738static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1739{
1740 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1741 u32 interruptibility = interruptibility_old;
1742
1743 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1744
48005f64 1745 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1746 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1747 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1748 interruptibility |= GUEST_INTR_STATE_STI;
1749
1750 if ((interruptibility != interruptibility_old))
1751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1752}
1753
6aa8b732
AK		 1754static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1755{
1756 unsigned long rip;
6aa8b732 1757
5fdbf976 1758 rip = kvm_rip_read(vcpu);
6aa8b732 1759 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1760 kvm_rip_write(vcpu, rip);
6aa8b732 1761
2809f5d2
GC		 1762 /* skipping an emulated instruction also counts */
1763 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1764}
1765
0b6ac343
NHE		 1766/*
1767 * KVM wants to inject page-faults which it got to the guest. This function
1768 * checks whether in a nested guest, we need to inject them to L1 or L2.
1769 * This function assumes it is called with the exit reason in vmcs02 being
1770 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1771 * is running).
1772 */
1773static int nested_pf_handled(struct kvm_vcpu *vcpu)
1774{
1775 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1776
1777 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1778 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1779 return 0;
1780
1781 nested_vmx_vmexit(vcpu);
1782 return 1;
1783}
1784
298101da 1785static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1786 bool has_error_code, u32 error_code,
1787 bool reinject)
298101da 1788{
77ab6db0 1789 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1790 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1791
0b6ac343
NHE		 1792 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1793 nested_pf_handled(vcpu))
1794 return;
1795
8ab2d2e2 1796 if (has_error_code) {
77ab6db0 1797 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1798 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1799 }
77ab6db0 1800
7ffd92c5 1801 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1802 int inc_eip = 0;
1803 if (kvm_exception_is_soft(nr))
1804 inc_eip = vcpu->arch.event_exit_inst_len;
1805 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1806 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1807 return;
1808 }
1809
66fd3f7f
GN		 1810 if (kvm_exception_is_soft(nr)) {
1811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1812 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1813 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1814 } else
1815 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1816
1817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1818}
1819
4e47c7a6
SY		 1820static bool vmx_rdtscp_supported(void)
1821{
1822 return cpu_has_vmx_rdtscp();
1823}
1824
ad756a16
MJ		 1825static bool vmx_invpcid_supported(void)
1826{
1827 return cpu_has_vmx_invpcid() && enable_ept;
1828}
1829
a75beee6
ED		 1830/*
1831 * Swap MSR entry in host/guest MSR entry array.
1832 */
8b9cf98c 1833static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1834{
26bb0981 1835 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1836
1837 tmp = vmx->guest_msrs[to];
1838 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1839 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1840}
1841
8d14695f
YZ		 1842static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1843{
1844 unsigned long *msr_bitmap;
1845
1846 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1847 if (is_long_mode(vcpu))
1848 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1849 else
1850 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1851 } else {
1852 if (is_long_mode(vcpu))
1853 msr_bitmap = vmx_msr_bitmap_longmode;
1854 else
1855 msr_bitmap = vmx_msr_bitmap_legacy;
1856 }
1857
1858 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1859}
1860
e38aea3e
AK		 1861/*
1862 * Set up the vmcs to automatically save and restore system
1863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1864 * mode, as fiddling with msrs is very expensive.
1865 */
8b9cf98c 1866static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1867{
26bb0981 1868 int save_nmsrs, index;
e38aea3e 1869
a75beee6
ED		 1870 save_nmsrs = 0;
1871#ifdef CONFIG_X86_64
8b9cf98c 1872 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1873 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1874 if (index >= 0)
8b9cf98c
RR		 1875 move_msr_up(vmx, index, save_nmsrs++);
1876 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1877 if (index >= 0)
8b9cf98c
RR		 1878 move_msr_up(vmx, index, save_nmsrs++);
1879 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1880 if (index >= 0)
8b9cf98c 1881 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1882 index = __find_msr_index(vmx, MSR_TSC_AUX);
1883 if (index >= 0 && vmx->rdtscp_enabled)
1884 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1885 /*
8c06585d 1886 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1887 * if efer.sce is enabled.
1888 */
8c06585d 1889 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1890 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1891 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1892 }
1893#endif
92c0d900
AK		 1894 index = __find_msr_index(vmx, MSR_EFER);
1895 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1896 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1897
26bb0981 1898 vmx->save_nmsrs = save_nmsrs;
5897297b 1899
8d14695f
YZ		 1900 if (cpu_has_vmx_msr_bitmap())
1901 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1902}
1903
6aa8b732
AK		 1904/*
1905 * reads and returns guest's timestamp counter "register"
1906 * guest_tsc = host_tsc + tsc_offset -- 21.3
1907 */
1908static u64 guest_read_tsc(void)
1909{
1910 u64 host_tsc, tsc_offset;
1911
1912 rdtscll(host_tsc);
1913 tsc_offset = vmcs_read64(TSC_OFFSET);
1914 return host_tsc + tsc_offset;
1915}
1916
d5c1785d
NHE		 1917/*
1918 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919 * counter, even if a nested guest (L2) is currently running.
1920 */
886b470c 1921u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1922{
886b470c 1923 u64 tsc_offset;
d5c1785d 1924
d5c1785d
NHE		 1925 tsc_offset = is_guest_mode(vcpu) ?
1926 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1927 vmcs_read64(TSC_OFFSET);
1928 return host_tsc + tsc_offset;
1929}
1930
4051b188 1931/*
cc578287
ZA		 1932 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1933 * software catchup for faster rates on slower CPUs.
4051b188 1934 */
cc578287 1935static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1936{
cc578287
ZA		 1937 if (!scale)
1938 return;
1939
1940 if (user_tsc_khz > tsc_khz) {
1941 vcpu->arch.tsc_catchup = 1;
1942 vcpu->arch.tsc_always_catchup = 1;
1943 } else
1944 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1945}
1946
ba904635
WA		 1947static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1948{
1949 return vmcs_read64(TSC_OFFSET);
1950}
1951
6aa8b732 1952/*
99e3e30a 1953 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1954 */
99e3e30a 1955static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1956{
27fc51b2 1957 if (is_guest_mode(vcpu)) {
7991825b 1958 /*
27fc51b2
NHE		 1959 * We're here if L1 chose not to trap WRMSR to TSC. According
1960 * to the spec, this should set L1's TSC; The offset that L1
1961 * set for L2 remains unchanged, and still needs to be added
1962 * to the newly set TSC to get L2's TSC.
7991825b 1963 */
27fc51b2
NHE		 1964 struct vmcs12 *vmcs12;
1965 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1966 /* recalculate vmcs02.TSC_OFFSET: */
1967 vmcs12 = get_vmcs12(vcpu);
1968 vmcs_write64(TSC_OFFSET, offset +
1969 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1970 vmcs12->tsc_offset : 0));
1971 } else {
1972 vmcs_write64(TSC_OFFSET, offset);
1973 }
6aa8b732
AK		 1974}
1975
f1e2b260 1976static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1977{
1978 u64 offset = vmcs_read64(TSC_OFFSET);
1979 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1980 if (is_guest_mode(vcpu)) {
1981 /* Even when running L2, the adjustment needs to apply to L1 */
1982 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1983 }
e48672fa
ZA		 1984}
1985
857e4099
JR		 1986static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1987{
1988 return target_tsc - native_read_tsc();
1989}
1990
801d3424
NHE		 1991static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1992{
1993 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1994 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1995}
1996
1997/*
1998 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000 * all guests if the "nested" module option is off, and can also be disabled
2001 * for a single guest by disabling its VMX cpuid bit.
2002 */
2003static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2004{
2005 return nested && guest_cpuid_has_vmx(vcpu);
2006}
2007
b87a51ae
NHE		 2008/*
2009 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010 * returned for the various VMX controls MSRs when nested VMX is enabled.
2011 * The same values should also be used to verify that vmcs12 control fields are
2012 * valid during nested entry from L1 to L2.
2013 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015 * bit in the high half is on if the corresponding bit in the control field
2016 * may be on. See also vmx_control_verify().
2017 * TODO: allow these variables to be modified (downgraded) by module options
2018 * or other means.
2019 */
2020static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2021static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2022static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2023static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2024static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2025static __init void nested_vmx_setup_ctls_msrs(void)
2026{
2027 /*
2028 * Note that as a general rule, the high half of the MSRs (bits in
2029 * the control fields which may be 1) should be initialized by the
2030 * intersection of the underlying hardware's MSR (i.e., features which
2031 * can be supported) and the list of features we want to expose -
2032 * because they are known to be properly supported in our code.
2033 * Also, usually, the low half of the MSRs (bits which must be 1) can
2034 * be set to 0, meaning that L1 may turn off any of these bits. The
2035 * reason is that if one of these bits is necessary, it will appear
2036 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037 * fields of vmcs01 and vmcs02, will turn these bits off - and
2038 * nested_vmx_exit_handled() will not pass related exits to L1.
2039 * These rules have exceptions below.
2040 */
2041
2042 /* pin-based controls */
eabeaacc
JK		 2043 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2044 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2045 /*
2046 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2047 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2048 */
eabeaacc
JK		 2049 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2050 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2051 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2052 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2053
33fb20c3
JK		 2054 /*
2055 * Exit controls
2056 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2057 * 17 must be 1.
2058 */
2059 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2060 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2061#ifdef CONFIG_X86_64
2062 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2063#else
2064 nested_vmx_exit_ctls_high = 0;
2065#endif
33fb20c3 2066 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2067
2068 /* entry controls */
2069 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2070 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2071 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2072 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2073 nested_vmx_entry_ctls_high &=
2074 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2075 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2076
2077 /* cpu-based controls */
2078 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2079 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2080 nested_vmx_procbased_ctls_low = 0;
2081 nested_vmx_procbased_ctls_high &=
2082 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2083 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2084 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2085 CPU_BASED_CR3_STORE_EXITING |
2086#ifdef CONFIG_X86_64
2087 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2088#endif
2089 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2090 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2091 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2092 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2093 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2094 /*
2095 * We can allow some features even when not supported by the
2096 * hardware. For example, L1 can specify an MSR bitmap - and we
2097 * can use it to avoid exits to L1 - even when L0 runs L2
2098 * without MSR bitmaps.
2099 */
2100 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2101
2102 /* secondary cpu-based controls */
2103 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2104 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2105 nested_vmx_secondary_ctls_low = 0;
2106 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2107 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2108 SECONDARY_EXEC_WBINVD_EXITING;
b87a51ae
NHE		 2109}
2110
2111static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2112{
2113 /*
2114 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2115 */
2116 return ((control & high) | low) == control;
2117}
2118
2119static inline u64 vmx_control_msr(u32 low, u32 high)
2120{
2121 return low | ((u64)high << 32);
2122}
2123
2124/*
2125 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2126 * also let it use VMX-specific MSRs.
2127 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2128 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2129 * like all other MSRs).
2130 */
2131static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2132{
2133 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2134 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2135 /*
2136 * According to the spec, processors which do not support VMX
2137 * should throw a #GP(0) when VMX capability MSRs are read.
2138 */
2139 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2140 return 1;
2141 }
2142
2143 switch (msr_index) {
2144 case MSR_IA32_FEATURE_CONTROL:
2145 *pdata = 0;
2146 break;
2147 case MSR_IA32_VMX_BASIC:
2148 /*
2149 * This MSR reports some information about VMX support. We
2150 * should return information about the VMX we emulate for the
2151 * guest, and the VMCS structure we give it - not about the
2152 * VMX support of the underlying hardware.
2153 */
2154 *pdata = VMCS12_REVISION |
2155 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2156 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2157 break;
2158 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2159 case MSR_IA32_VMX_PINBASED_CTLS:
2160 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2161 nested_vmx_pinbased_ctls_high);
2162 break;
2163 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2164 case MSR_IA32_VMX_PROCBASED_CTLS:
2165 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2166 nested_vmx_procbased_ctls_high);
2167 break;
2168 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2169 case MSR_IA32_VMX_EXIT_CTLS:
2170 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2171 nested_vmx_exit_ctls_high);
2172 break;
2173 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2174 case MSR_IA32_VMX_ENTRY_CTLS:
2175 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2176 nested_vmx_entry_ctls_high);
2177 break;
2178 case MSR_IA32_VMX_MISC:
2179 *pdata = 0;
2180 break;
2181 /*
2182 * These MSRs specify bits which the guest must keep fixed (on or off)
2183 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2184 * We picked the standard core2 setting.
2185 */
2186#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2187#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2188 case MSR_IA32_VMX_CR0_FIXED0:
2189 *pdata = VMXON_CR0_ALWAYSON;
2190 break;
2191 case MSR_IA32_VMX_CR0_FIXED1:
2192 *pdata = -1ULL;
2193 break;
2194 case MSR_IA32_VMX_CR4_FIXED0:
2195 *pdata = VMXON_CR4_ALWAYSON;
2196 break;
2197 case MSR_IA32_VMX_CR4_FIXED1:
2198 *pdata = -1ULL;
2199 break;
2200 case MSR_IA32_VMX_VMCS_ENUM:
2201 *pdata = 0x1f;
2202 break;
2203 case MSR_IA32_VMX_PROCBASED_CTLS2:
2204 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2205 nested_vmx_secondary_ctls_high);
2206 break;
2207 case MSR_IA32_VMX_EPT_VPID_CAP:
2208 /* Currently, no nested ept or nested vpid */
2209 *pdata = 0;
2210 break;
2211 default:
2212 return 0;
2213 }
2214
2215 return 1;
2216}
2217
2218static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2219{
2220 if (!nested_vmx_allowed(vcpu))
2221 return 0;
2222
2223 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2224 /* TODO: the right thing. */
2225 return 1;
2226 /*
2227 * No need to treat VMX capability MSRs specially: If we don't handle
2228 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2229 */
2230 return 0;
2231}
2232
6aa8b732
AK		 2233/*
2234 * Reads an msr value (of 'msr_index') into 'pdata'.
2235 * Returns 0 on success, non-0 otherwise.
2236 * Assumes vcpu_load() was already called.
2237 */
2238static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2239{
2240 u64 data;
26bb0981 2241 struct shared_msr_entry *msr;
6aa8b732
AK		 2242
2243 if (!pdata) {
2244 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2245 return -EINVAL;
2246 }
2247
2248 switch (msr_index) {
05b3e0c2 2249#ifdef CONFIG_X86_64
6aa8b732
AK		 2250 case MSR_FS_BASE:
2251 data = vmcs_readl(GUEST_FS_BASE);
2252 break;
2253 case MSR_GS_BASE:
2254 data = vmcs_readl(GUEST_GS_BASE);
2255 break;
44ea2b17
AK		 2256 case MSR_KERNEL_GS_BASE:
2257 vmx_load_host_state(to_vmx(vcpu));
2258 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2259 break;
26bb0981 2260#endif
6aa8b732 2261 case MSR_EFER:
3bab1f5d 2262 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2263 case MSR_IA32_TSC:
6aa8b732
AK		 2264 data = guest_read_tsc();
2265 break;
2266 case MSR_IA32_SYSENTER_CS:
2267 data = vmcs_read32(GUEST_SYSENTER_CS);
2268 break;
2269 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2270 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2271 break;
2272 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2273 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2274 break;
4e47c7a6
SY		 2275 case MSR_TSC_AUX:
2276 if (!to_vmx(vcpu)->rdtscp_enabled)
2277 return 1;
2278 /* Otherwise falls through */
6aa8b732 2279 default:
b87a51ae
NHE		 2280 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2281 return 0;
8b9cf98c 2282 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2283 if (msr) {
2284 data = msr->data;
2285 break;
6aa8b732 2286 }
3bab1f5d 2287 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2288 }
2289
2290 *pdata = data;
2291 return 0;
2292}
2293
2294/*
2295 * Writes msr value into into the appropriate "register".
2296 * Returns 0 on success, non-0 otherwise.
2297 * Assumes vcpu_load() was already called.
2298 */
8fe8ab46 2299static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2300{
a2fa3e9f 2301 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2302 struct shared_msr_entry *msr;
2cc51560 2303 int ret = 0;
8fe8ab46
WA		 2304 u32 msr_index = msr_info->index;
2305 u64 data = msr_info->data;
2cc51560 2306
6aa8b732 2307 switch (msr_index) {
3bab1f5d 2308 case MSR_EFER:
8fe8ab46 2309 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2310 break;
16175a79 2311#ifdef CONFIG_X86_64
6aa8b732 2312 case MSR_FS_BASE:
2fb92db1 2313 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2314 vmcs_writel(GUEST_FS_BASE, data);
2315 break;
2316 case MSR_GS_BASE:
2fb92db1 2317 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2318 vmcs_writel(GUEST_GS_BASE, data);
2319 break;
44ea2b17
AK		 2320 case MSR_KERNEL_GS_BASE:
2321 vmx_load_host_state(vmx);
2322 vmx->msr_guest_kernel_gs_base = data;
2323 break;
6aa8b732
AK		 2324#endif
2325 case MSR_IA32_SYSENTER_CS:
2326 vmcs_write32(GUEST_SYSENTER_CS, data);
2327 break;
2328 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2329 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2330 break;
2331 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2332 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2333 break;
af24a4e4 2334 case MSR_IA32_TSC:
8fe8ab46 2335 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2336 break;
468d472f
SY		 2337 case MSR_IA32_CR_PAT:
2338 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2339 vmcs_write64(GUEST_IA32_PAT, data);
2340 vcpu->arch.pat = data;
2341 break;
2342 }
8fe8ab46 2343 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2344 break;
ba904635
WA		 2345 case MSR_IA32_TSC_ADJUST:
2346 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2347 break;
2348 case MSR_TSC_AUX:
2349 if (!vmx->rdtscp_enabled)
2350 return 1;
2351 /* Check reserved bit, higher 32 bits should be zero */
2352 if ((data >> 32) != 0)
2353 return 1;
2354 /* Otherwise falls through */
6aa8b732 2355 default:
b87a51ae
NHE		 2356 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2357 break;
8b9cf98c 2358 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2359 if (msr) {
2360 msr->data = data;
2225fd56
AK		 2361 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2362 preempt_disable();
9ee73970
AK		 2363 kvm_set_shared_msr(msr->index, msr->data,
2364 msr->mask);
2225fd56
AK		 2365 preempt_enable();
2366 }
3bab1f5d 2367 break;
6aa8b732 2368 }
8fe8ab46 2369 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2370 }
2371
2cc51560 2372 return ret;
6aa8b732
AK		 2373}
2374
5fdbf976 2375static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2376{
5fdbf976
MT		 2377 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2378 switch (reg) {
2379 case VCPU_REGS_RSP:
2380 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2381 break;
2382 case VCPU_REGS_RIP:
2383 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2384 break;
6de4f3ad
AK		 2385 case VCPU_EXREG_PDPTR:
2386 if (enable_ept)
2387 ept_save_pdptrs(vcpu);
2388 break;
5fdbf976
MT		 2389 default:
2390 break;
2391 }
6aa8b732
AK		 2392}
2393
6aa8b732
AK		 2394static __init int cpu_has_kvm_support(void)
2395{
6210e37b 2396 return cpu_has_vmx();
6aa8b732
AK		 2397}
2398
2399static __init int vmx_disabled_by_bios(void)
2400{
2401 u64 msr;
2402
2403 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2404 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2405 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2406 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2407 && tboot_enabled())
2408 return 1;
23f3e991 2409 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2410 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2411 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2412 && !tboot_enabled()) {
2413 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2414 "activate TXT before enabling KVM\n");
cafd6659 2415 return 1;
f9335afe 2416 }
23f3e991
JC		 2417 /* launched w/o TXT and VMX disabled */
2418 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2419 && !tboot_enabled())
2420 return 1;
cafd6659
SW		 2421 }
2422
2423 return 0;
6aa8b732
AK		 2424}
2425
7725b894
DX		 2426static void kvm_cpu_vmxon(u64 addr)
2427{
2428 asm volatile (ASM_VMX_VMXON_RAX
2429 : : "a"(&addr), "m"(addr)
2430 : "memory", "cc");
2431}
2432
10474ae8 2433static int hardware_enable(void *garbage)
6aa8b732
AK		 2434{
2435 int cpu = raw_smp_processor_id();
2436 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2437 u64 old, test_bits;
6aa8b732 2438
10474ae8
AG		 2439 if (read_cr4() & X86_CR4_VMXE)
2440 return -EBUSY;
2441
d462b819 2442 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2443
2444 /*
2445 * Now we can enable the vmclear operation in kdump
2446 * since the loaded_vmcss_on_cpu list on this cpu
2447 * has been initialized.
2448 *
2449 * Though the cpu is not in VMX operation now, there
2450 * is no problem to enable the vmclear operation
2451 * for the loaded_vmcss_on_cpu list is empty!
2452 */
2453 crash_enable_local_vmclear(cpu);
2454
6aa8b732 2455 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2456
2457 test_bits = FEATURE_CONTROL_LOCKED;
2458 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2459 if (tboot_enabled())
2460 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2461
2462 if ((old & test_bits) != test_bits) {
6aa8b732 2463 /* enable and lock */
cafd6659
SW		 2464 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2465 }
66aee91a 2466 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2467
4610c9cc
DX		 2468 if (vmm_exclusive) {
2469 kvm_cpu_vmxon(phys_addr);
2470 ept_sync_global();
2471 }
10474ae8 2472
3444d7da
AK		 2473 store_gdt(&__get_cpu_var(host_gdt));
2474
10474ae8 2475 return 0;
6aa8b732
AK		 2476}
2477
d462b819 2478static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2479{
2480 int cpu = raw_smp_processor_id();
d462b819 2481 struct loaded_vmcs *v, *n;
543e4243 2482
d462b819
NHE		 2483 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2484 loaded_vmcss_on_cpu_link)
2485 __loaded_vmcs_clear(v);
543e4243
AK		 2486}
2487
710ff4a8
EH		 2488
2489/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2490 * tricks.
2491 */
2492static void kvm_cpu_vmxoff(void)
6aa8b732 2493{
4ecac3fd 2494 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2495}
2496
710ff4a8
EH		 2497static void hardware_disable(void *garbage)
2498{
4610c9cc 2499 if (vmm_exclusive) {
d462b819 2500 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2501 kvm_cpu_vmxoff();
2502 }
7725b894 2503 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2504}
2505
1c3d14fe 2506static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2507 u32 msr, u32 *result)
1c3d14fe
YS		 2508{
2509 u32 vmx_msr_low, vmx_msr_high;
2510 u32 ctl = ctl_min | ctl_opt;
2511
2512 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2513
2514 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2515 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2516
2517 /* Ensure minimum (required) set of control bits are supported. */
2518 if (ctl_min & ~ctl)
002c7f7c 2519 return -EIO;
1c3d14fe
YS		 2520
2521 *result = ctl;
2522 return 0;
2523}
2524
110312c8
AK		 2525static __init bool allow_1_setting(u32 msr, u32 ctl)
2526{
2527 u32 vmx_msr_low, vmx_msr_high;
2528
2529 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2530 return vmx_msr_high & ctl;
2531}
2532
002c7f7c 2533static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2534{
2535 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2536 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2537 u32 _pin_based_exec_control = 0;
2538 u32 _cpu_based_exec_control = 0;
f78e0e2e 2539 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2540 u32 _vmexit_control = 0;
2541 u32 _vmentry_control = 0;
2542
2543 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2544 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2545 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2546 &_pin_based_exec_control) < 0)
002c7f7c 2547 return -EIO;
1c3d14fe 2548
10166744 2549 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2550#ifdef CONFIG_X86_64
2551 CPU_BASED_CR8_LOAD_EXITING |
2552 CPU_BASED_CR8_STORE_EXITING |
2553#endif
d56f546d
SY		 2554 CPU_BASED_CR3_LOAD_EXITING |
2555 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2556 CPU_BASED_USE_IO_BITMAPS |
2557 CPU_BASED_MOV_DR_EXITING |
a7052897 2558 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2559 CPU_BASED_MWAIT_EXITING |
2560 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2561 CPU_BASED_INVLPG_EXITING |
2562 CPU_BASED_RDPMC_EXITING;
443381a8 2563
f78e0e2e 2564 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2565 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2566 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2567 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2568 &_cpu_based_exec_control) < 0)
002c7f7c 2569 return -EIO;
6e5d865c
YS		 2570#ifdef CONFIG_X86_64
2571 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2572 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2573 ~CPU_BASED_CR8_STORE_EXITING;
2574#endif
f78e0e2e 2575 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2576 min2 = 0;
2577 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2578 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2579 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2580 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2581 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2582 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2583 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2584 SECONDARY_EXEC_RDTSCP |
83d4c286 2585 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c
YZ		 2586 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2587 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
d56f546d
SY		 2588 if (adjust_vmx_controls(min2, opt2,
2589 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2590 &_cpu_based_2nd_exec_control) < 0)
2591 return -EIO;
2592 }
2593#ifndef CONFIG_X86_64
2594 if (!(_cpu_based_2nd_exec_control &
2595 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2596 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2597#endif
83d4c286
YZ		 2598
2599 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2600 _cpu_based_2nd_exec_control &= ~(
8d14695f 2601 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2602 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2603 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2604
d56f546d 2605 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2606 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2607 enabled */
5fff7d27
GN		 2608 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2609 CPU_BASED_CR3_STORE_EXITING |
2610 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2611 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2612 vmx_capability.ept, vmx_capability.vpid);
2613 }
1c3d14fe
YS		 2614
2615 min = 0;
2616#ifdef CONFIG_X86_64
2617 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2618#endif
468d472f 2619 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2620 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2621 &_vmexit_control) < 0)
002c7f7c 2622 return -EIO;
1c3d14fe 2623
468d472f
SY		 2624 min = 0;
2625 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2626 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2627 &_vmentry_control) < 0)
002c7f7c 2628 return -EIO;
6aa8b732 2629
c68876fd 2630 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2631
2632 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2633 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2634 return -EIO;
1c3d14fe
YS		 2635
2636#ifdef CONFIG_X86_64
2637 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2638 if (vmx_msr_high & (1u<<16))
002c7f7c 2639 return -EIO;
1c3d14fe
YS		 2640#endif
2641
2642 /* Require Write-Back (WB) memory type for VMCS accesses. */
2643 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2644 return -EIO;
1c3d14fe 2645
002c7f7c
YS		 2646 vmcs_conf->size = vmx_msr_high & 0x1fff;
2647 vmcs_conf->order = get_order(vmcs_config.size);
2648 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2649
002c7f7c
YS		 2650 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2651 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2652 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2653 vmcs_conf->vmexit_ctrl = _vmexit_control;
2654 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2655
110312c8
AK		 2656 cpu_has_load_ia32_efer =
2657 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2658 VM_ENTRY_LOAD_IA32_EFER)
2659 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2660 VM_EXIT_LOAD_IA32_EFER);
2661
8bf00a52
GN		 2662 cpu_has_load_perf_global_ctrl =
2663 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2664 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2665 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2666 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2667
2668 /*
2669 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2670 * but due to arrata below it can't be used. Workaround is to use
2671 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2672 *
2673 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2674 *
2675 * AAK155 (model 26)
2676 * AAP115 (model 30)
2677 * AAT100 (model 37)
2678 * BC86,AAY89,BD102 (model 44)
2679 * BA97 (model 46)
2680 *
2681 */
2682 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2683 switch (boot_cpu_data.x86_model) {
2684 case 26:
2685 case 30:
2686 case 37:
2687 case 44:
2688 case 46:
2689 cpu_has_load_perf_global_ctrl = false;
2690 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2691 "does not work properly. Using workaround\n");
2692 break;
2693 default:
2694 break;
2695 }
2696 }
2697
1c3d14fe 2698 return 0;
c68876fd 2699}
6aa8b732
AK		 2700
2701static struct vmcs *alloc_vmcs_cpu(int cpu)
2702{
2703 int node = cpu_to_node(cpu);
2704 struct page *pages;
2705 struct vmcs *vmcs;
2706
6484eb3e 2707 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2708 if (!pages)
2709 return NULL;
2710 vmcs = page_address(pages);
1c3d14fe
YS		 2711 memset(vmcs, 0, vmcs_config.size);
2712 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2713 return vmcs;
2714}
2715
2716static struct vmcs *alloc_vmcs(void)
2717{
d3b2c338 2718 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2719}
2720
2721static void free_vmcs(struct vmcs *vmcs)
2722{
1c3d14fe 2723 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2724}
2725
d462b819
NHE		 2726/*
2727 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2728 */
2729static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2730{
2731 if (!loaded_vmcs->vmcs)
2732 return;
2733 loaded_vmcs_clear(loaded_vmcs);
2734 free_vmcs(loaded_vmcs->vmcs);
2735 loaded_vmcs->vmcs = NULL;
2736}
2737
39959588 2738static void free_kvm_area(void)
6aa8b732
AK		 2739{
2740 int cpu;
2741
3230bb47 2742 for_each_possible_cpu(cpu) {
6aa8b732 2743 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2744 per_cpu(vmxarea, cpu) = NULL;
2745 }
6aa8b732
AK		 2746}
2747
6aa8b732
AK		 2748static __init int alloc_kvm_area(void)
2749{
2750 int cpu;
2751
3230bb47 2752 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2753 struct vmcs *vmcs;
2754
2755 vmcs = alloc_vmcs_cpu(cpu);
2756 if (!vmcs) {
2757 free_kvm_area();
2758 return -ENOMEM;
2759 }
2760
2761 per_cpu(vmxarea, cpu) = vmcs;
2762 }
2763 return 0;
2764}
2765
2766static __init int hardware_setup(void)
2767{
002c7f7c
YS		 2768 if (setup_vmcs_config(&vmcs_config) < 0)
2769 return -EIO;
50a37eb4
JR		 2770
2771 if (boot_cpu_has(X86_FEATURE_NX))
2772 kvm_enable_efer_bits(EFER_NX);
2773
93ba03c2
SY		 2774 if (!cpu_has_vmx_vpid())
2775 enable_vpid = 0;
2776
4bc9b982
SY		 2777 if (!cpu_has_vmx_ept() ||
2778 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2779 enable_ept = 0;
3a624e29 2780 enable_unrestricted_guest = 0;
83c3a331 2781 enable_ept_ad_bits = 0;
3a624e29
NK		 2782 }
2783
83c3a331
XH		 2784 if (!cpu_has_vmx_ept_ad_bits())
2785 enable_ept_ad_bits = 0;
2786
3a624e29
NK		 2787 if (!cpu_has_vmx_unrestricted_guest())
2788 enable_unrestricted_guest = 0;
93ba03c2
SY		 2789
2790 if (!cpu_has_vmx_flexpriority())
2791 flexpriority_enabled = 0;
2792
95ba8273
GN		 2793 if (!cpu_has_vmx_tpr_shadow())
2794 kvm_x86_ops->update_cr8_intercept = NULL;
2795
54dee993
MT		 2796 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2797 kvm_disable_largepages();
2798
4b8d54f9
ZE		 2799 if (!cpu_has_vmx_ple())
2800 ple_gap = 0;
2801
c7c9c56c
YZ		 2802 if (!cpu_has_vmx_apic_register_virt() ||
2803 !cpu_has_vmx_virtual_intr_delivery())
2804 enable_apicv_reg_vid = 0;
2805
2806 if (enable_apicv_reg_vid)
2807 kvm_x86_ops->update_cr8_intercept = NULL;
2808 else
2809 kvm_x86_ops->hwapic_irr_update = NULL;
83d4c286 2810
b87a51ae
NHE		 2811 if (nested)
2812 nested_vmx_setup_ctls_msrs();
2813
6aa8b732
AK		 2814 return alloc_kvm_area();
2815}
2816
2817static __exit void hardware_unsetup(void)
2818{
2819 free_kvm_area();
2820}
2821
14168786
GN		 2822static bool emulation_required(struct kvm_vcpu *vcpu)
2823{
2824 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2825}
2826
91b0aa2c 2827static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2828 struct kvm_segment *save)
6aa8b732 2829{
d99e4152
GN		 2830 if (!emulate_invalid_guest_state) {
2831 /*
2832 * CS and SS RPL should be equal during guest entry according
2833 * to VMX spec, but in reality it is not always so. Since vcpu
2834 * is in the middle of the transition from real mode to
2835 * protected mode it is safe to assume that RPL 0 is a good
2836 * default value.
2837 */
2838 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2839 save->selector &= ~SELECTOR_RPL_MASK;
2840 save->dpl = save->selector & SELECTOR_RPL_MASK;
2841 save->s = 1;
6aa8b732 2842 }
d99e4152 2843 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2844}
2845
2846static void enter_pmode(struct kvm_vcpu *vcpu)
2847{
2848 unsigned long flags;
a89a8fb9 2849 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2850
d99e4152
GN		 2851 /*
2852 * Update real mode segment cache. It may be not up-to-date if sement
2853 * register was written while vcpu was in a guest mode.
2854 */
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2859 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2860 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2861
7ffd92c5 2862 vmx->rmode.vm86_active = 0;
6aa8b732 2863
2fb92db1
AK		 2864 vmx_segment_cache_clear(vmx);
2865
f5f7b2fe 2866 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2867
2868 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2869 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2870 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2871 vmcs_writel(GUEST_RFLAGS, flags);
2872
66aee91a
RR		 2873 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2874 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2875
2876 update_exception_bitmap(vcpu);
2877
91b0aa2c
GN		 2878 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2879 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2880 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2881 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2882 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2883 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 2884
2885 /* CPL is always 0 when CPU enters protected mode */
2886 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2887 vmx->cpl = 0;
6aa8b732
AK		 2888}
2889
d77c26fc 2890static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2891{
bfc6d222 2892 if (!kvm->arch.tss_addr) {
bc6678a3 2893 struct kvm_memslots *slots;
28a37544 2894 struct kvm_memory_slot *slot;
bc6678a3
MT		 2895 gfn_t base_gfn;
2896
90d83dc3 2897 slots = kvm_memslots(kvm);
28a37544
XG		 2898 slot = id_to_memslot(slots, 0);
2899 base_gfn = slot->base_gfn + slot->npages - 3;
2900
cbc94022
IE		 2901 return base_gfn << PAGE_SHIFT;
2902 }
bfc6d222 2903 return kvm->arch.tss_addr;
6aa8b732
AK		 2904}
2905
f5f7b2fe 2906static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2907{
772e0318 2908 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2909 struct kvm_segment var = *save;
2910
2911 var.dpl = 0x3;
2912 if (seg == VCPU_SREG_CS)
2913 var.type = 0x3;
2914
2915 if (!emulate_invalid_guest_state) {
2916 var.selector = var.base >> 4;
2917 var.base = var.base & 0xffff0;
2918 var.limit = 0xffff;
2919 var.g = 0;
2920 var.db = 0;
2921 var.present = 1;
2922 var.s = 1;
2923 var.l = 0;
2924 var.unusable = 0;
2925 var.type = 0x3;
2926 var.avl = 0;
2927 if (save->base & 0xf)
2928 printk_once(KERN_WARNING "kvm: segment base is not "
2929 "paragraph aligned when entering "
2930 "protected mode (seg=%d)", seg);
2931 }
6aa8b732 2932
d99e4152
GN		 2933 vmcs_write16(sf->selector, var.selector);
2934 vmcs_write32(sf->base, var.base);
2935 vmcs_write32(sf->limit, var.limit);
2936 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2937}
2938
2939static void enter_rmode(struct kvm_vcpu *vcpu)
2940{
2941 unsigned long flags;
a89a8fb9 2942 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2943
f5f7b2fe
AK		 2944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2948 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2949 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2950 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2951
7ffd92c5 2952 vmx->rmode.vm86_active = 1;
6aa8b732 2953
776e58ea
GN		 2954 /*
2955 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2956 * vcpu. Call it here with phys address pointing 16M below 4G.
2957 */
2958 if (!vcpu->kvm->arch.tss_addr) {
2959 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2960 "called before entering vcpu\n");
2961 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2962 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2963 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2964 }
2965
2fb92db1
AK		 2966 vmx_segment_cache_clear(vmx);
2967
6aa8b732 2968 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2969 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2970 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2971
2972 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2973 vmx->rmode.save_rflags = flags;
6aa8b732 2974
053de044 2975 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2976
2977 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2978 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2979 update_exception_bitmap(vcpu);
2980
d99e4152
GN		 2981 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2982 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2983 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2984 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2985 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2986 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2987
8668a3c4 2988 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2989}
2990
401d10de
AS		 2991static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2992{
2993 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2994 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2995
2996 if (!msr)
2997 return;
401d10de 2998
44ea2b17
AK		 2999 /*
3000 * Force kernel_gs_base reloading before EFER changes, as control
3001 * of this msr depends on is_long_mode().
3002 */
3003 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3004 vcpu->arch.efer = efer;
401d10de
AS		 3005 if (efer & EFER_LMA) {
3006 vmcs_write32(VM_ENTRY_CONTROLS,
3007 vmcs_read32(VM_ENTRY_CONTROLS) |
3008 VM_ENTRY_IA32E_MODE);
3009 msr->data = efer;
3010 } else {
3011 vmcs_write32(VM_ENTRY_CONTROLS,
3012 vmcs_read32(VM_ENTRY_CONTROLS) &
3013 ~VM_ENTRY_IA32E_MODE);
3014
3015 msr->data = efer & ~EFER_LME;
3016 }
3017 setup_msrs(vmx);
3018}
3019
05b3e0c2 3020#ifdef CONFIG_X86_64
6aa8b732
AK		 3021
3022static void enter_lmode(struct kvm_vcpu *vcpu)
3023{
3024 u32 guest_tr_ar;
3025
2fb92db1
AK		 3026 vmx_segment_cache_clear(to_vmx(vcpu));
3027
6aa8b732
AK		 3028 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3029 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3030 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3031 __func__);
6aa8b732
AK		 3032 vmcs_write32(GUEST_TR_AR_BYTES,
3033 (guest_tr_ar & ~AR_TYPE_MASK)
3034 | AR_TYPE_BUSY_64_TSS);
3035 }
da38f438 3036 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3037}
3038
3039static void exit_lmode(struct kvm_vcpu *vcpu)
3040{
6aa8b732
AK		 3041 vmcs_write32(VM_ENTRY_CONTROLS,
3042 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3043 & ~VM_ENTRY_IA32E_MODE);
da38f438 3044 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3045}
3046
3047#endif
3048
2384d2b3
SY		 3049static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3050{
b9d762fa 3051 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3052 if (enable_ept) {
3053 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3054 return;
4e1096d2 3055 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3056 }
2384d2b3
SY		 3057}
3058
e8467fda
AK		 3059static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3060{
3061 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3062
3063 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3064 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3065}
3066
aff48baa
AK		 3067static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3068{
3069 if (enable_ept && is_paging(vcpu))
3070 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3071 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3072}
3073
25c4c276 3074static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3075{
fc78f519
AK		 3076 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3077
3078 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3079 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3080}
3081
1439442c
SY		 3082static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3083{
6de4f3ad
AK		 3084 if (!test_bit(VCPU_EXREG_PDPTR,
3085 (unsigned long *)&vcpu->arch.regs_dirty))
3086 return;
3087
1439442c 3088 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3089 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3090 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3091 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3092 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3093 }
3094}
3095
8f5d549f
AK		 3096static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3097{
3098 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3099 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3100 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3101 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3102 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3103 }
6de4f3ad
AK		 3104
3105 __set_bit(VCPU_EXREG_PDPTR,
3106 (unsigned long *)&vcpu->arch.regs_avail);
3107 __set_bit(VCPU_EXREG_PDPTR,
3108 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3109}
3110
5e1746d6 3111static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3112
3113static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3114 unsigned long cr0,
3115 struct kvm_vcpu *vcpu)
3116{
5233dd51
MT		 3117 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3118 vmx_decache_cr3(vcpu);
1439442c
SY		 3119 if (!(cr0 & X86_CR0_PG)) {
3120 /* From paging/starting to nonpaging */
3121 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3122 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3123 (CPU_BASED_CR3_LOAD_EXITING |
3124 CPU_BASED_CR3_STORE_EXITING));
3125 vcpu->arch.cr0 = cr0;
fc78f519 3126 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3127 } else if (!is_paging(vcpu)) {
3128 /* From nonpaging to paging */
3129 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3130 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3131 ~(CPU_BASED_CR3_LOAD_EXITING |
3132 CPU_BASED_CR3_STORE_EXITING));
3133 vcpu->arch.cr0 = cr0;
fc78f519 3134 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3135 }
95eb84a7
SY		 3136
3137 if (!(cr0 & X86_CR0_WP))
3138 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3139}
3140
6aa8b732
AK		 3141static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3142{
7ffd92c5 3143 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3144 unsigned long hw_cr0;
3145
5037878e 3146 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3147 if (enable_unrestricted_guest)
5037878e 3148 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3149 else {
5037878e 3150 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3151
218e763f
GN		 3152 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3153 enter_pmode(vcpu);
6aa8b732 3154
218e763f
GN		 3155 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3156 enter_rmode(vcpu);
3157 }
6aa8b732 3158
05b3e0c2 3159#ifdef CONFIG_X86_64
f6801dff 3160 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3161 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3162 enter_lmode(vcpu);
707d92fa 3163 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3164 exit_lmode(vcpu);
3165 }
3166#endif
3167
089d034e 3168 if (enable_ept)
1439442c
SY		 3169 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3170
02daab21 3171 if (!vcpu->fpu_active)
81231c69 3172 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3173
6aa8b732 3174 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3175 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3176 vcpu->arch.cr0 = cr0;
14168786
GN		 3177
3178 /* depends on vcpu->arch.cr0 to be set to a new value */
3179 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3180}
3181
1439442c
SY		 3182static u64 construct_eptp(unsigned long root_hpa)
3183{
3184 u64 eptp;
3185
3186 /* TODO write the value reading from MSR */
3187 eptp = VMX_EPT_DEFAULT_MT |
3188 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3189 if (enable_ept_ad_bits)
3190 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3191 eptp |= (root_hpa & PAGE_MASK);
3192
3193 return eptp;
3194}
3195
6aa8b732
AK		 3196static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3197{
1439442c
SY		 3198 unsigned long guest_cr3;
3199 u64 eptp;
3200
3201 guest_cr3 = cr3;
089d034e 3202 if (enable_ept) {
1439442c
SY		 3203 eptp = construct_eptp(cr3);
3204 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3205 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3206 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3207 ept_load_pdptrs(vcpu);
1439442c
SY		 3208 }
3209
2384d2b3 3210 vmx_flush_tlb(vcpu);
1439442c 3211 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3212}
3213
5e1746d6 3214static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3215{
7ffd92c5 3216 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3217 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3218
5e1746d6
NHE		 3219 if (cr4 & X86_CR4_VMXE) {
3220 /*
3221 * To use VMXON (and later other VMX instructions), a guest
3222 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3223 * So basically the check on whether to allow nested VMX
3224 * is here.
3225 */
3226 if (!nested_vmx_allowed(vcpu))
3227 return 1;
1a0d74e6
JK		 3228 }
3229 if (to_vmx(vcpu)->nested.vmxon &&
3230 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3231 return 1;
3232
ad312c7c 3233 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3234 if (enable_ept) {
3235 if (!is_paging(vcpu)) {
3236 hw_cr4 &= ~X86_CR4_PAE;
3237 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3238 /*
3239 * SMEP is disabled if CPU is in non-paging mode in
3240 * hardware. However KVM always uses paging mode to
3241 * emulate guest non-paging mode with TDP.
3242 * To emulate this behavior, SMEP needs to be manually
3243 * disabled when guest switches to non-paging mode.
3244 */
3245 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3246 } else if (!(cr4 & X86_CR4_PAE)) {
3247 hw_cr4 &= ~X86_CR4_PAE;
3248 }
3249 }
1439442c
SY		 3250
3251 vmcs_writel(CR4_READ_SHADOW, cr4);
3252 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3253 return 0;
6aa8b732
AK		 3254}
3255
6aa8b732
AK		 3256static void vmx_get_segment(struct kvm_vcpu *vcpu,
3257 struct kvm_segment *var, int seg)
3258{
a9179499 3259 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3260 u32 ar;
3261
c6ad1153 3262 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3263 *var = vmx->rmode.segs[seg];
a9179499 3264 if (seg == VCPU_SREG_TR
2fb92db1 3265 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3266 return;
1390a28b
AK		 3267 var->base = vmx_read_guest_seg_base(vmx, seg);
3268 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3269 return;
a9179499 3270 }
2fb92db1
AK		 3271 var->base = vmx_read_guest_seg_base(vmx, seg);
3272 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3273 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3274 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3275 var->type = ar & 15;
3276 var->s = (ar >> 4) & 1;
3277 var->dpl = (ar >> 5) & 3;
3278 var->present = (ar >> 7) & 1;
3279 var->avl = (ar >> 12) & 1;
3280 var->l = (ar >> 13) & 1;
3281 var->db = (ar >> 14) & 1;
3282 var->g = (ar >> 15) & 1;
3283 var->unusable = (ar >> 16) & 1;
3284}
3285
a9179499
AK		 3286static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3287{
a9179499
AK		 3288 struct kvm_segment s;
3289
3290 if (to_vmx(vcpu)->rmode.vm86_active) {
3291 vmx_get_segment(vcpu, &s, seg);
3292 return s.base;
3293 }
2fb92db1 3294 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3295}
3296
b09408d0 3297static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3298{
b09408d0
MT		 3299 struct vcpu_vmx *vmx = to_vmx(vcpu);
3300
3eeb3288 3301 if (!is_protmode(vcpu))
2e4d2653
IE		 3302 return 0;
3303
f4c63e5d
AK		 3304 if (!is_long_mode(vcpu)
3305 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3306 return 3;
3307
69c73028
AK		 3308 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3309 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3310 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3311 }
d881e6f6
AK		 3312
3313 return vmx->cpl;
69c73028
AK		 3314}
3315
3316
653e3108 3317static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3318{
6aa8b732
AK		 3319 u32 ar;
3320
f0495f9b 3321 if (var->unusable || !var->present)
6aa8b732
AK		 3322 ar = 1 << 16;
3323 else {
3324 ar = var->type & 15;
3325 ar |= (var->s & 1) << 4;
3326 ar |= (var->dpl & 3) << 5;
3327 ar |= (var->present & 1) << 7;
3328 ar |= (var->avl & 1) << 12;
3329 ar |= (var->l & 1) << 13;
3330 ar |= (var->db & 1) << 14;
3331 ar |= (var->g & 1) << 15;
3332 }
653e3108
AK		 3333
3334 return ar;
3335}
3336
3337static void vmx_set_segment(struct kvm_vcpu *vcpu,
3338 struct kvm_segment *var, int seg)
3339{
7ffd92c5 3340 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3341 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3342
2fb92db1 3343 vmx_segment_cache_clear(vmx);
2f143240
GN		 3344 if (seg == VCPU_SREG_CS)
3345 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3346
1ecd50a9
GN		 3347 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3348 vmx->rmode.segs[seg] = *var;
3349 if (seg == VCPU_SREG_TR)
3350 vmcs_write16(sf->selector, var->selector);
3351 else if (var->s)
3352 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3353 goto out;
653e3108 3354 }
1ecd50a9 3355
653e3108
AK		 3356 vmcs_writel(sf->base, var->base);
3357 vmcs_write32(sf->limit, var->limit);
3358 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3359
3360 /*
3361 * Fix the "Accessed" bit in AR field of segment registers for older
3362 * qemu binaries.
3363 * IA32 arch specifies that at the time of processor reset the
3364 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3365 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3366 * state vmexit when "unrestricted guest" mode is turned on.
3367 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3368 * tree. Newer qemu binaries with that qemu fix would not need this
3369 * kvm hack.
3370 */
3371 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3372 var->type |= 0x1; /* Accessed */
3a624e29 3373
f924d66d 3374 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3375
3376out:
14168786 3377 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3378}
3379
6aa8b732
AK		 3380static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3381{
2fb92db1 3382 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3383
3384 *db = (ar >> 14) & 1;
3385 *l = (ar >> 13) & 1;
3386}
3387
89a27f4d 3388static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3389{
89a27f4d
GN		 3390 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3391 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3392}
3393
89a27f4d 3394static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3395{
89a27f4d
GN		 3396 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3397 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3398}
3399
89a27f4d 3400static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3401{
89a27f4d
GN		 3402 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3403 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3404}
3405
89a27f4d 3406static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3407{
89a27f4d
GN		 3408 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3409 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3410}
3411
648dfaa7
MG		 3412static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3413{
3414 struct kvm_segment var;
3415 u32 ar;
3416
3417 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3418 var.dpl = 0x3;
0647f4aa
GN		 3419 if (seg == VCPU_SREG_CS)
3420 var.type = 0x3;
648dfaa7
MG		 3421 ar = vmx_segment_access_rights(&var);
3422
3423 if (var.base != (var.selector << 4))
3424 return false;
89efbed0 3425 if (var.limit != 0xffff)
648dfaa7 3426 return false;
07f42f5f 3427 if (ar != 0xf3)
648dfaa7
MG		 3428 return false;
3429
3430 return true;
3431}
3432
3433static bool code_segment_valid(struct kvm_vcpu *vcpu)
3434{
3435 struct kvm_segment cs;
3436 unsigned int cs_rpl;
3437
3438 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3439 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3440
1872a3f4
AK		 3441 if (cs.unusable)
3442 return false;
648dfaa7
MG		 3443 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3444 return false;
3445 if (!cs.s)
3446 return false;
1872a3f4 3447 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3448 if (cs.dpl > cs_rpl)
3449 return false;
1872a3f4 3450 } else {
648dfaa7
MG		 3451 if (cs.dpl != cs_rpl)
3452 return false;
3453 }
3454 if (!cs.present)
3455 return false;
3456
3457 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3458 return true;
3459}
3460
3461static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3462{
3463 struct kvm_segment ss;
3464 unsigned int ss_rpl;
3465
3466 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3467 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3468
1872a3f4
AK		 3469 if (ss.unusable)
3470 return true;
3471 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3472 return false;
3473 if (!ss.s)
3474 return false;
3475 if (ss.dpl != ss_rpl) /* DPL != RPL */
3476 return false;
3477 if (!ss.present)
3478 return false;
3479
3480 return true;
3481}
3482
3483static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3484{
3485 struct kvm_segment var;
3486 unsigned int rpl;
3487
3488 vmx_get_segment(vcpu, &var, seg);
3489 rpl = var.selector & SELECTOR_RPL_MASK;
3490
1872a3f4
AK		 3491 if (var.unusable)
3492 return true;
648dfaa7
MG		 3493 if (!var.s)
3494 return false;
3495 if (!var.present)
3496 return false;
3497 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3498 if (var.dpl < rpl) /* DPL < RPL */
3499 return false;
3500 }
3501
3502 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3503 * rights flags
3504 */
3505 return true;
3506}
3507
3508static bool tr_valid(struct kvm_vcpu *vcpu)
3509{
3510 struct kvm_segment tr;
3511
3512 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3513
1872a3f4
AK		 3514 if (tr.unusable)
3515 return false;
648dfaa7
MG		 3516 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3517 return false;
1872a3f4 3518 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3519 return false;
3520 if (!tr.present)
3521 return false;
3522
3523 return true;
3524}
3525
3526static bool ldtr_valid(struct kvm_vcpu *vcpu)
3527{
3528 struct kvm_segment ldtr;
3529
3530 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3531
1872a3f4
AK		 3532 if (ldtr.unusable)
3533 return true;
648dfaa7
MG		 3534 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3535 return false;
3536 if (ldtr.type != 2)
3537 return false;
3538 if (!ldtr.present)
3539 return false;
3540
3541 return true;
3542}
3543
3544static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3545{
3546 struct kvm_segment cs, ss;
3547
3548 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3549 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3550
3551 return ((cs.selector & SELECTOR_RPL_MASK) ==
3552 (ss.selector & SELECTOR_RPL_MASK));
3553}
3554
3555/*
3556 * Check if guest state is valid. Returns true if valid, false if
3557 * not.
3558 * We assume that registers are always usable
3559 */
3560static bool guest_state_valid(struct kvm_vcpu *vcpu)
3561{
c5e97c80
GN		 3562 if (enable_unrestricted_guest)
3563 return true;
3564
648dfaa7 3565 /* real mode guest state checks */
3eeb3288 3566 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3567 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3568 return false;
3569 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3570 return false;
3571 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3572 return false;
3573 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3574 return false;
3575 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3576 return false;
3577 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3578 return false;
3579 } else {
3580 /* protected mode guest state checks */
3581 if (!cs_ss_rpl_check(vcpu))
3582 return false;
3583 if (!code_segment_valid(vcpu))
3584 return false;
3585 if (!stack_segment_valid(vcpu))
3586 return false;
3587 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3588 return false;
3589 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3590 return false;
3591 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3592 return false;
3593 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3594 return false;
3595 if (!tr_valid(vcpu))
3596 return false;
3597 if (!ldtr_valid(vcpu))
3598 return false;
3599 }
3600 /* TODO:
3601 * - Add checks on RIP
3602 * - Add checks on RFLAGS
3603 */
3604
3605 return true;
3606}
3607
d77c26fc 3608static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3609{
40dcaa9f 3610 gfn_t fn;
195aefde 3611 u16 data = 0;
40dcaa9f 3612 int r, idx, ret = 0;
6aa8b732 3613
40dcaa9f
XG		 3614 idx = srcu_read_lock(&kvm->srcu);
3615 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3616 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3617 if (r < 0)
10589a46 3618 goto out;
195aefde 3619 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3620 r = kvm_write_guest_page(kvm, fn++, &data,
3621 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3622 if (r < 0)
10589a46 3623 goto out;
195aefde
IE		 3624 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3625 if (r < 0)
10589a46 3626 goto out;
195aefde
IE		 3627 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3628 if (r < 0)
10589a46 3629 goto out;
195aefde 3630 data = ~0;
10589a46
MT		 3631 r = kvm_write_guest_page(kvm, fn, &data,
3632 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3633 sizeof(u8));
195aefde 3634 if (r < 0)
10589a46
MT		 3635 goto out;
3636
3637 ret = 1;
3638out:
40dcaa9f 3639 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3640 return ret;
6aa8b732
AK		 3641}
3642
b7ebfb05
SY		 3643static int init_rmode_identity_map(struct kvm *kvm)
3644{
40dcaa9f 3645 int i, idx, r, ret;
b7ebfb05
SY		 3646 pfn_t identity_map_pfn;
3647 u32 tmp;
3648
089d034e 3649 if (!enable_ept)
b7ebfb05
SY		 3650 return 1;
3651 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3652 printk(KERN_ERR "EPT: identity-mapping pagetable "
3653 "haven't been allocated!\n");
3654 return 0;
3655 }
3656 if (likely(kvm->arch.ept_identity_pagetable_done))
3657 return 1;
3658 ret = 0;
b927a3ce 3659 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3660 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3661 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3662 if (r < 0)
3663 goto out;
3664 /* Set up identity-mapping pagetable for EPT in real mode */
3665 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3666 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3667 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3668 r = kvm_write_guest_page(kvm, identity_map_pfn,
3669 &tmp, i * sizeof(tmp), sizeof(tmp));
3670 if (r < 0)
3671 goto out;
3672 }
3673 kvm->arch.ept_identity_pagetable_done = true;
3674 ret = 1;
3675out:
40dcaa9f 3676 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3677 return ret;
3678}
3679
6aa8b732
AK		 3680static void seg_setup(int seg)
3681{
772e0318 3682 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3683 unsigned int ar;
6aa8b732
AK		 3684
3685 vmcs_write16(sf->selector, 0);
3686 vmcs_writel(sf->base, 0);
3687 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3688 ar = 0x93;
3689 if (seg == VCPU_SREG_CS)
3690 ar |= 0x08; /* code segment */
3a624e29
NK		 3691
3692 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3693}
3694
f78e0e2e
SY		 3695static int alloc_apic_access_page(struct kvm *kvm)
3696{
4484141a 3697 struct page *page;
f78e0e2e
SY		 3698 struct kvm_userspace_memory_region kvm_userspace_mem;
3699 int r = 0;
3700
79fac95e 3701 mutex_lock(&kvm->slots_lock);
bfc6d222 3702 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3703 goto out;
3704 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3705 kvm_userspace_mem.flags = 0;
3706 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3707 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3708 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3709 if (r)
3710 goto out;
72dc67a6 3711
4484141a
XG		 3712 page = gfn_to_page(kvm, 0xfee00);
3713 if (is_error_page(page)) {
3714 r = -EFAULT;
3715 goto out;
3716 }
3717
3718 kvm->arch.apic_access_page = page;
f78e0e2e 3719out:
79fac95e 3720 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3721 return r;
3722}
3723
b7ebfb05
SY		 3724static int alloc_identity_pagetable(struct kvm *kvm)
3725{
4484141a 3726 struct page *page;
b7ebfb05
SY		 3727 struct kvm_userspace_memory_region kvm_userspace_mem;
3728 int r = 0;
3729
79fac95e 3730 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3731 if (kvm->arch.ept_identity_pagetable)
3732 goto out;
3733 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3734 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3735 kvm_userspace_mem.guest_phys_addr =
3736 kvm->arch.ept_identity_map_addr;
b7ebfb05 3737 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3738 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3739 if (r)
3740 goto out;
3741
4484141a
XG		 3742 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3743 if (is_error_page(page)) {
3744 r = -EFAULT;
3745 goto out;
3746 }
3747
3748 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3749out:
79fac95e 3750 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3751 return r;
3752}
3753
2384d2b3
SY		 3754static void allocate_vpid(struct vcpu_vmx *vmx)
3755{
3756 int vpid;
3757
3758 vmx->vpid = 0;
919818ab 3759 if (!enable_vpid)
2384d2b3
SY		 3760 return;
3761 spin_lock(&vmx_vpid_lock);
3762 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3763 if (vpid < VMX_NR_VPIDS) {
3764 vmx->vpid = vpid;
3765 __set_bit(vpid, vmx_vpid_bitmap);
3766 }
3767 spin_unlock(&vmx_vpid_lock);
3768}
3769
cdbecfc3
LJ		 3770static void free_vpid(struct vcpu_vmx *vmx)
3771{
3772 if (!enable_vpid)
3773 return;
3774 spin_lock(&vmx_vpid_lock);
3775 if (vmx->vpid != 0)
3776 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3777 spin_unlock(&vmx_vpid_lock);
3778}
3779
8d14695f
YZ		 3780#define MSR_TYPE_R 1
3781#define MSR_TYPE_W 2
3782static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3783 u32 msr, int type)
25c5f225 3784{
3e7c73e9 3785 int f = sizeof(unsigned long);
25c5f225
SY		 3786
3787 if (!cpu_has_vmx_msr_bitmap())
3788 return;
3789
3790 /*
3791 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3792 * have the write-low and read-high bitmap offsets the wrong way round.
3793 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3794 */
25c5f225 3795 if (msr <= 0x1fff) {
8d14695f
YZ		 3796 if (type & MSR_TYPE_R)
3797 /* read-low */
3798 __clear_bit(msr, msr_bitmap + 0x000 / f);
3799
3800 if (type & MSR_TYPE_W)
3801 /* write-low */
3802 __clear_bit(msr, msr_bitmap + 0x800 / f);
3803
25c5f225
SY		 3804 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3805 msr &= 0x1fff;
8d14695f
YZ		 3806 if (type & MSR_TYPE_R)
3807 /* read-high */
3808 __clear_bit(msr, msr_bitmap + 0x400 / f);
3809
3810 if (type & MSR_TYPE_W)
3811 /* write-high */
3812 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3813
3814 }
3815}
3816
3817static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3818 u32 msr, int type)
3819{
3820 int f = sizeof(unsigned long);
3821
3822 if (!cpu_has_vmx_msr_bitmap())
3823 return;
3824
3825 /*
3826 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3827 * have the write-low and read-high bitmap offsets the wrong way round.
3828 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3829 */
3830 if (msr <= 0x1fff) {
3831 if (type & MSR_TYPE_R)
3832 /* read-low */
3833 __set_bit(msr, msr_bitmap + 0x000 / f);
3834
3835 if (type & MSR_TYPE_W)
3836 /* write-low */
3837 __set_bit(msr, msr_bitmap + 0x800 / f);
3838
3839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3840 msr &= 0x1fff;
3841 if (type & MSR_TYPE_R)
3842 /* read-high */
3843 __set_bit(msr, msr_bitmap + 0x400 / f);
3844
3845 if (type & MSR_TYPE_W)
3846 /* write-high */
3847 __set_bit(msr, msr_bitmap + 0xc00 / f);
3848
25c5f225 3849 }
25c5f225
SY		 3850}
3851
5897297b
AK		 3852static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3853{
3854 if (!longmode_only)
8d14695f
YZ		 3855 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3856 msr, MSR_TYPE_R | MSR_TYPE_W);
3857 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3858 msr, MSR_TYPE_R | MSR_TYPE_W);
3859}
3860
3861static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3862{
3863 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3864 msr, MSR_TYPE_R);
3865 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3866 msr, MSR_TYPE_R);
3867}
3868
3869static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3870{
3871 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3872 msr, MSR_TYPE_R);
3873 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3874 msr, MSR_TYPE_R);
3875}
3876
3877static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3878{
3879 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3880 msr, MSR_TYPE_W);
3881 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3882 msr, MSR_TYPE_W);
5897297b
AK		 3883}
3884
a3a8ff8e
NHE		 3885/*
3886 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3887 * will not change in the lifetime of the guest.
3888 * Note that host-state that does change is set elsewhere. E.g., host-state
3889 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3890 */
3891static void vmx_set_constant_host_state(void)
3892{
3893 u32 low32, high32;
3894 unsigned long tmpl;
3895 struct desc_ptr dt;
3896
b1a74bf8 3897 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3898 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3899 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3900
3901 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3902#ifdef CONFIG_X86_64
3903 /*
3904 * Load null selectors, so we can avoid reloading them in
3905 * __vmx_load_host_state(), in case userspace uses the null selectors
3906 * too (the expected case).
3907 */
3908 vmcs_write16(HOST_DS_SELECTOR, 0);
3909 vmcs_write16(HOST_ES_SELECTOR, 0);
3910#else
a3a8ff8e
NHE		 3911 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3912 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3913#endif
a3a8ff8e
NHE		 3914 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3915 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3916
3917 native_store_idt(&dt);
3918 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3919
83287ea4 3920 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3921
3922 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3923 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3924 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3925 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3926
3927 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3928 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3929 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3930 }
3931}
3932
bf8179a0
NHE		 3933static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3934{
3935 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3936 if (enable_ept)
3937 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3938 if (is_guest_mode(&vmx->vcpu))
3939 vmx->vcpu.arch.cr4_guest_owned_bits &=
3940 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3941 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3942}
3943
3944static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3945{
3946 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3947 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3948 exec_control &= ~CPU_BASED_TPR_SHADOW;
3949#ifdef CONFIG_X86_64
3950 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3951 CPU_BASED_CR8_LOAD_EXITING;
3952#endif
3953 }
3954 if (!enable_ept)
3955 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3956 CPU_BASED_CR3_LOAD_EXITING |
3957 CPU_BASED_INVLPG_EXITING;
3958 return exec_control;
3959}
3960
c7c9c56c
YZ		 3961static int vmx_vm_has_apicv(struct kvm *kvm)
3962{
3963 return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3964}
3965
bf8179a0
NHE		 3966static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3967{
3968 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3969 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3970 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3971 if (vmx->vpid == 0)
3972 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3973 if (!enable_ept) {
3974 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3975 enable_unrestricted_guest = 0;
ad756a16
MJ		 3976 /* Enable INVPCID for non-ept guests may cause performance regression. */
3977 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3978 }
3979 if (!enable_unrestricted_guest)
3980 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3981 if (!ple_gap)
3982 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 3983 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3984 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3985 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3986 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
bf8179a0
NHE		 3987 return exec_control;
3988}
3989
ce88decf
XG		 3990static void ept_set_mmio_spte_mask(void)
3991{
3992 /*
3993 * EPT Misconfigurations can be generated if the value of bits 2:0
3994 * of an EPT paging-structure entry is 110b (write/execute).
3995 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3996 * spte.
3997 */
3998 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3999}
4000
6aa8b732
AK		 4001/*
4002 * Sets up the vmcs for emulated real mode.
4003 */
8b9cf98c 4004static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4005{
2e4ce7f5 4006#ifdef CONFIG_X86_64
6aa8b732 4007 unsigned long a;
2e4ce7f5 4008#endif
6aa8b732 4009 int i;
6aa8b732 4010
6aa8b732 4011 /* I/O */
3e7c73e9
AK		 4012 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4013 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4014
25c5f225 4015 if (cpu_has_vmx_msr_bitmap())
5897297b 4016 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4017
6aa8b732
AK		 4018 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4019
6aa8b732 4020 /* Control */
1c3d14fe
YS		 4021 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4022 vmcs_config.pin_based_exec_ctrl);
6e5d865c 4023
bf8179a0 4024 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4025
83ff3b9d 4026 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4027 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4028 vmx_secondary_exec_control(vmx));
83ff3b9d 4029 }
f78e0e2e 4030
c7c9c56c
YZ		 4031 if (enable_apicv_reg_vid) {
4032 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4033 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4034 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4035 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4036
4037 vmcs_write16(GUEST_INTR_STATUS, 0);
4038 }
4039
4b8d54f9
ZE		 4040 if (ple_gap) {
4041 vmcs_write32(PLE_GAP, ple_gap);
4042 vmcs_write32(PLE_WINDOW, ple_window);
4043 }
4044
c3707958
XG		 4045 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4046 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4047 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4048
9581d442
AK		 4049 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4050 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 4051 vmx_set_constant_host_state();
05b3e0c2 4052#ifdef CONFIG_X86_64
6aa8b732
AK		 4053 rdmsrl(MSR_FS_BASE, a);
4054 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4055 rdmsrl(MSR_GS_BASE, a);
4056 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4057#else
4058 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4059 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4060#endif
4061
2cc51560
ED		 4062 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4063 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4064 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4065 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4066 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4067
468d472f 4068 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4069 u32 msr_low, msr_high;
4070 u64 host_pat;
468d472f
SY		 4071 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4072 host_pat = msr_low | ((u64) msr_high << 32);
4073 /* Write the default value follow host pat */
4074 vmcs_write64(GUEST_IA32_PAT, host_pat);
4075 /* Keep arch.pat sync with GUEST_IA32_PAT */
4076 vmx->vcpu.arch.pat = host_pat;
4077 }
4078
6aa8b732
AK		 4079 for (i = 0; i < NR_VMX_MSR; ++i) {
4080 u32 index = vmx_msr_index[i];
4081 u32 data_low, data_high;
a2fa3e9f 4082 int j = vmx->nmsrs;
6aa8b732
AK		 4083
4084 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4085 continue;
432bd6cb
AK		 4086 if (wrmsr_safe(index, data_low, data_high) < 0)
4087 continue;
26bb0981
AK		 4088 vmx->guest_msrs[j].index = i;
4089 vmx->guest_msrs[j].data = 0;
d5696725 4090 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4091 ++vmx->nmsrs;
6aa8b732 4092 }
6aa8b732 4093
1c3d14fe 4094 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4095
4096 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4097 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4098
e00c8cf2 4099 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4100 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4101
4102 return 0;
4103}
4104
57f252f2 4105static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4106{
4107 struct vcpu_vmx *vmx = to_vmx(vcpu);
4108 u64 msr;
e00c8cf2 4109
7ffd92c5 4110 vmx->rmode.vm86_active = 0;
e00c8cf2 4111
3b86cd99
JK		 4112 vmx->soft_vnmi_blocked = 0;
4113
ad312c7c 4114 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4115 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4116 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4117 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4118 msr |= MSR_IA32_APICBASE_BSP;
4119 kvm_set_apic_base(&vmx->vcpu, msr);
4120
2fb92db1
AK		 4121 vmx_segment_cache_clear(vmx);
4122
5706be0d 4123 seg_setup(VCPU_SREG_CS);
66450a21 4124 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
e00c8cf2
AK		 4125
4126 seg_setup(VCPU_SREG_DS);
4127 seg_setup(VCPU_SREG_ES);
4128 seg_setup(VCPU_SREG_FS);
4129 seg_setup(VCPU_SREG_GS);
4130 seg_setup(VCPU_SREG_SS);
4131
4132 vmcs_write16(GUEST_TR_SELECTOR, 0);
4133 vmcs_writel(GUEST_TR_BASE, 0);
4134 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4135 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4136
4137 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4138 vmcs_writel(GUEST_LDTR_BASE, 0);
4139 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4140 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4141
4142 vmcs_write32(GUEST_SYSENTER_CS, 0);
4143 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4144 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4145
4146 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4147 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4148
e00c8cf2
AK		 4149 vmcs_writel(GUEST_GDTR_BASE, 0);
4150 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4151
4152 vmcs_writel(GUEST_IDTR_BASE, 0);
4153 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4154
443381a8 4155 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4156 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4157 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4158
e00c8cf2
AK		 4159 /* Special registers */
4160 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4161
4162 setup_msrs(vmx);
4163
6aa8b732
AK		 4164 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4165
f78e0e2e
SY		 4166 if (cpu_has_vmx_tpr_shadow()) {
4167 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4168 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4169 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4170 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4171 vmcs_write32(TPR_THRESHOLD, 0);
4172 }
4173
4174 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4175 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4176 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4177
2384d2b3
SY		 4178 if (vmx->vpid != 0)
4179 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4180
fa40052c 4181 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4182 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4183 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4184 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4185 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4186 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4187 vmx_fpu_activate(&vmx->vcpu);
4188 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4189
b9d762fa 4190 vpid_sync_context(vmx);
6aa8b732
AK		 4191}
4192
b6f1250e
NHE		 4193/*
4194 * In nested virtualization, check if L1 asked to exit on external interrupts.
4195 * For most existing hypervisors, this will always return true.
4196 */
4197static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4198{
4199 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4200 PIN_BASED_EXT_INTR_MASK;
4201}
4202
3b86cd99
JK		 4203static void enable_irq_window(struct kvm_vcpu *vcpu)
4204{
4205 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4206 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4207 /*
4208 * We get here if vmx_interrupt_allowed() said we can't
4209 * inject to L1 now because L2 must run. Ask L2 to exit
4210 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4211 */
d6185f20 4212 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4213 return;
d6185f20 4214 }
3b86cd99
JK		 4215
4216 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4217 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4218 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4219}
4220
4221static void enable_nmi_window(struct kvm_vcpu *vcpu)
4222{
4223 u32 cpu_based_vm_exec_control;
4224
4225 if (!cpu_has_virtual_nmis()) {
4226 enable_irq_window(vcpu);
4227 return;
4228 }
4229
30bd0c4c
AK		 4230 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4231 enable_irq_window(vcpu);
4232 return;
4233 }
3b86cd99
JK		 4234 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4235 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4236 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4237}
4238
66fd3f7f 4239static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4240{
9c8cba37 4241 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4242 uint32_t intr;
4243 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4244
229456fc 4245 trace_kvm_inj_virq(irq);
2714d1d3 4246
fa89a817 4247 ++vcpu->stat.irq_injections;
7ffd92c5 4248 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4249 int inc_eip = 0;
4250 if (vcpu->arch.interrupt.soft)
4251 inc_eip = vcpu->arch.event_exit_inst_len;
4252 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4253 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4254 return;
4255 }
66fd3f7f
GN		 4256 intr = irq | INTR_INFO_VALID_MASK;
4257 if (vcpu->arch.interrupt.soft) {
4258 intr |= INTR_TYPE_SOFT_INTR;
4259 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4260 vmx->vcpu.arch.event_exit_inst_len);
4261 } else
4262 intr |= INTR_TYPE_EXT_INTR;
4263 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4264}
4265
f08864b4
SY		 4266static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4267{
66a5a347
JK		 4268 struct vcpu_vmx *vmx = to_vmx(vcpu);
4269
0b6ac343
NHE		 4270 if (is_guest_mode(vcpu))
4271 return;
4272
3b86cd99
JK		 4273 if (!cpu_has_virtual_nmis()) {
4274 /*
4275 * Tracking the NMI-blocked state in software is built upon
4276 * finding the next open IRQ window. This, in turn, depends on
4277 * well-behaving guests: They have to keep IRQs disabled at
4278 * least as long as the NMI handler runs. Otherwise we may
4279 * cause NMI nesting, maybe breaking the guest. But as this is
4280 * highly unlikely, we can live with the residual risk.
4281 */
4282 vmx->soft_vnmi_blocked = 1;
4283 vmx->vnmi_blocked_time = 0;
4284 }
4285
487b391d 4286 ++vcpu->stat.nmi_injections;
9d58b931 4287 vmx->nmi_known_unmasked = false;
7ffd92c5 4288 if (vmx->rmode.vm86_active) {
71f9833b 4289 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4290 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4291 return;
4292 }
f08864b4
SY		 4293 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4294 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4295}
4296
c4282df9 4297static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4298{
3b86cd99 4299 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4300 return 0;
33f089ca 4301
c4282df9 4302 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4303 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4304 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4305}
4306
3cfc3092
JK		 4307static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4308{
4309 if (!cpu_has_virtual_nmis())
4310 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4311 if (to_vmx(vcpu)->nmi_known_unmasked)
4312 return false;
c332c83a 4313 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4314}
4315
4316static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4317{
4318 struct vcpu_vmx *vmx = to_vmx(vcpu);
4319
4320 if (!cpu_has_virtual_nmis()) {
4321 if (vmx->soft_vnmi_blocked != masked) {
4322 vmx->soft_vnmi_blocked = masked;
4323 vmx->vnmi_blocked_time = 0;
4324 }
4325 } else {
9d58b931 4326 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4327 if (masked)
4328 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4329 GUEST_INTR_STATE_NMI);
4330 else
4331 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4332 GUEST_INTR_STATE_NMI);
4333 }
4334}
4335
78646121
GN		 4336static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4337{
b6f1250e 4338 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4339 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4340 if (to_vmx(vcpu)->nested.nested_run_pending ||
4341 (vmcs12->idt_vectoring_info_field &
4342 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4343 return 0;
4344 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4345 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4346 vmcs12->vm_exit_intr_info = 0;
4347 /* fall through to normal code, but now in L1, not L2 */
4348 }
4349
c4282df9
GN		 4350 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4351 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4352 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4353}
4354
cbc94022
IE		 4355static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4356{
4357 int ret;
4358 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4359 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4360 .guest_phys_addr = addr,
4361 .memory_size = PAGE_SIZE * 3,
4362 .flags = 0,
4363 };
4364
47ae31e2 4365 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4366 if (ret)
4367 return ret;
bfc6d222 4368 kvm->arch.tss_addr = addr;
93ea5388
GN		 4369 if (!init_rmode_tss(kvm))
4370 return -ENOMEM;
4371
cbc94022
IE		 4372 return 0;
4373}
4374
0ca1b4f4 4375static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4376{
77ab6db0 4377 switch (vec) {
77ab6db0 4378 case BP_VECTOR:
c573cd22
JK		 4379 /*
4380 * Update instruction length as we may reinject the exception
4381 * from user space while in guest debugging mode.
4382 */
4383 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4384 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4385 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4386 return false;
4387 /* fall through */
4388 case DB_VECTOR:
4389 if (vcpu->guest_debug &
4390 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4391 return false;
d0bfb940
JK		 4392 /* fall through */
4393 case DE_VECTOR:
77ab6db0
JK		 4394 case OF_VECTOR:
4395 case BR_VECTOR:
4396 case UD_VECTOR:
4397 case DF_VECTOR:
4398 case SS_VECTOR:
4399 case GP_VECTOR:
4400 case MF_VECTOR:
0ca1b4f4
GN		 4401 return true;
4402 break;
77ab6db0 4403 }
0ca1b4f4
GN		 4404 return false;
4405}
4406
4407static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4408 int vec, u32 err_code)
4409{
4410 /*
4411 * Instruction with address size override prefix opcode 0x67
4412 * Cause the #SS fault with 0 error code in VM86 mode.
4413 */
4414 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4415 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4416 if (vcpu->arch.halt_request) {
4417 vcpu->arch.halt_request = 0;
4418 return kvm_emulate_halt(vcpu);
4419 }
4420 return 1;
4421 }
4422 return 0;
4423 }
4424
4425 /*
4426 * Forward all other exceptions that are valid in real mode.
4427 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4428 * the required debugging infrastructure rework.
4429 */
4430 kvm_queue_exception(vcpu, vec);
4431 return 1;
6aa8b732
AK		 4432}
4433
a0861c02
AK		 4434/*
4435 * Trigger machine check on the host. We assume all the MSRs are already set up
4436 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4437 * We pass a fake environment to the machine check handler because we want
4438 * the guest to be always treated like user space, no matter what context
4439 * it used internally.
4440 */
4441static void kvm_machine_check(void)
4442{
4443#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4444 struct pt_regs regs = {
4445 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4446 .flags = X86_EFLAGS_IF,
4447 };
4448
4449 do_machine_check(&regs, 0);
4450#endif
4451}
4452
851ba692 4453static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4454{
4455 /* already handled by vcpu_run */
4456 return 1;
4457}
4458
851ba692 4459static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4460{
1155f76a 4461 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4462 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4463 u32 intr_info, ex_no, error_code;
42dbaa5a 4464 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4465 u32 vect_info;
4466 enum emulation_result er;
4467
1155f76a 4468 vect_info = vmx->idt_vectoring_info;
88786475 4469 intr_info = vmx->exit_intr_info;
6aa8b732 4470
a0861c02 4471 if (is_machine_check(intr_info))
851ba692 4472 return handle_machine_check(vcpu);
a0861c02 4473
e4a41889 4474 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4475 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4476
4477 if (is_no_device(intr_info)) {
5fd86fcf 4478 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4479 return 1;
4480 }
4481
7aa81cc0 4482 if (is_invalid_opcode(intr_info)) {
51d8b661 4483 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4484 if (er != EMULATE_DONE)
7ee5d940 4485 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4486 return 1;
4487 }
4488
6aa8b732 4489 error_code = 0;
2e11384c 4490 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4491 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4492
4493 /*
4494 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4495 * MMIO, it is better to report an internal error.
4496 * See the comments in vmx_handle_exit.
4497 */
4498 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4499 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4500 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4501 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4502 vcpu->run->internal.ndata = 2;
4503 vcpu->run->internal.data[0] = vect_info;
4504 vcpu->run->internal.data[1] = intr_info;
4505 return 0;
4506 }
4507
6aa8b732 4508 if (is_page_fault(intr_info)) {
1439442c 4509 /* EPT won't cause page fault directly */
cf3ace79 4510 BUG_ON(enable_ept);
6aa8b732 4511 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4512 trace_kvm_page_fault(cr2, error_code);
4513
3298b75c 4514 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4515 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4516 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4517 }
4518
d0bfb940 4519 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4520
4521 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4522 return handle_rmode_exception(vcpu, ex_no, error_code);
4523
42dbaa5a
JK		 4524 switch (ex_no) {
4525 case DB_VECTOR:
4526 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4527 if (!(vcpu->guest_debug &
4528 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4529 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4530 kvm_queue_exception(vcpu, DB_VECTOR);
4531 return 1;
4532 }
4533 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4534 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4535 /* fall through */
4536 case BP_VECTOR:
c573cd22
JK		 4537 /*
4538 * Update instruction length as we may reinject #BP from
4539 * user space while in guest debugging mode. Reading it for
4540 * #DB as well causes no harm, it is not used in that case.
4541 */
4542 vmx->vcpu.arch.event_exit_inst_len =
4543 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4544 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4545 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4546 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4547 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4548 break;
4549 default:
d0bfb940
JK		 4550 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4551 kvm_run->ex.exception = ex_no;
4552 kvm_run->ex.error_code = error_code;
42dbaa5a 4553 break;
6aa8b732 4554 }
6aa8b732
AK		 4555 return 0;
4556}
4557
851ba692 4558static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4559{
1165f5fe 4560 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4561 return 1;
4562}
4563
851ba692 4564static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4565{
851ba692 4566 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4567 return 0;
4568}
6aa8b732 4569
851ba692 4570static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4571{
bfdaab09 4572 unsigned long exit_qualification;
34c33d16 4573 int size, in, string;
039576c0 4574 unsigned port;
6aa8b732 4575
bfdaab09 4576 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4577 string = (exit_qualification & 16) != 0;
cf8f70bf 4578 in = (exit_qualification & 8) != 0;
e70669ab 4579
cf8f70bf 4580 ++vcpu->stat.io_exits;
e70669ab 4581
cf8f70bf 4582 if (string || in)
51d8b661 4583 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4584
cf8f70bf
GN		 4585 port = exit_qualification >> 16;
4586 size = (exit_qualification & 7) + 1;
e93f36bc 4587 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4588
4589 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4590}
4591
102d8325
IM		 4592static void
4593vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4594{
4595 /*
4596 * Patch in the VMCALL instruction:
4597 */
4598 hypercall[0] = 0x0f;
4599 hypercall[1] = 0x01;
4600 hypercall[2] = 0xc1;
102d8325
IM		 4601}
4602
0fa06071 4603/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4604static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4605{
eeadf9e7 4606 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4607 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4608 unsigned long orig_val = val;
4609
eeadf9e7
NHE		 4610 /*
4611 * We get here when L2 changed cr0 in a way that did not change
4612 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4613 * but did change L0 shadowed bits. So we first calculate the
4614 * effective cr0 value that L1 would like to write into the
4615 * hardware. It consists of the L2-owned bits from the new
4616 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4617 */
1a0d74e6
JK		 4618 val = (val & ~vmcs12->cr0_guest_host_mask) |
4619 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4620
4621 /* TODO: will have to take unrestricted guest mode into
4622 * account */
4623 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4624 return 1;
1a0d74e6
JK		 4625
4626 if (kvm_set_cr0(vcpu, val))
4627 return 1;
4628 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4629 return 0;
1a0d74e6
JK		 4630 } else {
4631 if (to_vmx(vcpu)->nested.vmxon &&
4632 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4633 return 1;
eeadf9e7 4634 return kvm_set_cr0(vcpu, val);
1a0d74e6 4635 }
eeadf9e7
NHE		 4636}
4637
4638static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4639{
4640 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4641 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4642 unsigned long orig_val = val;
4643
4644 /* analogously to handle_set_cr0 */
4645 val = (val & ~vmcs12->cr4_guest_host_mask) |
4646 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4647 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4648 return 1;
1a0d74e6 4649 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4650 return 0;
4651 } else
4652 return kvm_set_cr4(vcpu, val);
4653}
4654
4655/* called to set cr0 as approriate for clts instruction exit. */
4656static void handle_clts(struct kvm_vcpu *vcpu)
4657{
4658 if (is_guest_mode(vcpu)) {
4659 /*
4660 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4661 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4662 * just pretend it's off (also in arch.cr0 for fpu_activate).
4663 */
4664 vmcs_writel(CR0_READ_SHADOW,
4665 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4666 vcpu->arch.cr0 &= ~X86_CR0_TS;
4667 } else
4668 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4669}
4670
851ba692 4671static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4672{
229456fc 4673 unsigned long exit_qualification, val;
6aa8b732
AK		 4674 int cr;
4675 int reg;
49a9b07e 4676 int err;
6aa8b732 4677
bfdaab09 4678 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4679 cr = exit_qualification & 15;
4680 reg = (exit_qualification >> 8) & 15;
4681 switch ((exit_qualification >> 4) & 3) {
4682 case 0: /* mov to cr */
229456fc
MT		 4683 val = kvm_register_read(vcpu, reg);
4684 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4685 switch (cr) {
4686 case 0:
eeadf9e7 4687 err = handle_set_cr0(vcpu, val);
db8fcefa 4688 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4689 return 1;
4690 case 3:
2390218b 4691 err = kvm_set_cr3(vcpu, val);
db8fcefa 4692 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4693 return 1;
4694 case 4:
eeadf9e7 4695 err = handle_set_cr4(vcpu, val);
db8fcefa 4696 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4697 return 1;
0a5fff19
GN		 4698 case 8: {
4699 u8 cr8_prev = kvm_get_cr8(vcpu);
4700 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4701 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4702 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4703 if (irqchip_in_kernel(vcpu->kvm))
4704 return 1;
4705 if (cr8_prev <= cr8)
4706 return 1;
851ba692 4707 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4708 return 0;
4709 }
4b8073e4 4710 }
6aa8b732 4711 break;
25c4c276 4712 case 2: /* clts */
eeadf9e7 4713 handle_clts(vcpu);
4d4ec087 4714 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4715 skip_emulated_instruction(vcpu);
6b52d186 4716 vmx_fpu_activate(vcpu);
25c4c276 4717 return 1;
6aa8b732
AK		 4718 case 1: /*mov from cr*/
4719 switch (cr) {
4720 case 3:
9f8fe504
AK		 4721 val = kvm_read_cr3(vcpu);
4722 kvm_register_write(vcpu, reg, val);
4723 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4724 skip_emulated_instruction(vcpu);
4725 return 1;
4726 case 8:
229456fc
MT		 4727 val = kvm_get_cr8(vcpu);
4728 kvm_register_write(vcpu, reg, val);
4729 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4730 skip_emulated_instruction(vcpu);
4731 return 1;
4732 }
4733 break;
4734 case 3: /* lmsw */
a1f83a74 4735 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4736 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4737 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4738
4739 skip_emulated_instruction(vcpu);
4740 return 1;
4741 default:
4742 break;
4743 }
851ba692 4744 vcpu->run->exit_reason = 0;
a737f256 4745 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4746 (int)(exit_qualification >> 4) & 3, cr);
4747 return 0;
4748}
4749
851ba692 4750static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4751{
bfdaab09 4752 unsigned long exit_qualification;
6aa8b732
AK		 4753 int dr, reg;
4754
f2483415 4755 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4756 if (!kvm_require_cpl(vcpu, 0))
4757 return 1;
42dbaa5a
JK		 4758 dr = vmcs_readl(GUEST_DR7);
4759 if (dr & DR7_GD) {
4760 /*
4761 * As the vm-exit takes precedence over the debug trap, we
4762 * need to emulate the latter, either for the host or the
4763 * guest debugging itself.
4764 */
4765 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4766 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4767 vcpu->run->debug.arch.dr7 = dr;
4768 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4769 vmcs_readl(GUEST_CS_BASE) +
4770 vmcs_readl(GUEST_RIP);
851ba692
AK		 4771 vcpu->run->debug.arch.exception = DB_VECTOR;
4772 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4773 return 0;
4774 } else {
4775 vcpu->arch.dr7 &= ~DR7_GD;
4776 vcpu->arch.dr6 |= DR6_BD;
4777 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4778 kvm_queue_exception(vcpu, DB_VECTOR);
4779 return 1;
4780 }
4781 }
4782
bfdaab09 4783 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4784 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4785 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4786 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4787 unsigned long val;
4788 if (!kvm_get_dr(vcpu, dr, &val))
4789 kvm_register_write(vcpu, reg, val);
4790 } else
4791 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4792 skip_emulated_instruction(vcpu);
4793 return 1;
4794}
4795
020df079
GN		 4796static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4797{
4798 vmcs_writel(GUEST_DR7, val);
4799}
4800
851ba692 4801static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4802{
06465c5a
AK		 4803 kvm_emulate_cpuid(vcpu);
4804 return 1;
6aa8b732
AK		 4805}
4806
851ba692 4807static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4808{
ad312c7c 4809 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4810 u64 data;
4811
4812 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4813 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4814 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4815 return 1;
4816 }
4817
229456fc 4818 trace_kvm_msr_read(ecx, data);
2714d1d3 4819
6aa8b732 4820 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4821 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4822 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4823 skip_emulated_instruction(vcpu);
4824 return 1;
4825}
4826
851ba692 4827static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4828{
8fe8ab46 4829 struct msr_data msr;
ad312c7c
ZX		 4830 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4831 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4832 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4833
8fe8ab46
WA		 4834 msr.data = data;
4835 msr.index = ecx;
4836 msr.host_initiated = false;
4837 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4838 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4839 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4840 return 1;
4841 }
4842
59200273 4843 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4844 skip_emulated_instruction(vcpu);
4845 return 1;
4846}
4847
851ba692 4848static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4849{
3842d135 4850 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4851 return 1;
4852}
4853
851ba692 4854static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4855{
85f455f7
ED		 4856 u32 cpu_based_vm_exec_control;
4857
4858 /* clear pending irq */
4859 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4860 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4861 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4862
3842d135
AK		 4863 kvm_make_request(KVM_REQ_EVENT, vcpu);
4864
a26bf12a 4865 ++vcpu->stat.irq_window_exits;
2714d1d3 4866
c1150d8c
DL		 4867 /*
4868 * If the user space waits to inject interrupts, exit as soon as
4869 * possible
4870 */
8061823a 4871 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4872 vcpu->run->request_interrupt_window &&
8061823a 4873 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4874 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4875 return 0;
4876 }
6aa8b732
AK		 4877 return 1;
4878}
4879
851ba692 4880static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4881{
4882 skip_emulated_instruction(vcpu);
d3bef15f 4883 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4884}
4885
851ba692 4886static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4887{
510043da 4888 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4889 kvm_emulate_hypercall(vcpu);
4890 return 1;
c21415e8
IM		 4891}
4892
ec25d5e6
GN		 4893static int handle_invd(struct kvm_vcpu *vcpu)
4894{
51d8b661 4895 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4896}
4897
851ba692 4898static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4899{
f9c617f6 4900 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4901
4902 kvm_mmu_invlpg(vcpu, exit_qualification);
4903 skip_emulated_instruction(vcpu);
4904 return 1;
4905}
4906
fee84b07
AK		 4907static int handle_rdpmc(struct kvm_vcpu *vcpu)
4908{
4909 int err;
4910
4911 err = kvm_rdpmc(vcpu);
4912 kvm_complete_insn_gp(vcpu, err);
4913
4914 return 1;
4915}
4916
851ba692 4917static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4918{
4919 skip_emulated_instruction(vcpu);
f5f48ee1 4920 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4921 return 1;
4922}
4923
2acf923e
DC		 4924static int handle_xsetbv(struct kvm_vcpu *vcpu)
4925{
4926 u64 new_bv = kvm_read_edx_eax(vcpu);
4927 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4928
4929 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4930 skip_emulated_instruction(vcpu);
4931 return 1;
4932}
4933
851ba692 4934static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4935{
58fbbf26
KT		 4936 if (likely(fasteoi)) {
4937 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4938 int access_type, offset;
4939
4940 access_type = exit_qualification & APIC_ACCESS_TYPE;
4941 offset = exit_qualification & APIC_ACCESS_OFFSET;
4942 /*
4943 * Sane guest uses MOV to write EOI, with written value
4944 * not cared. So make a short-circuit here by avoiding
4945 * heavy instruction emulation.
4946 */
4947 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4948 (offset == APIC_EOI)) {
4949 kvm_lapic_set_eoi(vcpu);
4950 skip_emulated_instruction(vcpu);
4951 return 1;
4952 }
4953 }
51d8b661 4954 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4955}
4956
c7c9c56c
YZ		 4957static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4958{
4959 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4960 int vector = exit_qualification & 0xff;
4961
4962 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4963 kvm_apic_set_eoi_accelerated(vcpu, vector);
4964 return 1;
4965}
4966
83d4c286
YZ		 4967static int handle_apic_write(struct kvm_vcpu *vcpu)
4968{
4969 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4970 u32 offset = exit_qualification & 0xfff;
4971
4972 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4973 kvm_apic_write_nodecode(vcpu, offset);
4974 return 1;
4975}
4976
851ba692 4977static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4978{
60637aac 4979 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4980 unsigned long exit_qualification;
e269fb21
JK		 4981 bool has_error_code = false;
4982 u32 error_code = 0;
37817f29 4983 u16 tss_selector;
7f3d35fd 4984 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4985
4986 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4987 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4988 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4989
4990 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4991
4992 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4993 if (reason == TASK_SWITCH_GATE && idt_v) {
4994 switch (type) {
4995 case INTR_TYPE_NMI_INTR:
4996 vcpu->arch.nmi_injected = false;
654f06fc 4997 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4998 break;
4999 case INTR_TYPE_EXT_INTR:
66fd3f7f 5000 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5001 kvm_clear_interrupt_queue(vcpu);
5002 break;
5003 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5004 if (vmx->idt_vectoring_info &
5005 VECTORING_INFO_DELIVER_CODE_MASK) {
5006 has_error_code = true;
5007 error_code =
5008 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5009 }
5010 /* fall through */
64a7ec06
GN		 5011 case INTR_TYPE_SOFT_EXCEPTION:
5012 kvm_clear_exception_queue(vcpu);
5013 break;
5014 default:
5015 break;
5016 }
60637aac 5017 }
37817f29
IE		 5018 tss_selector = exit_qualification;
5019
64a7ec06
GN		 5020 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5021 type != INTR_TYPE_EXT_INTR &&
5022 type != INTR_TYPE_NMI_INTR))
5023 skip_emulated_instruction(vcpu);
5024
7f3d35fd
KW		 5025 if (kvm_task_switch(vcpu, tss_selector,
5026 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5027 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5028 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5029 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5030 vcpu->run->internal.ndata = 0;
42dbaa5a 5031 return 0;
acb54517 5032 }
42dbaa5a
JK		 5033
5034 /* clear all local breakpoint enable flags */
5035 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5036
5037 /*
5038 * TODO: What about debug traps on tss switch?
5039 * Are we supposed to inject them and update dr6?
5040 */
5041
5042 return 1;
37817f29
IE		 5043}
5044
851ba692 5045static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5046{
f9c617f6 5047 unsigned long exit_qualification;
1439442c 5048 gpa_t gpa;
4f5982a5 5049 u32 error_code;
1439442c 5050 int gla_validity;
1439442c 5051
f9c617f6 5052 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5053
1439442c
SY		 5054 gla_validity = (exit_qualification >> 7) & 0x3;
5055 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5056 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5057 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5058 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5059 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5060 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5061 (long unsigned int)exit_qualification);
851ba692
AK		 5062 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5063 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5064 return 0;
1439442c
SY		 5065 }
5066
5067 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5068 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5069
5070 /* It is a write fault? */
5071 error_code = exit_qualification & (1U << 1);
5072 /* ept page table is present? */
5073 error_code |= (exit_qualification >> 3) & 0x1;
5074
5075 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5076}
5077
68f89400
MT		 5078static u64 ept_rsvd_mask(u64 spte, int level)
5079{
5080 int i;
5081 u64 mask = 0;
5082
5083 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5084 mask |= (1ULL << i);
5085
5086 if (level > 2)
5087 /* bits 7:3 reserved */
5088 mask |= 0xf8;
5089 else if (level == 2) {
5090 if (spte & (1ULL << 7))
5091 /* 2MB ref, bits 20:12 reserved */
5092 mask |= 0x1ff000;
5093 else
5094 /* bits 6:3 reserved */
5095 mask |= 0x78;
5096 }
5097
5098 return mask;
5099}
5100
5101static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5102 int level)
5103{
5104 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5105
5106 /* 010b (write-only) */
5107 WARN_ON((spte & 0x7) == 0x2);
5108
5109 /* 110b (write/execute) */
5110 WARN_ON((spte & 0x7) == 0x6);
5111
5112 /* 100b (execute-only) and value not supported by logical processor */
5113 if (!cpu_has_vmx_ept_execute_only())
5114 WARN_ON((spte & 0x7) == 0x4);
5115
5116 /* not 000b */
5117 if ((spte & 0x7)) {
5118 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5119
5120 if (rsvd_bits != 0) {
5121 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5122 __func__, rsvd_bits);
5123 WARN_ON(1);
5124 }
5125
5126 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5127 u64 ept_mem_type = (spte & 0x38) >> 3;
5128
5129 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5130 ept_mem_type == 7) {
5131 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5132 __func__, ept_mem_type);
5133 WARN_ON(1);
5134 }
5135 }
5136 }
5137}
5138
851ba692 5139static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5140{
5141 u64 sptes[4];
ce88decf 5142 int nr_sptes, i, ret;
68f89400
MT		 5143 gpa_t gpa;
5144
5145 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5146
ce88decf
XG		 5147 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5148 if (likely(ret == 1))
5149 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5150 EMULATE_DONE;
5151 if (unlikely(!ret))
5152 return 1;
5153
5154 /* It is the real ept misconfig */
68f89400
MT		 5155 printk(KERN_ERR "EPT: Misconfiguration.\n");
5156 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5157
5158 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5159
5160 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5161 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5162
851ba692
AK		 5163 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5164 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5165
5166 return 0;
5167}
5168
851ba692 5169static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5170{
5171 u32 cpu_based_vm_exec_control;
5172
5173 /* clear pending NMI */
5174 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5175 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5176 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5177 ++vcpu->stat.nmi_window_exits;
3842d135 5178 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5179
5180 return 1;
5181}
5182
80ced186 5183static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5184{
8b3079a5
AK		 5185 struct vcpu_vmx *vmx = to_vmx(vcpu);
5186 enum emulation_result err = EMULATE_DONE;
80ced186 5187 int ret = 1;
49e9d557
AK		 5188 u32 cpu_exec_ctrl;
5189 bool intr_window_requested;
b8405c18 5190 unsigned count = 130;
49e9d557
AK		 5191
5192 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5193 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5194
b8405c18 5195 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5196 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5197 return handle_interrupt_window(&vmx->vcpu);
5198
de87dcdd
AK		 5199 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5200 return 1;
5201
51d8b661 5202 err = emulate_instruction(vcpu, 0);
ea953ef0 5203
80ced186
MG		 5204 if (err == EMULATE_DO_MMIO) {
5205 ret = 0;
5206 goto out;
5207 }
1d5a4d9b 5208
de5f70e0
AK		 5209 if (err != EMULATE_DONE) {
5210 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5211 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5212 vcpu->run->internal.ndata = 0;
6d77dbfc 5213 return 0;
de5f70e0 5214 }
ea953ef0
MG		 5215
5216 if (signal_pending(current))
80ced186 5217 goto out;
ea953ef0
MG		 5218 if (need_resched())
5219 schedule();
5220 }
5221
14168786 5222 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5223out:
5224 return ret;
ea953ef0
MG		 5225}
5226
4b8d54f9
ZE		 5227/*
5228 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5229 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5230 */
9fb41ba8 5231static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5232{
5233 skip_emulated_instruction(vcpu);
5234 kvm_vcpu_on_spin(vcpu);
5235
5236 return 1;
5237}
5238
59708670
SY		 5239static int handle_invalid_op(struct kvm_vcpu *vcpu)
5240{
5241 kvm_queue_exception(vcpu, UD_VECTOR);
5242 return 1;
5243}
5244
ff2f6fe9
NHE		 5245/*
5246 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5247 * We could reuse a single VMCS for all the L2 guests, but we also want the
5248 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5249 * allows keeping them loaded on the processor, and in the future will allow
5250 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5251 * every entry if they never change.
5252 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5253 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5254 *
5255 * The following functions allocate and free a vmcs02 in this pool.
5256 */
5257
5258/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5259static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5260{
5261 struct vmcs02_list *item;
5262 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5263 if (item->vmptr == vmx->nested.current_vmptr) {
5264 list_move(&item->list, &vmx->nested.vmcs02_pool);
5265 return &item->vmcs02;
5266 }
5267
5268 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5269 /* Recycle the least recently used VMCS. */
5270 item = list_entry(vmx->nested.vmcs02_pool.prev,
5271 struct vmcs02_list, list);
5272 item->vmptr = vmx->nested.current_vmptr;
5273 list_move(&item->list, &vmx->nested.vmcs02_pool);
5274 return &item->vmcs02;
5275 }
5276
5277 /* Create a new VMCS */
0fa24ce3 5278 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5279 if (!item)
5280 return NULL;
5281 item->vmcs02.vmcs = alloc_vmcs();
5282 if (!item->vmcs02.vmcs) {
5283 kfree(item);
5284 return NULL;
5285 }
5286 loaded_vmcs_init(&item->vmcs02);
5287 item->vmptr = vmx->nested.current_vmptr;
5288 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5289 vmx->nested.vmcs02_num++;
5290 return &item->vmcs02;
5291}
5292
5293/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5294static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5295{
5296 struct vmcs02_list *item;
5297 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5298 if (item->vmptr == vmptr) {
5299 free_loaded_vmcs(&item->vmcs02);
5300 list_del(&item->list);
5301 kfree(item);
5302 vmx->nested.vmcs02_num--;
5303 return;
5304 }
5305}
5306
5307/*
5308 * Free all VMCSs saved for this vcpu, except the one pointed by
5309 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5310 * currently used, if running L2), and vmcs01 when running L2.
5311 */
5312static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5313{
5314 struct vmcs02_list *item, *n;
5315 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5316 if (vmx->loaded_vmcs != &item->vmcs02)
5317 free_loaded_vmcs(&item->vmcs02);
5318 list_del(&item->list);
5319 kfree(item);
5320 }
5321 vmx->nested.vmcs02_num = 0;
5322
5323 if (vmx->loaded_vmcs != &vmx->vmcs01)
5324 free_loaded_vmcs(&vmx->vmcs01);
5325}
5326
ec378aee
NHE		 5327/*
5328 * Emulate the VMXON instruction.
5329 * Currently, we just remember that VMX is active, and do not save or even
5330 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5331 * do not currently need to store anything in that guest-allocated memory
5332 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5333 * argument is different from the VMXON pointer (which the spec says they do).
5334 */
5335static int handle_vmon(struct kvm_vcpu *vcpu)
5336{
5337 struct kvm_segment cs;
5338 struct vcpu_vmx *vmx = to_vmx(vcpu);
5339
5340 /* The Intel VMX Instruction Reference lists a bunch of bits that
5341 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5342 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5343 * Otherwise, we should fail with #UD. We test these now:
5344 */
5345 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5346 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5347 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5348 kvm_queue_exception(vcpu, UD_VECTOR);
5349 return 1;
5350 }
5351
5352 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5353 if (is_long_mode(vcpu) && !cs.l) {
5354 kvm_queue_exception(vcpu, UD_VECTOR);
5355 return 1;
5356 }
5357
5358 if (vmx_get_cpl(vcpu)) {
5359 kvm_inject_gp(vcpu, 0);
5360 return 1;
5361 }
5362
ff2f6fe9
NHE		 5363 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5364 vmx->nested.vmcs02_num = 0;
5365
ec378aee
NHE		 5366 vmx->nested.vmxon = true;
5367
5368 skip_emulated_instruction(vcpu);
5369 return 1;
5370}
5371
5372/*
5373 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5374 * for running VMX instructions (except VMXON, whose prerequisites are
5375 * slightly different). It also specifies what exception to inject otherwise.
5376 */
5377static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5378{
5379 struct kvm_segment cs;
5380 struct vcpu_vmx *vmx = to_vmx(vcpu);
5381
5382 if (!vmx->nested.vmxon) {
5383 kvm_queue_exception(vcpu, UD_VECTOR);
5384 return 0;
5385 }
5386
5387 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5388 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5389 (is_long_mode(vcpu) && !cs.l)) {
5390 kvm_queue_exception(vcpu, UD_VECTOR);
5391 return 0;
5392 }
5393
5394 if (vmx_get_cpl(vcpu)) {
5395 kvm_inject_gp(vcpu, 0);
5396 return 0;
5397 }
5398
5399 return 1;
5400}
5401
5402/*
5403 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5404 * just stops using VMX.
5405 */
5406static void free_nested(struct vcpu_vmx *vmx)
5407{
5408 if (!vmx->nested.vmxon)
5409 return;
5410 vmx->nested.vmxon = false;
a9d30f33
NHE		 5411 if (vmx->nested.current_vmptr != -1ull) {
5412 kunmap(vmx->nested.current_vmcs12_page);
5413 nested_release_page(vmx->nested.current_vmcs12_page);
5414 vmx->nested.current_vmptr = -1ull;
5415 vmx->nested.current_vmcs12 = NULL;
5416 }
fe3ef05c
NHE		 5417 /* Unpin physical memory we referred to in current vmcs02 */
5418 if (vmx->nested.apic_access_page) {
5419 nested_release_page(vmx->nested.apic_access_page);
5420 vmx->nested.apic_access_page = 0;
5421 }
ff2f6fe9
NHE		 5422
5423 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5424}
5425
5426/* Emulate the VMXOFF instruction */
5427static int handle_vmoff(struct kvm_vcpu *vcpu)
5428{
5429 if (!nested_vmx_check_permission(vcpu))
5430 return 1;
5431 free_nested(to_vmx(vcpu));
5432 skip_emulated_instruction(vcpu);
5433 return 1;
5434}
5435
064aea77
NHE		 5436/*
5437 * Decode the memory-address operand of a vmx instruction, as recorded on an
5438 * exit caused by such an instruction (run by a guest hypervisor).
5439 * On success, returns 0. When the operand is invalid, returns 1 and throws
5440 * #UD or #GP.
5441 */
5442static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5443 unsigned long exit_qualification,
5444 u32 vmx_instruction_info, gva_t *ret)
5445{
5446 /*
5447 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5448 * Execution", on an exit, vmx_instruction_info holds most of the
5449 * addressing components of the operand. Only the displacement part
5450 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5451 * For how an actual address is calculated from all these components,
5452 * refer to Vol. 1, "Operand Addressing".
5453 */
5454 int scaling = vmx_instruction_info & 3;
5455 int addr_size = (vmx_instruction_info >> 7) & 7;
5456 bool is_reg = vmx_instruction_info & (1u << 10);
5457 int seg_reg = (vmx_instruction_info >> 15) & 7;
5458 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5459 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5460 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5461 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5462
5463 if (is_reg) {
5464 kvm_queue_exception(vcpu, UD_VECTOR);
5465 return 1;
5466 }
5467
5468 /* Addr = segment_base + offset */
5469 /* offset = base + [index * scale] + displacement */
5470 *ret = vmx_get_segment_base(vcpu, seg_reg);
5471 if (base_is_valid)
5472 *ret += kvm_register_read(vcpu, base_reg);
5473 if (index_is_valid)
5474 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5475 *ret += exit_qualification; /* holds the displacement */
5476
5477 if (addr_size == 1) /* 32 bit */
5478 *ret &= 0xffffffff;
5479
5480 /*
5481 * TODO: throw #GP (and return 1) in various cases that the VM*
5482 * instructions require it - e.g., offset beyond segment limit,
5483 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5484 * address, and so on. Currently these are not checked.
5485 */
5486 return 0;
5487}
5488
0140caea
NHE		 5489/*
5490 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5491 * set the success or error code of an emulated VMX instruction, as specified
5492 * by Vol 2B, VMX Instruction Reference, "Conventions".
5493 */
5494static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5495{
5496 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5497 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5498 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5499}
5500
5501static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5502{
5503 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5504 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5505 X86_EFLAGS_SF | X86_EFLAGS_OF))
5506 | X86_EFLAGS_CF);
5507}
5508
5509static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5510 u32 vm_instruction_error)
5511{
5512 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5513 /*
5514 * failValid writes the error number to the current VMCS, which
5515 * can't be done there isn't a current VMCS.
5516 */
5517 nested_vmx_failInvalid(vcpu);
5518 return;
5519 }
5520 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5521 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5522 X86_EFLAGS_SF | X86_EFLAGS_OF))
5523 | X86_EFLAGS_ZF);
5524 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5525}
5526
27d6c865
NHE		 5527/* Emulate the VMCLEAR instruction */
5528static int handle_vmclear(struct kvm_vcpu *vcpu)
5529{
5530 struct vcpu_vmx *vmx = to_vmx(vcpu);
5531 gva_t gva;
5532 gpa_t vmptr;
5533 struct vmcs12 *vmcs12;
5534 struct page *page;
5535 struct x86_exception e;
5536
5537 if (!nested_vmx_check_permission(vcpu))
5538 return 1;
5539
5540 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5541 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5542 return 1;
5543
5544 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5545 sizeof(vmptr), &e)) {
5546 kvm_inject_page_fault(vcpu, &e);
5547 return 1;
5548 }
5549
5550 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5551 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5552 skip_emulated_instruction(vcpu);
5553 return 1;
5554 }
5555
5556 if (vmptr == vmx->nested.current_vmptr) {
5557 kunmap(vmx->nested.current_vmcs12_page);
5558 nested_release_page(vmx->nested.current_vmcs12_page);
5559 vmx->nested.current_vmptr = -1ull;
5560 vmx->nested.current_vmcs12 = NULL;
5561 }
5562
5563 page = nested_get_page(vcpu, vmptr);
5564 if (page == NULL) {
5565 /*
5566 * For accurate processor emulation, VMCLEAR beyond available
5567 * physical memory should do nothing at all. However, it is
5568 * possible that a nested vmx bug, not a guest hypervisor bug,
5569 * resulted in this case, so let's shut down before doing any
5570 * more damage:
5571 */
5572 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5573 return 1;
5574 }
5575 vmcs12 = kmap(page);
5576 vmcs12->launch_state = 0;
5577 kunmap(page);
5578 nested_release_page(page);
5579
5580 nested_free_vmcs02(vmx, vmptr);
5581
5582 skip_emulated_instruction(vcpu);
5583 nested_vmx_succeed(vcpu);
5584 return 1;
5585}
5586
cd232ad0
NHE		 5587static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5588
5589/* Emulate the VMLAUNCH instruction */
5590static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5591{
5592 return nested_vmx_run(vcpu, true);
5593}
5594
5595/* Emulate the VMRESUME instruction */
5596static int handle_vmresume(struct kvm_vcpu *vcpu)
5597{
5598
5599 return nested_vmx_run(vcpu, false);
5600}
5601
49f705c5
NHE		 5602enum vmcs_field_type {
5603 VMCS_FIELD_TYPE_U16 = 0,
5604 VMCS_FIELD_TYPE_U64 = 1,
5605 VMCS_FIELD_TYPE_U32 = 2,
5606 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5607};
5608
5609static inline int vmcs_field_type(unsigned long field)
5610{
5611 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5612 return VMCS_FIELD_TYPE_U32;
5613 return (field >> 13) & 0x3 ;
5614}
5615
5616static inline int vmcs_field_readonly(unsigned long field)
5617{
5618 return (((field >> 10) & 0x3) == 1);
5619}
5620
5621/*
5622 * Read a vmcs12 field. Since these can have varying lengths and we return
5623 * one type, we chose the biggest type (u64) and zero-extend the return value
5624 * to that size. Note that the caller, handle_vmread, might need to use only
5625 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5626 * 64-bit fields are to be returned).
5627 */
5628static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5629 unsigned long field, u64 *ret)
5630{
5631 short offset = vmcs_field_to_offset(field);
5632 char *p;
5633
5634 if (offset < 0)
5635 return 0;
5636
5637 p = ((char *)(get_vmcs12(vcpu))) + offset;
5638
5639 switch (vmcs_field_type(field)) {
5640 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5641 *ret = *((natural_width *)p);
5642 return 1;
5643 case VMCS_FIELD_TYPE_U16:
5644 *ret = *((u16 *)p);
5645 return 1;
5646 case VMCS_FIELD_TYPE_U32:
5647 *ret = *((u32 *)p);
5648 return 1;
5649 case VMCS_FIELD_TYPE_U64:
5650 *ret = *((u64 *)p);
5651 return 1;
5652 default:
5653 return 0; /* can never happen. */
5654 }
5655}
5656
5657/*
5658 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5659 * used before) all generate the same failure when it is missing.
5660 */
5661static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5662{
5663 struct vcpu_vmx *vmx = to_vmx(vcpu);
5664 if (vmx->nested.current_vmptr == -1ull) {
5665 nested_vmx_failInvalid(vcpu);
5666 skip_emulated_instruction(vcpu);
5667 return 0;
5668 }
5669 return 1;
5670}
5671
5672static int handle_vmread(struct kvm_vcpu *vcpu)
5673{
5674 unsigned long field;
5675 u64 field_value;
5676 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5677 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5678 gva_t gva = 0;
5679
5680 if (!nested_vmx_check_permission(vcpu) ||
5681 !nested_vmx_check_vmcs12(vcpu))
5682 return 1;
5683
5684 /* Decode instruction info and find the field to read */
5685 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5686 /* Read the field, zero-extended to a u64 field_value */
5687 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5688 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5689 skip_emulated_instruction(vcpu);
5690 return 1;
5691 }
5692 /*
5693 * Now copy part of this value to register or memory, as requested.
5694 * Note that the number of bits actually copied is 32 or 64 depending
5695 * on the guest's mode (32 or 64 bit), not on the given field's length.
5696 */
5697 if (vmx_instruction_info & (1u << 10)) {
5698 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5699 field_value);
5700 } else {
5701 if (get_vmx_mem_address(vcpu, exit_qualification,
5702 vmx_instruction_info, &gva))
5703 return 1;
5704 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5705 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5706 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5707 }
5708
5709 nested_vmx_succeed(vcpu);
5710 skip_emulated_instruction(vcpu);
5711 return 1;
5712}
5713
5714
5715static int handle_vmwrite(struct kvm_vcpu *vcpu)
5716{
5717 unsigned long field;
5718 gva_t gva;
5719 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5720 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5721 char *p;
5722 short offset;
5723 /* The value to write might be 32 or 64 bits, depending on L1's long
5724 * mode, and eventually we need to write that into a field of several
5725 * possible lengths. The code below first zero-extends the value to 64
5726 * bit (field_value), and then copies only the approriate number of
5727 * bits into the vmcs12 field.
5728 */
5729 u64 field_value = 0;
5730 struct x86_exception e;
5731
5732 if (!nested_vmx_check_permission(vcpu) ||
5733 !nested_vmx_check_vmcs12(vcpu))
5734 return 1;
5735
5736 if (vmx_instruction_info & (1u << 10))
5737 field_value = kvm_register_read(vcpu,
5738 (((vmx_instruction_info) >> 3) & 0xf));
5739 else {
5740 if (get_vmx_mem_address(vcpu, exit_qualification,
5741 vmx_instruction_info, &gva))
5742 return 1;
5743 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5744 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5745 kvm_inject_page_fault(vcpu, &e);
5746 return 1;
5747 }
5748 }
5749
5750
5751 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5752 if (vmcs_field_readonly(field)) {
5753 nested_vmx_failValid(vcpu,
5754 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5755 skip_emulated_instruction(vcpu);
5756 return 1;
5757 }
5758
5759 offset = vmcs_field_to_offset(field);
5760 if (offset < 0) {
5761 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5762 skip_emulated_instruction(vcpu);
5763 return 1;
5764 }
5765 p = ((char *) get_vmcs12(vcpu)) + offset;
5766
5767 switch (vmcs_field_type(field)) {
5768 case VMCS_FIELD_TYPE_U16:
5769 *(u16 *)p = field_value;
5770 break;
5771 case VMCS_FIELD_TYPE_U32:
5772 *(u32 *)p = field_value;
5773 break;
5774 case VMCS_FIELD_TYPE_U64:
5775 *(u64 *)p = field_value;
5776 break;
5777 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5778 *(natural_width *)p = field_value;
5779 break;
5780 default:
5781 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5782 skip_emulated_instruction(vcpu);
5783 return 1;
5784 }
5785
5786 nested_vmx_succeed(vcpu);
5787 skip_emulated_instruction(vcpu);
5788 return 1;
5789}
5790
63846663
NHE		 5791/* Emulate the VMPTRLD instruction */
5792static int handle_vmptrld(struct kvm_vcpu *vcpu)
5793{
5794 struct vcpu_vmx *vmx = to_vmx(vcpu);
5795 gva_t gva;
5796 gpa_t vmptr;
5797 struct x86_exception e;
5798
5799 if (!nested_vmx_check_permission(vcpu))
5800 return 1;
5801
5802 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5803 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5804 return 1;
5805
5806 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5807 sizeof(vmptr), &e)) {
5808 kvm_inject_page_fault(vcpu, &e);
5809 return 1;
5810 }
5811
5812 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5813 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5814 skip_emulated_instruction(vcpu);
5815 return 1;
5816 }
5817
5818 if (vmx->nested.current_vmptr != vmptr) {
5819 struct vmcs12 *new_vmcs12;
5820 struct page *page;
5821 page = nested_get_page(vcpu, vmptr);
5822 if (page == NULL) {
5823 nested_vmx_failInvalid(vcpu);
5824 skip_emulated_instruction(vcpu);
5825 return 1;
5826 }
5827 new_vmcs12 = kmap(page);
5828 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5829 kunmap(page);
5830 nested_release_page_clean(page);
5831 nested_vmx_failValid(vcpu,
5832 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5833 skip_emulated_instruction(vcpu);
5834 return 1;
5835 }
5836 if (vmx->nested.current_vmptr != -1ull) {
5837 kunmap(vmx->nested.current_vmcs12_page);
5838 nested_release_page(vmx->nested.current_vmcs12_page);
5839 }
5840
5841 vmx->nested.current_vmptr = vmptr;
5842 vmx->nested.current_vmcs12 = new_vmcs12;
5843 vmx->nested.current_vmcs12_page = page;
5844 }
5845
5846 nested_vmx_succeed(vcpu);
5847 skip_emulated_instruction(vcpu);
5848 return 1;
5849}
5850
6a4d7550
NHE		 5851/* Emulate the VMPTRST instruction */
5852static int handle_vmptrst(struct kvm_vcpu *vcpu)
5853{
5854 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5855 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5856 gva_t vmcs_gva;
5857 struct x86_exception e;
5858
5859 if (!nested_vmx_check_permission(vcpu))
5860 return 1;
5861
5862 if (get_vmx_mem_address(vcpu, exit_qualification,
5863 vmx_instruction_info, &vmcs_gva))
5864 return 1;
5865 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5866 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5867 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5868 sizeof(u64), &e)) {
5869 kvm_inject_page_fault(vcpu, &e);
5870 return 1;
5871 }
5872 nested_vmx_succeed(vcpu);
5873 skip_emulated_instruction(vcpu);
5874 return 1;
5875}
5876
6aa8b732
AK		 5877/*
5878 * The exit handlers return 1 if the exit was handled fully and guest execution
5879 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5880 * to be done to userspace and return 0.
5881 */
772e0318 5882static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5883 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5884 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5885 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5886 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5887 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5888 [EXIT_REASON_CR_ACCESS] = handle_cr,
5889 [EXIT_REASON_DR_ACCESS] = handle_dr,
5890 [EXIT_REASON_CPUID] = handle_cpuid,
5891 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5892 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5893 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5894 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5895 [EXIT_REASON_INVD] = handle_invd,
a7052897 5896 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5897 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5898 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5899 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5900 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5901 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5902 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5903 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5904 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5905 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5906 [EXIT_REASON_VMOFF] = handle_vmoff,
5907 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5908 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5909 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 5910 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 5911 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 5912 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5913 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5914 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5915 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5916 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5917 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5918 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5919 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5920 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5921};
5922
5923static const int kvm_vmx_max_exit_handlers =
50a3485c 5924 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5925
908a7bdd
JK		 5926static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5927 struct vmcs12 *vmcs12)
5928{
5929 unsigned long exit_qualification;
5930 gpa_t bitmap, last_bitmap;
5931 unsigned int port;
5932 int size;
5933 u8 b;
5934
5935 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5936 return 1;
5937
5938 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5939 return 0;
5940
5941 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5942
5943 port = exit_qualification >> 16;
5944 size = (exit_qualification & 7) + 1;
5945
5946 last_bitmap = (gpa_t)-1;
5947 b = -1;
5948
5949 while (size > 0) {
5950 if (port < 0x8000)
5951 bitmap = vmcs12->io_bitmap_a;
5952 else if (port < 0x10000)
5953 bitmap = vmcs12->io_bitmap_b;
5954 else
5955 return 1;
5956 bitmap += (port & 0x7fff) / 8;
5957
5958 if (last_bitmap != bitmap)
5959 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5960 return 1;
5961 if (b & (1 << (port & 7)))
5962 return 1;
5963
5964 port++;
5965 size--;
5966 last_bitmap = bitmap;
5967 }
5968
5969 return 0;
5970}
5971
644d711a
NHE		 5972/*
5973 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5974 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5975 * disinterest in the current event (read or write a specific MSR) by using an
5976 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5977 */
5978static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5979 struct vmcs12 *vmcs12, u32 exit_reason)
5980{
5981 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5982 gpa_t bitmap;
5983
cbd29cb6 5984 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 5985 return 1;
5986
5987 /*
5988 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5989 * for the four combinations of read/write and low/high MSR numbers.
5990 * First we need to figure out which of the four to use:
5991 */
5992 bitmap = vmcs12->msr_bitmap;
5993 if (exit_reason == EXIT_REASON_MSR_WRITE)
5994 bitmap += 2048;
5995 if (msr_index >= 0xc0000000) {
5996 msr_index -= 0xc0000000;
5997 bitmap += 1024;
5998 }
5999
6000 /* Then read the msr_index'th bit from this bitmap: */
6001 if (msr_index < 1024*8) {
6002 unsigned char b;
bd31a7f5
JK		 6003 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6004 return 1;
644d711a
NHE		 6005 return 1 & (b >> (msr_index & 7));
6006 } else
6007 return 1; /* let L1 handle the wrong parameter */
6008}
6009
6010/*
6011 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6012 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6013 * intercept (via guest_host_mask etc.) the current event.
6014 */
6015static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6016 struct vmcs12 *vmcs12)
6017{
6018 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6019 int cr = exit_qualification & 15;
6020 int reg = (exit_qualification >> 8) & 15;
6021 unsigned long val = kvm_register_read(vcpu, reg);
6022
6023 switch ((exit_qualification >> 4) & 3) {
6024 case 0: /* mov to cr */
6025 switch (cr) {
6026 case 0:
6027 if (vmcs12->cr0_guest_host_mask &
6028 (val ^ vmcs12->cr0_read_shadow))
6029 return 1;
6030 break;
6031 case 3:
6032 if ((vmcs12->cr3_target_count >= 1 &&
6033 vmcs12->cr3_target_value0 == val) ||
6034 (vmcs12->cr3_target_count >= 2 &&
6035 vmcs12->cr3_target_value1 == val) ||
6036 (vmcs12->cr3_target_count >= 3 &&
6037 vmcs12->cr3_target_value2 == val) ||
6038 (vmcs12->cr3_target_count >= 4 &&
6039 vmcs12->cr3_target_value3 == val))
6040 return 0;
6041 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6042 return 1;
6043 break;
6044 case 4:
6045 if (vmcs12->cr4_guest_host_mask &
6046 (vmcs12->cr4_read_shadow ^ val))
6047 return 1;
6048 break;
6049 case 8:
6050 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6051 return 1;
6052 break;
6053 }
6054 break;
6055 case 2: /* clts */
6056 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6057 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6058 return 1;
6059 break;
6060 case 1: /* mov from cr */
6061 switch (cr) {
6062 case 3:
6063 if (vmcs12->cpu_based_vm_exec_control &
6064 CPU_BASED_CR3_STORE_EXITING)
6065 return 1;
6066 break;
6067 case 8:
6068 if (vmcs12->cpu_based_vm_exec_control &
6069 CPU_BASED_CR8_STORE_EXITING)
6070 return 1;
6071 break;
6072 }
6073 break;
6074 case 3: /* lmsw */
6075 /*
6076 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6077 * cr0. Other attempted changes are ignored, with no exit.
6078 */
6079 if (vmcs12->cr0_guest_host_mask & 0xe &
6080 (val ^ vmcs12->cr0_read_shadow))
6081 return 1;
6082 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6083 !(vmcs12->cr0_read_shadow & 0x1) &&
6084 (val & 0x1))
6085 return 1;
6086 break;
6087 }
6088 return 0;
6089}
6090
6091/*
6092 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6093 * should handle it ourselves in L0 (and then continue L2). Only call this
6094 * when in is_guest_mode (L2).
6095 */
6096static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6097{
644d711a
NHE		 6098 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6099 struct vcpu_vmx *vmx = to_vmx(vcpu);
6100 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6101 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6102
6103 if (vmx->nested.nested_run_pending)
6104 return 0;
6105
6106 if (unlikely(vmx->fail)) {
bd80158a
JK		 6107 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6108 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6109 return 1;
6110 }
6111
6112 switch (exit_reason) {
6113 case EXIT_REASON_EXCEPTION_NMI:
6114 if (!is_exception(intr_info))
6115 return 0;
6116 else if (is_page_fault(intr_info))
6117 return enable_ept;
6118 return vmcs12->exception_bitmap &
6119 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6120 case EXIT_REASON_EXTERNAL_INTERRUPT:
6121 return 0;
6122 case EXIT_REASON_TRIPLE_FAULT:
6123 return 1;
6124 case EXIT_REASON_PENDING_INTERRUPT:
6125 case EXIT_REASON_NMI_WINDOW:
6126 /*
6127 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6128 * (aka Interrupt Window Exiting) only when L1 turned it on,
6129 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6130 * Same for NMI Window Exiting.
6131 */
6132 return 1;
6133 case EXIT_REASON_TASK_SWITCH:
6134 return 1;
6135 case EXIT_REASON_CPUID:
6136 return 1;
6137 case EXIT_REASON_HLT:
6138 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6139 case EXIT_REASON_INVD:
6140 return 1;
6141 case EXIT_REASON_INVLPG:
6142 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6143 case EXIT_REASON_RDPMC:
6144 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6145 case EXIT_REASON_RDTSC:
6146 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6147 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6148 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6149 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6150 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6151 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6152 /*
6153 * VMX instructions trap unconditionally. This allows L1 to
6154 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6155 */
6156 return 1;
6157 case EXIT_REASON_CR_ACCESS:
6158 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6159 case EXIT_REASON_DR_ACCESS:
6160 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6161 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6162 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6163 case EXIT_REASON_MSR_READ:
6164 case EXIT_REASON_MSR_WRITE:
6165 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6166 case EXIT_REASON_INVALID_STATE:
6167 return 1;
6168 case EXIT_REASON_MWAIT_INSTRUCTION:
6169 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6170 case EXIT_REASON_MONITOR_INSTRUCTION:
6171 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6172 case EXIT_REASON_PAUSE_INSTRUCTION:
6173 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6174 nested_cpu_has2(vmcs12,
6175 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6176 case EXIT_REASON_MCE_DURING_VMENTRY:
6177 return 0;
6178 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6179 return 1;
6180 case EXIT_REASON_APIC_ACCESS:
6181 return nested_cpu_has2(vmcs12,
6182 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6183 case EXIT_REASON_EPT_VIOLATION:
6184 case EXIT_REASON_EPT_MISCONFIG:
6185 return 0;
6186 case EXIT_REASON_WBINVD:
6187 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6188 case EXIT_REASON_XSETBV:
6189 return 1;
6190 default:
6191 return 1;
6192 }
6193}
6194
586f9607
AK		 6195static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6196{
6197 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6198 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6199}
6200
6aa8b732
AK		 6201/*
6202 * The guest has exited. See if we can fix it or if we need userspace
6203 * assistance.
6204 */
851ba692 6205static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6206{
29bd8a78 6207 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6208 u32 exit_reason = vmx->exit_reason;
1155f76a 6209 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6210
80ced186 6211 /* If guest state is invalid, start emulating */
14168786 6212 if (vmx->emulation_required)
80ced186 6213 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6214
b6f1250e
NHE		 6215 /*
6216 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6217 * we did not inject a still-pending event to L1 now because of
6218 * nested_run_pending, we need to re-enable this bit.
6219 */
6220 if (vmx->nested.nested_run_pending)
6221 kvm_make_request(KVM_REQ_EVENT, vcpu);
6222
509c75ea
NHE		 6223 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6224 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6225 vmx->nested.nested_run_pending = 1;
6226 else
6227 vmx->nested.nested_run_pending = 0;
6228
6229 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6230 nested_vmx_vmexit(vcpu);
6231 return 1;
6232 }
6233
5120702e
MG		 6234 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6235 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6236 vcpu->run->fail_entry.hardware_entry_failure_reason
6237 = exit_reason;
6238 return 0;
6239 }
6240
29bd8a78 6241 if (unlikely(vmx->fail)) {
851ba692
AK		 6242 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6243 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6244 = vmcs_read32(VM_INSTRUCTION_ERROR);
6245 return 0;
6246 }
6aa8b732 6247
b9bf6882
XG		 6248 /*
6249 * Note:
6250 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6251 * delivery event since it indicates guest is accessing MMIO.
6252 * The vm-exit can be triggered again after return to guest that
6253 * will cause infinite loop.
6254 */
d77c26fc 6255 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6256 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6257 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6258 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6259 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6260 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6261 vcpu->run->internal.ndata = 2;
6262 vcpu->run->internal.data[0] = vectoring_info;
6263 vcpu->run->internal.data[1] = exit_reason;
6264 return 0;
6265 }
3b86cd99 6266
644d711a
NHE		 6267 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6268 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6269 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6270 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6271 vmx->soft_vnmi_blocked = 0;
3b86cd99 6272 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6273 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6274 /*
6275 * This CPU don't support us in finding the end of an
6276 * NMI-blocked window if the guest runs with IRQs
6277 * disabled. So we pull the trigger after 1 s of
6278 * futile waiting, but inform the user about this.
6279 */
6280 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6281 "state on VCPU %d after 1 s timeout\n",
6282 __func__, vcpu->vcpu_id);
6283 vmx->soft_vnmi_blocked = 0;
3b86cd99 6284 }
3b86cd99
JK		 6285 }
6286
6aa8b732
AK		 6287 if (exit_reason < kvm_vmx_max_exit_handlers
6288 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6289 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6290 else {
851ba692
AK		 6291 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6292 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6293 }
6294 return 0;
6295}
6296
95ba8273 6297static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6298{
95ba8273 6299 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6300 vmcs_write32(TPR_THRESHOLD, 0);
6301 return;
6302 }
6303
95ba8273 6304 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6305}
6306
8d14695f
YZ		 6307static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6308{
6309 u32 sec_exec_control;
6310
6311 /*
6312 * There is not point to enable virtualize x2apic without enable
6313 * apicv
6314 */
c7c9c56c
YZ		 6315 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6316 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6317 return;
6318
6319 if (!vm_need_tpr_shadow(vcpu->kvm))
6320 return;
6321
6322 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6323
6324 if (set) {
6325 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6326 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6327 } else {
6328 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6329 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6330 }
6331 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6332
6333 vmx_set_msr_bitmap(vcpu);
6334}
6335
c7c9c56c
YZ		 6336static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6337{
6338 u16 status;
6339 u8 old;
6340
6341 if (!vmx_vm_has_apicv(kvm))
6342 return;
6343
6344 if (isr == -1)
6345 isr = 0;
6346
6347 status = vmcs_read16(GUEST_INTR_STATUS);
6348 old = status >> 8;
6349 if (isr != old) {
6350 status &= 0xff;
6351 status |= isr << 8;
6352 vmcs_write16(GUEST_INTR_STATUS, status);
6353 }
6354}
6355
6356static void vmx_set_rvi(int vector)
6357{
6358 u16 status;
6359 u8 old;
6360
6361 status = vmcs_read16(GUEST_INTR_STATUS);
6362 old = (u8)status & 0xff;
6363 if ((u8)vector != old) {
6364 status &= ~0xff;
6365 status |= (u8)vector;
6366 vmcs_write16(GUEST_INTR_STATUS, status);
6367 }
6368}
6369
6370static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6371{
6372 if (max_irr == -1)
6373 return;
6374
6375 vmx_set_rvi(max_irr);
6376}
6377
6378static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6379{
6380 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6381 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6382 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6383 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6384}
6385
51aa01d1 6386static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6387{
00eba012
AK		 6388 u32 exit_intr_info;
6389
6390 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6391 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6392 return;
6393
c5ca8e57 6394 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6395 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6396
6397 /* Handle machine checks before interrupts are enabled */
00eba012 6398 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6399 kvm_machine_check();
6400
20f65983 6401 /* We need to handle NMIs before interrupts are enabled */
00eba012 6402 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6403 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6404 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6405 asm("int $2");
ff9d07a0
ZY		 6406 kvm_after_handle_nmi(&vmx->vcpu);
6407 }
51aa01d1 6408}
20f65983 6409
51aa01d1
AK		 6410static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6411{
c5ca8e57 6412 u32 exit_intr_info;
51aa01d1
AK		 6413 bool unblock_nmi;
6414 u8 vector;
6415 bool idtv_info_valid;
6416
6417 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6418
cf393f75 6419 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6420 if (vmx->nmi_known_unmasked)
6421 return;
c5ca8e57
AK		 6422 /*
6423 * Can't use vmx->exit_intr_info since we're not sure what
6424 * the exit reason is.
6425 */
6426 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6427 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6428 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6429 /*
7b4a25cb 6430 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6431 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6432 * a guest IRET fault.
7b4a25cb
GN		 6433 * SDM 3: 23.2.2 (September 2008)
6434 * Bit 12 is undefined in any of the following cases:
6435 * If the VM exit sets the valid bit in the IDT-vectoring
6436 * information field.
6437 * If the VM exit is due to a double fault.
cf393f75 6438 */
7b4a25cb
GN		 6439 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6440 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6441 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6442 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6443 else
6444 vmx->nmi_known_unmasked =
6445 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6446 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6447 } else if (unlikely(vmx->soft_vnmi_blocked))
6448 vmx->vnmi_blocked_time +=
6449 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6450}
6451
3ab66e8a 6452static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6453 u32 idt_vectoring_info,
6454 int instr_len_field,
6455 int error_code_field)
51aa01d1 6456{
51aa01d1
AK		 6457 u8 vector;
6458 int type;
6459 bool idtv_info_valid;
6460
6461 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6462
3ab66e8a
JK		 6463 vcpu->arch.nmi_injected = false;
6464 kvm_clear_exception_queue(vcpu);
6465 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6466
6467 if (!idtv_info_valid)
6468 return;
6469
3ab66e8a 6470 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6471
668f612f
AK		 6472 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6473 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6474
64a7ec06 6475 switch (type) {
37b96e98 6476 case INTR_TYPE_NMI_INTR:
3ab66e8a 6477 vcpu->arch.nmi_injected = true;
668f612f 6478 /*
7b4a25cb 6479 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6480 * Clear bit "block by NMI" before VM entry if a NMI
6481 * delivery faulted.
668f612f 6482 */
3ab66e8a 6483 vmx_set_nmi_mask(vcpu, false);
37b96e98 6484 break;
37b96e98 6485 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6486 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6487 /* fall through */
6488 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6489 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6490 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6491 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6492 } else
3ab66e8a 6493 kvm_queue_exception(vcpu, vector);
37b96e98 6494 break;
66fd3f7f 6495 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6496 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6497 /* fall through */
37b96e98 6498 case INTR_TYPE_EXT_INTR:
3ab66e8a 6499 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6500 break;
6501 default:
6502 break;
f7d9238f 6503 }
cf393f75
AK		 6504}
6505
83422e17
AK		 6506static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6507{
66c78ae4
NHE		 6508 if (is_guest_mode(&vmx->vcpu))
6509 return;
3ab66e8a 6510 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6511 VM_EXIT_INSTRUCTION_LEN,
6512 IDT_VECTORING_ERROR_CODE);
6513}
6514
b463a6f7
AK		 6515static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6516{
66c78ae4
NHE		 6517 if (is_guest_mode(vcpu))
6518 return;
3ab66e8a 6519 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6520 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6521 VM_ENTRY_INSTRUCTION_LEN,
6522 VM_ENTRY_EXCEPTION_ERROR_CODE);
6523
6524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6525}
6526
d7cd9796
GN		 6527static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6528{
6529 int i, nr_msrs;
6530 struct perf_guest_switch_msr *msrs;
6531
6532 msrs = perf_guest_get_msrs(&nr_msrs);
6533
6534 if (!msrs)
6535 return;
6536
6537 for (i = 0; i < nr_msrs; i++)
6538 if (msrs[i].host == msrs[i].guest)
6539 clear_atomic_switch_msr(vmx, msrs[i].msr);
6540 else
6541 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6542 msrs[i].host);
6543}
6544
a3b5ba49 6545static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6546{
a2fa3e9f 6547 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6548 unsigned long debugctlmsr;
104f226b 6549
66c78ae4
NHE		 6550 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6551 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6552 if (vmcs12->idt_vectoring_info_field &
6553 VECTORING_INFO_VALID_MASK) {
6554 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6555 vmcs12->idt_vectoring_info_field);
6556 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6557 vmcs12->vm_exit_instruction_len);
6558 if (vmcs12->idt_vectoring_info_field &
6559 VECTORING_INFO_DELIVER_CODE_MASK)
6560 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6561 vmcs12->idt_vectoring_error_code);
6562 }
6563 }
6564
104f226b
AK		 6565 /* Record the guest's net vcpu time for enforced NMI injections. */
6566 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6567 vmx->entry_time = ktime_get();
6568
6569 /* Don't enter VMX if guest state is invalid, let the exit handler
6570 start emulation until we arrive back to a valid state */
14168786 6571 if (vmx->emulation_required)
104f226b
AK		 6572 return;
6573
6574 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6575 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6576 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6577 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6578
6579 /* When single-stepping over STI and MOV SS, we must clear the
6580 * corresponding interruptibility bits in the guest state. Otherwise
6581 * vmentry fails as it then expects bit 14 (BS) in pending debug
6582 * exceptions being set, but that's not correct for the guest debugging
6583 * case. */
6584 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6585 vmx_set_interrupt_shadow(vcpu, 0);
6586
d7cd9796 6587 atomic_switch_perf_msrs(vmx);
2a7921b7 6588 debugctlmsr = get_debugctlmsr();
d7cd9796 6589
d462b819 6590 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6591 asm(
6aa8b732 6592 /* Store host registers */
b188c81f
AK		 6593 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6594 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6595 "push %%" _ASM_CX " \n\t"
6596 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6597 "je 1f \n\t"
b188c81f 6598 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6599 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6600 "1: \n\t"
d3edefc0 6601 /* Reload cr2 if changed */
b188c81f
AK		 6602 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6603 "mov %%cr2, %%" _ASM_DX " \n\t"
6604 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6605 "je 2f \n\t"
b188c81f 6606 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6607 "2: \n\t"
6aa8b732 6608 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6609 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6610 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6611 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6612 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6613 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6614 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6615 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6616 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6617#ifdef CONFIG_X86_64
e08aa78a
AK		 6618 "mov %c[r8](%0), %%r8 \n\t"
6619 "mov %c[r9](%0), %%r9 \n\t"
6620 "mov %c[r10](%0), %%r10 \n\t"
6621 "mov %c[r11](%0), %%r11 \n\t"
6622 "mov %c[r12](%0), %%r12 \n\t"
6623 "mov %c[r13](%0), %%r13 \n\t"
6624 "mov %c[r14](%0), %%r14 \n\t"
6625 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6626#endif
b188c81f 6627 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6628
6aa8b732 6629 /* Enter guest mode */
83287ea4 6630 "jne 1f \n\t"
4ecac3fd 6631 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6632 "jmp 2f \n\t"
6633 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6634 "2: "
6aa8b732 6635 /* Save guest registers, load host registers, keep flags */
b188c81f 6636 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6637 "pop %0 \n\t"
b188c81f
AK		 6638 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6639 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6640 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6641 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6642 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6643 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6644 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6645#ifdef CONFIG_X86_64
e08aa78a
AK		 6646 "mov %%r8, %c[r8](%0) \n\t"
6647 "mov %%r9, %c[r9](%0) \n\t"
6648 "mov %%r10, %c[r10](%0) \n\t"
6649 "mov %%r11, %c[r11](%0) \n\t"
6650 "mov %%r12, %c[r12](%0) \n\t"
6651 "mov %%r13, %c[r13](%0) \n\t"
6652 "mov %%r14, %c[r14](%0) \n\t"
6653 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6654#endif
b188c81f
AK		 6655 "mov %%cr2, %%" _ASM_AX " \n\t"
6656 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6657
b188c81f 6658 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6659 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6660 ".pushsection .rodata \n\t"
6661 ".global vmx_return \n\t"
6662 "vmx_return: " _ASM_PTR " 2b \n\t"
6663 ".popsection"
e08aa78a 6664 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6665 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6666 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6667 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6668 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6669 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6670 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6671 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6672 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6673 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6674 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6675#ifdef CONFIG_X86_64
ad312c7c
ZX		 6676 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6677 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6678 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6679 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6680 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6681 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6682 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6683 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6684#endif
40712fae
AK		 6685 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6686 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6687 : "cc", "memory"
6688#ifdef CONFIG_X86_64
b188c81f 6689 , "rax", "rbx", "rdi", "rsi"
c2036300 6690 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6691#else
6692 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6693#endif
6694 );
6aa8b732 6695
2a7921b7
GN		 6696 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6697 if (debugctlmsr)
6698 update_debugctlmsr(debugctlmsr);
6699
aa67f609
AK		 6700#ifndef CONFIG_X86_64
6701 /*
6702 * The sysexit path does not restore ds/es, so we must set them to
6703 * a reasonable value ourselves.
6704 *
6705 * We can't defer this to vmx_load_host_state() since that function
6706 * may be executed in interrupt context, which saves and restore segments
6707 * around it, nullifying its effect.
6708 */
6709 loadsegment(ds, __USER_DS);
6710 loadsegment(es, __USER_DS);
6711#endif
6712
6de4f3ad 6713 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6714 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6715 | (1 << VCPU_EXREG_CPL)
aff48baa 6716 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6717 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6718 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6719 vcpu->arch.regs_dirty = 0;
6720
1155f76a
AK		 6721 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6722
66c78ae4
NHE		 6723 if (is_guest_mode(vcpu)) {
6724 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6725 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6726 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6727 vmcs12->idt_vectoring_error_code =
6728 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6729 vmcs12->vm_exit_instruction_len =
6730 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6731 }
6732 }
6733
d462b819 6734 vmx->loaded_vmcs->launched = 1;
1b6269db 6735
51aa01d1 6736 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6737 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6738
6739 vmx_complete_atomic_exit(vmx);
6740 vmx_recover_nmi_blocking(vmx);
cf393f75 6741 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6742}
6743
6aa8b732
AK		 6744static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6745{
fb3f0f51
RR		 6746 struct vcpu_vmx *vmx = to_vmx(vcpu);
6747
cdbecfc3 6748 free_vpid(vmx);
ec378aee 6749 free_nested(vmx);
d462b819 6750 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6751 kfree(vmx->guest_msrs);
6752 kvm_vcpu_uninit(vcpu);
a4770347 6753 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6754}
6755
fb3f0f51 6756static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6757{
fb3f0f51 6758 int err;
c16f862d 6759 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6760 int cpu;
6aa8b732 6761
a2fa3e9f 6762 if (!vmx)
fb3f0f51
RR		 6763 return ERR_PTR(-ENOMEM);
6764
2384d2b3
SY		 6765 allocate_vpid(vmx);
6766
fb3f0f51
RR		 6767 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6768 if (err)
6769 goto free_vcpu;
965b58a5 6770
a2fa3e9f 6771 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6772 err = -ENOMEM;
fb3f0f51 6773 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6774 goto uninit_vcpu;
6775 }
965b58a5 6776
d462b819
NHE		 6777 vmx->loaded_vmcs = &vmx->vmcs01;
6778 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6779 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6780 goto free_msrs;
d462b819
NHE		 6781 if (!vmm_exclusive)
6782 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6783 loaded_vmcs_init(vmx->loaded_vmcs);
6784 if (!vmm_exclusive)
6785 kvm_cpu_vmxoff();
a2fa3e9f 6786
15ad7146
AK		 6787 cpu = get_cpu();
6788 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6789 vmx->vcpu.cpu = cpu;
8b9cf98c 6790 err = vmx_vcpu_setup(vmx);
fb3f0f51 6791 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6792 put_cpu();
fb3f0f51
RR		 6793 if (err)
6794 goto free_vmcs;
5e4a0b3c 6795 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6796 err = alloc_apic_access_page(kvm);
6797 if (err)
5e4a0b3c 6798 goto free_vmcs;
fb3f0f51 6799
b927a3ce
SY		 6800 if (enable_ept) {
6801 if (!kvm->arch.ept_identity_map_addr)
6802 kvm->arch.ept_identity_map_addr =
6803 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6804 err = -ENOMEM;
b7ebfb05
SY		 6805 if (alloc_identity_pagetable(kvm) != 0)
6806 goto free_vmcs;
93ea5388
GN		 6807 if (!init_rmode_identity_map(kvm))
6808 goto free_vmcs;
b927a3ce 6809 }
b7ebfb05 6810
a9d30f33
NHE		 6811 vmx->nested.current_vmptr = -1ull;
6812 vmx->nested.current_vmcs12 = NULL;
6813
fb3f0f51
RR		 6814 return &vmx->vcpu;
6815
6816free_vmcs:
5f3fbc34 6817 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6818free_msrs:
fb3f0f51
RR		 6819 kfree(vmx->guest_msrs);
6820uninit_vcpu:
6821 kvm_vcpu_uninit(&vmx->vcpu);
6822free_vcpu:
cdbecfc3 6823 free_vpid(vmx);
a4770347 6824 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6825 return ERR_PTR(err);
6aa8b732
AK		 6826}
6827
002c7f7c
YS		 6828static void __init vmx_check_processor_compat(void *rtn)
6829{
6830 struct vmcs_config vmcs_conf;
6831
6832 *(int *)rtn = 0;
6833 if (setup_vmcs_config(&vmcs_conf) < 0)
6834 *(int *)rtn = -EIO;
6835 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6836 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6837 smp_processor_id());
6838 *(int *)rtn = -EIO;
6839 }
6840}
6841
67253af5
SY		 6842static int get_ept_level(void)
6843{
6844 return VMX_EPT_DEFAULT_GAW + 1;
6845}
6846
4b12f0de 6847static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6848{
4b12f0de
SY		 6849 u64 ret;
6850
522c68c4
SY		 6851 /* For VT-d and EPT combination
6852 * 1. MMIO: always map as UC
6853 * 2. EPT with VT-d:
6854 * a. VT-d without snooping control feature: can't guarantee the
6855 * result, try to trust guest.
6856 * b. VT-d with snooping control feature: snooping control feature of
6857 * VT-d engine can guarantee the cache correctness. Just set it
6858 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6859 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6860 * consistent with host MTRR
6861 */
4b12f0de
SY		 6862 if (is_mmio)
6863 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6864 else if (vcpu->kvm->arch.iommu_domain &&
6865 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6866 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6867 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6868 else
522c68c4 6869 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6870 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6871
6872 return ret;
64d4d521
SY		 6873}
6874
17cc3935 6875static int vmx_get_lpage_level(void)
344f414f 6876{
878403b7
SY		 6877 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6878 return PT_DIRECTORY_LEVEL;
6879 else
6880 /* For shadow and EPT supported 1GB page */
6881 return PT_PDPE_LEVEL;
344f414f
JR		 6882}
6883
0e851880
SY		 6884static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6885{
4e47c7a6
SY		 6886 struct kvm_cpuid_entry2 *best;
6887 struct vcpu_vmx *vmx = to_vmx(vcpu);
6888 u32 exec_control;
6889
6890 vmx->rdtscp_enabled = false;
6891 if (vmx_rdtscp_supported()) {
6892 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6893 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6894 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6895 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6896 vmx->rdtscp_enabled = true;
6897 else {
6898 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6899 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6900 exec_control);
6901 }
6902 }
6903 }
ad756a16 6904
ad756a16
MJ		 6905 /* Exposing INVPCID only when PCID is exposed */
6906 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6907 if (vmx_invpcid_supported() &&
4f977045 6908 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6909 guest_cpuid_has_pcid(vcpu)) {
29282fde 6910 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6911 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6912 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6913 exec_control);
6914 } else {
29282fde
TI		 6915 if (cpu_has_secondary_exec_ctrls()) {
6916 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6917 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6918 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6919 exec_control);
6920 }
ad756a16 6921 if (best)
4f977045 6922 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6923 }
0e851880
SY		 6924}
6925
d4330ef2
JR		 6926static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6927{
7b8050f5
NHE		 6928 if (func == 1 && nested)
6929 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6930}
6931
fe3ef05c
NHE		 6932/*
6933 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6934 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6935 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6936 * guest in a way that will both be appropriate to L1's requests, and our
6937 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6938 * function also has additional necessary side-effects, like setting various
6939 * vcpu->arch fields.
6940 */
6941static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6942{
6943 struct vcpu_vmx *vmx = to_vmx(vcpu);
6944 u32 exec_control;
6945
6946 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6947 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6948 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6949 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6950 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6951 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6952 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6953 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6954 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6955 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6956 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6957 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6958 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6959 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6960 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6961 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6962 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6963 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6964 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6965 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6966 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6967 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6968 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6969 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6970 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6971 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6972 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6973 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6974 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6975 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6976 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6977 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6978 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6979 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6980 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6981 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6982
6983 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6984 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6985 vmcs12->vm_entry_intr_info_field);
6986 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6987 vmcs12->vm_entry_exception_error_code);
6988 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6989 vmcs12->vm_entry_instruction_len);
6990 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6991 vmcs12->guest_interruptibility_info);
6992 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6993 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 6994 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 6995 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6996 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6997 vmcs12->guest_pending_dbg_exceptions);
6998 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6999 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7000
7001 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7002
7003 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7004 (vmcs_config.pin_based_exec_ctrl |
7005 vmcs12->pin_based_vm_exec_control));
7006
7007 /*
7008 * Whether page-faults are trapped is determined by a combination of
7009 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7010 * If enable_ept, L0 doesn't care about page faults and we should
7011 * set all of these to L1's desires. However, if !enable_ept, L0 does
7012 * care about (at least some) page faults, and because it is not easy
7013 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7014 * to exit on each and every L2 page fault. This is done by setting
7015 * MASK=MATCH=0 and (see below) EB.PF=1.
7016 * Note that below we don't need special code to set EB.PF beyond the
7017 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7018 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7019 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7020 *
7021 * A problem with this approach (when !enable_ept) is that L1 may be
7022 * injected with more page faults than it asked for. This could have
7023 * caused problems, but in practice existing hypervisors don't care.
7024 * To fix this, we will need to emulate the PFEC checking (on the L1
7025 * page tables), using walk_addr(), when injecting PFs to L1.
7026 */
7027 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7028 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7029 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7030 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7031
7032 if (cpu_has_secondary_exec_ctrls()) {
7033 u32 exec_control = vmx_secondary_exec_control(vmx);
7034 if (!vmx->rdtscp_enabled)
7035 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7036 /* Take the following fields only from vmcs12 */
7037 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7038 if (nested_cpu_has(vmcs12,
7039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7040 exec_control |= vmcs12->secondary_vm_exec_control;
7041
7042 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7043 /*
7044 * Translate L1 physical address to host physical
7045 * address for vmcs02. Keep the page pinned, so this
7046 * physical address remains valid. We keep a reference
7047 * to it so we can release it later.
7048 */
7049 if (vmx->nested.apic_access_page) /* shouldn't happen */
7050 nested_release_page(vmx->nested.apic_access_page);
7051 vmx->nested.apic_access_page =
7052 nested_get_page(vcpu, vmcs12->apic_access_addr);
7053 /*
7054 * If translation failed, no matter: This feature asks
7055 * to exit when accessing the given address, and if it
7056 * can never be accessed, this feature won't do
7057 * anything anyway.
7058 */
7059 if (!vmx->nested.apic_access_page)
7060 exec_control &=
7061 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7062 else
7063 vmcs_write64(APIC_ACCESS_ADDR,
7064 page_to_phys(vmx->nested.apic_access_page));
7065 }
7066
7067 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7068 }
7069
7070
7071 /*
7072 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7073 * Some constant fields are set here by vmx_set_constant_host_state().
7074 * Other fields are different per CPU, and will be set later when
7075 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7076 */
7077 vmx_set_constant_host_state();
7078
7079 /*
7080 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7081 * entry, but only if the current (host) sp changed from the value
7082 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7083 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7084 * here we just force the write to happen on entry.
7085 */
7086 vmx->host_rsp = 0;
7087
7088 exec_control = vmx_exec_control(vmx); /* L0's desires */
7089 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7090 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7091 exec_control &= ~CPU_BASED_TPR_SHADOW;
7092 exec_control |= vmcs12->cpu_based_vm_exec_control;
7093 /*
7094 * Merging of IO and MSR bitmaps not currently supported.
7095 * Rather, exit every time.
7096 */
7097 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7098 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7099 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7100
7101 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7102
7103 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7104 * bitwise-or of what L1 wants to trap for L2, and what we want to
7105 * trap. Note that CR0.TS also needs updating - we do this later.
7106 */
7107 update_exception_bitmap(vcpu);
7108 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7109 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7110
7111 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7112 vmcs_write32(VM_EXIT_CONTROLS,
7113 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7114 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7115 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7116
7117 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7118 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7119 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7120 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7121
7122
7123 set_cr4_guest_host_mask(vmx);
7124
27fc51b2
NHE		 7125 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7126 vmcs_write64(TSC_OFFSET,
7127 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7128 else
7129 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7130
7131 if (enable_vpid) {
7132 /*
7133 * Trivially support vpid by letting L2s share their parent
7134 * L1's vpid. TODO: move to a more elaborate solution, giving
7135 * each L2 its own vpid and exposing the vpid feature to L1.
7136 */
7137 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7138 vmx_flush_tlb(vcpu);
7139 }
7140
7141 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7142 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7143 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7144 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7145 else
7146 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7147 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7148 vmx_set_efer(vcpu, vcpu->arch.efer);
7149
7150 /*
7151 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7152 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7153 * The CR0_READ_SHADOW is what L2 should have expected to read given
7154 * the specifications by L1; It's not enough to take
7155 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7156 * have more bits than L1 expected.
7157 */
7158 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7159 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7160
7161 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7162 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7163
7164 /* shadow page tables on either EPT or shadow page tables */
7165 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7166 kvm_mmu_reset_context(vcpu);
7167
7168 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7169 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7170}
7171
cd232ad0
NHE		 7172/*
7173 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7174 * for running an L2 nested guest.
7175 */
7176static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7177{
7178 struct vmcs12 *vmcs12;
7179 struct vcpu_vmx *vmx = to_vmx(vcpu);
7180 int cpu;
7181 struct loaded_vmcs *vmcs02;
7182
7183 if (!nested_vmx_check_permission(vcpu) ||
7184 !nested_vmx_check_vmcs12(vcpu))
7185 return 1;
7186
7187 skip_emulated_instruction(vcpu);
7188 vmcs12 = get_vmcs12(vcpu);
7189
7c177938
NHE		 7190 /*
7191 * The nested entry process starts with enforcing various prerequisites
7192 * on vmcs12 as required by the Intel SDM, and act appropriately when
7193 * they fail: As the SDM explains, some conditions should cause the
7194 * instruction to fail, while others will cause the instruction to seem
7195 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7196 * To speed up the normal (success) code path, we should avoid checking
7197 * for misconfigurations which will anyway be caught by the processor
7198 * when using the merged vmcs02.
7199 */
7200 if (vmcs12->launch_state == launch) {
7201 nested_vmx_failValid(vcpu,
7202 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7203 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7204 return 1;
7205 }
7206
7207 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7208 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7209 /*TODO: Also verify bits beyond physical address width are 0*/
7210 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7211 return 1;
7212 }
7213
7214 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7215 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7216 /*TODO: Also verify bits beyond physical address width are 0*/
7217 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7218 return 1;
7219 }
7220
7221 if (vmcs12->vm_entry_msr_load_count > 0 ||
7222 vmcs12->vm_exit_msr_load_count > 0 ||
7223 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7224 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7225 __func__);
7c177938
NHE		 7226 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7227 return 1;
7228 }
7229
7230 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7231 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7232 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7233 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7234 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7235 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7236 !vmx_control_verify(vmcs12->vm_exit_controls,
7237 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7238 !vmx_control_verify(vmcs12->vm_entry_controls,
7239 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7240 {
7241 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7242 return 1;
7243 }
7244
7245 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7246 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7247 nested_vmx_failValid(vcpu,
7248 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7249 return 1;
7250 }
7251
7252 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7253 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7254 nested_vmx_entry_failure(vcpu, vmcs12,
7255 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7256 return 1;
7257 }
7258 if (vmcs12->vmcs_link_pointer != -1ull) {
7259 nested_vmx_entry_failure(vcpu, vmcs12,
7260 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7261 return 1;
7262 }
7263
7264 /*
7265 * We're finally done with prerequisite checking, and can start with
7266 * the nested entry.
7267 */
7268
cd232ad0
NHE		 7269 vmcs02 = nested_get_current_vmcs02(vmx);
7270 if (!vmcs02)
7271 return -ENOMEM;
7272
7273 enter_guest_mode(vcpu);
7274
7275 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7276
7277 cpu = get_cpu();
7278 vmx->loaded_vmcs = vmcs02;
7279 vmx_vcpu_put(vcpu);
7280 vmx_vcpu_load(vcpu, cpu);
7281 vcpu->cpu = cpu;
7282 put_cpu();
7283
36c3cc42
JK		 7284 vmx_segment_cache_clear(vmx);
7285
cd232ad0
NHE		 7286 vmcs12->launch_state = 1;
7287
7288 prepare_vmcs02(vcpu, vmcs12);
7289
7290 /*
7291 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7292 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7293 * returned as far as L1 is concerned. It will only return (and set
7294 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7295 */
7296 return 1;
7297}
7298
4704d0be
NHE		 7299/*
7300 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7301 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7302 * This function returns the new value we should put in vmcs12.guest_cr0.
7303 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7304 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7305 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7306 * didn't trap the bit, because if L1 did, so would L0).
7307 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7308 * been modified by L2, and L1 knows it. So just leave the old value of
7309 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7310 * isn't relevant, because if L0 traps this bit it can set it to anything.
7311 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7312 * changed these bits, and therefore they need to be updated, but L0
7313 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7314 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7315 */
7316static inline unsigned long
7317vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7318{
7319 return
7320 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7321 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7322 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7323 vcpu->arch.cr0_guest_owned_bits));
7324}
7325
7326static inline unsigned long
7327vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7328{
7329 return
7330 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7331 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7332 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7333 vcpu->arch.cr4_guest_owned_bits));
7334}
7335
7336/*
7337 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7338 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7339 * and this function updates it to reflect the changes to the guest state while
7340 * L2 was running (and perhaps made some exits which were handled directly by L0
7341 * without going back to L1), and to reflect the exit reason.
7342 * Note that we do not have to copy here all VMCS fields, just those that
7343 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7344 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7345 * which already writes to vmcs12 directly.
7346 */
733568f9 7347static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7348{
7349 /* update guest state fields: */
7350 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7351 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7352
7353 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7354 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7355 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7356 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7357
7358 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7359 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7360 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7361 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7362 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7363 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7364 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7365 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7366 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7367 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7368 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7369 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7370 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7371 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7372 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7373 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7374 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7375 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7376 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7377 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7378 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7379 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7380 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7381 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7382 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7383 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7384 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7385 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7386 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7387 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7388 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7389 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7390 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7391 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7392 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7393 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7394
7395 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7396 vmcs12->guest_interruptibility_info =
7397 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7398 vmcs12->guest_pending_dbg_exceptions =
7399 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7400
7401 /* TODO: These cannot have changed unless we have MSR bitmaps and
7402 * the relevant bit asks not to trap the change */
7403 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7404 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7405 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7406 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7407 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7408 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7409
7410 /* update exit information fields: */
7411
957c897e 7412 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7413 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7414
7415 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7416 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
44ceb9d6 7417 vmcs12->idt_vectoring_info_field = to_vmx(vcpu)->idt_vectoring_info;
4704d0be
NHE		 7418 vmcs12->idt_vectoring_error_code =
7419 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7420 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7421 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7422
7423 /* clear vm-entry fields which are to be cleared on exit */
7424 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7425 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7426}
7427
7428/*
7429 * A part of what we need to when the nested L2 guest exits and we want to
7430 * run its L1 parent, is to reset L1's guest state to the host state specified
7431 * in vmcs12.
7432 * This function is to be called not only on normal nested exit, but also on
7433 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7434 * Failures During or After Loading Guest State").
7435 * This function should be called when the active VMCS is L1's (vmcs01).
7436 */
733568f9
JK		 7437static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7438 struct vmcs12 *vmcs12)
4704d0be
NHE		 7439{
7440 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7441 vcpu->arch.efer = vmcs12->host_ia32_efer;
7442 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7443 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7444 else
7445 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7446 vmx_set_efer(vcpu, vcpu->arch.efer);
7447
7448 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7449 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7450 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7451 /*
7452 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7453 * actually changed, because it depends on the current state of
7454 * fpu_active (which may have changed).
7455 * Note that vmx_set_cr0 refers to efer set above.
7456 */
7457 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7458 /*
7459 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7460 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7461 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7462 */
7463 update_exception_bitmap(vcpu);
7464 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7465 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7466
7467 /*
7468 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7469 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7470 */
7471 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7472 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7473
7474 /* shadow page tables on either EPT or shadow page tables */
7475 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7476 kvm_mmu_reset_context(vcpu);
7477
7478 if (enable_vpid) {
7479 /*
7480 * Trivially support vpid by letting L2s share their parent
7481 * L1's vpid. TODO: move to a more elaborate solution, giving
7482 * each L2 its own vpid and exposing the vpid feature to L1.
7483 */
7484 vmx_flush_tlb(vcpu);
7485 }
7486
7487
7488 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7489 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7490 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7491 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7492 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7493 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7494 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7495 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7496 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7497 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7498 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7499 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7500 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7501 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7502 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7503
7504 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7505 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7506 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7507 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7508 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7509
7510 kvm_set_dr(vcpu, 7, 0x400);
7511 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7512}
7513
7514/*
7515 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7516 * and modify vmcs12 to make it see what it would expect to see there if
7517 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7518 */
7519static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7520{
7521 struct vcpu_vmx *vmx = to_vmx(vcpu);
7522 int cpu;
7523 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7524
7525 leave_guest_mode(vcpu);
7526 prepare_vmcs12(vcpu, vmcs12);
7527
7528 cpu = get_cpu();
7529 vmx->loaded_vmcs = &vmx->vmcs01;
7530 vmx_vcpu_put(vcpu);
7531 vmx_vcpu_load(vcpu, cpu);
7532 vcpu->cpu = cpu;
7533 put_cpu();
7534
36c3cc42
JK		 7535 vmx_segment_cache_clear(vmx);
7536
4704d0be
NHE		 7537 /* if no vmcs02 cache requested, remove the one we used */
7538 if (VMCS02_POOL_SIZE == 0)
7539 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7540
7541 load_vmcs12_host_state(vcpu, vmcs12);
7542
27fc51b2 7543 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7544 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7545
7546 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7547 vmx->host_rsp = 0;
7548
7549 /* Unpin physical memory we referred to in vmcs02 */
7550 if (vmx->nested.apic_access_page) {
7551 nested_release_page(vmx->nested.apic_access_page);
7552 vmx->nested.apic_access_page = 0;
7553 }
7554
7555 /*
7556 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7557 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7558 * success or failure flag accordingly.
7559 */
7560 if (unlikely(vmx->fail)) {
7561 vmx->fail = 0;
7562 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7563 } else
7564 nested_vmx_succeed(vcpu);
7565}
7566
7c177938
NHE		 7567/*
7568 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7569 * 23.7 "VM-entry failures during or after loading guest state" (this also
7570 * lists the acceptable exit-reason and exit-qualification parameters).
7571 * It should only be called before L2 actually succeeded to run, and when
7572 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7573 */
7574static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7575 struct vmcs12 *vmcs12,
7576 u32 reason, unsigned long qualification)
7577{
7578 load_vmcs12_host_state(vcpu, vmcs12);
7579 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7580 vmcs12->exit_qualification = qualification;
7581 nested_vmx_succeed(vcpu);
7582}
7583
8a76d7f2
JR		 7584static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7585 struct x86_instruction_info *info,
7586 enum x86_intercept_stage stage)
7587{
7588 return X86EMUL_CONTINUE;
7589}
7590
cbdd1bea 7591static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7592 .cpu_has_kvm_support = cpu_has_kvm_support,
7593 .disabled_by_bios = vmx_disabled_by_bios,
7594 .hardware_setup = hardware_setup,
7595 .hardware_unsetup = hardware_unsetup,
002c7f7c 7596 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7597 .hardware_enable = hardware_enable,
7598 .hardware_disable = hardware_disable,
04547156 7599 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7600
7601 .vcpu_create = vmx_create_vcpu,
7602 .vcpu_free = vmx_free_vcpu,
04d2cc77 7603 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7604
04d2cc77 7605 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7606 .vcpu_load = vmx_vcpu_load,
7607 .vcpu_put = vmx_vcpu_put,
7608
c8639010 7609 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7610 .get_msr = vmx_get_msr,
7611 .set_msr = vmx_set_msr,
7612 .get_segment_base = vmx_get_segment_base,
7613 .get_segment = vmx_get_segment,
7614 .set_segment = vmx_set_segment,
2e4d2653 7615 .get_cpl = vmx_get_cpl,
6aa8b732 7616 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7617 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7618 .decache_cr3 = vmx_decache_cr3,
25c4c276 7619 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7620 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7621 .set_cr3 = vmx_set_cr3,
7622 .set_cr4 = vmx_set_cr4,
6aa8b732 7623 .set_efer = vmx_set_efer,
6aa8b732
AK		 7624 .get_idt = vmx_get_idt,
7625 .set_idt = vmx_set_idt,
7626 .get_gdt = vmx_get_gdt,
7627 .set_gdt = vmx_set_gdt,
020df079 7628 .set_dr7 = vmx_set_dr7,
5fdbf976 7629 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7630 .get_rflags = vmx_get_rflags,
7631 .set_rflags = vmx_set_rflags,
ebcbab4c 7632 .fpu_activate = vmx_fpu_activate,
02daab21 7633 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7634
7635 .tlb_flush = vmx_flush_tlb,
6aa8b732 7636
6aa8b732 7637 .run = vmx_vcpu_run,
6062d012 7638 .handle_exit = vmx_handle_exit,
6aa8b732 7639 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7640 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7641 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7642 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7643 .set_irq = vmx_inject_irq,
95ba8273 7644 .set_nmi = vmx_inject_nmi,
298101da 7645 .queue_exception = vmx_queue_exception,
b463a6f7 7646 .cancel_injection = vmx_cancel_injection,
78646121 7647 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7648 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7649 .get_nmi_mask = vmx_get_nmi_mask,
7650 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7651 .enable_nmi_window = enable_nmi_window,
7652 .enable_irq_window = enable_irq_window,
7653 .update_cr8_intercept = update_cr8_intercept,
8d14695f 7654 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 7655 .vm_has_apicv = vmx_vm_has_apicv,
7656 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7657 .hwapic_irr_update = vmx_hwapic_irr_update,
7658 .hwapic_isr_update = vmx_hwapic_isr_update,
95ba8273 7659
cbc94022 7660 .set_tss_addr = vmx_set_tss_addr,
67253af5 7661 .get_tdp_level = get_ept_level,
4b12f0de 7662 .get_mt_mask = vmx_get_mt_mask,
229456fc 7663
586f9607 7664 .get_exit_info = vmx_get_exit_info,
586f9607 7665
17cc3935 7666 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7667
7668 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7669
7670 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7671 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7672
7673 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7674
7675 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7676
4051b188 7677 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7678 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7679 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7680 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7681 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7682 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7683
7684 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7685
7686 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7687};
7688
7689static int __init vmx_init(void)
7690{
8d14695f 7691 int r, i, msr;
26bb0981
AK		 7692
7693 rdmsrl_safe(MSR_EFER, &host_efer);
7694
7695 for (i = 0; i < NR_VMX_MSR; ++i)
7696 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7697
3e7c73e9 7698 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7699 if (!vmx_io_bitmap_a)
7700 return -ENOMEM;
7701
2106a548
GC		 7702 r = -ENOMEM;
7703
3e7c73e9 7704 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7705 if (!vmx_io_bitmap_b)
fdef3ad1 7706 goto out;
fdef3ad1 7707
5897297b 7708 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7709 if (!vmx_msr_bitmap_legacy)
25c5f225 7710 goto out1;
2106a548 7711
8d14695f
YZ		 7712 vmx_msr_bitmap_legacy_x2apic =
7713 (unsigned long *)__get_free_page(GFP_KERNEL);
7714 if (!vmx_msr_bitmap_legacy_x2apic)
7715 goto out2;
25c5f225 7716
5897297b 7717 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7718 if (!vmx_msr_bitmap_longmode)
8d14695f 7719 goto out3;
2106a548 7720
8d14695f
YZ		 7721 vmx_msr_bitmap_longmode_x2apic =
7722 (unsigned long *)__get_free_page(GFP_KERNEL);
7723 if (!vmx_msr_bitmap_longmode_x2apic)
7724 goto out4;
5897297b 7725
fdef3ad1
HQ		 7726 /*
7727 * Allow direct access to the PC debug port (it is often used for I/O
7728 * delays, but the vmexits simply slow things down).
7729 */
3e7c73e9
AK		 7730 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7731 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7732
3e7c73e9 7733 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7734
5897297b
AK		 7735 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7736 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7737
2384d2b3
SY		 7738 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7739
0ee75bea
AK		 7740 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7741 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7742 if (r)
5897297b 7743 goto out3;
25c5f225 7744
8f536b76
ZY		 7745#ifdef CONFIG_KEXEC
7746 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7747 crash_vmclear_local_loaded_vmcss);
7748#endif
7749
5897297b
AK		 7750 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7751 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7752 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7753 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7754 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7755 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 7756 memcpy(vmx_msr_bitmap_legacy_x2apic,
7757 vmx_msr_bitmap_legacy, PAGE_SIZE);
7758 memcpy(vmx_msr_bitmap_longmode_x2apic,
7759 vmx_msr_bitmap_longmode, PAGE_SIZE);
7760
c7c9c56c 7761 if (enable_apicv_reg_vid) {
8d14695f
YZ		 7762 for (msr = 0x800; msr <= 0x8ff; msr++)
7763 vmx_disable_intercept_msr_read_x2apic(msr);
7764
7765 /* According SDM, in x2apic mode, the whole id reg is used.
7766 * But in KVM, it only use the highest eight bits. Need to
7767 * intercept it */
7768 vmx_enable_intercept_msr_read_x2apic(0x802);
7769 /* TMCCT */
7770 vmx_enable_intercept_msr_read_x2apic(0x839);
7771 /* TPR */
7772 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 7773 /* EOI */
7774 vmx_disable_intercept_msr_write_x2apic(0x80b);
7775 /* SELF-IPI */
7776 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 7777 }
fdef3ad1 7778
089d034e 7779 if (enable_ept) {
3f6d8c8a
XH		 7780 kvm_mmu_set_mask_ptes(0ull,
7781 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7782 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7783 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7784 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7785 kvm_enable_tdp();
7786 } else
7787 kvm_disable_tdp();
1439442c 7788
fdef3ad1
HQ		 7789 return 0;
7790
8d14695f 7791out4:
5897297b 7792 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 7793out3:
7794 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 7795out2:
5897297b 7796 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7797out1:
3e7c73e9 7798 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7799out:
3e7c73e9 7800 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7801 return r;
6aa8b732
AK		 7802}
7803
7804static void __exit vmx_exit(void)
7805{
8d14695f
YZ		 7806 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7807 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 7808 free_page((unsigned long)vmx_msr_bitmap_legacy);
7809 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7810 free_page((unsigned long)vmx_io_bitmap_b);
7811 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7812
8f536b76
ZY		 7813#ifdef CONFIG_KEXEC
7814 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7815 synchronize_rcu();
7816#endif
7817
cb498ea2 7818 kvm_exit();
6aa8b732
AK		 7819}
7820
7821module_init(vmx_init)
7822module_exit(vmx_exit)
Linux kernel - Deliverables
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